Semiconductor structure fabrication methods

Abstract

This disclosure relates to the semiconductor field and provides a method for fabricating a semiconductor structure. The method includes: providing a substrate with a stacked structure on its surface, the stacked structure including a first dielectric layer, a first conductive layer, and a second dielectric layer sequentially stacked, the stacked structure having a plurality of grooves extending through the thickness of the stacked structure into the substrate, the grooves defining bit line contact regions; forming a seed conductive layer, the seed conductive layer at least covering the sides of the grooves and being in electrical contact with the first conductive layer; and forming a second conductive layer, the second conductive layer covering the seed conductive layer and filling the grooves. This can reduce the probability of voids in the second conductive layer and its resistance, thereby improving the overall performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure. Background Technology

[0002] The manufacturing process of semiconductor structures, including integrated circuits, involves processes such as photolithography, etching, and thin film deposition. Etching processes can create at least one opening (including trenches, vias, and contact windows) in specific areas or locations within a semiconductor structure. Combined with deposition processes, target structures, such as gate lines, bit lines, memory cells, and metal interconnect structures, can be formed in these specific areas or locations.

[0003] During the manufacturing process of semiconductor structures, when a target structure is deposited in a specific region or location, the quality and performance of the deposited target structure can fluctuate significantly, which has a certain impact on the reliability and yield of the semiconductor structure. Summary of the Invention

[0004] This disclosure provides a method for fabricating a semiconductor structure, which can at least improve the reliability and yield of the semiconductor structure and reduce the resistance of the second conductive layer in the semiconductor structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate, the surface of which has a stacked structure, the stacked structure including a first dielectric layer, a first conductive layer and a second dielectric layer sequentially stacked, the stacked structure having a plurality of grooves extending through the thickness of the stacked structure and extending into the substrate, the grooves being used to define bit line contact regions; forming a seed conductive layer, the seed conductive layer at least covering the side surface of the grooves and being in electrical contact with the first conductive layer; and forming a second conductive layer, the second conductive layer covering the seed conductive layer and filling the grooves.

[0006] In some embodiments, the seed conductive layer is formed using an atomic layer deposition process.

[0007] In some embodiments, the process parameters of the atomic layer deposition process include a temperature of 400°C to 480°C.

[0008] In some embodiments, the process parameters of the atomic layer deposition process include a pressure of 0.1 torr to 1.5 torr.

[0009] In some embodiments, the thickness of the seed conductive layer is 1 nm to 3 nm.

[0010] In some embodiments, the material of the seed conductive layer is an intrinsic semiconductor material; after forming the seed conductive layer, the method further includes: introducing a first doping source gas into the groove, the first doping source gas having a first doping ion for reducing the resistivity of the seed conductive layer.

[0011] In some embodiments, the duration of introducing the first doped source gas is 30 min to 90 min.

[0012] In some embodiments, the process steps for forming the second conductive layer include: forming an initial second conductive layer using a full-surface deposition process, wherein the initial second conductive layer fills the groove and covers the top surface of the stacked structure; removing the initial second conductive layer on the top surface of the stacked structure to expose the stacked structure, and the remaining initial second conductive layer serving as the second conductive layer.

[0013] In some embodiments, the initial second conductive layer is formed using a chemical vapor deposition process.

[0014] In some embodiments, the material of the seed conductive layer is the same as the material of the second conductive layer and both are semiconductor materials; the second conductive layer is formed using a selective epitaxial growth process.

[0015] In some embodiments, the process steps for forming the second conductive layer further include: doping the second conductive layer to dope the second conductive layer with second dopant ions, wherein the second dopant ions are used to reduce the resistivity of the second conductive layer.

[0016] In some embodiments, the doping process includes: in the process step of forming the second conductive layer, providing a second doping source gas for in-situ doping, wherein the second doping source gas contains the second doping ions.

[0017] In some embodiments, after forming the seed conductive layer and before forming the second conductive layer, the method further includes: removing the seed conductive layer located on the bottom surface of the groove to expose the bottom surface of the groove, wherein the second conductive layer is in contact with the bottom surface of the groove.

[0018] In some embodiments, the seed conductive layer is made of metal; the second conductive layer is made of semiconductor material.

[0019] In some embodiments, after forming the second conductive layer, the method further includes: removing the second dielectric layer; and patterning the first conductive layer to form a plurality of spaced bit lines.

[0020] The technical solution provided by the embodiments of this disclosure has at least the following advantages: by first forming a seed conductive layer on the side of the groove that defines the bit line contact area, covering the side of the groove and electrically contacting the first conductive layer, the substrate is made uniform when the side of the groove is used as the substrate for the deposition of the second conductive layer. This makes the growth rate of the second conductive layer on the side of the groove consistent, avoiding the problem of voids forming inside the second conductive layer due to inconsistent deposition rates at different positions in the stacked structure, reducing the resistance of the formed second conductive layer, and improving the overall performance and yield of the second conductive layer and the semiconductor structure. Attached Figure Description

[0021] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figures 1 to 6 This is a schematic diagram illustrating the steps of a method for fabricating a semiconductor structure according to an embodiment of this disclosure. Detailed Implementation

[0023] As is known from the background technology, when a target structure is deposited at a specific location or in a specific region in a current semiconductor structure, the quality and yield of the target structure are very unstable, which in turn leads to poor overall performance and yield of the semiconductor structure.

[0024] In the fabrication of bit line contact structures for semiconductor structures, conductive material is typically filled into the grooves defining the bit line contact structure. The sides of these grooves expose multiple functional layers, and the growth rate of the conductive material differs on each layer. Since the bit line contact structure needs to directly contact the substrate, the grooves filled with conductive material extend through the stacked structure into the substrate, meaning they have a considerable depth. Therefore, when filling the grooves with conductive material, the varying growth rates of the conductive material on the sides of the grooves and the significant groove depth can easily lead to voids in the fabricated bit line contact structure. This results in excessively high resistance within the bit line contact structure, negatively impacting the overall performance and yield of the semiconductor structure.

[0025] This disclosure provides a method for fabricating a semiconductor structure. By forming a seed conductive layer on the side of a groove that covers the side of the groove and is in electrical contact with a first conductive layer, the substrate is made uniform when the side of the groove is used as a substrate for the deposition of a second conductive layer. This avoids the problem of voids forming inside the second conductive layer due to inconsistent deposition rates at different positions in the stacked structure, reduces the resistance of the formed second conductive layer, and improves the overall performance and yield of the second conductive layer and the semiconductor structure.

[0026] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0027] Figures 1 to 6 This is a schematic diagram illustrating the steps of a method for fabricating a semiconductor structure provided in this disclosure.

[0028] Figure 1 This is a schematic diagram of the structure of a substrate without a seed conductive layer provided in an embodiment of this disclosure. Figure 2 This is a schematic diagram of a substrate structure for completing the preparation of a seed conductive layer according to an embodiment of this disclosure. Figure 3 This is a schematic diagram of another substrate structure for completing the preparation of the seed conductive layer according to an embodiment of this disclosure. Figure 4 This is a schematic diagram of a substrate structure for completing the fabrication of the second conductive layer, provided by an embodiment of this disclosure. Figure 5 This is a schematic diagram of a substrate structure after the initial second conductive layer has been fabricated, according to an embodiment of this disclosure. Figure 6 This is a schematic diagram of a substrate structure for forming an initial bit line contact structure, provided in an embodiment of the present disclosure.

[0029] refer to Figure 1 , Figure 2 and Figure 4In some embodiments, the method for fabricating a semiconductor structure includes: providing a substrate 100, the surface of which has a stacked structure 110, the stacked structure including a first dielectric layer 111, a first conductive layer 112, and a second dielectric layer 113 sequentially stacked, the stacked structure 110 having a plurality of grooves 120 extending through the thickness of the stacked structure, the grooves 120 extending into the substrate 100, and the grooves 120 defining bit line contact regions; forming a seed conductive layer 130, the seed conductive layer 130 at least covering the sides of the grooves 120 and electrically contacting the first conductive layer 112; forming a second conductive layer 140, the second conductive layer 140 covering the seed conductive layer 130 and filling the grooves 120. By forming a seed conductive layer 130 within the grooves 120 that at least covers the sides of the grooves 120 and is electrically contacting the first conductive layer 112, the growth substrate on the sides of the grooves 120 is made as uniform as possible during subsequent conductive material deposition, and the growth rate difference of the second conductive layer 140 on the sides of the grooves 120 is small or negligible. This significantly reduces the probability of voids within the grown second conductive layer 140, thereby reducing the resistance of the second conductive layer 140 and the formed bit line contact structure, and improving the reliability and yield of the formed bit line contact structure and the subsequently fabricated semiconductor structure.

[0030] In some embodiments, the material of substrate 100 may include semiconductor materials, such as, but not limited to, silicon. In some embodiments, substrate 100 may include: basic semiconductors, compound semiconductors, or alloy semiconductors. For example, basic semiconductors include germanium; compound semiconductors include silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or group III-V semiconductor materials; alloy semiconductors include silicon germanium, silicon germanium carbide, germanium tin, silicon germanium tin, gallium arsenide phosphide, gallium indium phosphide, gallium indium arsenide, indium gallium arsenide, aluminum indium arsenide, and / or aluminum gallium arsenide. In some embodiments, substrate 100 may also be a silicon-on-insulator structure, a germanium-silicon-on-insulator structure, a germanium-on-insulator structure, or a combination thereof.

[0031] Additionally, the substrate 100 can be doped according to design requirements (e.g., a P-type substrate or an N-type substrate). In some embodiments, the substrate 100 may be doped with P-type dopant ions (e.g., boron ions, aluminum ions) or N-type dopant ions (e.g., phosphorus ions, arsenic ions). In some embodiments, the first dielectric layer 111 may be a nitride layer.

[0032] In some embodiments, the second dielectric layer 113 may be an oxide layer.

[0033] In some embodiments, the first conductive layer 112 may be a conductive layer of semiconductor materials such as polycrystalline silicon, monocrystalline silicon, or monocrystalline germanium, or a metal conductive layer of metal materials such as gold, silver, or copper.

[0034] In some embodiments, the material of the seed conductive layer 130 can be an elemental semiconductor material with good conductivity, such as germanium, silicon, selenium, boron or antimony, or it can be a compound semiconductor material, such as gallium arsenide, indium phosphide, indium antimonide, silicon carbide or cadmium sulfide.

[0035] The seed conductive layer 130 at least covers the side surface of the groove 120 and is in contact with the first conductive layer 112. That is, the seed conductive layer 130 covering the side surface of the groove 120 extends from the bottom of the groove 120 away from the substrate 100. The top surface of the seed conductive layer 130 can be located at any position between the first surface and the second surface, where the first surface is the surface where the first conductive layer 112 contacts the first dielectric layer 111, and the second surface is the surface of the second dielectric layer 113 away from the first conductive layer 112. For example, the seed conductive layer 130 can extend from the bottom of the groove 120 to the surface where the second dielectric layer 113 contacts the first conductive layer 112, the surface where the second dielectric layer 113 is away from the first conductive layer 112, or the surface where the first conductive layer 112 contacts the first dielectric layer 111. In some embodiments, the seed conductive layer 130 can also completely cover the side surface of the groove 120 and extend outside the groove 120, covering the surface of the second dielectric layer 113 away from the first conductive layer 112.

[0036] In addition, refer to Figure 3 The seed conductive layer 130 can cover not only the sides of the groove 120, but also the bottom surface of the groove 120 and the top surface of the stacked structure constituting the groove 120.

[0037] In some embodiments, an atomic layer deposition (ALD) process is used to form a seed conductive layer 130. The main function of the seed conductive layer 130 is to serve as a substrate on the sides of the groove 120 when the conductive layer is grown in the groove 120, thereby ensuring that the growth rate of the conductive layer in the groove 120 is as uniform as possible. Therefore, the thickness of the seed conductive layer 130 does not need to be too large, and it is sufficient to ensure that the seed conductive layer 130 can uniformly cover the sides of the groove 120 as much as possible. During the formation of the seed conductive layer 130, an ALD process can be used to deposit the material constituting the seed conductive layer 130 layer by layer in the form of a single atomic film on the sides of the groove 120, thereby forming a seed conductive layer 130 with uniform coverage of the sides of the groove 120 and a small thickness. This improves the uniformity and morphology of the seed conductive layer 130, thereby avoiding the influence of different thicknesses of the seed conductive layer 130 in different areas on the sides of the groove 120 on the quality of the subsequently formed conductive layer, and further improving the overall performance of the prepared conductive layer.

[0038] In some embodiments, the process parameters for atomic layer deposition include a temperature of 400°C to 480°C. During the deposition of the seed conductive layer 130, if the temperature is too high, the precursor used during deposition may experience parasitic chemical vapor deposition reactions due to excessively high temperatures, even exceeding the decomposition temperature of the precursor. This may also cause the deposited seed conductive layer 130 to detach from the sidewalls of the groove 120. If the temperature is too low, it may not provide sufficient energy for the reaction during deposition. Simultaneously, the precursor used during deposition may accumulate on the surface of the sidewalls of the groove 120 due to condensation, failing to form a uniform seed conductive layer 130 and damaging the morphology of the sidewalls of the groove 120.

[0039] Therefore, during the formation of the seed conductive layer 130 via atomic layer deposition (ALD), the temperature in the process parameters can be set within the range of 400°C to 480°C. For example, the deposition temperature can be set to 405°C, 410°C, 420°C, 425°C, 440°C, 450°C, 465°C, or 475°C. By setting the temperature in the ALD process at an appropriate level, parasitic chemical vapor deposition reactions can be avoided, while simultaneously improving the uniformity and morphology of the formed seed conductive layer 130, enhancing the stability of the bond between the seed conductive layer 130 and the side of the groove 120, and reducing the probability of the seed conductive layer 130 detaching.

[0040] It should be noted that when the seed conductive layer 130 is made of metal, the precursor in the atomic layer deposition process can be titanium tetrachloride, tungsten boride, or an organometallic compound; when the seed conductive layer 130 is made of semiconductor material, the precursor in the atomic layer deposition process can be silane, silane, or dichlorosilane.

[0041] In some embodiments, the process parameters of the atomic layer deposition process include a pressure of 0.1 torr to 1.5 torr. During the formation of the seed conductive layer 130 by atomic layer deposition, if the pressure during the deposition process is too high, the precursor used in the deposition process cannot diffuse in a timely and uniform manner, resulting in poor uniformity and morphology of the seed conductive layer 130 covering the sides of the groove 120 during the deposition process. If the pressure during the deposition process is too low, the seed conductive layer 130, which is mainly deposited by adsorption, will have a slow deposition rate during the deposition process, making it impossible to efficiently form the seed conductive layer 130.

[0042] Therefore, during the formation of the seed conductive layer 130 via atomic layer deposition, the deposition pressure can be set within the range of 0.1 torr to 1.5 torr, for example, at 0.15 torr, 0.2 torr, 0.25 torr, 0.35 torr, 0.5 torr, 0.75 torr, 0.9 torr, 1 torr, 1.15 torr, 1.25 torr, 1.35 torr, or 1.45 torr. By setting the pressure during the atomic layer deposition process within a suitable range, a seed conductive layer 130 with good uniformity and morphology can be formed on the side of the groove 120, ensuring the formation efficiency of the seed conductive layer 130 and minimizing the time required for semiconductor structure fabrication.

[0043] In some embodiments, a chemical vapor deposition process can also be used to form the seed conductive layer 130.

[0044] In some embodiments, the thickness of the seed conductive layer 130 is 1 nm to 3 nm. The thickness of the seed conductive layer 130 refers to the distance *d* between the surface of the seed conductive layer 130 in contact with the groove 120 and the surface of the seed conductive layer 130 away from the groove 120 in a direction perpendicular to the side surface of the groove 120. The main function of the seed conductive layer 130 is to serve as a homogenizing substrate during the conductive material deposition process. Due to its thinness, it is difficult to achieve high-concentration doping of doped ions. If the thickness of the seed conductive layer 130 is too large, its volume is also correspondingly large. After conductive material deposition and subsequent processes, the large volume of the seed conductive layer 130 and the difficulty in achieving high-concentration doping result in a low overall doping concentration and high resistance in the formed bit line contact structure. If the thickness of the seed conductive layer 130 is too small, the bonding strength between the seed conductive layer 130 and the side surface of the groove 120 is low. During conductive material deposition, the seed conductive layer 130 is prone to detachment, leading to increased resistance and decreased yield in the conductive layer and the formed semiconductor structure.

[0045] Therefore, when forming the seed conductive layer 130, the thickness of the seed conductive layer 130 can be controlled within the range of 1 nm to 3 nm. For example, seed conductive layers 130 with thicknesses of 1.2 nm, 1.25 nm, 1.5 nm, 1.75 nm, 2 nm, 2.25 nm, 2.5 nm, or 2.8 nm can be formed. By forming a seed conductive layer 130 of suitable thickness, the volume ratio of the seed conductive layer 130 in the semiconductor structure is reduced, the overall doping concentration of doped ions in the subsequently formed bit line contact structure is increased, the probability of seed conductive layer 130 falling off is reduced, and the yield of the semiconductor structure is improved.

[0046] In some embodiments, the seed conductive layer 130 is made of an intrinsic semiconductor material. After forming the seed conductive layer 130, the process further includes: introducing a first doping source gas into the groove 120, the first doping source gas containing first doping ions for reducing the resistivity of the seed conductive layer 130. The seed conductive layer 130 is located inside the ultimately formed word line contact structure and is in electrical contact with the first conductive layer 112. When the seed conductive layer 130 is made of an intrinsic semiconductor material, its own resistance is relatively high, which will lead to a high overall resistance of the word line contact structure of the semiconductor structure formed by subsequent processes, affecting the performance of the semiconductor structure.

[0047] After the seed conductive layer 130 is formed, a first dopant source gas is introduced into the groove 120, which is at least partially covered by the seed conductive layer 130. The first dopant ions contained in the first dopant source gas diffuse into the seed conductive layer 130, thereby doping the seed conductive layer 130 with first dopant ions that help reduce its resistivity and thus lower its resistance. By introducing the first dopant source gas into the groove 120 where the seed conductive layer 130 has been formed, the first dopant source ions are doped into the seed conductive layer 130, effectively reducing the resistance of the seed conductive layer 130 made of intrinsic semiconductor material, thereby improving the performance of the final word line contact structure and semiconductor structure.

[0048] In some embodiments, the first doping source gas can be introduced into the groove 120 by continuously introducing the first doping source gas into the groove 120 at a preset flow rate. By continuously providing a large number of first doping source ions, the speed of doping the first doping ions into the seed conductive layer 130 and the doping concentration in the seed conductive layer 130 after doping are increased as much as possible, thereby reducing the resistance of the seed conductive layer 130 as much as possible.

[0049] In some embodiments, the first doping source gas can be introduced into the groove 120 intermittently according to a preset period. By periodically introducing the first doping source gas, the total amount of first doping gas required to dope the first doping ions into the seed conductive layer 130 is reduced, thereby reducing the cost of doping the first doping ions into the seed conductive layer 130 and effectively controlling the fabrication cost of the bit line contact structure and the semiconductor structure.

[0050] In some embodiments, the first doping source gas can be introduced into the groove 120 intermittently according to random time intervals or gradually changing time intervals.

[0051] In some embodiments, the duration of introducing the first dopant source gas into the groove 120 is 30 min to 90 min. When other external conditions, such as the concentration of the first dopant source gas, the pressure within the groove 120, and the temperature, are constant during the introduction of the first dopant source gas into the groove 120, the duration of introducing the first dopant source gas into the groove 120 will affect the doping effect of the first doped ions in the seed conductive layer 130. If the duration of introducing the first dopant source gas is too short, the total amount of first doped ions provided is small, and the diffusion time of the first doped ions is short, resulting in poor concentration and uniformity of the first doped ions in the seed conductive layer 130. If the duration of introducing the first dopant source gas is too long, the total amount of first doped ions provided is too large. Since the upper limit of the doping concentration of the first doped ions in the seed conductive layer 130 is low, there are too many useless first doped ions, resulting in excessive doping cost of the seed conductive layer 130.

[0052] Therefore, when introducing the first dopant source gas into the groove 120, the duration of introducing the first dopant source gas can be controlled within the range of 30 min to 90 min. For example, the duration of introducing the first dopant source gas can be set to 35 min, 40 min, 45 min, 50 min, 60 min, 65 min, 75 min, or 85 min. By controlling the duration of introducing the first dopant source gas within an appropriate range, a certain concentration of first dopant source ions can be uniformly doped into the seed conductive layer 130, effectively reducing the resistance of the seed conductive layer 130 while reducing the doping cost of the seed conductive layer 130.

[0053] The duration of introducing the first dopant source gas into the groove 120 refers to the time interval between the start of introducing the first dopant source gas into the groove 120 and the completion of doping the seed conductive layer 130 with the first dopant source ions. When the first dopant source gas is continuously introduced, it is the time elapsed from the start of introducing the first dopant source gas to the stop of introducing the first dopant source gas; when the first dopant source gas is intermittently introduced, it is the time elapsed from the first start of introducing the first dopant source gas to the last stop of introducing the first dopant source gas.

[0054] In some embodiments, the first dopant ion can be a P-type dopant ion, such as boron, indium, or gallium, or an N-type dopant ion, such as phosphorus or antimony. Depending on the type of substrate 100, either P-type or N-type dopant ions are selectively used as the first dopant ion to ensure that the semiconductor structure has normal operating performance.

[0055] In some embodiments, the intrinsic semiconductor material of the seed conductive layer 130 may be one or a combination of polycrystalline silicon, monocrystalline silicon, monocrystalline germanium, or gallium arsenide.

[0056] refer to Figure 1 , Figure 4 and Figure 5 In some embodiments, the process steps for forming the second conductive layer 140 include: forming an initial second conductive layer 150 using a full-surface deposition process, wherein the initial second conductive layer 150 fills the groove 120 and covers the top surface of the stacked structure; removing the initial second conductive layer 150 on the top surface of the stacked structure to expose the stacked structure, and the remaining initial second conductive layer 150 serves as the second conductive layer 140. When the second conductive layer 140 is formed using a full-surface deposition process, the initial second conductive layer 150 filling the groove 120 and covering the top surface of the stacked structure can be formed efficiently, thereby improving the formation efficiency of the second conductive layer 140. After forming the initial second conductive layer 150, the portion of the initial second conductive layer 150 above the top surface of the stacked structure is removed using a back-etching process until the stacked structure covered by the initial second conductive layer 150 is exposed. By using back-etching, the second conductive layer 140 is accurately formed, facilitating subsequent process steps and improving the fabrication efficiency of the semiconductor structure.

[0057] In some embodiments, the process steps for forming the initial second conductive layer 150 include: forming the initial second conductive layer 150 using a chemical vapor deposition process. The initial second conductive layer 150 is used to subsequently form the second conductive layer 140 that constructs the bit line contact structure. The chemical vapor deposition process can form the initial second conductive layer 150 as efficiently as possible, thereby reducing the time required to form the second conductive layer 140 and the bit line contact structure, and improving the production efficiency of the semiconductor structure.

[0058] In some embodiments, the seed conductive layer 130 is made of metal, and the second conductive layer 140 is made of semiconductor material. The seed conductive layer 130 serves as the substrate for the growth of the second conductive layer 140 and needs to be in electrical contact with both the second conductive layer 140 and the first conductive layer 112. As part of the bit line contact structure, it needs to have good conductivity. Since the seed conductive layer 130 is thin, it is difficult to dope it. Therefore, a metal material can be directly used to form the seed conductive layer 130, and then a semiconductor material can be used to form the second conductive layer 140. Using a metal material to form the seed conductive layer 130 and a semiconductor material to form the second conductive layer 140 reduces the probability of voids in the second conductive layer 140 while maximizing the conductivity of the seed conductive layer 130, thereby reducing the resistance of the bit line contact structure and improving the overall performance of the semiconductor structure.

[0059] In some embodiments, the seed conductive layer 130 can be made of a single metallic element, such as copper, silver, aluminum or gold, or it can be an alloy of multiple metallic elements, such as copper-aluminum alloy, copper-silver alloy, copper-tin alloy, etc.

[0060] In some embodiments, the seed conductive layer 130 and the second conductive layer 140 can both be elemental semiconductors such as polycrystalline silicon, single-crystal silicon, germanium, selenium, boron or antimony, or they can be compound semiconductor materials, such as gallium arsenide, indium phosphide, indium antimonide, silicon carbide or cadmium sulfide.

[0061] In some embodiments, the seed conductive layer 130 is made of the same material as the second conductive layer 140, and both are semiconductor materials. The second conductive layer 140 is formed using a selective epitaxial growth process. Using a selective epitaxial growth process to form the second conductive layer 140 can improve the uniformity and morphology of the grown second conductive layer 140, increase the yield of the second conductive layer 140, and reduce the resistance of the second conductive layer 140.

[0062] In some embodiments, the process steps for forming the second conductive layer 140 further include: doping the second conductive layer 140 to dope it with second dopant ions, which are used to reduce the resistance of the second conductive layer. The second conductive layer 140 is used to construct the bit line contact structure, and therefore needs to have good conductivity. However, when the material of the second conductive layer 140 is a semiconductor material, its resistance is relatively high. When the second conductive layer 140 is formed by a full-area deposition process combined with a selective removal process or by a selective epitaxial growth process, doping the second conductive layer 140 with second dopant ions that help reduce its resistivity can effectively improve the conductivity of the formed second conductive layer 140, reduce the overall resistance of the second conductive layer 140 and the formed bit line contact structure, and improve the bit line contact structure and performance.

[0063] In some embodiments, the doping method includes providing a second doping source gas for in-situ doping during the process of forming the second conductive layer 140, wherein the second doping source gas contains second doped ions. When doping the second conductive layer 140, the second doping source gas is provided simultaneously during the growth of the second conductive layer 140, performing in-situ doping on the growing second conductive layer 140. This allows the second doped ions from the second doping source gas to be uniformly doped into the second conductive layer 140, improving the doping uniformity of the second doped ions in the second conductive layer 140, minimizing the resistivity of the second conductive layer 140, and also reducing the process steps and fabrication time for the bit line contact structure.

[0064] In some embodiments, the doping treatment method may also be to inject second dopant ions into the second conductive layer 140 by ion implantation after the second conductive layer 140 is formed by deposition process to reduce the resistivity of the second conductive layer 140. The use of ion implantation is beneficial to reduce the process requirements and difficulty in the formation of the second conductive layer 140.

[0065] In some embodiments, the second dopant ion can be a p-type dopant ion, such as boron, indium, or gallium, or an n-type dopant ion, such as phosphorus or antimony. Furthermore, the first and second dopant ions can be the same dopant ion or different dopant ions.

[0066] In some embodiments, after forming the seed conductive layer 130 and before forming the second conductive layer 140, the process further includes: removing the seed conductive layer 130 located on the bottom surface of the groove 120 to expose the bottom surface of the groove 120, with the second conductive layer 140 in contact with the bottom surface of the groove 120. When the seed conductive layer 130 is formed by a deposition process, a seed conductive layer 130 covering the bottom surface of the groove 120 is generally also formed. When the material of the seed conductive layer 130 is a semiconductor material, the resistance of the seed conductive layer 130 on the bottom surface of the groove 120 is relatively high, which will lead to excessive contact resistance between the formed bit line contact structure and the substrate 100. Therefore, after forming the seed conductive layer 130 and before forming the second conductive layer 140, the seed conductive layer 130 located on the bottom surface of the groove 120 is removed to expose the bottom surface of the groove 120, and then the second conductive layer 140 is formed in the groove 120 so that the second conductive layer 140 directly contacts the substrate 100 on the bottom surface of the groove 120. By removing the seed conductive layer 130 on the bottom surface of the groove 120 and forming a second conductive layer 140 that directly contacts the substrate 100 on the bottom surface of the groove 120, the bit line contact structure contacts the substrate 100 through the second conductive layer 140, thereby reducing the contact resistance between the bit line contact structure and the substrate 100 and improving the overall performance of the semiconductor structure.

[0067] Furthermore, due to the small thickness of the seed conductive layer 130, it is difficult to achieve a high concentration of doping in the seed conductive layer 130 on the bottom surface of the groove 120. After removing the seed conductive layer 130 on the bottom surface of the groove 120, the bit line contact structure will contact the substrate 100 through the second conductive layer 140. After the second conductive layer 140 is doped with second doped ions through in-situ doping or ion implantation, the doping concentration of the second doped ions in the second conductive layer 140 is much greater than the doping concentration of the first doped ions in the seed conductive layer 130. The resistivity of the second conductive layer 140 is also lower than that of the seed conductive layer 130, thereby further reducing the contact resistance between the bit line contact structure and the substrate 100.

[0068] Furthermore, during the doping process of the second conductive layer 140, the interface between the second conductive layer 140 and the substrate 100 will repel the second doped ions, thereby ensuring that the second doped ions remain within the second conductive layer 140 as much as possible. This increases the doping concentration of the second conductive layer 140 while reducing the damage to the substrate 100 caused by the diffusion of the second doped ions into the substrate 100. Taking a polycrystalline silicon material for the second conductive layer 140, a monocrystalline silicon material for the substrate 100, and phosphorus ions as an example, when phosphorus ions are provided into the second conductive layer 140, the polycrystalline silicon-monocrystalline silicon interface between the second conductive layer 140 and the substrate 100 will repel the phosphorus ions, ensuring that the provided phosphorus ions remain within the second conductive layer 140 as much as possible.

[0069] refer to Figure 1 and Figure 6 In some embodiments, after forming the second conductive layer 140, the process further includes: removing the second dielectric layer 113; and patterning the first conductive layer 112 to form multiple spaced bit lines. After completing the fabrication of the second conductive layer 140, the second dielectric layer 113 is removed to obtain an initial bit line contact structure composed of the mutually electrically contacting first conductive layer 112, seed conductive layer 130, and second conductive layer 140. Then, the first conductive layer 112 is patterned to form bit line contact structures corresponding to the multiple spaced bit lines, and then multiple spaced bit lines are formed in conjunction with subsequent processes. Multiple bit lines are formed by patterning the first conductive layer 112 after removing the second dielectric layer 113.

[0070] This embodiment first forms a seed conductive layer 130 on the side of the groove 120 that defines the bit line contact area, covering the side of the groove 120 and electrically contacting the first conductive layer 112. This makes the substrate uniform when the second conductive layer 140 is deposited using the side of the groove 120 as the substrate. This ensures that the growth rate of the second conductive layer 140 is consistent on the side of the groove 120, avoiding the problem of voids forming inside the second conductive layer 140 due to inconsistent deposition rates at different positions in the stacked structure. This reduces the resistance of the formed second conductive layer 140 and improves the overall performance and yield of the second conductive layer 140 and the semiconductor structure.

[0071] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the surface of which has a stacked structure, the stacked structure including a first dielectric layer, a first conductive layer and a second dielectric layer stacked sequentially, the stacked structure having a plurality of grooves extending through the thickness of the stacked structure and extending into the substrate, the grooves being used to define bit line contact areas; A seed conductive layer is formed using an atomic layer deposition process. The thickness of the seed conductive layer is 1 nm to 3 nm. The material of the seed conductive layer is an intrinsic semiconductor material. The seed conductive layer at least covers the side of the groove and is in electrical contact with the first conductive layer. A first doping source gas is introduced into the groove, the first doping source gas containing first doping ions for reducing the resistivity of the seed conductive layer; A second conductive layer is formed, which covers the seed conductive layer and fills the groove.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The process parameters for the atomic layer deposition process include a temperature of 400°C to 480°C and a pressure of 0.1 torr to 1.5 torr.

3. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The duration of introducing the first doped source gas is 30 min to 90 min.

4. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The process steps for forming the second conductive layer include: An initial second conductive layer is formed using a chemical vapor deposition process, which fills the groove and covers the top surface of the stacked structure. Remove the initial second conductive layer on the top surface of the stacked structure to expose the stacked structure, and the remaining initial second conductive layer serves as the second conductive layer.

5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, The process steps for forming the second conductive layer further include: The second conductive layer is doped to dope it with second dopant ions, which are used to reduce the resistivity of the second conductive layer.

6. The method for fabricating a semiconductor structure according to claim 5, characterized in that, The doping treatment method includes: In the process step of forming the second conductive layer, a second doping source gas is also provided for in-situ doping, wherein the second doping source gas contains the second doped ions.

7. The method for fabricating a semiconductor structure according to claim 5, characterized in that, After the seed conductive layer is formed and before the second conductive layer is formed, the method further includes: Remove the seed conductive layer located on the bottom surface of the groove to expose the bottom surface of the groove, and the second conductive layer is in contact with the bottom surface of the groove.

8. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The seed conductive layer is made of metal; the second conductive layer is made of semiconductor material.

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