Semiconductor packaging structure and manufacturing method thereof

Abstract

Disclosed are a semiconductor packaging structure and a manufacturing method thereof. The semiconductor packaging structure comprises: a supporting substrate; a chip stack located on a central region of the supporting substrate and comprising a plurality of chips; a first connector located on a first edge region of the supporting substrate, with a first redistribution layer located on the first connector; a second connector located on a second edge region of the supporting substrate opposite the first edge region, with a second redistribution layer located on the second connector; bonding wires electrically connecting the plurality of chips to the first redistribution layer and the second redistribution layer, respectively; a dummy chip located on the chip stack; and an encapsulation layer encapsulating the chip stack, the dummy chip, the first connector, the second connector, and the bonding wires, wherein the upper surface of the dummy chip is coplanar with the upper surface of the encapsulation layer, and external connection terminals are located on the first redistribution layer and the second redistribution layer.

Description

Technical Field

[0001] Example embodiments of the present disclosure relate to the field of semiconductor packaging, and in particular, to a semiconductor packaging structure and a method for manufacturing the same. Background Art

[0002] Typically, in order to achieve multi-chip stacking, wire bonding technology can be used to connect the individual chips constituting the package structure to the corresponding substrate, and then the exposed chips stacked on the substrate are encapsulated by molding to form a package structure.

[0003] Figure 1 FIG. 1 shows a semiconductor package structure according to the related art. Figure 1 The semiconductor package structure 10 may include a substrate 1, a plurality of chips 2, bonding wires 3, an encapsulation layer 4, and solder balls 5. The plurality of chips 2 are stacked with their active surfaces facing upward and fixed to the upper side of the substrate 1. The plurality of chips 2 are staggered relative to each other to expose the pads on the active surface of each chip 2. The bonding wires 3 electrically connect the plurality of chips 2 to each other and to the substrate 1 via the pads. The solder balls 5 are provided on the lower side of the substrate 1 for outputting signals from the chips 2 or receiving signals from the outside.

[0004] The above-mentioned semiconductor packaging structure has the following problems: first, since the packaging structure uses a substrate, its thickness is difficult to reduce; second, the interconnection density of the substrate-level packaging structure is low; third, for ultra-thin packaging structures, the use of a thin substrate is not only prone to reliability risks, but also increases the difficulty of the packaging process.

[0005] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not form the relevant technology that is already known in this country to a person of ordinary skill in the art. Summary of the Invention

[0006] To solve the above problems, example embodiments of the present disclosure disclose a semiconductor package structure having high interconnection density, small thickness, and / or enhanced bottom heat dissipation, and a method for manufacturing the same.

[0007] According to one aspect of the present disclosure, a semiconductor package structure is provided, comprising: a supporting substrate; a chip stack located in a central region of the supporting substrate and comprising a plurality of chips stacked on the supporting substrate; a first connector disposed in a first edge region of the supporting substrate, a first redistribution layer being formed on an upper surface of the first connector; a second connector disposed in a second edge region of the supporting substrate opposite to the first edge region, a second redistribution layer being formed on an upper surface of the second connector; bonding wires electrically connecting the plurality of chips to the first redistribution layer and the second redistribution layer, respectively; a dummy chip located on the chip stack; and an encapsulation layer encapsulating the chip stack, the dummy chip, the first connector, the second connector, and the bonding wires on the supporting substrate. The upper surface of the dummy chip is coplanar with the upper surface of the encapsulation layer, and the encapsulation layer exposes external connection terminals disposed on the first redistribution layer and the second redistribution layer.

[0008] Further, each of the plurality of chips may include an active surface and an inactive surface, wherein the active surface faces the dummy chip, and the inactive surface faces the supporting substrate.

[0009] Further, the plurality of chips may include a plurality of first chips on the supporting substrate and a plurality of second chips between the plurality of first chips and the dummy chip, each of the plurality of first chips being offset along a first horizontal direction to expose a first pad on the active surface, and each of the plurality of second chips being offset from each other along a second horizontal direction opposite to the first horizontal direction to expose a second pad on the active surface.

[0010] Further, the bonding wire may include a first bonding wire and a second bonding wire, the first bonding wire electrically connecting the first pad to the first redistribution layer, and the second bonding wire electrically connecting the second pad to the second redistribution layer.

[0011] Furthermore, upper surfaces of the first connector and the second connector may be lower than an upper surface of the dummy chip.

[0012] Further, upper surfaces of the first connector and the second connector may be coplanar with an active surface of an uppermost chip among the plurality of chips.

[0013] Further, a plurality of bumps may be provided on the first and second rewiring layers, the encapsulation layer surrounds side surfaces of the plurality of bumps, and the external connection terminals are provided on the plurality of bumps.

[0014] Further, the plurality of bumps may have a pillar shape and include a metal material.

[0015] Furthermore, the dummy chip may not have an electrical function and may be configured to control the thickness of the encapsulation layer by measuring the height of the dummy chip.

[0016] Further, the dummy chip may be configured as a heat sink for the plurality of chips.

[0017] Further, the supporting base may be formed of a resin film.

[0018] According to another aspect of the present disclosure, a method for manufacturing a semiconductor package structure is provided, the method comprising: providing a first connector and a second connector in a first edge region and a second edge region opposite to the first edge region of a support substrate, respectively, wherein a first redistribution layer is formed on an upper surface of the first connector and a second redistribution layer is formed on an upper surface of the second connector; stacking a plurality of chips on a central region of the support substrate; electrically connecting the plurality of chips to the first redistribution layer and the second redistribution layer, respectively, using bonding wires; providing a dummy chip on a chip stack formed by the plurality of chips; and encapsulating the plurality of chips, the dummy chip, the first connector, the second connector, and the bonding wires on the support substrate using an encapsulation layer. The upper surface of the dummy chip is coplanar with the upper surface of the encapsulation layer, and the encapsulation layer exposes external connection terminals provided on the first redistribution layer and the second redistribution layer.

[0019] Furthermore, the step of encapsulating using an encapsulation layer may also include: inverting the structure obtained in the previous step and placing it into a plastic encapsulation mold, wherein the plastic encapsulation mold includes an upper cavity and a lower cavity; closing the upper cavity and the lower cavity and injecting an encapsulant; curing the encapsulant to form the encapsulation layer; and removing the obtained structure from the plastic encapsulation mold.

[0020] Furthermore, an auxiliary material layer may be provided in the lower cavity of the plastic encapsulation mold, and when the upper cavity and the lower cavity are closed, the external connection terminal may be pressed into the auxiliary material layer.

[0021] Furthermore, when the structure obtained in the previous step is taken out from the plastic encapsulation mold, the external connection terminals can be separated from the auxiliary material layer.

[0022] Further, each of the plurality of chips may include an active surface and an inactive surface, wherein the active surface faces the dummy chip, and the inactive surface faces the supporting substrate.

[0023] Further, the plurality of chips may include a plurality of first chips on the supporting substrate and a plurality of second chips between the plurality of first chips and the dummy chip, each of the plurality of first chips being offset along a first horizontal direction to expose a first pad on the active surface, and each of the plurality of second chips being offset from each other along a second horizontal direction opposite to the first horizontal direction to expose a second pad on the active surface.

[0024] Further, the bonding wire may include a first bonding wire and a second bonding wire, the first bonding wire electrically connecting the first pad to the first redistribution layer, and the second bonding wire electrically connecting the second pad to the second redistribution layer.

[0025] Furthermore, when injecting the encapsulant, the thickness of the encapsulation layer to be formed can be controlled by measuring the height of the dummy chip.

[0026] Furthermore, the dummy chip can be used as a heat sink for the multiple chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other aspects of the present disclosure and their advantages will become clear through the following detailed description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings. In the accompanying drawings, the same reference numerals will always indicate the same elements.

[0028] Figure 1 A semiconductor package structure according to the related art is shown.

[0029] Figure 2 A semiconductor package structure according to an example embodiment of the present disclosure is shown.

[0030] Figure 3 A process flow chart illustrating a method for manufacturing a semiconductor package structure according to an example embodiment of the present disclosure is shown.

[0031] Figure 4 、 Figure 5 and Figure 6 Various steps of a method for manufacturing a semiconductor package structure according to an example embodiment of the present disclosure are shown. DETAILED DESCRIPTION

[0032] Hereinafter, various embodiments of the present disclosure will be more fully described with reference to the accompanying drawings in which some embodiments are shown. However, the present disclosure can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this description will be thorough and complete, and will convey the scope of the present disclosure to those skilled in the art. In the drawings, the dimensions of layers and regions may be exaggerated for clarity.

[0033] For ease of description, spatially relative terms such as "under," "beneath," "below," "above," "above," etc. may be used herein to describe the relationship of one element to other elements as shown in the accompanying drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, an element described as "under" or "beneath" other elements would then be oriented "above" the other elements. Thus, the term "under" can include both the orientations of "above" and "under." The device can be oriented otherwise (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein interpreted accordingly.

[0034] Terms such as first, second, etc. may be used herein to describe various elements, but these elements should not be limited by these terms. The above terms are only used to distinguish one component from another component. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this disclosure.

[0035] Unless the context clearly indicates otherwise, a singular expression may include a plural expression. Terms such as "include" or "have" may be interpreted as adding features, numbers, steps, operations, components, parts, or a combination thereof described in the specification.

[0036] It should be understood that when an element or layer is referred to as being “on,” “connected to,” “coupled to,” “attached to,” or “contacting” another element or layer, it can be directly on, connected to, coupled to, attached to, or contacting the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to,” “directly coupled to,” “directly attached to,” or “directly contacting” another element or layer, there are no intervening elements or layers. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0037] When the terms "approximately" or "substantially" are used in conjunction with a numerical value in this specification, it is intended that the relevant numerical value include a manufacturing or operating tolerance (e.g., ±10%) around the numerical value. In addition, when the words "approximately" and "substantially" are used in conjunction with a geometric shape, it is intended that the accuracy of the geometric shape is not required, but rather the tolerance of the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified to "approximately" or "substantially", it should be understood that these values ​​and shapes should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the numerical value or shape. When a range is specified, the range includes all values ​​therebetween, such as increments of 0.1%.

[0038] It will be understood that elements and / or properties thereof may be described herein as being “the same” or “equivalent” to other elements, and it will be further understood that elements and / or properties thereof described herein as being “the same”, “equivalent” or “equivalent” to other elements may be “the same”, “equivalent” or “equivalent” or “substantially the same”, “substantially equivalent” or “substantially equivalent” to other elements and / or properties. Elements and / or properties thereof that are “substantially the same”, “substantially equivalent” or “substantially equivalent” to other elements and / or properties will be understood to include elements and / or properties thereof that are the same, equivalent or equivalent to other elements and / or properties within manufacturing tolerances and / or material tolerances. Elements and / or properties that are the same or substantially the same and / or equivalent or substantially equivalent to other elements and / or properties may be structurally the same or substantially the same, functionally the same or substantially the same, and / or compositionally the same or substantially the same.

[0039] Figure 2 FIG. 1 shows a semiconductor package structure according to an example embodiment of the present disclosure. Figure 2The semiconductor package structure 100 includes: a supporting substrate 110; a chip stack body STK located on a central region CR of the supporting substrate 110 and including a plurality of chips 120 stacked on the supporting substrate 110; a first connector 130 disposed on a first edge region ER1 of the supporting substrate 110, a first redistribution layer 131 being formed on an upper surface 130U of the first connector 130; a second connector 140 disposed on a second edge region ER2 of the supporting substrate 110 opposite to the first edge region ER1, a second redistribution layer 141 being formed on an upper surface 140U of the second connector 140; and a bonding wire 150 connecting the plurality of chips 120 to each other. 20 are electrically connected to the first redistribution layer 131 and the second redistribution layer 141 respectively; a dummy chip 160, located on the chip stack STK; and an encapsulation layer 170, which encapsulates (for example, encapsulates or at least partially encapsulates) the chip stack STK, the dummy chip 160, the first joint 130, the second joint 140 and the bonding wire 150 on the supporting substrate 110, wherein the upper surface 160U of the dummy chip 160 can be basically coplanar with the upper surface 170U of the encapsulation layer 170, and the encapsulation layer 170 can expose or at least partially expose the external connection terminals 180 arranged on the first redistribution layer 131 and the second redistribution layer 141.

[0040] The semiconductor package structure according to the example embodiment of the present disclosure can electrically connect the bonding wire to the interconnection structure including the redistribution layer (such as the first redistribution layer 131 and / or the second redistribution layer 141) formed on the upper surface of the joints (such as the first joint 130 and / or the second joint 140) by providing joints (such as a plurality of joints) (respectively) on the edge region of the support substrate (such as the first edge region ER1 and / or the second edge region ER2). Figure 1 Compared with the semiconductor package structure according to the related art shown in , the thickness of the substrate can be eliminated or reduced, and the density of the interconnection structure can be increased, so that the overall thickness of the semiconductor package structure is reduced while the integration of the semiconductor package structure is improved.

[0041] In an embodiment, the support substrate 110 may be formed of a resin film, such as an EMC film. The support substrate 110 may be formed as a flexible substrate or a rigid substrate. The support substrate 110 may include a central region CR and an edge region ER. The edge region ER may be located on both sides of the central region CR. The edge region ER may include a first edge region ER1 located on a first side of the support substrate 110 and a second edge region ER2 located on a second side of the support substrate 110 opposite the first side. Circuit elements may not be formed in the first edge region ER1 and the second edge region ER2.

[0042] In an embodiment, each of the plurality of chips 120 included in the chip stack STK may include an active surface and a passive surface. Circuit patterns, wiring, pads, and input / output terminals may be formed on the active surface of each chip 120. The passive surface may face away from the active surface, for example, opposite to the active surface. In an embodiment, the active surface of each chip 120 may face the dummy chip 160, and the passive surface of each chip 120 may face the supporting substrate 110.

[0043] In an embodiment, the plurality of chips 120 may include a plurality of first chips 121 on the supporting substrate 110 and a plurality of second chips 122 between the plurality of first chips 121 and the dummy chip 160 (e.g., in a vertical direction). Each of the plurality of first chips 121 may be offset or staggered relative to each other along a first horizontal direction (e.g., +X direction) to expose or at least partially expose the first pad PD1 on the respective active surface. Each of the plurality of second chips 122 may be offset or staggered relative to each other along a second horizontal direction (e.g., -X direction) opposite to the first horizontal direction +X to expose or at least partially expose the second pad PD2 on the respective active surface.

[0044] In an embodiment, the bonding wire 150 may include a first bonding wire 151 and a second bonding wire 152. The first bonding wire 151 may electrically connect the first pad PD1 to the first redistribution layer 131. The second bonding wire 152 may electrically connect the second pad PD2 to the second redistribution layer 141. Specifically, since the offset or staggered direction of each of the plurality of first chips 121 is different from the offset or staggered direction of each of the plurality of second chips 122, a wider space may be formed (e.g., defined or at least partially defined) between the chip stack STK and the first joint 130 to accommodate or allow the arc of the (e.g., longer) first bonding wire 151, and a closer spacing may be formed between the chip stack STK and the second joint 140 to shorten the length of the (e.g., shorter) second bonding wire 152, so that the density of the first bonding wire 151 can be increased to increase the integration, and the resistance of the second bonding wire 152 can be reduced to speed up the signal transmission speed.

[0045] In an embodiment, at least one of the upper surface 130U of the first connector 130 and the upper surface 140U of the second connector 140 may be lower than the upper surface 160U of the dummy chip 160. Specifically, the upper surface 130U of the first connector 130 and the upper surface 140U of the second connector 140 may be substantially coplanar with the active surface of the uppermost chip in the plurality of chips 120, but example embodiments are not limited thereto. Therefore, the uppermost chip 120 (e.g., the second chip 122) in the chip stack STK may have ample wire bonding space, so that the second bonding wires 152 may be relatively shorter and densely arranged between the second pad PD2 and the second redistribution layer 141 to increase integration.

[0046] In an embodiment, a plurality of bumps 180B may be provided on the first redistribution layer 131 and / or the second redistribution layer 141. The encapsulation layer 170 may surround (e.g., cover or at least partially cover) the side surfaces of the plurality of bumps 180B, and the external connection terminals 180 may be provided on the plurality of bumps 180B, respectively. The bumps in the plurality of bumps 180B may also be understood to be included in the first redistribution layer 131 and / or the second redistribution layer 141.

[0047] In an embodiment, any or each of the plurality of bumps 180B may have, for example, a pillar shape and may include, for example, one or more metal materials such as at least one of copper, silver, gold, and tin, but example embodiments are not limited thereto. Figure 2 2 shows that the first re-wiring layer 131 and the second re-wiring layer 141 include the same number of bumps, but the present disclosure is not limited thereto, and the first re-wiring layer 131 and the second re-wiring layer 141 may include different numbers of bumps, respectively.

[0048] In an embodiment, the dummy chip 160 may not have an electrical function and may be configured to control the thickness of the encapsulation layer 170 by measuring its height. Specifically, when performing the molding process, a layer such as a dummy chip 160 may be formed thereon. Figure 2 The supporting substrate 110, shown in FIG, is placed into a molding die along with the other components except the encapsulation layer 170. The height of the upper surface 160U of the dummy chip 160 is then measured, and the amount of encapsulant injected is determined based on the measurement result, so that the encapsulation layer 170 formed with an appropriate amount of encapsulant has an appropriate thickness to expose the external connection terminals 180 (e.g., so that one or more of the external connection terminals 180 are exposed or at least partially exposed from the encapsulation layer 170 and are not encapsulated or at least partially unencapsulated).

[0049] In an embodiment, the dummy chip 160 can be configured as a heat sink for the plurality of chips 120 to quickly dissipate heat generated during operation. Since no additional heat sink is required, the semiconductor package structure 100 can have a smaller thickness and a faster operating speed.

[0050] Figure 3 A process flow chart illustrating a method for manufacturing a semiconductor package structure according to an example embodiment of the present disclosure is shown. Figure 4 、 Figure 5 and Figure 6 The various steps of the method for manufacturing a semiconductor package structure according to an exemplary embodiment of the present disclosure are shown. Figures 3 to 6 To describe Figure 2 The manufacturing method of the semiconductor package structure 100 shown in FIG.

[0051] Reference Figures 3 to 5 The method for manufacturing a semiconductor package structure may include: first, performing step S100, providing a first connector 130 and a second connector 140 in a first edge region ER1 and a second edge region ER2 opposite to the first edge region ER1 of a support substrate 110, respectively, wherein a first redistribution layer 131 is formed on an upper surface 130U of the first connector 130, and a second redistribution layer 141 is formed on an upper surface 140U of the second connector 140.

[0052] Next, step S200 is performed to stack a plurality of chips 120 on the central region CR of the support substrate 110. In an embodiment, when step S200 is performed, the active surface of any or each of the plurality of chips 120 may be stacked upward (for example, the plurality of chips 120 may be stacked so that the active surface of any or each of them faces upward). The plurality of chips 120 may include a plurality of first chips 121 and a plurality of second chips 122 sequentially stacked on the support substrate 110. When step S200 is performed, any or each of the plurality of first chips 121 may be offset (for example, staggered from each other) along a first horizontal direction (for example, +X direction) to expose or at least partially expose the first pad PD1 located on the respective active surface. Alternatively or additionally, any or each of the plurality of second chips 122 may be offset (for example, staggered from each other) along a second horizontal direction (for example, -X direction) opposite to the first horizontal direction +X to expose the second pad PD2 located on the respective active surface. After step S200 is performed (eg, as a result of performing step S200 ), the first pad PD1 may be located between the chip stack STK and the first joint 130 , and the second pad PD2 may be located between the chip stack STK and the second joint 140 .

[0053] Next, step S300 is performed to electrically connect the plurality of chips 120 to the first redistribution layer 131 and the second redistribution layer 141 using bonding wires 150. In an embodiment, one end of the first bonding wire 151 may be connected to the first pad PD1, and the other end may be electrically connected to the first redistribution layer 131. One end of the second bonding wire 152 may be connected to the second pad PD2, and the other end may be electrically connected to the second redistribution layer 141.

[0054] Next, step S400 is performed to arrange a dummy chip 160 on a chip stack STK formed by a plurality of chips 120 (e.g., including a plurality of chips 120 or at least partially formed by a plurality of chips 120) to form a structure. In an embodiment, at least one of the upper surface 130U of the first joint 130 and the upper surface 140U of the second joint 140 can be lower than the upper surface 160U of the dummy chip 160. Specifically, the upper surface 130U of the first redistribution layer 131 and the upper surface 141 of the second redistribution layer can be lower than the upper surface 160U of the dummy chip 160, but example embodiments are not limited thereto. For example, the upper surface 130U of the first joint 130 and / or the upper surface 140U of the second joint 140 can be coplanar or substantially coplanar with the active surface of the uppermost chip among the plurality of chips 120, but example embodiments are not limited thereto.

[0055] In an embodiment, after step S400 is performed, an active surface of each of the plurality of chips 120 may face the dummy chip 160 , and an inactive surface of each of the plurality of chips 120 may face the support substrate 110 , but example embodiments are not limited thereto.

[0056] Next, step S500 is performed to form a package using the encapsulation layer 170 to encapsulate (eg, encapsulate or at least partially encapsulate) a plurality of chips 120 , dummy chips 160 , first connectors 130 , second connectors 140 and / or bonding wires 150 on the supporting substrate 110 .

[0057] After step S500 is performed, the upper surface of the dummy chip 160 is coplanar or substantially coplanar with the upper surface of the encapsulation layer 170, and the encapsulation layer 170 exposes (e.g., at least partially exposes) any or each of the external connection terminals 180 arranged on the first redistribution layer 131 and / or the second redistribution layer 141.

[0058] In an embodiment, Figure 6As shown in FIG, step S500 of encapsulating using encapsulation layer 170 may further include: inverting the structure obtained in the previous step S400 and placing it into a plastic encapsulation mold, the plastic encapsulation mold including an upper cavity and a lower cavity; closing the upper cavity and the lower cavity and injecting an encapsulant; curing the encapsulant to form encapsulation layer 170 and the package; and removing the obtained structure from the plastic encapsulation mold (e.g., removing the package). Although not shown, the plastic encapsulation mold may be a device commonly used in the art for performing a plastic encapsulation process, such as a mold for performing a glue potting process, and example embodiments are not limited thereto.

[0059] In an embodiment, Figure 6 As shown in FIG, an auxiliary material layer 190 may be provided in the lower cavity of the molding mold. When the upper cavity and the lower cavity are closed, the external connection terminal 180 may be pressed into the auxiliary material layer 190. Then, an encapsulant may be injected into the molding mold to form the encapsulation layer 170.

[0060] In an embodiment, Figure 6 As shown in FIG5 , when the resultant structure of step S500 is removed from the plastic encapsulation mold, the external connection terminals 180 may be separated from the auxiliary material layer 190. Therefore, the auxiliary material layer 190 may protect the external connection terminals 180 during the molding process to prevent them from being damaged.

[0061] In an embodiment, Figure 6 As shown in FIG, when the encapsulant is injected, the thickness of the encapsulation layer 170 to be formed can be controlled by measuring the height of the dummy chip 160.

[0062] As a summary and review, first, the semiconductor packaging structure according to the example embodiment of the present disclosure eliminates or reduces the thickness of the substrate of the traditional package and reduces the thickness of the package as a whole. Secondly, eliminating or reducing the substrate of the traditional package can also improve reliability issues caused by multiple interfaces (for example, EMC-PCB interface). Third, the semiconductor packaging structure according to the example embodiment of the present disclosure adopts a first connector and a second connector to realize the electrical interconnection of multiple chips and the redistribution layer via wire bonding, which increases the interconnection density and improves the electrical characteristics of the package. Fourth, the dummy chip of the semiconductor packaging structure according to the example embodiment of the present disclosure can be used as a heat sink, which enhances the heat dissipation of the bottom of the package and does not require an additional heat sink, which not only reduces the overall thickness of the package, but also improves the performance and operating speed of the package.

[0063] While embodiments of the present disclosure have been shown and described herein, it will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit and scope of the disclosure as defined by the appended claims.

Claims

1. A semiconductor package structure, comprising: Support substrate; a chip stack located on a central area of ​​the support substrate and comprising a plurality of chips stacked on the support substrate; a first connector on a first edge region of the support substrate, the first redistribution layer being on an upper surface of the first connector; a second connector on a second edge region of the support substrate, the second edge region being opposite to the first edge region, and a second redistribution layer being on an upper surface of the second connector; bonding wires to electrically connect the plurality of chips to the first redistribution layer and the second redistribution layer respectively; a dummy chip, located on the chip stack; as well as an encapsulation layer on the supporting substrate, the encapsulation layer at least partially encapsulating the chip stack, the dummy chip, the first connector, the second connector, and the bonding wire; The upper surface of the dummy chip is coplanar with the upper surface of the encapsulation layer, and External connection terminals are at least partially exposed by the encapsulation layer, the external connection terminals being respectively on the first and second re-wiring layers.

2. The semiconductor package structure according to claim 1, wherein: Each of the plurality of chips includes an active surface and an inactive surface, the active surface faces the dummy chip, and the inactive surface faces the supporting substrate.

3. The semiconductor package structure according to claim 2, wherein: The plurality of chips include a plurality of first chips and a plurality of second chips, wherein the plurality of second chips are between the plurality of first chips and the dummy chip. Each of the plurality of first chips is offset along a first horizontal direction relative to any first chip vertically above the first chip, such that a first pad is exposed on the active surface of each of the plurality of first chips, and Each of the plurality of second chips is offset relative to any second chip vertically above the second chip in a second horizontal direction opposite to the first horizontal direction so that a second pad is exposed on the active surface of each of the plurality of second chips.

4. The semiconductor package structure according to claim 3, wherein: The bonding wires include a first bonding wire and a second bonding wire, The first bonding wire electrically connects the first pad of at least one of the plurality of first chips to the first redistribution layer, and The second bonding wire electrically connects the second pad of at least one of the plurality of second chips to the second redistribution layer.

5. The semiconductor package structure according to claim 1, wherein: The upper surface of the first connector and the upper surface of the second connector are lower than the upper surface of the dummy chip.

6. The semiconductor package structure according to claim 2, wherein: The upper surface of the first connector and the upper surface of the second connector are coplanar with the active surface of an uppermost chip of the plurality of chips.

7. The semiconductor package structure according to claim 5, wherein: A plurality of bumps are on the first and second re-wiring layers, the encapsulation layer at least partially covers side surfaces of the plurality of bumps, and the external connection terminals are respectively provided on the plurality of bumps.

8. The semiconductor package structure according to claim 7, wherein: At least one of the plurality of bumps has a pillar shape and includes at least one metal material.

9. The semiconductor package structure according to claim 1, wherein: The dummy chip has no electrical function.

10. The semiconductor package structure according to claim 1, wherein: The dummy chip is a heat sink for the plurality of chips.

11. The semiconductor package structure according to claim 1, wherein: The supporting base includes a resin film.

12. A method for manufacturing a semiconductor package structure, comprising: A first connector and a second connector are respectively provided on a first edge region of the support substrate and a second edge region opposite to the first edge region, wherein a first redistribution layer is formed on an upper surface of the first connector and a second redistribution layer is formed on an upper surface of the second connector; stacking a plurality of chips on a central area of ​​the supporting substrate; electrically connecting the plurality of chips to the first redistribution layer and the second redistribution layer respectively using bonding wires; disposing a dummy chip on a chip stack to form a structure, the chip stack including the plurality of chips; and at least partially encapsulating the plurality of chips, the dummy chip, the first connector, the second connector, and the bonding wire using an encapsulation layer to form a package, The upper surface of the dummy chip is coplanar with the upper surface of the encapsulation layer, and External connection terminals are at least partially exposed through the encapsulation layer, the external connection terminals being respectively on the first and second re-wiring layers.

13. The method according to claim 12, wherein: The step of at least partially encapsulating with an encapsulation layer further comprises: Inverting the structure and placing the structure into a plastic encapsulation mold, wherein the plastic encapsulation mold includes an upper cavity and a lower cavity; closing the upper cavity and the lower cavity and injecting an encapsulating agent; curing the encapsulant to form the encapsulation layer and the package; and The package is removed from the plastic mold.

14. The method according to claim 13, wherein An auxiliary material layer is provided in the lower cavity of the plastic encapsulation mold, and when the upper cavity and the lower cavity are closed, the external connection terminal is pressed into the auxiliary material layer.

15. The method according to claim 14, wherein When the package is removed from the plastic encapsulation mold, the external connection terminals are separated from the auxiliary material layer.

16. The method according to claim 12, wherein: Each of the plurality of chips includes an active surface and an inactive surface, the active surface faces the dummy chip, and the inactive surface faces the supporting substrate.

17. The method according to claim 16, wherein The plurality of chips include a plurality of first chips and a plurality of second chips, wherein the plurality of second chips are between the plurality of first chips and the dummy chip. Each of the plurality of first chips is offset along a first horizontal direction relative to any first chip vertically above the first chip, such that a first pad is exposed on the active surface of each of the plurality of first chips, and Each of the plurality of second chips is offset relative to any second chip vertically above the second chip in a second horizontal direction opposite to the first horizontal direction so that a second pad is exposed on the active surface of each of the plurality of second chips.

18. The method according to claim 17, wherein The bonding wires include a first bonding wire and a second bonding wire, The first bonding wire electrically connects the first pad of at least one of the plurality of first chips to the first redistribution layer, and The second bonding wire electrically connects the second pad of at least one of the plurality of second chips to the second redistribution layer.

19. The method according to claim 13, wherein The injection of the encapsulant is controlled by measuring the height of the dummy chip to form a desired thickness of the encapsulation layer.

20. The method according to claim 12, wherein The dummy chip is a heat sink for the plurality of chips.

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