A ferroelectric field effect transistor with wide window ferroelectric regulation hysteresis effect and a preparation method thereof

Abstract

The application relates to a ferroelectric field effect transistor with a wide-window ferroelectric regulation hysteresis effect and a preparation method thereof, which comprises a graphene layer, a thin dielectric layer, a two-dimensional ferroelectric AgInP2Se6 layer and a p-type two-dimensional semiconductor channel layer stacked on a substrate, source and drain electrodes are arranged at two ends of the p-type two-dimensional semiconductor channel layer, and a gate electrode is arranged on the graphene layer; the thin dielectric layer and the two-dimensional ferroelectric AgInP2Se6 layer are capacitively matched; under the condition that the source-drain voltage is certain, the gate voltage is scanned, the ferroelectric field effect transistor shows excellent ferroelectric current regulation characteristics, the ferroelectric window increases with the increase of the scanned gate voltage, when the scanning range of V gs is-4V, the window size is about 4V, and a wide ferroelectric window is presented.

Description

Technical Field

[0001] The present invention relates to the technical field of field effect tubes, and in particular to a ferroelectric field effect tube with a wide-window ferroelectrically controlled hysteresis effect and a preparation method thereof. Background Art

[0002] Ferroelectric materials, due to their many excellent electrical properties, have become one of the hottest research topics in solid-state electronics. Ferroelectric materials exhibit spontaneous polarization within a certain temperature range. This is due to the misalignment of the positive and negative charge centers in their crystal lattice. This allows them to generate an electric dipole moment even without an applied electric field, and this spontaneous polarization can change direction under the influence of an external electric field. Over the past few decades, research on two-dimensional materials, including graphene and boron nitride, has become a hot topic in materials science. These materials have attracted widespread attention due to their unique electronic structures and properties, and have shown great potential for application in fields such as nanoelectronics and optoelectronics. However, the application of traditional ferroelectric materials in devices has been limited, and two-dimensional ferroelectric materials have gradually emerged. Two-dimensional ferroelectric materials are two-dimensional materials that exhibit ferroelectric properties.

[0003] Therefore, people have tried to use ferroelectric materials as gate materials in field-effect transistors, and by applying an external electric field, they can control the source and leakage currents in the field-effect transistor. At the same time, because the saturation current of the field-effect transistor is directly proportional to the dielectric constant of the gate material, ferroelectric materials have a higher dielectric constant than the gate insulator materials in traditional field-effect transistors. Summary of the Invention

[0004] In response to the technical problems existing in the prior art, the primary purpose of the present invention is to provide a ferroelectric field effect transistor with a wide-window ferroelectrically controlled hysteresis effect and a preparation method thereof. Based on the two-dimensional ferroelectric material AgInP2Se6, the present invention constructs a ferroelectric control field effect transistor with at least four material layers of graphene layer-thin dielectric layer-two-dimensional ferroelectric AgInP2Se6 layer-p-type two-dimensional semiconductor channel layer. The ferroelectric control field effect transistor is applied to memory and has a wide ferroelectric window.

[0005] One aspect of the present invention is to provide a ferroelectric field effect transistor with a wide-window ferroelectrically controlled hysteresis effect, comprising a substrate, a graphene layer on the substrate, a thin dielectric layer on the graphene layer, a two-dimensional ferroelectric AgInP2Se6 layer on the thin dielectric layer, a p-type two-dimensional semiconductor channel layer on the two-dimensional ferroelectric AgInP2Se6 layer, a source and a drain at both ends of the p-type two-dimensional semiconductor channel layer, and a gate on the graphene layer;

[0006] Wherein, the capacitance between the thin dielectric layer and the two-dimensional ferroelectric AgInP2Se6 layer is matched.

[0007] One aspect of the present application is to provide a ferroelectric field effect transistor with wide window ferroelectric regulation hysteresis effect, comprising a substrate, a graphene layer on the substrate, a two-dimensional ferroelectric AgInP2Se6 layer on the graphene layer, a thin dielectric layer on the two-dimensional ferroelectric AgInP2Se6 layer, a p-type two-dimensional semiconductor channel layer on the thin dielectric layer, a source and a drain at both ends of the p-type two-dimensional semiconductor channel layer, and a gate on the graphene layer.

[0008] The thin dielectric layer and the two-dimensional ferroelectric AgInP2Se6 layer are capacitively matched.

[0009] One aspect of the present application is to provide a ferroelectric field effect transistor with wide window ferroelectric regulation hysteresis effect, comprising a substrate, a graphene layer on the substrate, a first thin dielectric layer on the graphene layer, a two-dimensional ferroelectric AgInP2Se6 layer on the first thin dielectric layer, a second thin dielectric layer on the two-dimensional ferroelectric AgInP2Se6 layer, a p-type two-dimensional semiconductor channel layer on the second thin dielectric layer, a source and a drain at both ends of the p-type two-dimensional semiconductor channel layer, and a gate on the graphene layer.

[0010] The first thin dielectric layer, the second thin dielectric layer and the two-dimensional ferroelectric AgInP2Se6 layer are capacitively matched.

[0011] Further, the thickness of the thin dielectric layer is 1-50 nm.

[0012] Further, the material of the thin dielectric layer is h-BN, Al2O3, HfO2, SiO2 or MoO3.

[0013] Further, the thickness of the two-dimensional ferroelectric AgInP2Se6 layer is 1-50 nm.

[0014] Further, the material of the p-type two-dimensional semiconductor channel layer is MoTe2, WSe2, Te or bP; and the thickness of the p-type two-dimensional semiconductor channel layer is 1-50 nm.

[0015] Further, the material of the thin dielectric layer is h-BN, and the material of the p-type two-dimensional semiconductor channel layer is MoTe2, when V gs The scanning range of V is -4 V, and the window is 4 V.

[0016] Further, the material of the source, the drain and the gate is a Gr / Au composite layer, the thickness of the Gr layer is 10 nm, and the thickness of the Au layer is 50 nm.

[0017] Further, the graphene layer, the thin dielectric layer, the two-dimensional ferroelectric AgInP2Se6 layer and the p-type two-dimensional semiconductor channel layer are obtained by the following transfer method as target materials.

[0018] A certain area of PDMS flexible material is taken, the soft layer is pasted on the adhesive tape full of target materials after tearing off the soft layer film, the PDMS is taken out after pressing the hard layer for a certain time, the target material with the target thickness area is found, and the target material with the target thickness area is transferred to the target area.

[0019] The application further provides the application of the ferroelectric regulating field effect transistor in a memory.

[0020] Compared with the prior art, the application has at least the following beneficial effects:

[0021] The application selects a thin dielectric layer matched with the two-dimensional ferroelectric AgInP2Se6 layer in capacitance, and constructs a four-layer ferroelectric field effect transistor of ferroelectric regulation hysteresis effect containing a graphene layer / thin dielectric layer / two-dimensional ferroelectric AgInP2Se6 layer / p-type two-dimensional semiconductor channel layer, wherein the two-dimensional ferroelectric AgInP2Se6 layer is used for the first time to realize the storage function, the thin dielectric layer is matched with the two-dimensional ferroelectric AgInP2Se6 layer in capacitance, the ferroelectric regulation hysteresis effect is realized, the leakage current is reduced, the surface defects are passivated, a wide ferroelectric window is obtained, and the overall performance is improved, and the ferroelectric field effect transistor of the application is suitable for application in a memory. ds In a certain case, the device is scanned in different ranges of V gs , and the ferroelectric window continuously increases with the increase of the range of V gs . In an embodiment of the application, when the scanning range of V gs is-4V, the window size is about 4V. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 FIG. 1 is a schematic diagram of the principle structure of the field effect transistor of Example 1.

[0023] Figure 2 FIG. 2 is an optical image of the field effect transistor of Example 1.

[0024] Figure 3 In FIG. 3, (a) is an AgInP2Se6 Raman spectrum detection diagram of the field effect transistor of Example 1; and (b) is a MoTe2 Raman spectrum detection diagram of the field effect transistor of Example 1.

[0025] Figure 4 In FIG. 4, (a) is a V dsFigure (a) is a linear plot of the transfer characteristics of the field effect transistor of Example 1 at Vg = 0.2 V; Figure (b) is a log plot of the transfer characteristics of the field effect transistor of Example 1 at Vg = 0.2 V; Figure (c) is a linear plot of the transfer characteristics of the field effect transistor of Example 1 at Vg = -0.2 V; and Figure (d) is a log plot of the transfer characteristics of the field effect transistor of Example 1 at Vg = -0.2 V. ds Figure (a) is a linear plot of the transfer characteristics of the field effect transistor of Example 1 at Vg = 0.2 V; Figure (b) is a log plot of the transfer characteristics of the field effect transistor of Example 1 at Vg = 0.2 V; Figure (c) is a linear plot of the transfer characteristics of the field effect transistor of Example 1 at Vg = -0.2 V; and Figure (d) is a log plot of the transfer characteristics of the field effect transistor of Example 1 at Vg = -0.2 V. ds Figure (a) is a linear plot of the transfer characteristics of the field effect transistor of Example 1 at Vg = 0.2 V; Figure (b) is a log plot of the transfer characteristics of the field effect transistor of Example 1 at Vg = 0.2 V; Figure (c) is a linear plot of the transfer characteristics of the field effect transistor of Example 1 at Vg = -0.2 V; and Figure (d) is a log plot of the transfer characteristics of the field effect transistor of Example 1 at Vg = -0.2 V. ds Figure (a) is a linear plot of the transfer characteristics of the field effect transistor of Example 1 at Vg = 0.2 V; Figure (b) is a log plot of the transfer characteristics of the field effect transistor of Example 1 at Vg = 0.2 V; Figure (c) is a linear plot of the transfer characteristics of the field effect transistor of Example 1 at Vg = -0.2 V; and Figure (d) is a log plot of the transfer characteristics of the field effect transistor of Example 1 at Vg = -0.2 V. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings of the present application. The described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application. In the following embodiments, the experimental methods are conventional methods unless otherwise specified, and the reagents and materials are commercially available unless otherwise specified.

[0027] Spatial relative terms such as "under", "below", "lower", "on", "above", "upper" and the like, are used herein for explaining the position of an element relative to the second element. These terms are intended to encompass different orientations of the device, except for those different orientations which are explicitly different from those shown in the figures.

[0028] In addition, terms such as "first", "second" and the like are used to describe various elements, layers, regions, sections and the like, and are not intended to be limiting. The use of "have", "has", "including", "including", "including" and the like is an open term, indicating the presence of the stated element or feature, but not excluding additional elements or features. Unless the context clearly indicates otherwise.

[0029] In one aspect, the present application provides a ferroelectric field effect transistor with a wide window ferroelectric regulation hysteresis effect, which includes a substrate, such as a SiO2 / Si substrate. In one embodiment, a graphene layer, a thin dielectric layer, a two-dimensional ferroelectric AgInP2Se6 layer, and a p-type two-dimensional semiconductor channel layer are sequentially arranged on the SiO2 / Si substrate. In another embodiment, a graphene layer, a two-dimensional ferroelectric AgInP2Se6 layer, a thin dielectric layer, and a p-type two-dimensional semiconductor channel layer are sequentially arranged on the SiO2 / Si substrate. In another embodiment, a graphene layer, a first thin dielectric layer, a two-dimensional ferroelectric AgInP2Se6 layer, a second thin dielectric layer, and a p-type two-dimensional semiconductor channel layer are sequentially arranged on the SiO2 / Si substrate.

[0030] The thickness of the graphene layer is 1-20 nm. In an embodiment, the graphene layer is transferred onto the SiO2 layer using a mechanical exfoliation method. Specifically, the SiO2 / Si substrate is first rinsed with anhydrous ethanol and then soaked with distilled water to ensure that the surface of the substrate is free of dust and other impurities; a PDMS flexible material with a certain area size, for example, 0.5 cm x 0.5 cm, is cut, and after the soft film is torn off, it is laid on the graphene-coated tape for 15 seconds to obtain a large amount of few-layer graphene, and then few-layer graphene with a suitable area and a thickness of 1-20 nm and a relatively flat surface is selected. Next, using a transfer platform, the selected graphene is transferred to the SiO2 / Si substrate, ensuring that its position is at the center of the substrate to facilitate subsequent photolithography, and the material is attached and the temperature of the heating table is adjusted to 50°C, and the transfer is completed after 1 minute of continuous heating.

[0031] In an embodiment, a thin dielectric layer is disposed on the graphene layer, and the thickness of the thin dielectric layer is 1-50 nm. The thin dielectric layer is, for example, h-BN, Al2O3, HfO2, SiO2, or MoO3, etc. The thin dielectric layer is capacitively matched with the two-dimensional ferroelectric AgInP2Se6 layer, which can reduce the leakage current. In a preferred embodiment, the thin dielectric layer is h-BN. Similarly, the h-BN is transferred onto the graphene layer using a mechanical exfoliation method. Specifically, a PDMS flexible material with a certain area size, for example, 0.5 cm x 0.5 cm, is cut, and after the soft film is torn off, it is attached to the h-BN-coated tape, and the h-BN is pressed for 15 seconds, and then the PDMS is taken out, and the side with h-BN is placed upward, and under an optical microscope, h-BN with a thickness of 1-50 nm and a relatively flat surface is found. Using a transfer platform, the selected h-BN is transferred to the graphene, and the material is attached and the temperature of the heating table is adjusted to 50°C, and the transfer is completed after 1 minute of continuous heating.

[0032] In an embodiment, the two-dimensional ferroelectric AgInP2Se6 layer is disposed on the thin dielectric layer, and the thickness of the two-dimensional ferroelectric AgInP2Se6 layer is 1-50 nm. Similarly, the two-dimensional ferroelectric AgInP2Se6 layer is transferred to the thin dielectric layer by using a mechanical exfoliation method. Specifically, a PDMS flexible material with a certain area size, for example, 0.5 cm x 0.5 cm, is cut, and after the soft layer film is torn off, the soft layer is attached to the AgInP2Se6 tape, and after the hard layer is pressed for 15 seconds, the PDMS is taken out, and the side with the AgInP2Se6 is placed upward. Under an optical microscope, the AgInP2Se6 with a thickness of 1-50 nm and a relatively flat material surface is found. The selected AgInP2Se6 is transferred to the h-BN by using a transfer platform, the material is attached, and the temperature of the heating table is adjusted to 50°C. After 1 minute, the transfer is completed. When the AgInP2Se6 layer is transferred, it should be ensured that there is a large area of overlap with the thin dielectric layer, and the surface of the non-overlapping part on the graphene is reserved for photolithography of the electrode.

[0033] In an embodiment, the p-type two-dimensional semiconductor channel layer is disposed on the two-dimensional ferroelectric AgInP2Se6 layer, and the thickness of the p-type two-dimensional semiconductor channel layer is 1-50 nm. The material of the p-type two-dimensional semiconductor channel layer is MoTe2, WSe2, Te, or bP (black phosphorus). In a preferred embodiment, the p-type two-dimensional semiconductor channel layer is selected from MoTe2 material. Similarly, the MoTe2 material layer is transferred to the thin dielectric layer by using a mechanical exfoliation method. Specifically, a PDMS flexible material with a certain area size, for example, 0.5 cm x 0.5 cm, is cut, and after the soft layer film is torn off, the soft layer is attached to the MoTe2 material layer tape, and after the hard layer is pressed for 30 seconds, the PDMS is taken out, and the side with the MoTe2 is placed upward. Under an optical microscope, the MoTe2 material layer with a thickness of 1-50 nm and a relatively flat material surface is found. The selected MoTe2 material layer is transferred to the two-dimensional ferroelectric AgInP2Se6 layer by using a transfer platform, the material is attached, and the temperature of the heating table is adjusted to 50°C. After 1 minute, the transfer is completed. When the MoTe2 material layer is transferred, it should be ensured that there is a large area of overlap with the AgInP2Se6 layer while not contacting the graphene layer at the bottom, and the surface of the non-overlapping part on the MoTe2 is reserved for photolithography of the electrode.

[0034] In another embodiment, the two-dimensional ferroelectric AgInP2Se6 layer is disposed on the graphene layer, the thin dielectric layer is disposed on the two-dimensional ferroelectric AgInP2Se6 layer, and the p-type two-dimensional semiconductor channel layer is disposed on the two-dimensional ferroelectric AgInP2Se6 layer. The transfer method of each material layer is the same as the transfer method of the above material layer, which is not described here.

[0035] In another embodiment, a first thin dielectric layer is disposed on the graphene layer, a two-dimensional ferroelectric AgInP2Se6 layer is disposed on the first thin dielectric layer, a second thin dielectric layer is disposed on the two-dimensional ferroelectric AgInP2Se6 layer, and a p-type two-dimensional semiconductor channel layer is disposed on the second thin dielectric layer. The first thin dielectric layer and the second thin dielectric layer are made of the same material, and each has a thickness of 1-50 nm. The thin dielectric layer is, for example, h-BN, Al2O3, HfO2, SiO2, or MoO3, etc. The transfer method of each material layer is the same as the transfer method of the material layer described above, and will not be described here again.

[0036] In an embodiment, after the transfer of the material layers described above is completed, the prepared ferroelectric field effect transistor is placed in a spin coater, a rubber bulb dropper is used to uniformly drop photoresist on the surface of the silicon wafer, and the running steps of the spin coater are set. After the spin coating is completed, the silicon wafer is placed on a heating table to perform photoresist baking, and the temperature is set to 100°C and heated for 4 minutes. The silicon wafer after photoresist baking is placed in a photoetching machine, and electrodes are photoetched on both ends of MoTe2 as source and drain electrodes. An electrode is photoetched on one end of graphene as a gate electrode and cannot be in contact with MoTe2. After photoetching is completed, development is performed, and then electron beam evaporation is performed on the silicon wafer after development. A Gr layer with a thickness of 10 nm and an Au layer with a thickness of 50 nm are evaporated, the evaporation rate of chromium is 0.1 nm / min, the evaporation rate of Au is 0.1 nm / min when the thickness of Au is 0-20 nm, and the evaporation rate of Au is 0.3 nm / min when the thickness of Au is 20-50 nm.

[0037] After evaporation is completed, the silicon wafer is immersed in an acetone solution, a rubber bulb dropper is used to rinse off the gold on the silicon wafer, and then distilled water is immediately used to rinse it, and then the surface residual distilled water is blown away with an air gun.

[0038] Finally, under an optical microscope, the length and width data of the electrodes are measured and the area is calculated. The silicon wafer is placed on a heating table in a glove box, the temperature is set to 100°C-200°C, and the duration is 20 minutes, and an AgInP2Se6 ferroelectric field effect transistor is prepared. The optical image of the ferroelectric field effect transistor is as shown in Figure 2 Figure 3 The Raman spectrum detection diagram of the AgInP2Se6 layer and the Raman spectrum detection diagram of the MoTe2 material layer obtained by transferring in the preparation process of the ferroelectric field effect transistor of the present application clearly show the typical Raman peaks of the two materials, and the peak value is sharp, showing high crystal quality.

[0039] The graphene / h-BN / AgInP2Se6 / MoTe2 ferroelectric field effect transistor prepared above is taken, I-V electrical testing is performed on a probe station, and the gate voltage is scanned under source-drain voltage V ds = 0.2V and -0.2V, as shown in Figure 4 ​As shown, the ferroelectric field effect transistor exhibits excellent ferroelectric current regulation characteristics, and its ferroelectric window increases with the increase of the scanning gate voltage, and when the scanning range of V gs is the largest (-4V), the window size is about 4V. The ferroelectric field effect transistor of the present application helps to promote the further development of ferroelectric materials in the field of field effect transistors.

[0040] The above embodiments are the preferred embodiments of the present application, but the embodiments of the present application are not limited to the above embodiments, and any changes, modifications, substitutions, combinations, simplifications made without departing from the spirit and principles of the present application should be equivalent replacement methods, and are all included in the protection scope of the present application.

Claims

1. A ferroelectric field effect transistor with a wide window ferroelectrically controlled hysteresis effect, characterized in that: The device comprises a substrate, a graphene layer on the substrate, a thin dielectric layer on the graphene layer, a two-dimensional ferroelectric AgInP2Se6 layer on the thin dielectric layer, a p-type two-dimensional semiconductor channel layer on the two-dimensional ferroelectric AgInP2Se6 layer, a source electrode and a drain electrode at both ends of the p-type two-dimensional semiconductor channel layer, and a gate electrode on the graphene layer; Wherein, the capacitance between the thin dielectric layer and the two-dimensional ferroelectric AgInP2Se6 layer is matched.

2. A ferroelectric field effect transistor with a wide window ferroelectrically controlled hysteresis effect, characterized in that: The device comprises a substrate, a graphene layer on the substrate, a two-dimensional ferroelectric AgInP2Se6 layer on the graphene layer, a thin dielectric layer on the two-dimensional ferroelectric AgInP2Se6 layer, a p-type two-dimensional semiconductor channel layer on the thin dielectric layer, a source and a drain at both ends of the p-type two-dimensional semiconductor channel layer, and a gate on the graphene layer; Wherein, the capacitance between the thin dielectric layer and the two-dimensional ferroelectric AgInP2Se6 layer is matched.

3. A ferroelectric field effect transistor with a wide window ferroelectrically controlled hysteresis effect, characterized in that: The device comprises a substrate, a graphene layer on the substrate, a first thin dielectric layer on the graphene layer, a two-dimensional ferroelectric AgInP2Se6 layer on the first thin dielectric layer, a second thin dielectric layer on the two-dimensional ferroelectric AgInP2Se6 layer, a p-type two-dimensional semiconductor channel layer on the second thin dielectric layer, a source and a drain at both ends of the p-type two-dimensional semiconductor channel layer, and a gate on the graphene layer; The capacitance between the first thin dielectric layer, the second thin dielectric layer and the two-dimensional ferroelectric AgInP2Se6 layer is matched.

4. The ferroelectric field effect transistor according to any one of claims 1 to 3, characterized in that: The thickness of the thin dielectric layer is 1-50 nm.

5. The ferroelectric field effect transistor according to claim 4, characterized in that: The material of the thin dielectric layer is h-BN, Al2O3, HfO2, SiO2 or MoO3.

6. The ferroelectric field effect transistor according to any one of claims 1 to 3 and 5, characterized in that: The thickness of the two-dimensional ferroelectric AgInP2Se6 layer is 1 to 50 nm.

7. The ferroelectric field effect transistor according to any one of claims 1 to 3 and 5, characterized in that: The material of the p-type two-dimensional semiconductor channel layer is MoTe2, WSe2, Te or bP (black phosphorus); the thickness of the p-type two-dimensional semiconductor channel layer is 1 to 50 nm.

8. The ferroelectric field effect transistor according to claim 7, characterized in that: The source electrode, the drain electrode and the gate electrode are made of a Gr / Au composite layer, the thickness of the Gr layer is 10 nm, and the thickness of the Au layer is 50 nm.

9. The ferroelectric field effect transistor according to any one of claims 1 to 3, 5 and 8, characterized in that: The graphene layer, the thin dielectric layer, the two-dimensional ferroelectric AgInP2Se6 layer and the p-type two-dimensional semiconductor channel layer are used as target materials and are obtained by the following transfer method: Take a certain area of ​​PDMS flexible material, tear off the soft layer film and stick the soft layer on the tape covered with the target material. After pressing the hard layer for a certain time, take out the PDMS and place it with the side covered with the target material facing up. Find the target material in the target thickness area, transfer the target material in the target thickness area to the target area, stick the material tightly and heat it to 50℃~60℃.

10. Use of the ferroelectric field effect transistor according to any one of claims 1 to 9 in a memory.

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