Control Circuit and Control Method, Power Conversion Circuit and Electronic Device

Abstract

The present application discloses a control circuit, a control method, a power conversion circuit and an electronic device, relating to the technical field of electronic circuits. The control circuit outputs a first pulse width modulation signal and a second pulse width modulation signal for controlling a switched-capacitor converter. The control circuit includes a signal generation module and a signal setting module. The signal generation module outputs a first indication signal when the output voltage drops to a first preset voltage, and outputs a second indication signal when the output voltage rises to a second preset voltage. When the switched-capacitor converter is in the charge pump operating mode, the signal setting module sets the first pulse width modulation signal and the second pulse width modulation signal to signals with a duty cycle of 50%. When the switched-capacitor converter is in the pulse frequency modulation operating mode, if the first indication signal is received, the first pulse width modulation signal is set to a high level, and if the second indication signal is received, the second pulse width modulation signal is set to a high level. By the above method, the voltage conversion efficiency can be improved.

Description

Technical Field

[0001] Embodiments of the present application relate to the technical field of electronic circuits, and particularly to a control circuit and a control method, a power conversion circuit, and an electronic device. Background Art

[0002] Currently, a switched-capacitor converter based on a charge pump architecture has been widely used in the field of consumer electronics, such as in smartphones to achieve fast charging. This switched-capacitor converter is used to achieve a step-down ratio of J:1, where J is an integer greater than 1. For example, Figure 1 An exemplary circuit structure of the switched-capacitor converter when J = 2 is shown.

[0003] For a switched-capacitor converter, a control circuit is usually used to control it to alternately operate in a charge pump (CP) operating mode and a pulse skipping (PS) operating mode, so as to achieve a ratio of the input voltage to the output voltage of the switched-capacitor converter of J:1.

[0004] However, in the above control method, since a fixed clock signal needs to be used, the power consumption will be relatively large, and then the proportion of the power consumption of the control circuit in the output power of the switched-capacitor converter is very high when the switched-capacitor converter is in the pulse skipping operating mode, resulting in a low overall voltage conversion efficiency. Summary of the Invention

[0005] Embodiments of the present application provide a control circuit and a control method, a power conversion circuit, and an electronic device, which can improve the voltage conversion efficiency.

[0006] In a first aspect, an embodiment of the present application provides a control circuit for outputting complementary first pulse width modulation signals and second pulse width modulation signals for controlling switching tubes in a switched-capacitor converter, where the switched-capacitor converter is used to convert an input voltage into an output voltage, and the ratio of the output voltage to the input voltage is 1:N, where N is an integer greater than 1. The control circuit includes:

[0007] A signal generation module, which inputs the input voltage and the output voltage, and is configured to output a first indication signal when the output voltage drops to a first preset voltage and output a second indication signal when the output voltage rises to a second preset voltage when the switched-capacitor converter is in a pulse frequency modulation operating mode, where the first preset voltage and the second preset voltage are both less than 1 / N of the input voltage, and the first preset voltage is less than the second preset voltage;

[0008] A signal setting module, connected to the signal generation module, is configured to set the first pulse width modulation signal and the second pulse width modulation signal to signals with a duty cycle of 50% when the switched-capacitor converter is in the charge pump operating mode, and is configured to set the first pulse width modulation signal to a high level if the first indication signal is received when the switched-capacitor converter is in the pulse frequency modulation operating mode, and set the second pulse width modulation signal to a high level if the second indication signal is received.

[0009] In one or more embodiments, the control circuit further includes:

[0010] A mode switching module, respectively connected to the signal generation module and the signal setting module, is configured to switch the operating mode of the switched-capacitor converter to the charge pump operating mode when the switched-capacitor converter is in the pulse frequency modulation operating mode and the duration of receiving the first indication signal is greater than a first preset duration, and is configured to switch the operating mode of the switched-capacitor converter to the pulse frequency modulation operating mode when the switched-capacitor converter is in the charge pump operating mode and the duration of receiving the second indication signal is greater than a second preset duration.

[0011] In one or more embodiments, the signal generation module includes a first comparator, a second comparator and a first latch;

[0012] The non-inverting input terminal of the first comparator inputs the first preset voltage, the inverting input terminal of the first comparator inputs the output voltage, the output terminal of the first comparator is connected to the set terminal of the first latch, the inverting input terminal of the second comparator inputs the second preset voltage, the non-inverting input terminal of the second comparator inputs the output voltage, the output terminal of the second comparator is connected to the reset terminal of the first latch, the non-inverting output terminal of the first latch is used to output the first indication signal, and the inverting output terminal of the first latch is used to output the second indication signal.

[0013] In one or more embodiments, the control circuit further includes:

[0014] A pulse width setting module, connected to the signal generation module, is configured to output a first pulse to the signal generation module when the signal generation module outputs the first indication signal, wherein the pulse width of the first pulse is a first duration;

[0015] The signal generation module is further configured to output the second indication signal after the first pulse ends and the output voltage has risen to the second preset voltage.

[0016] In one or more embodiments, the signal generation module further includes a first AND gate, and the pulse width setting module includes a first single flip-flop and a first NOT gate;

[0017] The input end of the first single flip-flop is connected to the in-phase output end of the first latch, the output end of the first single flip-flop is connected to the input end of the first NOT gate, the output end of the first NOT gate is connected to the second input end of the first AND gate, the first input end of the first AND gate is connected to the output end of the second comparator, and the output end of the first AND gate is connected to the reset end of the first latch.

[0018] In one or more embodiments, the control circuit further includes:

[0019] A frequency setting module, connected to the signal generation module, configured to determine the switching frequency of the switching transistor in the switched-capacitor converter based on the first indication signal and the second indication signal, and output a frequency setting signal when the switching frequency is less than or equal to a preset frequency;

[0020] The signal generation module is further configured to output the first indication signal when receiving the frequency setting signal and the output voltage is less than the first preset voltage.

[0021] In one or more embodiments, the preset frequency is configured to be the switching frequency of the switching transistor in the switched-capacitor converter when the switched-capacitor converter is in the charge pump operating mode.

[0022] In one or more embodiments, the signal generation module further includes a second AND gate, and the frequency setting module includes a first OR gate, a first switch, a second switch, a first current source, a second single flip-flop, a first capacitor and a third comparator;

[0023] The first input end of the first OR gate is connected to the in-phase output end of the first latch, the second input end of the first OR gate is connected to the anti-phase output end of the first latch, the output end of the first OR gate outputs a signal for controlling the first switch, the first switch is connected between the first current source and the in-phase input end of the third comparator, the second switch is connected between the in-phase input end of the third comparator and the ground, the first capacitor is connected in parallel with the second switch, the anti-phase input end of the third comparator inputs a voltage corresponding to the preset frequency, the output end of the third comparator is connected to the first input end of the second AND gate, the second input end of the second AND gate is connected to the output end of the first comparator, and the output end of the second AND gate is connected to the set end of the first latch.

[0024] In one or more embodiments, the mode switching module is further configured to: when the switched-capacitor converter is in the pulse frequency modulation operating mode, and the duration of receiving the first indication signal is greater than a first preset duration, and the difference between the duration of receiving the first indication signal and half of the first switching period is less than a first preset difference, switch the operating mode of the switched-capacitor converter to the charge pump operating mode, where the first switching period is the switching period of the switching transistor in the switched-capacitor converter when the switched-capacitor converter is in the charge pump operating mode.

[0025] In one or more embodiments, the mode switching module is further configured to: when the switched-capacitor converter is in the charge pump operating mode, and the duration of receiving the second indication signal is greater than a second preset duration, and after M first switching periods have elapsed after the output voltage is equal to the second preset voltage, switch the operating mode of the switched-capacitor converter to the pulse frequency modulation operating mode, where the first switching period is the switching period of the switching transistor in the switched-capacitor converter when the switched-capacitor converter is in the charge pump operating mode, and M is an integer greater than or equal to 1.

[0026] In one or more embodiments, the mode switching module includes a third AND gate, a fourth AND gate, a second NOT gate, a third NOT gate, a third switch, a fourth switch, a fifth switch, a sixth switch, a second capacitor, a third capacitor, a second current source, a third current source, a fourth comparator, a fifth comparator, and a second latch;

[0027] The first input terminal of the third AND gate inputs the first indication signal, the second input terminal of the third AND gate inputs a third indication signal indicating that the switched-capacitor converter is in the pulse frequency modulation operating mode, the output terminal of the third AND gate outputs a signal for controlling the third switch, the output terminal of the third AND gate is further connected to the input terminal of the second NOT gate, the output terminal of the second NOT gate outputs a signal for controlling the fourth switch, the third switch is connected between the second current source and the non-inverting input terminal of the fourth comparator, the second capacitor is connected between the non-inverting input terminal of the fourth comparator and the ground, the fourth switch is connected in parallel with the second capacitor, the inverting input terminal of the fourth comparator inputs a voltage corresponding to the first preset duration, and the output terminal of the fourth comparator is connected to the set terminal of the second latch;

[0028] The first input terminal of the fourth AND gate receives the second indication signal, the second input terminal of the fourth AND gate receives a fourth indication signal indicating that the switched-capacitor converter is in the charge pump operating mode, the output terminal of the fourth AND gate outputs a signal for controlling the fifth switch, the output terminal of the fourth AND gate is further connected to the input terminal of the third NOT gate, the output terminal of the third NOT gate outputs a signal for controlling the sixth switch, the fifth switch is connected between the third current source and the non-inverting input terminal of the fifth comparator, the third capacitor is connected between the non-inverting input terminal of the fifth comparator and the ground, the fifth switch is connected in parallel with the third capacitor, the inverting input terminal of the fifth comparator receives a voltage corresponding to the second preset duration, the output terminal of the fifth comparator is connected to the reset terminal of the second latch, the non-inverting output terminal of the second latch outputs the fourth indication signal, and the inverting output terminal of the second latch outputs the third indication signal.

[0029] In one or more embodiments, the signal setting module includes a second OR gate, a third OR gate, a fourth OR gate, a fifth OR gate, a seventh switch, an eighth switch, a fourth capacitor, a fifth capacitor, a fourth current source, a fifth current source, a sixth comparator, a seventh comparator, a third single flip-flop, a fourth single flip-flop, and a third latch.

[0030] The first input terminal of the second OR gate is connected to the first input terminal of the third OR gate and receives a third indication signal indicating that the switched-capacitor converter is in the pulse frequency modulation operating mode. The second input terminal of the second OR gate is respectively connected to the non-inverting output terminal of the third latch and a switching transistor in the switched-capacitor converter, and the non-inverting output terminal of the third latch outputs the first pulse width modulation signal. The output terminal of the second OR gate outputs a signal for controlling the seventh switch. The seventh switch is connected between the non-inverting input terminal of the sixth comparator and the ground. The fourth capacitor is connected in parallel with the seventh switch. The non-inverting input terminal of the sixth comparator is further connected to the fourth current source. The inverting input terminal of the sixth comparator receives a third preset voltage. The output terminal of the sixth comparator is connected to the first input terminal of the fourth OR gate. The second input terminal of the fourth OR gate is connected to the output terminal of the third single flip-flop. The input terminal of the third single flip-flop receives the first indication signal. The output terminal of the fourth OR gate is connected to the set terminal of the third latch.

[0031] The second input terminal of the third OR gate is respectively connected to the inverted output terminal of the third latch and the switching transistor in the switched-capacitor converter, and the inverted output terminal of the third latch outputs the second pulse-width modulation signal. The output terminal of the third OR gate outputs a signal for controlling the eighth switch. The eighth switch is connected between the non-inverting input terminal of the seventh comparator and the ground. The fifth capacitor is connected in parallel with the eighth switch. The non-inverting input terminal of the seventh comparator is further connected to the fifth current source. The inverting input terminal of the seventh comparator inputs the third preset voltage. The output terminal of the seventh comparator is connected to the first input terminal of the fifth OR gate. The second input terminal of the fifth OR gate is connected to the output terminal of the fourth single flip-flop. The input terminal of the fourth single flip-flop inputs the second indication signal. The output terminal of the fifth OR gate is connected to the reset terminal of the third latch.

[0032] In a second aspect, an embodiment of the present application provides a power conversion circuit, including a switched-capacitor converter and the control circuit as described above. The control circuit is connected to the switched-capacitor converter;

[0033] The control circuit outputs complementary first and second pulse-width modulation signals;

[0034] The switched-capacitor converter is configured to, in response to the first pulse-width modulation signal, control a part of the switching transistors in the switched-capacitor converter to conduct during a part of the switching period of the switched-capacitor converter, so that the input voltage of the switched-capacitor converter charges the energy storage capacitor in the switched-capacitor converter;

[0035] The switched-capacitor converter is further configured to, in response to the second pulse-width modulation signal, control another part of the switching transistors in the switched-capacitor converter to conduct during another part of the switching period of the switched-capacitor converter, so that the energy storage capacitor discharges to the output terminal of the switched-capacitor converter.

[0036] In a third aspect, an embodiment of the present application provides a control method for controlling the conduction or cutoff of the switching transistors in a switched-capacitor converter. The switched-capacitor converter is used to convert an input voltage into an output voltage, and the ratio of the input voltage to the output voltage is N:1, where N is an integer greater than 1. The control method includes:

[0037] When the switched-capacitor converter is in the pulse frequency modulation operating mode, perform the following steps:

[0038] When the output voltage drops to the first preset voltage, control a part of the switching transistors in the switched-capacitor converter to conduct, so that the energy storage capacitor in the switched-capacitor converter discharges to the output terminal of the switched-capacitor converter;

[0039] When the output voltage rises to a second preset voltage, control another part of the switching tubes in the switched-capacitor converter to conduct, so that the input voltage of the switched-capacitor converter charges the energy storage capacitor, where the first preset voltage and the second preset voltage are both less than 1 / N of the input voltage, and the first preset voltage is less than the second preset voltage;

[0040] When the output voltage has not risen to the second preset voltage after a first preset duration from the moment when the output voltage drops to the first preset voltage, switch the operating mode of the switched-capacitor converter to the charge pump operating mode.

[0041] In one or more embodiments, the method further includes:

[0042] When the switched-capacitor converter is in the charge pump operating mode, perform the following steps:

[0043] Control the switching tubes in the switched-capacitor converter to alternately conduct and turn off with a duty cycle of 50%;

[0044] When the output voltage has not dropped to the first preset voltage after a duration greater than a second preset duration from the moment when the output voltage rises to the second preset voltage, switch the operating mode of the switched-capacitor converter to the pulse frequency modulation operating mode.

[0045] In one or more embodiments, the method further includes:

[0046] When the switched-capacitor converter is in the pulse frequency modulation operating mode, control the duration of each discharge of the energy storage capacitor in the switched-capacitor converter to the output terminal to be greater than or equal to a first duration.

[0047] In one or more embodiments, the method further includes:

[0048] When the switched-capacitor converter is in the pulse frequency modulation operating mode, control the switching frequency of the switching tubes in the switched-capacitor converter to be less than or equal to a preset frequency.

[0049] In one or more embodiments, the preset frequency is configured as: when the switched-capacitor converter is in the charge pump operating mode, the switching frequency of the switching tubes in the switched-capacitor converter.

[0050] In one or more embodiments, the difference between the first preset duration and half of the first switching period is less than a first preset difference, where the first switching period is the switching period of a switching transistor in the switched-capacitor converter when the switched-capacitor converter is in a charge pump operating mode, and the first preset duration is less than the first switching period.

[0051] In one or more embodiments, the second preset duration is greater than M first switching periods, where M is an integer greater than or equal to 1.

[0052] Fourthly, an embodiment of the present application provides an electronic device, including the power conversion circuit as described above.

[0053] The beneficial effects of the present application are as follows: The control circuit in the embodiment of the present application is configured to output complementary first and second pulse width modulation signals for controlling a switching transistor in a switched-capacitor converter. The switched-capacitor converter is configured to convert an input voltage into an output voltage, and the ratio of the output voltage to the input voltage is 1:N, where N is an integer greater than 1. The control circuit includes a signal generation module and a signal setting module. The signal generation module inputs the input voltage and the output voltage, and is configured to output a first indication signal when the output voltage drops to a first preset voltage and output a second indication signal when the output voltage rises to a second preset voltage when the switched-capacitor converter is in a pulse frequency modulation operating mode, where both the first preset voltage and the second preset voltage are less than 1 / N of the input voltage, and the first preset voltage is less than the second preset voltage. The signal setting module is configured to set the first and second pulse width modulation signals to signals with a duty cycle of 50% when the switched-capacitor converter is in a charge pump operating mode, and is configured to set the first pulse width modulation signal to a high level if the first indication signal is received and set the second pulse width modulation signal to a high level if the second indication signal is received when the switched-capacitor converter is in a pulse frequency modulation operating mode. Through the above method, the control process of the switched-capacitor converter is realized to achieve a ratio of the output voltage to the input voltage of 1:N, and in this process, it is not necessary to use a fixed clock signal as in the related art, which is beneficial to improving the voltage conversion efficiency. Description of the Drawings

[0054] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplary illustrations are not intended to limit the embodiments. Elements with the same reference numerals in the drawings represent similar elements.

[0055] Figure 1 is a schematic circuit diagram of a switched-capacitor converter and a controller in the related art;

[0056] Figure 2 is Figure 1Schematic diagram of each signal in the circuit structure shown;

[0057] Figure 3 Schematic diagram of the composition block diagram of the control circuit and the switched-capacitor converter provided by an embodiment of the present application Figure 1 ;

[0058] Figure 4 Schematic diagram of the composition block diagram of the control circuit and the switched-capacitor converter provided by an embodiment of the present application Figure 2 ;

[0059] Figure 5 Schematic diagram of the circuit structure of the signal generation module provided by an embodiment of the present application;

[0060] Figure 6 Schematic diagram of the circuit structure of the signal setting module provided by an embodiment of the present application;

[0061] Figure 7 When the switched-capacitor converter is in the charge pump operating mode Figure 6 Simplified circuit structure of the circuit structure shown;

[0062] Figure 8 Is Figure 7 Schematic diagram of each signal in the circuit structure shown;

[0063] Figure 9 When the switched-capacitor converter is in the pulse frequency modulation operating mode Figure 6 Schematic diagram of each signal in the circuit shown;

[0064] Figure 10 Schematic diagram of the circuit structure of the mode switching module provided by an embodiment of the present application;

[0065] Figure 11 Is provided by an embodiment of the present application by Figure 5 , Figure 6 And Figure 10 Schematic diagram of each signal in the control circuit composed of the circuits shown;

[0066] Figure 12 Schematic diagram of the composition block diagram of the control circuit and the switched-capacitor converter provided by an embodiment of the present application Figure 3 ;

[0067] Figure 13 Is with Figure 12 Schematic diagram of the circuit structure corresponding to the signal generation module and the pulse width setting module shown;

[0068] Figure 14 Schematic diagram of the composition block diagram of the control circuit and the switched-capacitor converter provided by an embodiment of the present application Figure 4 ;

[0069] Figure 15 is related to Figure 14 a schematic diagram of a circuit structure corresponding to the signal generation module, pulse width setting module, and frequency setting module shown;

[0070] Figure 16 is a schematic diagram of each signal in the control circuit composed of the circuits shown by Figure 6 , Figure 10 and Figure 15 provided in an embodiment of the present application;

[0071] Figure 17 is a schematic diagram of a block diagram of the power conversion circuit provided in an embodiment of the present application;

[0072] Figure 18 is a flowchart of the control method provided in an embodiment of the present application;

[0073] Figure 19 is a flowchart of the steps further included in the control method provided in an embodiment of the present application except for the steps shown by Figure 18 ; Detailed implementation manners

[0074] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and detailedly described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0075] It should be noted that when an element is expressed as "connected" to another element, it can be directly connected to the other element, or there can be one or more intermediate elements therebetween.

[0076] In addition, the technical features involved in the various embodiments of the present application described below can be combined with each other as long as there is no conflict between them.

[0077] Please refer to Figure 1 , Figure 1 which is a schematic diagram of a circuit structure of a switching capacitor converter and a controller in the related art. As shown in Figure 1 , the switching capacitor converter 200 is a switching capacitor converter with a step-down ratio of 2:1, and includes a voltage input terminal VI1, a voltage output terminal VO1, switching transistors 201, 202, 203, 204, capacitors 205, 206, and 207.

[0078] Among them, the capacitor 206 is connected between the voltage input terminal VI1 and the ground; the switching transistors 201, 202, 203, and 204 are connected in series between the voltage input terminal VI1 and the ground in sequence; the gates of the switching transistors 201 and 203 are both connected to the first terminal of the controller 210 to input the pulse width modulation signal PWM2 output by the controller 210; the gates of the switching transistors 202 and 204 are both connected to the second terminal of the controller 210 to input the pulse width modulation signal PWM1 output by the controller 210; the capacitor 205 is connected between the source of the switching transistor 201 and the source of the switching transistor 203; the source of the switching transistor 202 is connected to the voltage output terminal VO1; the capacitor 207 is connected between the voltage output terminal VO1 and the ground.

[0079] When Figure 1 the shown switched-capacitor converter works, the controller 210 controls the combination of the switching transistors 201 and 203 and the combination of the switching transistors 202 and 204 to conduct and turn off alternately, so that the voltage at the output terminal VO1 is approximately half of the voltage at the input terminal VI1. Among them, according to the magnitude of the output current IOUT, Figure 1 the shown switched-capacitor converter can work in the charge pump operating mode or the pulse skipping operating mode.

[0080] Specifically, the following will combine Figure 2 the shown control method to explain Figure 1 the principle of the described circuit. Figure 2 Exemplarily shows Figure 1 a schematic diagram of each signal in the shown circuit, where the abscissa is time; the ordinates from top to bottom are VI1 / 2, the voltage threshold VREFH1, the voltage VOUT at the output terminal VO1, the voltage threshold VREFL1, the clock signal CLK, the signal SW_ON1, the pulse width modulation signal PWM1, and the output current IOUT at the output terminal VO1.

[0081] Among them, the clock signal CLK is a clock signal with a fixed frequency, and its duty cycle is 50%. Both the voltage threshold VREFL1 and the voltage threshold VREFH1 are less than half of the voltage VIN of the input terminal VI1, and the voltage threshold VREFL1 is less than the voltage threshold VREFH1. The signal SW_ON1 is used to indicate the comparison results of the voltage VOUT of the output terminal VO1 with the voltage threshold VREFL1 and the voltage threshold VREFH1 respectively. Specifically, when the voltage VOUT of the output terminal VO1 drops to less than the voltage threshold VREFL, the signal SW_ON1 is configured to be at a high level; when the voltage VOUT of the output terminal VO1 rises to greater than the voltage threshold VREFH, the signal SW_ON1 is reset to a low level. The result of the logical AND operation between the signal SW_ON1 and the clock signal CLK is the pulse-width modulation signal PWM1 that controls the conduction and cut-off of the switching transistors 202 and 204; the result of the logical inversion operation of the pulse-width modulation signal PWM1 is the pulse-width modulation signal PWM2 that controls the conduction and cut-off of the switching transistors 201 and 203, and the pulse-width modulation signal PWM1 and the pulse-width modulation signal PWM2 maintain a complementary relationship.

[0082] Specifically, first, at time t0, the switched-capacitor converter 200 is in the charge pump operating mode. Since the voltage VOUT of the output terminal VO1 is lower than the voltage threshold VREFH1, the signal SW_ON1 remains at a high level. At this time, the pulse-width modulation signal PWM2 is the same as the clock signal CLK, that is, the combination of the switching transistors 201 and 203 and the combination of the switching transistors 202 and 204 are controlled by the controller 210 to conduct and cut off alternately at the frequency of the clock signal CLK and a duty cycle of 50%. When the clock signal CLK is at a low level, the switching transistors 201 and 203 are conducting, and the switching transistors 202 and 204 are cut off. The capacitors 205 and 207 are connected in series. The voltage VIN of the input terminal VI1 charges the capacitor 205 and supplies power to the load (not shown in the figure) connected to the voltage output terminal VO1, and the voltage VOUT of the output terminal VO1 decreases. When the clock signal CLK is at a high level, the switching transistors 201 and 203 are cut off, and the switching transistors 202 and 204 are conducting. The capacitors 205 and 207 are connected in parallel. The capacitor 205 charges the capacitor 207 and supplies power to the load, and the voltage VOUT of the output terminal VO1 rises rapidly. When the output current IOUT of the output terminal VO1 remains stable, such as within the time interval from time t0 to time t1, the voltage VOUT of the output terminal VO1 also remains stable and fluctuates within a small range.

[0083] During the time interval from time t1 to time t2, as the output current IOUT of the output terminal VO1 decreases, the conduction losses of the switching transistors in the switched-capacitor converter 200 decrease, causing the voltage VOUT of the output terminal VO1 to slowly increase. Until at time t2, the voltage VOUT of the output terminal VO1 rises to the voltage threshold VREFH1, and the switched-capacitor converter 200 enters the pulse-skipping operation mode. In the pulse-skipping operation mode, the switching frequency of each switching transistor is significantly reduced to reduce the switching losses, thereby improving the voltage conversion efficiency at light load (when the output current IOUT of the output terminal VO1 is small).

[0084] At time t2, the signal SW_ON1 becomes low level, shielding the clock signal CLK, causing the output of the pulse-width modulation signal PWM1 to remain low level. The switching transistors 201 and 203 are turned on, and the switching transistors 202 and 204 are turned off. The capacitor 205 and the capacitor 207 are connected in series. The voltage VIN of the input terminal VI1 charges the capacitor 205 and supplies power to the load. The voltage VOUT of the output terminal VO1 starts to continuously decrease until at time t3, the voltage VOUT of the output terminal VO1 decreases to the voltage threshold VREFL1.

[0085] At time t3, the signal SW_ON1 becomes high level, and the clock signal CLK is no longer shielded. However, at time t3, since the clock signal CLK is at low level, the pulse-width modulation signal PWM1 cannot immediately become high level. This results in the voltage VOUT of the output terminal VO1 continuously decreasing between time t3 and time t4 until at time t4, when the rising edge of the clock signal CLK arrives, the pulse-width modulation signal PWM1 is converted to high level. That is, at time t4, the switching transistors 201 and 203 are turned off, and the switching transistors 202 and 204 are turned on. The capacitor 205 and the capacitor 207 are connected in parallel. The capacitor 205 charges the capacitor 207 and supplies power to the load. The voltage VOUT of the output terminal VO1 rapidly increases.

[0086] After two processes of charging capacitor 207 with capacitor 205, at time t5, the voltage VOUT at the output terminal VO1 rises again to the voltage threshold VREFH1, and the signal SW_ON1 switches to the low level again, causing the pulse-width modulation signal PWM1 to remain low level, and the voltage VOUT at the output terminal VO1 starts to decrease continuously again. Until time t6, the voltage VOUT at the output terminal VO1 decreases to the voltage threshold VREFL1 again. Similar to the time interval between time t3 and time t4, before the rising edge of the clock signal CLK appears at time t7, the voltage VOUT at the output terminal VO1 continues to decrease. Until at time t7, the pulse-width modulation signal PWM1 is converted to the high level, capacitor 205 charges capacitor 207 again and supplies power to the load, and the voltage VOUT at the output terminal VO1 rises rapidly. Due to the continuous decrease of the output current IOUT at the output terminal VO1, one pulse of the pulse-width modulation signal PWM1 can raise the voltage VOUT at the output terminal VO1 to the voltage threshold VREFH1, causing the signal SW_ON1 to flip again, and the voltage VOUT at the output terminal VO1 starts to decrease continuously again. And so on. In the pulse-skipping operation mode, when the output current IOUT at the output terminal VO1 of the switched-capacitor converter 200 is low, the signal SW_ON1 is used to control each switching transistor to selectively conduct and turn off according to the high and low levels of the clock signal CLK, so as to basically keep the voltage VOUT at the output terminal VO1 between the voltage threshold VREFL1 and the voltage threshold VREFH1. This control method can also be considered as controlling each switching transistor to skip part of the clock signal CLK, making the equivalent switching frequency much lower than the frequency of the clock signal CLK, and improving the efficiency of the switched-capacitor converter 200 under light load.

[0087] At time t8, the output current IOUT of output terminal VO1 drops to the lowest point and a load jump occurs, that is, the output current IOUT of output terminal VO1 increases rapidly. This load jump causes the voltage VOUT of output terminal VO1 to drop rapidly and fall to the voltage threshold VREFL1 at time t9, triggering the signal SW_ON1 to jump to a high level. However, at this time, the clock signal CLK is at a low level. It is necessary to wait until the next rising edge of the clock signal CLK arrives at time t10 before the switching transistors 202 and 204 can be turned on, and the voltage VOUT of output terminal VO1 can stop dropping. At this time, the system exits the pulse skipping operation mode and re-enters the charge pump operation mode, that is, each switching transistor is controlled by the clock signal CLK to turn on and off at a fixed frequency and a duty cycle of 50%. After entering the charge pump operation mode, the voltage VOUT of output terminal VO1 continues to increase and finally reaches stability. Since the output current IOUT of output terminal VO1 at time t10 is larger than the output current IOUT of output terminal VO1 at time t0, the voltage VOUT of output terminal VO1 will also be correspondingly stabilized near a voltage value slightly lower than the starting moment.

[0088] It should be noted that in the embodiments of the present application, when the output current IOUT of output terminal VO1 is less than 100 mA, it can be expressed as a very light load or a relatively light load or a light load, etc.; and when the output current IOUT of output terminal VO1 is greater than 120 mA, it can be expressed as a very heavy load or a very light load or a heavy load, etc.

[0089] Although Figure 2 the control method shown has a simple circuit and is easy to implement, but Figure 2 the disadvantages of the control method shown are also relatively obvious. On the first hand, Figure 2 the control method shown will result in high power consumption and low voltage conversion efficiency. Specifically, whether in the charge pump operation mode or the pulse skipping operation mode, the control of the circuit always requires the clock signal CLK. However, in the case of a very light load, the power consumption of maintaining a clock signal CLK with a fixed frequency is relatively large, resulting in a low voltage conversion efficiency; on the second hand, Figure 2The control method shown above will result in a relatively large ripple in the voltage VOUT at the output terminal VO1. Specifically, since the rising edge of the signal SW_ON1 does not necessarily occur simultaneously with the rising edge of the clock signal CLK. For example, at time t4 or time t7, when the switching transistors 202 and 204 are turned on, the voltage VOUT at the output terminal VO1 has already fallen below the voltage threshold VREFL1. Moreover, as the relative delay between the rising edge of the signal SW_ON1 and the rising edge of the clock signal CLK changes, the degree to which the voltage VOUT at the output terminal VO1 dips below the voltage threshold VREFL1 also varies, which will cause the ripple of the voltage VOUT at the output terminal VO1 to increase and become uncontrollable. Thirdly, Figure 2 The control method shown above will cause the switching capacitor converter 200 to have a slow transient response. Specifically, for example, although at time t9, the voltage VOUT at the output terminal VO1 has dropped to the voltage threshold VREFL1 due to the rapid increase in the output current IOUT at the output terminal VO1, since the rising edge of the clock signal CLK has to wait until time t10 to arrive, the system cannot respond to the load mutation in a timely manner. At time t10, the switching transistors 202 and 204 can be controlled to turn on, and at this time, the voltage VOUT at the output terminal VO1 has dropped significantly below the voltage threshold VREFL1. It can be seen that the traditional pulse-skipping operating mode has a slow response to load dynamics.

[0090] For the above reasons, the embodiment of the present application provides a control circuit for controlling the switching transistors in a switching capacitor converter. When the control circuit controls the switching capacitor converter to operate in the pulse frequency modulation operating mode, it does not need to be synchronized with any clock signal, and can improve the voltage conversion efficiency, reduce the ripple of the output voltage, and maintain a fast transient response.

[0091] Please refer to Figure 3 , Figure 3 FIG. is a schematic diagram of a block diagram of the control circuit and the switching capacitor converter provided by the embodiment of the present application. Among them, the control circuit 100 is used to output complementary first pulse width modulation signal PWMA and second pulse width modulation signal PWMB for controlling the switching transistors in the switching capacitor converter 200. Among them, the switching capacitor converter 200 is used to convert the input voltage VIN into the output voltage VOUT, and the ratio of the input voltage VIN to the output voltage VOUT is N:1, and N is an integer greater than 1.

[0092] It should be noted that the control circuit 100 in the embodiment of the present application can not only be used to control Figure 1 the switching capacitor converter 200 with a step-down ratio of 2:1 shown above, but can also be used to control switching capacitor converters 200 with other step-down ratios, such as 3:1, 4:1, etc.

[0093] Among them, the switched-capacitor converter 200 includes 2K switching transistors, where K switching transistors are controlled by the first pulse-width modulation signal PWMA, and the other K switching transistors are controlled by the second pulse-width modulation signal PWMB, where K is an integer greater than or equal to 1. Taking the switched-capacitor converter 200 as Figure 1 the circuit structure shown as an example, K = 2, the switching transistor 201 and the switching transistor 203 are controlled by the second pulse-width modulation signal PWMB, and the switching transistor 202 and the switching transistor 204 are controlled by the first pulse-width modulation signal PWMA. During a part of the switching period of the switched-capacitor converter 200, control K of the switching transistors to conduct, so that the input voltage VIN of the switched-capacitor converter 200 charges the energy storage capacitor (such as Figure 1 the capacitor 205) in the switched-capacitor converter 200; during another part of the switching period of the switched-capacitor converter 200, control the other K switching transistors to conduct, so that the energy storage capacitor discharges to the output capacitor (such as Figure 1 the capacitor 207) in the switched-capacitor converter 200. In addition, the circuit composed of 2K switching transistors is directly connected to the voltage output terminal, that is, there is no inductor between the circuit composed of 2K switching transistors and the output capacitor.

[0094] As Figure 3 shown, the control circuit 100 includes a signal generation module 10 and a signal setting module 20. Among them, the signal generation module 10 inputs the input voltage VIN and the output voltage VOUT, and the signal setting module 20 is connected to the signal generation module 10. That is, the first end of the signal generation module 10 is connected to the input voltage VIN, the second end of the signal generation module 10 is connected to the output voltage VOUT, the third end of the signal generation module 10 is connected to the first end of the signal setting module 20, the fourth end of the signal generation module 10 is connected to the second end of the signal setting module 20, the third end of the signal setting module 20 is connected to the first end of the switched-capacitor converter 200, and the fourth end of the signal setting module 20 is connected to the second end of the switched-capacitor converter 200.

[0095] Specifically, the signal generation module 10 is configured to output a first indication signal SW_ON when the output voltage VOUT drops to a first preset voltage (denoted as VREFL) and output a second indication signal SW_OFF when the output voltage VOUT rises to a second preset voltage (denoted as VREFH) when the switched-capacitor converter 200 is in the pulse frequency modulation (PFM) operating mode. Herein, both the first preset voltage VREFL and the second preset voltage VREFH are less than 1 / N of the input voltage VIN, and the first preset voltage VREFL is less than the second preset voltage VREFH. The first preset voltage VREFL and the second preset voltage VREFH can be set based on the actual application scenario. In some embodiments, N = 2. The first indication signal SW_ON is used to indicate that the energy storage capacitor discharges to the output terminal in the switched-capacitor converter 200; the second indication signal SW_OFF is used to indicate that the input voltage VIN of the switched-capacitor converter 200 charges the energy storage capacitor in the switched-capacitor converter 200.

[0096] The signal setting module 20 is configured to set the first pulse width modulation signal PWMA and the second pulse width modulation signal PWMB as two complementary signals with a duty cycle of 50% when the switched-capacitor converter 200 is in the charge pump operating mode, and is configured to set the first pulse width modulation signal PWMA to a high level if the first indication signal SW_ON is received and set the second pulse width modulation signal PWMB to a high level if the second indication signal SW_OFF is received when the switched-capacitor converter 200 is in the pulse frequency modulation operating mode. Taking Figure 1 the shown switched-capacitor converter 200 as an example, when the switched-capacitor converter 200 is in the pulse frequency modulation operating mode, if the first indication signal SW_ON is received, the first pulse width modulation signal PWMA is set to a high level to drive the switch transistors 202 and 204 to conduct; if the second indication signal SW_OFF is received, the second pulse width modulation signal PWMB is set to a high level to drive the switch transistors 201 and 203 to conduct. Among them, the first pulse width modulation signal PWMA and the second pulse width modulation signal PWMB maintain a complementary relationship, and the first pulse width modulation signal PWMA and the second pulse width modulation signal PWMB are respectively triggered by the rising edges of the first indication signal SW_ON and the second indication signal SW_OFF.

[0097] So far, the control process of the control circuit 100 controlling the switched-capacitor converter 200 has been realized. In this control process, the control circuit 100 controls the switched-capacitor converter 200 to operate in a charge pump operating mode or a pulse frequency modulation operating mode. Among them, in the pulse frequency modulation operating mode, the first pulse width modulation signal PWMA and the second pulse width modulation signal PWMB are synchronized with the first indication signal SW_ON and the second indication signal SW_OFF respectively, which is equivalent to each switching tube being controlled by the first indication signal SW_ON and the second indication signal SW_OFF, without the need to use a fixed clock signal as in the related art, thereby facilitating the improvement of the voltage conversion efficiency. Secondly, in the pulse frequency modulation operating mode, each switching tube is independently controlled by the first indication signal SW_ON and the second indication signal SW_OFF, without the need to be synchronized with any clock signal, and the output voltage VOUT can be effectively controlled within a preset voltage range (such as between the first preset voltage VREFL and the second preset voltage VREFH), and the ripple of the output voltage VOUT is small. Furthermore, in the pulse frequency modulation operating mode, since the K switching tubes in the switched-capacitor converter 200 that control the energy storage capacitor to discharge to the output end are independently controlled by the first indication signal SW_ON, there is no need to wait for the arrival of any clock signal as in the pulse skipping operating mode in the prior art, and the sudden increase in the load can be immediately responded to, that is, a fast transient response can be achieved.

[0098] In one embodiment, as Figure 4 shown, the control circuit 100 further includes a mode switching module 30. The mode switching module 30 is connected between the signal generation module 10 and the signal setting module 20. That is, the third end of the signal generation module 10 is respectively connected to the first end of the signal setting module 20 and the first end of the mode switching module 30, the fourth end of the signal generation module 10 is respectively connected to the second end of the signal setting module 20 and the second end of the mode switching module 30, the third end of the mode switching module 30 is connected to the fifth end of the signal setting module 20, and the fourth end of the mode switching module 30 is connected to the sixth end of the signal setting module 20.

[0099] Specifically, the mode switching module 30 is configured to switch the operating mode of the switched-capacitor converter 200 to the charge pump operating mode when the switched-capacitor converter 200 is in the pulse frequency modulation operating mode and the duration of receiving the first indication signal SW_ON is greater than the first preset duration, and is configured to switch the operating mode of the switched-capacitor converter 200 to the pulse frequency modulation operating mode when the switched-capacitor converter 200 is in the charge pump operating mode and the duration of receiving the second indication signal SW_OFF is greater than the second preset duration. Among them, the first preset duration and the second preset duration can be set based on the actual application scenario, and the embodiments of the present application do not make specific limitations on this.

[0100] In practical applications, the mode switching module 30 is used to detect the charging time and discharging time of the energy storage capacitor in the switched-capacitor converter 200 respectively. Thus, when the discharging time of the energy storage capacitor is greater than a preset threshold (corresponding to the duration of receiving the first indication signal SW_ON being greater than the first preset duration), an output is generated to indicate that the switched-capacitor converter 200 enters the charge pump operating mode, i.e., the fourth indication signal M_CP. Subsequently, the switched-capacitor converter 200 should switch to the charge pump operating mode. When the charging time of the energy storage capacitor is greater than another preset threshold (corresponding to the duration of receiving the second indication signal SW_OFF being greater than the second preset duration), an output is generated to indicate that the switched-capacitor converter 200 enters the pulse frequency modulation operating mode, i.e., the third indication signal M_PFM. Subsequently, the switched-capacitor converter 200 should switch to the pulse frequency modulation operating mode.

[0101] It can be understood that in the embodiments of the present application, when the third indication signal M_PFM is at a high level, the fourth indication signal M_CP is at a low level, and the switched-capacitor converter 200 is in the pulse frequency modulation operating mode; when the third indication signal M_PFM is at a low level, the fourth indication signal M_CP is at a high level, and the switched-capacitor converter 200 is in the charge pump operating mode.

[0102] Please refer to Figure 5 , Figure 5 which exemplarily shows the circuit structure schematic diagram of the signal generation module 10. As Figure 5 shown, the signal generation module 10 includes a first comparator U1, a second comparator U2, and a first latch SR1.

[0103] Among them, the non-inverting input terminal of the first comparator U1 inputs a first preset voltage VREFL, the inverting input terminal of the first comparator U1 inputs an output voltage VOUT, the output terminal of the first comparator U1 is connected to the set terminal of the first latch SR1, the inverting input terminal of the second comparator U2 inputs a second preset voltage VREFH, the non-inverting input terminal of the second comparator U2 inputs an output voltage VOUT, the output terminal of the second comparator U2 is connected to the reset terminal of the first latch SR1, the non-inverting output terminal of the first latch SR1 is used to output the first indication signal SW_ON, and the inverting output terminal of the first latch SR1 is used to output the second indication signal SW_OFF.

[0104] In some embodiments, the signal generation module 10 is further configured to configure the first preset voltage VREFL as VIN / 2 - ∆v1, where ∆v1 is a fourth preset voltage, which can be set based on the actual application scenario; at the same time, the signal generation module 10 is further configured to configure the second preset voltage VREFH as VIN / 2 - ∆v2, where ∆v2 is a fifth preset voltage, and ∆v1 is greater than ∆v2.

[0105] The control circuit 100 is used to control Figure 1 The switching capacitor converter 200 shown in FIG. 2 is used as an example for explanation. Specifically, the first comparator U1 and the second comparator U2 are used to compare the output voltage VOUT with the first preset voltage VREFL and the second preset voltage VREFH, and output the comparison result to the first latch SR1. The in-phase output terminal of the first latch SR1 outputs an indication that the energy storage capacitor ( Figure 1 The first indication signal SW_ON for discharging the capacitor 205 in the middle. Whenever the output voltage VOUT drops to the first preset voltage VREFL, the first comparator U1 outputs a high level to the setting end of the first latch SR1, so that the in-phase output of the first latch SR1 is high (i.e., the first indication signal SW_ON). It can be understood that in the embodiment of the present application, when the in-phase output end of the first latch SR1 outputs a high level, the corresponding signal generation module 10 outputs the first indication signal SW_ON. The first indication signal SW_ON is high, indicating that the switch tube 202 and the switch tube 204 need to be controlled to be turned on, so that the capacitor 205 is connected in parallel with the capacitor 207 and the capacitor 205 discharges to the capacitor 207 and the load, thereby increasing the output voltage VOUT. Whenever the output voltage VOUT rises to the second preset voltage VREFH, the second comparator U2 outputs a high level to the reset end of the first latch SR1, so that the in-phase output end of the first latch SR1 is reset to a low level, and the corresponding signal generation module 10 stops outputting the first indication signal SW_ON; at the same time, the inverting output end of the first latch SR1 outputs a high level (i.e., the second indication signal SW_OFF). It can be understood that in the embodiment of the present application, when the inverting output end of the first latch SR1 outputs a high level, the corresponding signal generation module 10 outputs the second indication signal SW_OFF. The second indication signal SW_OFF is a high level, indicating that the switch tube 201 and the switch tube 203 need to be controlled to be turned on, so that the input end of the switch capacitor converter 200 provides current to the output end of the switch capacitor converter 200 through the series capacitor 205 and the capacitor 207, and the capacitor 205 is charged, and the output voltage VOUT is reduced.

[0106] Please refer to Figure 6 , Figure 6 FIG. 2 is an exemplary circuit diagram of the signal setting module 20. Figure 6 As shown, the signal setting module 20 includes a second OR gate OR2, a third OR gate OR3, a fourth OR gate OR4, a fifth OR gate OR5, a seventh switch S7, an eighth switch S8, a fourth capacitor C4, a fifth capacitor C5, a fourth current source I4, a fifth current source I5, a sixth comparator U6, a seventh comparator U7, a third single trigger UA3, a fourth single trigger UA4 and a third latch SR3.

[0107] Among them, the first input terminal of the second OR gate OR2 is connected to the first input terminal of the third OR gate OR3, and a third indication signal M_PFM indicating that the switched-capacitor converter 200 is in the pulse frequency modulation operating mode is input. When the switched-capacitor converter 200 is in the pulse frequency modulation operating mode, the third indication signal M_PFM is at a high level. The second input terminal of the second OR gate OR2 is respectively connected to the non-inverting output terminal of the third latch SR3 and the switching transistor in the switched-capacitor converter 200, and the non-inverting output terminal of the third latch SR3 outputs a first pulse width modulation signal PWMA. The output terminal of the second OR gate OR2 outputs a signal for controlling the seventh switch S7. The seventh switch S7 is connected between the non-inverting input terminal of the sixth comparator U6 and the ground. The fourth capacitor C4 is connected in parallel with the seventh switch S7. The non-inverting input terminal of the sixth comparator U6 is further connected to the fourth current source I4. The inverting input terminal of the sixth comparator U6 inputs a third preset voltage VREF. The output terminal of the sixth comparator U6 is connected to the first input terminal of the fourth OR gate OR4. The second input terminal of the fourth OR gate OR4 is connected to the output terminal of the third single flip-flop UA3. The input terminal of the third single flip-flop UA3 inputs a first indication signal SW_ON. The output terminal of the fourth OR gate OR4 is connected to the set terminal of the third latch SR3.

[0108] The second input terminal of the third OR gate OR3 is respectively connected to the inverting output terminal of the third latch SR3 and the switching transistor in the switched-capacitor converter 200, and the inverting output terminal of the third latch SR3 outputs a second pulse width modulation signal PWMB. The output terminal of the third OR gate OR3 outputs a signal for controlling the eighth switch S8. The eighth switch S8 is connected between the non-inverting input terminal of the seventh comparator U7 and the ground. The fifth capacitor C5 is connected in parallel with the eighth switch S8. The non-inverting input terminal of the seventh comparator U7 is further connected to the fifth current source I5. The inverting input terminal of the seventh comparator U7 inputs a third preset voltage VREF. The output terminal of the seventh comparator U7 is connected to the first input terminal of the fifth OR gate OR5. The second input terminal of the fifth OR gate OR5 is connected to the output terminal of the fourth single flip-flop UA4. The input terminal of the fourth single flip-flop UA4 inputs a second indication signal SW_OFF. The output terminal of the fifth OR gate OR5 is connected to the reset terminal of the third latch SR3.

[0109] Specifically, when the switched-capacitor converter 200 is in the charge pump operating mode, the third indication signal M_PFM is at a low level. And, the output voltage VOUT will not decrease to the first preset voltage VREFL or increase to the second preset voltage VREFH, and the first indication signal SW_ON and the second indication signal SW_OFF will not change in level. Then, the outputs of the third single flip-flop UA3 and the fourth single flip-flop UA4 are constantly 0. Based on this, Figure 6 the shown circuit structure can be simplified, and the simplified result is as Figure 7 shown.

[0110] The following is combined with Figure 8 to Figure 7 illustrate the principle of the circuit structure shown. Among them, Figure 8 exemplarily shows Figure 7 a schematic diagram of each signal in the circuit shown. In Figure 8 , the abscissa is time; the ordinates from top to bottom are the third preset voltage VREF, the voltage Ramp_RST at the non-inverting input terminal of the seventh comparator U7, the voltage CLK_RST at the output terminal of the seventh comparator U7, the third preset voltage VREF, the voltage Ramp_SET at the non-inverting input terminal of the sixth comparator U6, the voltage CLK_SET at the output terminal of the sixth comparator U6, the first pulse width modulation signal PWMA, and the second pulse width modulation signal PWMB.

[0111] Specifically, when the first pulse width modulation signal PWMA is at a low level (i.e., the second pulse width modulation signal PWMB is at a high level), the seventh switch S7 is turned off, and the fourth current source I4 charges the fourth capacitor C4, and the voltage Ramp_SET at the non-inverting input terminal of the sixth comparator U6 linearly rises. Until the voltage Ramp_SET exceeds the third preset voltage VREF, the voltage CLK_SET output by the sixth comparator U6 becomes high level and triggers the third latch SR3, so that the first pulse width modulation signal PWMA output by the third latch SR3 becomes high level, and then the seventh switch S7 is turned on to reset the voltage Ramp_SET to 0. Among them, the fourth current source I4, the fourth capacitor C4, and the seventh switch S7 form a first integration unit to perform integration based on time when the first pulse width modulation signal PWMA is at a low level, and the result of the integration is the voltage Ramp_SET, which represents the duration of the second pulse width modulation signal PWMB at a high level and the charging of the energy storage capacitor in the switched-capacitor converter 200.

[0112] When the second pulse width modulation signal PWMB is at a low level (i.e., when the first pulse width modulation signal PWMA is at a high level), the eighth switch S8 is turned off, the fifth current source I5 charges the fifth capacitor C5, and the voltage Ramp_RST at the non-inverting input terminal of the seventh comparator U7 linearly rises. Until the voltage Ramp_RST exceeds the third preset voltage VREF, the voltage CLK_RST output by the seventh comparator U7 becomes high level and triggers the third latch SR3 to reset, making the first pulse width modulation signal PWMA output by the third latch SR3 become low level, and the second pulse width modulation signal PWMB become high level, thereby turning on the eighth switch S8 to reset the voltage Ramp_RST to 0. Among them, the fifth current source I5, the fifth capacitor C5 and the eighth switch S8 form a second integration unit to perform integration based on time when the second pulse width modulation signal PWMB is at a low level. The result of the integration is the voltage Ramp_RST, which represents the duration of the first pulse width modulation signal PWMA at a high level and also represents the duration of the energy storage capacitor in the switched capacitor converter 200 discharging.

[0113] The above process repeats continuously, making the first pulse width modulation signal PWMA and the second pulse width modulation signal PWMB become clock signals with a fixed frequency. When the currents of the fourth current source I4 and the fifth current source I5 are equal, and the capacitance values of the fourth capacitor C4 and the fifth capacitor C5 are also equal, the duty cycles of the first pulse width modulation signal PWMA and the second pulse width modulation signal PWMB are both 50%. The frequency of the first pulse width modulation signal PWMA is determined by the current of the fourth current source I4, the capacitance value of the fourth capacitor C4 and the third preset voltage VREF; the frequency of the second pulse width modulation signal PWMB is determined by the current of the fifth current source I5, the capacitance value of the fifth capacitor C5 and the third preset voltage VREF.

[0114] Please refer back to Figure 6 , when the switched capacitor converter 200 is in the pulse frequency modulation operating mode, the third indication signal M_PFM is at a high level, the seventh switch S7 and the eighth switch S8 remain on, and the outputs of the sixth comparator U6 and the seventh comparator U7 are constantly at a low level. At this time, the output of the third latch SR3 is only controlled by these two signals, the first indication signal SW_ON and the second indication signal SW_OFF. In this case, Figure 6 The signals in the circuit shown in Figure 9 are as shown.

[0115] In Figure 9Among them, the abscissa is time; the ordinates from top to bottom are the second preset voltage VREFH, the output voltage VOUT, the first preset voltage VREFL, the first indication signal SW_ON, the second indication signal SW_OFF, the voltage at the output terminal of the fourth OR gate OR4 (i.e., the voltage at the set terminal of the third latch SR3) CLK_SET, the voltage at the output terminal of the fifth OR gate OR5 (i.e., the voltage at the reset terminal of the third latch SR3) CLK_RST, the first pulse width modulation signal PWMA, and the output current IOUT.

[0116] Take the control circuit 100 for controlling Figure 1 the shown switched-capacitor converter 200 as an example for illustration. Specifically, when the switched-capacitor converter 200 is in the pulse frequency modulation operating mode, when the output voltage VOUT rises to the second preset voltage VREFH, the second indication signal SW_OFF becomes high level. Through the fourth single flip-flop UA4 and the fifth OR gate OR5, the third latch SR3 is reset, causing the first pulse width modulation signal PWMA to flip to low level and the second pulse width modulation signal PWMB to flip to high level. Then, the switching transistors 201 and 203 are controlled to conduct, and immediately the output voltage VOUT starts to decrease. When the output voltage VOUT drops to the first preset voltage VREFL, the first indication signal SW_ON becomes high level. Through the third single flip-flop UA3 and the fourth OR gate OR4, the third latch SR3 is set, causing the first pulse width modulation signal PWMA to flip to high level and the second pulse width modulation signal PWMB to flip to low level. Then, the switching transistors 202 and 204 are controlled to conduct, and the capacitor 205 charges the capacitor 207, and immediately the output voltage VOUT starts to rise. It can be seen that when the switched-capacitor converter 200 is in the pulse frequency modulation operating mode, the duty cycle of the first pulse width modulation signal PWMA is relatively small because the output current IOUT is relatively low. As the output current IOUT increases, when the first pulse width modulation signal PWMA is at low level, the decreasing speed of the output voltage VOUT increases. Correspondingly, the frequency of the first pulse width modulation signal PWMA increases and the duty cycle increases until it is necessary to switch to the charge pump operating mode. At this time, the third indication signal M_PFM will convert from high level to low level, and the fourth indication signal M_CP converts to high level, thereby Figure 7 the circuit shown is started so that the duty cycles of both the first pulse width modulation signal PWMA and the second pulse width modulation signal PWMB are 50%.

[0117] Please refer to Figure 10 , Figure 10 which exemplarily shows the circuit structure schematic diagram of the mode switching module 30. As Figure 10As shown, the mode switching module 30 includes a third AND gate AND3, a fourth AND gate AND4, a second NOT gate NOT2, a third NOT gate NOT3, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a second capacitor C2, a third capacitor C3, a second current source I2, a third current source I3, a fourth comparator U4, a fifth comparator U5, and a second latch SR2.

[0118] Among them, a first input terminal of the third AND gate AND3 inputs a first indication signal SW_ON; a second input terminal of the third AND gate AND3 inputs a third indication signal M_PFM indicating that the switched-capacitor converter 200 is in a pulse frequency modulation operating mode; an output terminal of the third AND gate AND3 outputs a signal for controlling the third switch, and the output terminal of the third AND gate AND3 is further connected to an input terminal of the second NOT gate NOT2; an output terminal of the second NOT gate NOT2 outputs a signal for controlling the fourth switch S4; the third switch S3 is connected between the second current source I2 and a non-inverting input terminal of the fourth comparator U4; the second capacitor C2 is connected between the non-inverting input terminal of the fourth comparator U4 and the ground; the fourth switch S4 is connected in parallel with the second capacitor C2; a voltage VREF_CP_IN corresponding to a first preset duration is input to an inverting input terminal of the fourth comparator U4; an output terminal of the fourth comparator U4 is connected to a set terminal of the second latch SR2; a first input terminal of the fourth AND gate AND4 inputs a second indication signal SW_OFF; a second input terminal of the fourth AND gate AND4 inputs a fourth indication signal M_CP indicating that the switched-capacitor converter 200 is in a charge pump operating mode; an output terminal of the fourth AND gate AND4 outputs a signal for controlling the fifth switch S5, and the output terminal of the fourth AND gate AND4 is further connected to an input terminal of the third NOT gate NOT3; an output terminal of the third NOT gate NOT3 outputs a signal for controlling the sixth switch S6; the fifth switch S5 is connected between the third current source I3 and a non-inverting input terminal of the fifth comparator U5; the third capacitor C3 is connected between the non-inverting input terminal of the fifth comparator U5 and the ground; the fifth switch S5 is connected in parallel with the third capacitor C3; a voltage VREF_CP_OUT corresponding to a second preset duration is input to an inverting input terminal of the fifth comparator U5; an output terminal of the fifth comparator U5 is connected to a reset terminal of the second latch SR2, a non-inverting output terminal of the second latch SR2 outputs a fourth indication signal M_CP, and an inverting output terminal of the second latch SR2 outputs a third indication signal M_PFM.

[0119] In this embodiment, the mode switching module 30 respectively monitors the discharging duration of each energy storage capacitor in the switched-capacitor converter 200 in the charge pump operating mode (i.e., Figure 1 the conduction duration of the switching transistors 202 and 204 in the shown circuit) and monitors the charging duration of the energy storage capacitor in the switched-capacitor converter 200 in the pulse frequency modulation operating mode (i.e., Figure 1Based on the conduction durations of switch transistor 201 and switch transistor 203 in the shown circuit, it is determined whether the switched-capacitor converter 200 needs to perform a conversion of the operating mode.

[0120] Specifically, when the third indication signal M_PFM is at a high level (i.e., when the switched-capacitor converter 200 operates in the pulse frequency modulation mode), the first indication signal SW_ON controls the third switch S3 and the fourth switch S4 to charge and discharge the second capacitor C2, so as to perform integration over time when the first indication signal SW_ON is at a high level. That is, the second current source I2, the third switch S3, the fourth switch S4, and the second capacitor C2 form a third integration unit to perform integration based on time when the first indication signal SW_ON is at a high level, and the integration result is the voltage Ramp_CP_IN. Since in the pulse frequency modulation operating mode, the first indication signal SW_ON is used to control the conduction of switch transistor 202 and switch transistor 204, the voltage Ramp_CP_IN represents the conduction duration each time switch transistor 202 and switch transistor 204 are controlled to conduct, that is, the discharge duration of the energy storage capacitor 205. When the discharge duration of the energy storage capacitor in the switched-capacitor converter 200 exceeds the first preset duration (i.e., when the voltage VREF_CP_IN is greater than the voltage VREF_CP_IN), the fourth comparator U4 outputs a high level to the set terminal of the second latch SR2, and configures the fourth indication signal M_CP output from the non-inverting output terminal of the second latch SR2 to be at a high level. At this time, the switched-capacitor converter 200 enters the charge pump operating mode. At the same time, the third indication signal M_PFM output from the inverting output terminal of the second latch SR2 is configured to be at a low level, and the voltage Ramp_CP_IN is reset to 0. It should be noted that the voltage VREF_CP_IN represents the threshold duration for switching from the pulse frequency modulation operating mode to the charge pump operating mode. The fact that the discharge duration of the energy storage capacitor in the switched-capacitor converter 200 (i.e., the voltage Ramp_CP_IN) exceeds the voltage VREF_CP_IN means that the energy storage capacitor in the switched-capacitor converter 200 fails to raise the output voltage VOUT to the second preset voltage VREFH within the first preset duration, that is, it indicates that the output current IOUT of the switched-capacitor converter 200 is relatively large at this time, and the switched-capacitor converter 200 needs to switch to the charge pump operating mode to better maintain the stability of the output voltage VOUT under a relatively large output current IOUT.

[0121] Similarly, when the fourth indication signal M_CP is at a high level (i.e., when the switched-capacitor converter 200 operates in the charge pump mode), the second indication signal SW_OFF controls the fifth switch S5 and the sixth switch S6 to charge and discharge the third capacitor C3, so as to integrate time when the second indication signal SW_OFF is at a high level. That is to say, the third current source I3, the fifth switch S5, the sixth switch S6, and the third capacitor C3 form a fourth integration unit to integrate time when the second indication signal SW_OFF is at a high level, and the integration result is the voltage VREF_CP_OUT. Since in the charge pump mode, the second indication signal SW_OFF will only jump to a high level when the output voltage VOUT rises to the second preset voltage VREFH, the voltage Ramp_CP_OUT represents the conduction duration of the switching transistors 201 and 203, that is, the charging duration of the energy storage capacitor 205. When the charging duration of the energy storage capacitor in the switched-capacitor converter 200 exceeds the second preset duration (i.e., when the voltage Ramp_CP_OUT is greater than the voltage VREF_CP_OUT), the fifth comparator U5 outputs a high level to the reset terminal of the second latch SR2, resetting the fourth indication signal M_CP output from the non-inverting output terminal of the second latch SR2 to a low level. At this time, the switched-capacitor converter 200 enters the pulse frequency modulation mode. The third indication signal M_PFM output from the inverting output terminal of the second latch SR2 is configured to be at a high level, and the voltage Ramp_CP_OUT is reset to 0. It should be noted that the voltage VREF_CP_OUT represents the threshold duration for switching from the charge pump mode to the pulse frequency modulation mode. When the charging duration of the energy storage capacitor in the switched-capacitor converter 200 (i.e., the voltage Ramp_CP_OUT) exceeds the voltage VREF_CP_OUT, it means that the energy storage capacitor in the switched-capacitor converter 200 fails to discharge the output voltage VOUT to the first preset voltage VREFL within the second preset duration, that is, it indicates that the output current IOUT of the switched-capacitor converter 200 is small at this time, and the switched-capacitor converter 200 needs to switch to the pulse frequency modulation mode to achieve a more efficient voltage conversion.

[0122] Please refer to Figure 11 , Figure 11 which exemplarily shows Figure 5 , Figure 6 and Figure 10 the schematic diagram of each signal in the control circuit 100 composed of the circuits shown in Figure 11Among them, the abscissa is time; the ordinates from top to bottom are the second preset voltage VREFH, the output voltage VOUT, the first preset voltage VREFL, the first indication signal SW_ON, the first pulse width modulation signal PWMA, the voltage VREF_CP_IN at the inverting input terminal of the fourth comparator U4, the voltage Ramp_CP_IN at the non-inverting input terminal of the fourth comparator U4, the voltage VREF_CP_OUT at the inverting input terminal of the fifth comparator U5, the voltage Ramp_CP_OUT at the non-inverting input terminal of the fifth comparator U5, the fourth indication signal M_CP, and the output current IOUT.

[0123] Specifically, at time t11, the switched-capacitor converter 200 is in the pulse frequency modulation operating mode, the third indication signal M_PFM is at a high level, the fourth indication signal M_CP is at a low level, the output voltage VOUT is between the second preset voltage VREFH and the first preset voltage VREFL, and the first pulse width modulation signal PWMA is determined by the first indication signal SW_ON. The duration of each time the first indication signal SW_ON is at a high level is represented by the peak value of the voltage Ramp_CP_IN. Among them, the duration of the first indication signal SW_ON being at a high level is the duration from the moment when the output voltage VOUT drops to the first preset voltage VREFL to the moment when the output voltage VOUT rises to the second preset voltage VREFH. For example, the duration between time t12 (the moment when the output voltage VOUT drops to the first preset voltage VREFL) and time t13 (the moment when the output voltage VOUT rises to the second preset voltage VREFH). After time t11, as the output current IOUT increases, the frequency, conduction duration, and duty cycle of the first indication signal SW_ON all increase, and the peak value of the voltage Ramp_CP_IN in each cycle also gradually increases. Until time t13, when the switching transistors 202 and 204 are turned on under the control of the first pulse width modulation signal PWMA, that is, after the energy storage capacitor 205 discharges for a certain duration, the voltage Ramp_CP_IN reaches the voltage threshold VREF_CP_IN for switching to the charge pump operating mode, and the fourth indication signal M_CP is set high by the mode switching module 30. Figure 7 The circuit shown starts to operate to generate a clock signal with a period of T and a 50% duty cycle required in the charge pump operating mode. Before the output voltage VOUT reaches the second preset voltage VREFH, the first pulse width modulation signal PWMA turns off the switching transistors 202 and 204, and the second pulse width modulation signal PWMB turns on the switching transistors 201 and 203. The input voltage VIN starts to charge the energy storage capacitor 205, and at the same time, the output voltage VOUT starts to drop. Since the output voltage VOUT fails to reach the second preset voltage VREFH when the voltage Ramp_CP_IN reaches the voltage threshold VREF_CP_IN, the first indication signal SW_ON remains at a high level.

[0124] After half a cycle (T / 2) has elapsed at time t13, at time T14, the first pulse width modulation signal PWMA is set high based on Figure 7 the circuit shown, and the switching transistors 202 and 204 are turned on, i.e., the energy storage capacitor 205 starts discharging again, and the output voltage VOUT starts rising again. In the charge pump operating mode, the combination of the switching transistors 202 and 204 and the combination of the switching transistors 201 and 203 are always alternately turned on and off at a fixed frequency (1 / T) and a duty cycle of 50%. As the output current IOUT increases, the output voltage VOUT oscillates and decreases.

[0125] At time t15, the load suddenly decreases, causing the output current IOUT to suddenly decrease. Less than half a cycle after the first pulse width modulation signal PWMA is set high, the output voltage VOUT reaches the second preset voltage VREFH at time t16. Immediately, the first indication signal SW_ON is reset to low level, and at the same time, the second indication signal SW_OFF becomes high level, and the voltage RAMP_CP_OUT starts to increase over time. Until time t17, the voltage RAMP_CP_OUT rises to equal the threshold voltage VREF_CP_OUT for switching to the pulse frequency modulation operating mode, the fourth indication signal M_CP is set low, and the third indication signal M_PFM is set high. Figure 7 The circuit shown is shielded by the third indication signal M_PFM, and the switched capacitor converter 200 switches back to the pulse frequency modulation mode of operation.

[0126] At time t18, the load suddenly increases, causing the output current IOUT to suddenly increase, and the output voltage VOUT is quickly pulled down, dropping to the first preset voltage VREFL at time t19. Immediately, the first indication signal SW_ON is set high, and the switching transistors 202 and 204 are controlled to turn on by the first pulse width modulation signal PWMA. The energy storage capacitor 205 starts discharging to the output terminal, and the output voltage VOUT starts rising. At this time, the voltage Ramp_CP_IN also starts to rise. Until time t20, the voltage Ramp_CP_IN reaches the voltage VREF_CP_IN for switching to the charge pump operating mode, the fourth indication signal M_CP is set high again, and the switched capacitor converter 200 switches back to the charge pump operating mode. At the same time Figure 7 the circuit shown operates again. After half a cycle (T / 2) has elapsed from time t20, at time t21, the first pulse width modulation signal PWMA is reset to 0, and the switching transistors 202 and 204 are turned off, and the output voltage VOUT starts to decrease again.

[0127] As can be seen from the above description, the mode switching module 30 can select the operating mode according to the operating state of the switched capacitor converter 200 and the output current IOUT, and control the signal setting module 20 to perform a smooth mode switch, so as to achieve a higher voltage conversion efficiency when the load is relatively light. Compared with the related art (such as Figure 2 the control method shown), the embodiments of the present application have the following several advantages: First, the embodiments of the present application do not need to maintain the clock signal CLK in the pulse frequency modulation operating mode, but only generate the clock signal through the oscillation circuit (i.e., Figure 7 the circuit shown) in the charge pump operating mode, which can effectively improve the voltage conversion efficiency in the pulse frequency modulation operating mode. Second, in the present application, the control of each switching transistor in the pulse frequency modulation operating mode is independently controlled by the first indication signal SW_ON and the second indication signal SW_OFF, without being synchronized with any clock signal, and the output voltage VOUT will be effectively controlled within a preset voltage range (such as between the second preset voltage VREFH and the first preset voltage VREFL), so that the ripple of the output voltage VOUT is significantly reduced. Third, in the control circuit 100 of the present application, in the pulse frequency modulation operating mode, the discharge of the energy storage capacitor (i.e., the conduction of the switching transistors 202 and 204) can be independently controlled by the first indication signal SW_ON, and there is no need to wait for the arrival of any clock signal as in the pulse skipping operating mode in the prior art, so that an immediate response to a sudden increase in the load can be achieved, that is, it has a fast transient response. For example, at the moment t19 in Figure 11 , the control circuit 100 in the present application can immediately respond to raise the output voltage VOUT, and there will be no situation like at the moment t10 in Figure 2 .

[0128] In one embodiment, as shown in Figure 12 , the control circuit 100 further includes a pulse width setting module 40. The pulse width setting module 40 is connected to the signal generation module 10, that is, the first end of the pulse width setting module 40 is connected to the third end of the signal generation module 10, and the second end of the pulse width setting module 40 is connected to the fifth end of the signal generation module 10.

[0129] Specifically, the pulse width setting module 40 is configured to output a first pulse to the signal generation module 10 when the signal generation module 10 outputs the first indication signal SW_ON, where the pulse width of the first pulse is a first duration. The signal generation module 10 is further configured to output the second indication signal SW_OFF after the first pulse ends and the output voltage VOUT has risen to the second preset voltage VREFH.

[0130] So far, when the switched-capacitor converter 200 is in the pulse-frequency modulation operating mode, it is realized to control the conduction duration of a part of the switching transistors in the switched-capacitor converter 200 (this part of the switching transistors are the switching transistors that are turned on when the first pulse-width modulation signal PWMA is at a high level, such as Figure 1 the switching transistors 202 and 204 in the circuit shown) to be greater than or equal to the first duration, that is, to control the discharge duration of the energy storage capacitor in the switched-capacitor converter 200 to the output terminal to be greater than or equal to the first duration. Thus, the mode switching process of the switched-capacitor converter 200 can be made smoother, so as to improve the stability and reliability of the operation of the switched-capacitor converter 200.

[0131] Figure 13 Exemplarily shows a circuit structure corresponding to Figure 12 the signal generation module and the pulse-width setting module shown. As Figure 13 shown, the signal generation module 10 further includes a first AND gate AND1, and the pulse-width setting module 40 includes a first single flip-flop UA1 and a first NOT gate NOT1.

[0132] Wherein, the input end of the first single flip-flop UA1 is connected to the in-phase output end of the first latch SR1; the output end of the first single flip-flop UA1 is connected to the input end of the first NOT gate NOT1; the output end of the first NOT gate NOT1 is connected to the second input end of the first AND gate AND1; the first input end of the first AND gate NOT1 is connected to the output end of the second comparator U2; the output end of the first AND gate AND1 is connected to the reset end of the first latch SR1.

[0133] Specifically, each time the first indication signal SW_ON becomes high, the first single flip-flop UA1 will correspondingly output a signal with a fixed pulse width, and after being inverted by the first NOT gate NOT1, a masking signal is generated to perform a logical AND operation with the signal output by the second comparator U2. In this way, it can be ensured that the output of the first latch SR1 will not be quickly reset after being set high, that is, it is ensured that the duration of the first indication signal SW_ON being high is not less than the pulse width of the signal output by the first single flip-flop UA1. This is beneficial to the switched-capacitor converter 200 to operate more stably in the pulse-frequency modulation operating mode. Among them, in the embodiments of the present application, the pulse width of the output signal of each single flip-flop (such as the first single flip-flop UA1) can be set according to the actual application scenario, and the embodiments of the present application do not make specific limitations on this.

[0134] In one embodiment, as Figure 14As shown, the control circuit 100 further includes a frequency setting module 50. The frequency setting module 50 is connected to the signal generation module 10, that is, the first end of the frequency setting module 50 is connected to the third end of the signal generation module 10, the second end of the frequency setting module 50 is connected to the fourth end of the signal generation module 10, and the third end of the frequency setting module 50 is connected to the sixth end of the signal generation module 10.

[0135] Specifically, the frequency setting module 50 is configured to determine the switching frequency of the switching tube in the switched-capacitor converter 200 based on the first indication signal SW_ON and the second indication signal SW_OFF, and output a frequency setting signal when the switching frequency is less than or equal to a preset frequency. The signal generation module 10 is further configured to output the first indication signal SW_ON when receiving the frequency setting signal and the output voltage VOUT is less than the first preset voltage VREFL.

[0136] Thus, when the switched-capacitor converter 200 is in the pulse frequency modulation operating mode, the switching frequency of the switching tube in the switched-capacitor converter 200 is controlled to be lower than or equal to the preset frequency, which is beneficial to making the mode switching process of the switched-capacitor converter 200 smoother, so as to improve the stability and reliability of the operation of the switched-capacitor converter 200.

[0137] Figure 15 Exemplarily shows a circuit structure corresponding to Figure 14 the signal generation module, the pulse width setting module and the frequency setting module shown. As Figure 15 shown, the signal generation module 10 further includes a second AND gate AND2, and the frequency setting module 50 includes a first OR gate OR1, a first switch S1, a second switch S2, a first current source I1, a second single flip-flop UA2, a first capacitor C1 and a third comparator U3.

[0138] Among them, the first input end of the first OR gate OR1 is connected to the in-phase output end of the first latch SR1; the second input end of the first OR gate OR1 is connected to the inverted output end of the first latch SR1; the output end of the first OR gate OR1 outputs a signal for controlling the first switch S1, and the first switch S1 is connected between the first current source I1 and the non-inverting input end of the third comparator U3; the second switch S2 is connected between the non-inverting input end of the third comparator U3 and the ground; the first capacitor C1 is connected in parallel with the second switch S2; the inverted input end of the third comparator U3 inputs a voltage corresponding to the preset upper limit frequency; the output end of the third comparator U3 is connected to the first input end of the second AND gate AND2; the second input end of the second AND gate AND2 is connected to the output end of the first comparator U1; the output end of the second AND gate AND2 is connected to the set end of the first latch SR1.

[0139] Specifically, the result of the logical OR operation on the first indication signal SW_ON and the second indication signal SW_OFF can be used to represent the duration of a switching period T of each switching transistor in the switched-capacitor converter 200, which is used to control the first switch S1 to conduct to charge the first capacitor C1, and the voltage Ramp_FSW_LIM at the non-inverting input terminal of the third comparator U3 linearly increases as the first capacitor C1 is charged by the first current source I1. Among them, the first current source I1, the first switch S1, the second switch S2, and the first capacitor C1 form a fifth integration unit to realize integrating the time within each switching period T starting from the rising edge of the first indication signal SW_ON, and the integration result is the voltage Ramp_FSW_LIM, whose peak value represents the duration of a switching period T of each switching transistor in the switched-capacitor converter 200. When a new period starts, the rising edge of the first indication signal SW_ON drives the second single flip-flop UA2 to conduct the second switch S2 to discharge the first capacitor C1, and the voltage Ramp_FSW_LIM is also reset to zero accordingly, and then starts to linearly increase again after the pulse output by the second single flip-flop UA2 ends. The third comparator U3 compares the voltage Ramp_FSW_LIM with the voltage VREF_FSW_LIM representing the shortest switching period (i.e., the highest switching frequency, which is also the preset frequency). Only when the voltage Ramp_FSW_LIM rises to the voltage VREF_FSW_LIM, the signal FSW_LIM output by the third comparator U3 becomes high level. At this time, the signal TRIG_ON output by the first comparator U1 can trigger the first indication signal SW_ON output by the first latch SR1 to become high level.

[0140] The reason for configuring the frequency limiting module is that (for the control circuit 100 to be used for control Figure 1Taking the illustrated switched-capacitor converter 200 as an example for illustration): According to the characteristics of the switched-capacitor converter 200, when the switching transistors 202 and 204 are conducting and the switching transistors 201 and 203 are off, the energy storage capacitor 205 is in parallel with the capacitor 207. Since the equivalent series resistances (ESRs) of both capacitors are very small, the current for charge transfer between the capacitor 205 and the capacitor 207 can be very large, making the rate of increase of the output voltage VOUT very fast; while when the switching transistors 202 and 204 are off and the switching transistors 201 and 203 are conducting, the capacitor 205 is in series with the capacitor 207, and the rate of decrease of the output voltage VOUT is determined by the load. This also makes the rise time and fall time of the output voltage VOUT asymmetric even when the load is very heavy (i.e., the output current IOUT is very large). In other words, when the switched-capacitor converter 200 is in the pulse frequency modulation operating mode, the duty cycle of the first pulse width modulation signal PWMA increases with the increase of the output current IOUT, but it never reaches the duty cycle in the charge pump operating mode (i.e., 50%). The configured frequency setting module 50 can increase the duty cycle of the first pulse width modulation signal PWMA before switching from the pulse frequency modulation operating mode to the charge pump operating mode by limiting the maximum switching frequency, so as to make the process of switching from the pulse frequency modulation operating mode to the charge pump operating mode smoother.

[0141] Please refer to Figure 16 , Figure 16 exemplarily shows the schematic diagrams of the signals in the control circuit 100 composed of the circuits shown by Figure 6 , Figure 10 and Figure 15 . Among them, in Figure 16 , the abscissa is time; the ordinates from top to bottom are the second preset voltage VREFH, the output voltage VOUT, the first preset voltage VREFL, the first indication signal SW_ON, the fourth indication signal M_CP, the signal FSW_LIM output by the third comparator U3, the voltage VREF_FSW_LIM input to the inverting input terminal of the third comparator U3, the voltage Ramp_FSW_LIM input to the non-inverting input terminal of the third comparator U3, the signal SET output by the second AND gate AND, the signal RST output by the first AND gate AND1, the first pulse width modulation signal PWMA, the switching frequency FSW of the switching transistors in the switched-capacitor converter 200, and the discharging time Ton of the energy storage capacitor of the switched-capacitor converter 200 in each switching cycle, (corresponding to Figure 1 the conduction time of the switching transistors 202 and 204 in each switching cycle in the circuit shown).

[0142] Taking the control circuit 100 for controlling Figure 1Taking the shown switched-capacitor converter 200 as an example for illustration. Specifically, at time t30, the switched-capacitor converter 200 is in the pulse-frequency modulation operating mode, and the frequency of the first pulse-width modulation signal PWMA is lower than the highest frequency (i.e., the preset frequency) set by the frequency setting module 50. As the output current IOUT increases, the frequency of the first pulse-width modulation signal PWMA increases, and the conduction duration Ton of the switching transistor 202 and the switching transistor 204 slowly increases. Until time t31, the frequency of the first pulse-width modulation signal PWMA reaches the preset frequency, but it can be seen that the duty cycle of the first pulse-width modulation signal PWMA is still less than 50%. As the output current IOUT continues to increase, the frequency of the first pulse-width modulation signal PWMA is restricted by the signal FSW_LIM and cannot increase, which causes the first indication signal SW_ON not to immediately jump to the high level every time the output voltage VOUT drops to the first preset voltage VREFL, and the output voltage VOUT continues to decrease. Only when the frequency of the first pulse-width modulation signal PWMA reaches the preset frequency can the first indication signal SW_ON become high level, so as to drive the switching transistor 202 and the switching transistor 204 to conduct through the first pulse-width modulation signal PWMA, enabling the energy storage capacitor 205 to discharge to the output terminal to increase the output voltage VOUT. Since the output voltage VOUT is lower than the first preset voltage VREFL when the switching transistor 202 and the switching transistor 204 conduct, a longer conduction time is required to raise the output voltage VOUT to the second preset voltage VREFH. In this way, as the output current IOUT continuously increases, the duty cycle of the first pulse-width modulation signal PWMA continuously increases. During the time interval from time t31 to time t33, the switched-capacitor converter 200 operates in the frequency-limited pulse-frequency modulation operating mode. In this embodiment, close to time t32, the duty cycle of the first pulse-width modulation signal PWMA is already very close to 50%, and the preset frequency is also close to the switching frequency of the switched-capacitor converter 200 in the charge pump operating mode.

[0143] At time t32, the first pulse width modulation signal PWMA becomes high level. However, at the first preset duration starting from time t32, the output voltage VOUT fails to rise to the second preset voltage VREFH. At this time, the mode switching module 30 determines that the system starts to enter the charge pump operating mode. That is, at the first preset duration starting from time t32, at time t33, the fourth indication signal M_CP jumps to high level, and the switched-capacitor converter 200 officially enters the charge pump operating mode. In this embodiment, before the switched-capacitor converter 200 switches to the charge pump operating mode, within the pulse frequency modulation operating mode with limited frequency (the time interval from time t31 to time t33), through the selection of control parameters, both the operating frequency and the duty cycle of the first pulse width modulation signal PWMA are very close to the settings in the charge pump operating mode. This makes the conversion from the pulse frequency modulation operating mode to the charge pump operating mode not have sudden changes in the switching frequency or duty cycle, and the mode conversion process is very smooth.

[0144] Within the time interval from time t33 to time t34, the switched-capacitor converter 200 is in the charge pump operating mode. The first indication signal SW_ON remains high level all the time. The first pulse width modulation signal PWMA controls the on and off of each switching tube with a fixed period T and a 50% duty cycle. The output current IOUT reaches the highest value and starts to decrease during this period. Until time t34, the output voltage VOUT reaches the second preset voltage VREFH again. The first indication signal SW_ON becomes low level, and the timing for exiting the charge pump operating mode starts. After the second preset duration (i.e., the duration between time t34 and time t35), at time t35, the fourth indication signal M_CP jumps to low level, and the switched-capacitor converter 200 officially enters the pulse frequency modulation operating mode. However, in this embodiment, due to the frequency limiting effect of the frequency setting module 50, when the switched-capacitor converter 200 first enters the pulse frequency modulation operating mode (i.e., after time t35), the frequency of the first pulse width modulation signal PWMA is limited, making its initial duty cycle close to 50% after entering the pulse frequency modulation operating mode. This makes the conversion process from the charge pump operating mode to the pulse frequency modulation operating mode not have sudden changes in the switching frequency or duty cycle.

[0145] From time t35 to time t36, the switched-capacitor converter 200 has been operating in a frequency-limited pulse-frequency modulation mode. During this period, the switching period T of each switching transistor in the switched-capacitor converter 200 remains unchanged. However, the duty cycle of the first pulse-width modulation signal PWMA gradually decreases as the output current IOUT decreases. Until time t36, the output current IOUT is small enough that the oscillation frequency of the output voltage VOUT between the second preset voltage VREFH and the first preset voltage VREFL is less than the preset frequency, and the switched-capacitor converter 200 officially enters the frequency-unlimited pulse-frequency modulation mode.

[0146] In some embodiments, the preset frequency is configured as the switching frequency of each switching transistor in the switched-capacitor converter when the switched-capacitor converter is in the charge-pump mode. Thus, it is possible to ensure that there are no sudden changes in the switching frequency or duty cycle during the conversion process between the charge-pump mode and the pulse-frequency modulation mode, which is beneficial for achieving a smoother working mode switching process.

[0147] In some embodiments, the mode switching module 30 is further configured to: when the switched-capacitor converter 200 is in the pulse-frequency modulation mode, and the duration of receiving the first indication signal SW_ON is greater than the first preset duration, and the difference between the duration of receiving the first indication signal SW_ON and half of the first switching period is less than the first preset difference, switch the working mode of the switched-capacitor converter 200 to the charge-pump mode, where the first switching period is the switching period of the switching transistors in the switched-capacitor converter 200 when the switched-capacitor converter 200 is in the charge-pump mode. Thus, it is possible to ensure that there are no sudden changes in the switching frequency or duty cycle during the conversion process from the pulse-frequency modulation mode to the charge-pump mode, which is beneficial for achieving a smoother working mode switching process.

[0148] In some embodiments, the mode switching module 30 is further configured to: when the switched-capacitor converter 200 is in the charge-pump mode, and the duration of receiving the second indication signal SW_OFF is greater than the second preset duration, and after M first switching periods have elapsed since the output voltage VOUT became equal to the second preset voltage, switch the working mode of the switched-capacitor converter 200 to the pulse-frequency modulation mode, where the first switching period is the switching period of each switching transistor in the switched-capacitor converter when the switched-capacitor converter is in the charge-pump mode, and M is an integer greater than or equal to 1. Thus, it is possible to ensure that there are no sudden changes in the switching frequency or duty cycle during the conversion process from the charge-pump mode to the pulse-frequency modulation mode, which is beneficial for achieving a smoother working mode switching process.

[0149] Please refer to Figure 17 , Figure 17Schematic diagram of the composition block diagram of the power conversion circuit provided by the embodiment of the present application. As Figure 17 shown, the power conversion circuit 1000 includes a switched-capacitor converter 200 and a control circuit 100 in any embodiment of the present application. The control circuit 100 is connected to the switched-capacitor converter 200.

[0150] Among them, the control circuit 100 outputs complementary first pulse-width modulation signal PWMA and second pulse-width modulation signal PWMB. The switched-capacitor converter 200 is configured to respond to the first pulse-width modulation signal PWMA and control the conduction of a part of the switching tubes in the switched-capacitor converter 200 during a part of the switching period of the switched-capacitor converter 200, so that the energy storage capacitor in the switched-capacitor converter 200 discharges to the output terminal. The switched-capacitor converter 200 is further configured to respond to the second pulse-width modulation signal PWMB and control the conduction of another part of the switching tubes in the switched-capacitor converter 200 during another part of the switching period of the switched-capacitor converter 200, so that the input voltage VIN of the switched-capacitor converter charges the energy storage capacitor in the switched-capacitor converter.

[0151] It should be understood that for the specific control of the control circuit 100 over the switched-capacitor converter 200 and the beneficial effects produced in this embodiment, reference can be made to the corresponding descriptions in the above embodiments of the control circuit 100 and the switched-capacitor converter 200. For the sake of brevity, it will not be elaborated here.

[0152] Please refer to Figure 18 , Figure 18 Flowchart of the control method provided by the embodiment of the present application. Among them, this control method is used to control the conduction or cut-off of the switching tubes in the switched-capacitor converter, where the switched-capacitor converter is used to convert the input voltage into an output voltage, and the ratio of the input voltage to the output voltage is N:1, and N is an integer greater than 1. In some embodiments, the switched-capacitor converter here can be implemented by the switched-capacitor converter 200 in the above embodiments, and the specific implementation process has been described in detail in the above embodiments and will not be elaborated here. As Figure 18 shown, this control method includes the following method steps:

[0153] Step 1801: The switched-capacitor converter is in the pulse frequency modulation operating mode.

[0154] Step 1802: When the output voltage drops to the first preset voltage, control the conduction of a part of the switching tubes in the switched-capacitor converter, so that the energy storage capacitor in the switched-capacitor converter discharges to the output terminal of the switched-capacitor converter.

[0155] Step 1803: When the output voltage rises to the second preset voltage, control another part of the switching transistors in the switched-capacitor converter to conduct, so that the input voltage of the switched-capacitor converter charges the energy storage capacitor, where the first preset voltage and the second preset voltage are both less than 1 / N of the input voltage, and the first preset voltage is less than the second preset voltage.

[0156] Take this control method for controlling Figure 1 the switched-capacitor converter 200 shown as an example. When the switched-capacitor converter 200 is in the pulse frequency modulation operating mode, when the output voltage VOUT drops to the first preset voltage VREFL, the switching transistors 202 and 204 (corresponding to a part of the switching transistors in the switched-capacitor converter 200) need to be controlled to conduct, so that the capacitor 205 (corresponding to the energy storage capacitor) is paralleled with the capacitor 207 and discharges to the capacitor 207 (corresponding to the output capacitor) and the load, thereby increasing the output voltage VOUT.

[0157] When the output voltage VOUT rises to the second preset voltage VREFH, the switching transistors 201 and 203 (corresponding to another part of the switching transistors in the switched-capacitor converter 200) need to be controlled to conduct, so that the input end of the switched-capacitor converter 200 provides current for the output end of the switched-capacitor converter 200 through the series-connected capacitors 205 and 207, and at the same time the capacitor 205 is charged and the output voltage VOUT decreases.

[0158] Step 1804: When the output voltage has not risen to the second preset voltage after the first preset duration from the moment when the output voltage drops to the first preset voltage, switch the operating mode of the switched-capacitor converter to the charge pump operating mode.

[0159] In some embodiments, as Figure 19 shown, this control method further includes the following method steps:

[0160] Step 1901: The switched-capacitor converter is in the charge pump operating mode.

[0161] Step 1902: Control the switching transistors in the switched-capacitor converter to alternately conduct and turn off with a duty cycle of 50%.

[0162] Step 1903: When, starting from the moment when the output voltage rises to the second preset voltage, the output voltage has not dropped to the first preset voltage after a duration greater than the second preset duration, switch the operating mode of the switched-capacitor converter to the pulse frequency modulation operating mode.

[0163] In some embodiments, the method further includes the following method steps: when the switched-capacitor converter is in the pulse-frequency modulation operating mode, controlling the conduction duration of a part of the switching transistors in the switched-capacitor converter to be greater than or equal to a first duration, that is, controlling the discharge duration of the energy storage capacitor in the switched-capacitor converter to the output terminal to be greater than or equal to the first duration.

[0164] In some embodiments, the method further includes the following method steps: when the switched-capacitor converter is in the pulse-frequency modulation operating mode, controlling the switching frequency of each switching transistor in the switched-capacitor converter to be less than or equal to a preset frequency.

[0165] In some embodiments, the preset frequency is configured as: the switching frequency of the switching transistors in the switched-capacitor converter when the switched-capacitor converter is in the charge pump operating mode.

[0166] In some embodiments, the difference between the first preset duration and half of the first switching period is less than a first preset difference, where the first switching period is the switching period of the switching transistors in the switched-capacitor converter when the switched-capacitor converter is in the charge pump operating mode, and the first preset duration is less than the first switching period.

[0167] In some embodiments, a second preset duration is greater than M first switching periods, where M is an integer greater than or equal to 1.

[0168] It should be understood that for the specific control of the switched-capacitor converter 200 and the beneficial effects generated in the method embodiments, reference may be made to the corresponding descriptions in the above embodiments of the control circuit 100 and the switched-capacitor converter 200. For the sake of brevity, they are not described herein again.

[0169] An embodiment of the present application further provides an electronic device, which includes the power conversion circuit 1000 in any embodiment of the present application.

[0170] The above are only the embodiments of the present application, and thus do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present application.

[0171] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; under the idea of the present application, the technical features in the above embodiments or different embodiments can also be combined, and the steps can be implemented in any order. Those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A control circuit, characterized in that, For outputting complementary first and second pulse width modulation signals for switching tubes in a switched-capacitor converter, wherein the switched-capacitor converter is used to convert an input voltage into an output voltage, and the ratio of the output voltage to the input voltage is 1:N, N being an integer greater than 1. The switched-capacitor converter includes at least four serially-connected switching tubes. The first switching tube and the third switching tube among the four switching tubes are controlled by the second pulse width modulation signal, and the second switching tube and the fourth switching tube among the four switching tubes are controlled by the first pulse width modulation signal. Moreover, the circuit formed by the four switching tubes is directly connected to the voltage output terminal. The control circuit includes: A signal generation module, which inputs the input voltage and the output voltage, and is configured to output a first indication signal when the output voltage drops to a first preset voltage and output a second indication signal when the output voltage rises to a second preset voltage when the switched-capacitor converter is in a pulse frequency modulation operating mode. Wherein, both the first preset voltage and the second preset voltage are less than 1 / N of the input voltage, and the first preset voltage is less than the second preset voltage; A signal setting module, connected to the signal generation module, and is configured to set the first pulse width modulation signal and the second pulse width modulation signal to signals with a duty cycle of 50% when the switched-capacitor converter is in a charge pump operating mode, and is configured to set the first pulse width modulation signal to a high level if the first indication signal is received and set the second pulse width modulation signal to a high level if the second indication signal is received when the switched-capacitor converter is in a pulse frequency modulation operating mode.

2. The control circuit according to claim 1, characterized in that The control circuit further includes: A mode switching module, connected to the signal generation module and the signal setting module respectively, and is configured to switch the operating mode of the switched-capacitor converter to a charge pump operating mode when the switched-capacitor converter is in a pulse frequency modulation operating mode and the duration of receiving the first indication signal is greater than a first preset duration, and is configured to switch the operating mode of the switched-capacitor converter to a pulse frequency modulation operating mode when the switched-capacitor converter is in a charge pump operating mode and the duration of receiving the second indication signal is greater than a second preset duration.

3. The control circuit according to claim 1, wherein The signal generation module includes a first comparator, a second comparator and a first latch; The non-inverting input terminal of the first comparator inputs the first preset voltage, the inverting input terminal of the first comparator inputs the output voltage, the output terminal of the first comparator is connected to the set terminal of the first latch, the inverting input terminal of the second comparator inputs the second preset voltage, the non-inverting input terminal of the second comparator inputs the output voltage, the output terminal of the second comparator is connected to the reset terminal of the first latch, the non-inverting output terminal of the first latch is used to output the first indication signal, and the inverting output terminal of the first latch is used to output the second indication signal.

4. The control circuit according to claim 3, characterized in that The control circuit further includes: A pulse width setting module, connected to the signal generation module, is configured to output a first pulse to the signal generation module when the signal generation module outputs the first indication signal, wherein the pulse width of the first pulse is a first duration; The signal generation module is further configured to output the second indication signal after the first pulse ends and the output voltage has risen to the second preset voltage.

5. The control circuit according to claim 4, wherein The signal generation module further includes a first AND gate, and the pulse width setting module includes a first single flip-flop and a first NOT gate; The input end of the first single flip-flop is connected to the in-phase output end of the first latch, the output end of the first single flip-flop is connected to the input end of the first NOT gate, the output end of the first NOT gate is connected to the second input end of the first AND gate, the first input end of the first AND gate is connected to the output end of the second comparator, and the output end of the first AND gate is connected to the reset end of the first latch.

6. The control circuit according to claim 3, characterized in that, The control circuit further includes: A frequency setting module, connected to the signal generation module, is configured to determine the switching frequency of the switching tube in the switched-capacitor converter based on the first indication signal and the second indication signal, and output a frequency setting signal when the switching frequency is less than or equal to a preset frequency; The signal generation module is further configured to output the first indication signal when receiving the frequency setting signal and the output voltage is less than the first preset voltage.

7. The control circuit according to claim 6, characterized in that, The preset frequency is configured to be the switching frequency of the switching tube in the switched-capacitor converter when the switched-capacitor converter is in the charge pump operating mode.

8. The control circuit according to claim 6 or 7, characterized in that, The signal generation module further includes a second AND gate, and the frequency setting module includes a first OR gate, a first switch, a second switch, a first current source, a second single flip-flop, a first capacitor and a third comparator; The first input end of the first OR gate is connected to the in-phase output end of the first latch, the second input end of the first OR gate is connected to the anti-phase output end of the first latch, the output end of the first OR gate outputs a signal for controlling the first switch, the first switch is connected between the first current source and the in-phase input end of the third comparator, the second switch is connected between the in-phase input end of the third comparator and the ground, the first capacitor is connected in parallel with the second switch, the anti-phase input end of the third comparator inputs a voltage corresponding to the preset frequency, the output end of the third comparator is connected to the first input end of the second AND gate, the second input end of the second AND gate is connected to the output end of the first comparator, and the output end of the second AND gate is connected to the set end of the first latch.

9. The control circuit according to claim 2, wherein The mode switching module is further configured to: when the switched-capacitor converter is in the pulse frequency modulation operating mode, and the duration of receiving the first indication signal is greater than a first preset duration, and the difference between the duration of receiving the first indication signal and half of the first switching period is less than a first preset difference, switch the operating mode of the switched-capacitor converter to the charge pump operating mode, where the first switching period is the switching period of the switching transistor in the switched-capacitor converter when the switched-capacitor converter is in the charge pump operating mode.

10. The control circuit according to claim 2, wherein The mode switching module is further configured to: when the switched-capacitor converter is in the charge pump operating mode, and the duration of receiving the second indication signal is greater than a second preset duration, and after M first switching periods have elapsed after the output voltage is equal to the second preset voltage, switch the operating mode of the switched-capacitor converter to the pulse frequency modulation operating mode, where the first switching period is the switching period of the switching transistor in the switched-capacitor converter when the switched-capacitor converter is in the charge pump operating mode, and M is an integer greater than or equal to 1.

11. The control circuit according to any one of claims 2, 9 or 10, characterized in that, The mode switching module includes a third AND gate, a fourth AND gate, a second NOT gate, a third NOT gate, a third switch, a fourth switch, a fifth switch, a sixth switch, a second capacitor, a third capacitor, a second current source, a third current source, a fourth comparator, a fifth comparator, and a second latch. The first input terminal of the third AND gate inputs the first indication signal, the second input terminal of the third AND gate inputs a third indication signal indicating that the switched-capacitor converter is in the pulse frequency modulation operating mode, the output terminal of the third AND gate outputs a signal for controlling the third switch, the output terminal of the third AND gate is further connected to the input terminal of the second NOT gate, the output terminal of the second NOT gate outputs a signal for controlling the fourth switch, the third switch is connected between the second current source and the non-inverting input terminal of the fourth comparator, the second capacitor is connected between the non-inverting input terminal of the fourth comparator and the ground, the fourth switch is connected in parallel with the second capacitor, the inverting input terminal of the fourth comparator inputs a voltage corresponding to the first preset duration, and the output terminal of the fourth comparator is connected to the set terminal of the second latch. The first input terminal of the fourth AND gate inputs the second indication signal, the second input terminal of the fourth AND gate inputs a fourth indication signal indicating that the switched-capacitor converter is in the charge pump operating mode, the output terminal of the fourth AND gate outputs a signal for controlling the fifth switch, the output terminal of the fourth AND gate is further connected to the input terminal of the third NOT gate, the output terminal of the third NOT gate outputs a signal for controlling the sixth switch, the fifth switch is connected between the third current source and the non-inverting input terminal of the fifth comparator, the third capacitor is connected between the non-inverting input terminal of the fifth comparator and the ground, the fifth switch is connected in parallel with the third capacitor, the inverting input terminal of the fifth comparator inputs a voltage corresponding to the second preset duration, the output terminal of the fifth comparator is connected to the reset terminal of the second latch, the non-inverting output terminal of the second latch outputs the fourth indication signal, and the inverting output terminal of the second latch outputs the third indication signal.

12. The control circuit according to claim 1, wherein The signal setting module includes a second OR gate, a third OR gate, a fourth OR gate, a fifth OR gate, a seventh switch, an eighth switch, a fourth capacitor, a fifth capacitor, a fourth current source, a fifth current source, a sixth comparator, a seventh comparator, a third single flip-flop, a fourth single flip-flop, and a third latch; The first input terminal of the second OR gate is connected to the first input terminal of the third OR gate and inputs a third indication signal indicating that the switched-capacitor converter is in the pulse frequency modulation operating mode. The second input terminal of the second OR gate is respectively connected to the non-inverting output terminal of the third latch and a switching transistor in the switched-capacitor converter, and the non-inverting output terminal of the third latch outputs the first pulse width modulation signal. The output terminal of the second OR gate outputs a signal for controlling the seventh switch. The seventh switch is connected between the non-inverting input terminal of the sixth comparator and the ground. The fourth capacitor is connected in parallel with the seventh switch. The non-inverting input terminal of the sixth comparator is further connected to the fourth current source. The inverting input terminal of the sixth comparator inputs a third preset voltage. The output terminal of the sixth comparator is connected to the first input terminal of the fourth OR gate. The second input terminal of the fourth OR gate is connected to the output terminal of the third single flip-flop. The input terminal of the third single flip-flop inputs the first indication signal. The output terminal of the fourth OR gate is connected to the set terminal of the third latch; The second input terminal of the third OR gate is respectively connected to the inverted output terminal of the third latch and the switching transistor in the switched-capacitor converter, and the inverted output terminal of the third latch outputs the second pulse-width modulation signal. The output terminal of the third OR gate outputs a signal for controlling the eighth switch. The eighth switch is connected between the non-inverting input terminal of the seventh comparator and the ground. The fifth capacitor is connected in parallel with the eighth switch. The non-inverting input terminal of the seventh comparator is further connected to the fifth current source. The inverting input terminal of the seventh comparator inputs the third preset voltage. The output terminal of the seventh comparator is connected to the first input terminal of the fifth OR gate. The second input terminal of the fifth OR gate is connected to the output terminal of the fourth single flip-flop. The input terminal of the fourth single flip-flop inputs the second indication signal. The output terminal of the fifth OR gate is connected to the reset terminal of the third latch.

13. A power conversion circuit, characterized in that, Comprising a switched-capacitor converter and a control circuit as claimed in any one of claims 1-12, the control circuit being connected to the switched-capacitor converter; The control circuit outputs complementary first and second pulse-width modulation signals; The switched-capacitor converter is configured to, in response to the first pulse-width modulation signal, control a part of the switching transistors in the switched-capacitor converter to conduct during a part of the switching period of the switched-capacitor converter, so that the input voltage of the switched-capacitor converter charges the energy storage capacitor in the switched-capacitor converter; The switched-capacitor converter is further configured to, in response to the second pulse-width modulation signal, control another part of the switching transistors in the switched-capacitor converter to conduct during another part of the switching period of the switched-capacitor converter, so that the energy storage capacitor discharges to the output terminal in the switched-capacitor converter.

14. A control method, characterized in that, For controlling the conduction or cutoff of the switching transistors in a switched-capacitor converter, wherein the switched-capacitor converter is used to convert an input voltage into an output voltage, the ratio of the input voltage to the output voltage is N:1, N is an integer greater than 1, the switched-capacitor converter includes at least four series-connected switching transistors, the first and third switching transistors among the four switching transistors are controlled by the second pulse-width modulation signal, the second and fourth switching transistors among the four switching transistors are controlled by the first pulse-width modulation signal, and the circuit formed by the four switching transistors is directly connected to the voltage output terminal. The control method includes: When the switched-capacitor converter is in the pulse frequency modulation operating mode, perform the following steps: When the output voltage drops to the first preset voltage, control a part of the switching transistors in the switched-capacitor converter to conduct, so that the energy storage capacitor in the switched-capacitor converter discharges to the output terminal of the switched-capacitor converter; When the output voltage rises to a second preset voltage, control another part of the switching transistors in the switched-capacitor converter to conduct, so that the input voltage of the switched-capacitor converter charges the energy storage capacitor, where the first preset voltage and the second preset voltage are both less than 1 / N of the input voltage, and the first preset voltage is less than the second preset voltage; When the output voltage has not risen to the second preset voltage after a first preset duration from the moment when the output voltage drops to the first preset voltage, switch the operating mode of the switched-capacitor converter to the charge pump operating mode.

15. The control method according to claim 14, characterized in that, The method further includes: When the switched-capacitor converter is in the charge pump operating mode, perform the following steps: Control the switching transistors in the switched-capacitor converter to alternately conduct and turn off with a duty cycle of 50%; When the output voltage has not dropped to the first preset voltage after a time greater than a second preset duration from the moment when the output voltage rises to the second preset voltage, switch the operating mode of the switched-capacitor converter to the pulse frequency modulation operating mode.

16. The control method according to claim 15, wherein The method further includes: When the switched-capacitor converter is in the pulse frequency modulation operating mode, control the duration of each discharge of the energy storage capacitor in the switched-capacitor converter to the output terminal to be greater than or equal to a first duration.

17. The control method according to claim 15, characterized in that, The method further includes: When the switched-capacitor converter is in the pulse frequency modulation operating mode, control the switching frequency of the switching transistors in the switched-capacitor converter to be less than or equal to a preset frequency.

18. The control method according to claim 17, wherein The preset frequency is configured as: the switching frequency of the switching transistors in the switched-capacitor converter when the switched-capacitor converter is in the charge pump operating mode.

19. The control method according to claim 15, wherein The difference between the first preset duration and half of the first switching period is less than a first preset difference, where the first switching period is the switching period of the switching transistors in the switched-capacitor converter when the switched-capacitor converter is in the charge pump operating mode, and the first preset duration is less than the first switching period.

20. The control method according to claim 15, wherein The second preset duration is greater than M first switching periods, where M is an integer greater than or equal to 1.

21. An electronic device, characterized in that, Includes the power conversion circuit according to claim 13.

Images