Peak voltage threshold generation circuit, switching power supply, electronic device, and chip

Abstract

The application discloses a peak voltage threshold generation circuit, a switching power supply, an electronic device and a chip. The circuit comprises a peak voltage threshold subtraction circuit, a jitter control circuit and a voltage division jitter circuit. The subtraction circuit comprises a first resistor and a mirror current branch of a current mirror connected in series between an output feedback voltage end and a first ground end, and is used for outputting a subtraction voltage. An input end of the jitter control circuit is connected with a pulse signal generator, an output end is connected with a first input end of the voltage division jitter circuit, and is used for outputting a control signal. The control signal is used for adjusting a peak voltage threshold output by the peak voltage threshold voltage division jitter circuit. A second input end of the voltage division jitter circuit is connected with an output end of the subtraction circuit, and is used for outputting different peak voltage thresholds according to the subtraction voltage and the control signal. The application can flexibly set the system frequency hysteresis.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic equipment, in particular to a peak voltage threshold generation circuit, a switching power supply, an electronic device and a chip. BACKGROUND

[0002] Switching power supplies are widely used in the electronic field, such as mobile phone chargers, televisions and other equipment. For example, a commonly used flyback switching power supply. Flyback switching power supplies have been widely used in the electronic field of mobile phone chargers, televisions and other equipment due to their simple circuit structure, small electromagnetic interference and low cost.

[0003] Referring to Figure 1 , Figure 1 A flyback switching power supply is shown, which mainly includes a flyback transformer T1, a feedback loop and a modulation loop. Among them, the feedback loop is connected with the output end Vo of the flyback switching power supply, which is used to reflect the change of the load connected with the output end Vo to the modulation loop of the flyback switching power supply, so as to adjust the duty cycle of the control signal through the modulation loop to ensure the stability of the voltage output by the output end of the flyback switching power supply.

[0004] At present, the flyback switching power supply mainly adopts voltage mode control and peak current mode control, while the voltage mode control has the disadvantages of slow system response speed and difficult loop compensation, so the peak current mode control gradually becomes the mainstream control method. The peak current mode uses the peak current value of the primary winding to control the output voltage, which can reflect the output voltage information and the current information, so the system transient response speed is fast, and the feedback loop has only one pole, and the compensation network design is simpler.

[0005] Exemplarily, Figure 1The application relates to a peak current mode control system block diagram of a pulse width modulation (PWM) flyback switching power supply. A resistor Rcs samples a primary winding inductance current and converts the same into a sampling voltage Vcs, which is then sent to a positive input end of a PWM comparator. A TL431 and an optocoupler are connected to an output end of the flyback switching power supply, so that an output feedback voltage VFB is obtained through the TL431 and the optocoupler. In addition, in order to reduce the sampling power consumption of the primary inductance current, the resistance value of the sampling resistor Rcs is usually reduced, so that the feedback voltage VFB also needs to be correspondingly reduced, and then a peak voltage threshold VTH is obtained, and the VTH is sent to a negative input end of the PWM comparator. The PWM comparator compares the sampling voltage Vcs with the peak voltage threshold VTH, when the Vcs is greater than the VTH, the PWM comparator outputs change from low to high, the RS flip-flop is reset, a low voltage is output, and the power tube Q1 is turned off through a driving circuit; the oscillator controls the opening of the power tube Q1 through the RS flip-flop and the driving circuit, so as to adjust the duty cycle of a driving signal DRV, thereby stabilizing the output voltage. Figure 1 For more details, please refer to the attached Figure 1 Or refer to the related description of the prior art, which will not be described in detail herein.

[0006] From Figure 1 It can be known that the peak voltage threshold VTH is a very important parameter in the switching power supply, and therefore the setting of the peak voltage threshold VTH has also attracted attention in the industry. Exemplarily, a peak voltage threshold generating circuit is shown in the formula (1) as shown in the formula (1), the circuit realizes voltage subtraction through a first operational amplifier OP1 and a second operational amplifier OP2 to generate a subtraction voltage Vsub signal, and the Vsub is as follows: Figure 2

[0007]

[0008] And then the peak voltage threshold VTH is obtained through resistance voltage division, and the VTH is as follows:

[0009]

[0010] From the above formula (2), it can be known that the proportionality coefficient of each resistor can be reasonably set to obtain a suitable peak voltage threshold VTH. Although the two operational amplifiers (the first operational amplifier and the second operational amplifier) and the resistance voltage division are used to realize voltage subtraction, the proportionality coefficient can also be accurately set, but the two operational amplifiers will cause the problems of large area consumption and standby power consumption, which is contrary to the development trend of miniaturization and low power consumption of the switching power supply chip; and when the Vsub needs to be adjusted, the sizes of the four resistors R18, R19, R21 and R22 need to be considered at the same time, so that the size of the Vsub cannot be flexibly controlled, and the frequency hysteresis is serious.​ SUMMARY

[0011] The purpose of the present application is to provide a peak voltage threshold generation circuit, a switching power supply, an electronic device and a chip to solve the problems described in the background art.

[0012] To achieve the above purpose, the present application provides the following solutions.

[0013] In a first aspect, the present application provides a peak voltage threshold generation circuit, comprising: a peak voltage threshold subtraction circuit, a peak voltage threshold jitter control circuit and a peak voltage threshold voltage division jitter circuit.

[0014] The peak voltage threshold subtraction circuit comprises a first resistor and a current mirror, and a mirror current branch of the current mirror is connected between an output feedback voltage end and a first ground end in sequence; an output end of the peak voltage threshold subtraction circuit is connected between the first resistor and the mirror current branch, for outputting a subtraction voltage.

[0015] The input end of the peak voltage threshold jitter control circuit is connected with the output end of the clock pulse signal generator, the output end is connected with the first input end of the peak voltage threshold voltage division jitter circuit, for outputting a control signal, and the control signal is used to adjust the peak voltage threshold output by the peak voltage threshold voltage division jitter circuit.

[0016] The second input end of the peak voltage threshold voltage division jitter circuit is connected with the output end of the peak voltage threshold subtraction circuit, for outputting different peak voltage thresholds according to the subtraction voltage and the control signal.

[0017] Optionally, the peak voltage threshold jitter control circuit comprises a frequency division circuit and a decoding circuit; the input end of the frequency division circuit is connected with the output end of the clock pulse signal generator, a plurality of clock pulse signal output ends of the frequency division circuit are connected with a plurality of clock pulse signal input ends of the decoding circuit in correspondence, and a plurality of output ends of the decoding circuit are connected with the first input end of the peak voltage threshold voltage division jitter circuit in correspondence, for controlling the number of resistors accessed to the peak voltage threshold voltage division jitter circuit through the pulse signals outputted thereby.

[0018] Optionally, the peak voltage threshold voltage dividing and dithering circuit comprises a third operational amplifier, a first MOS transistor, a third resistor, a plurality of dithering resistors connected in series, a twelfth resistor and a second ground terminal connected in series, the positive input terminal of the third operational amplifier is connected with the output terminal of the peak voltage threshold subtraction circuit, the negative input terminal of the third operational amplifier is connected with the third resistor, the output terminal of the third operational amplifier is connected with the gate of the first MOS transistor, and the output terminal of the peak voltage threshold voltage dividing and dithering circuit is arranged between the twelfth resistor and the plurality of dithering resistors connected in series; each dithering resistor of the plurality of dithering resistors connected in series is connected with a first switch in parallel, so that the number of resistors connected in the peak voltage threshold voltage dividing and dithering circuit is controlled by controlling the first switch to be opened or closed through the pulse signal.

[0019] Optionally, the decoding circuit comprises a decoder, a first auxiliary circuit and a second auxiliary circuit.

[0020] The decoder receives q0-q2 sent by the D flip-flop at the input terminal, and is controlled by q0 and the clock pulse signal at the reset terminal, and the output terminal is s0-s7, s0-s7 become high level in turn with the period Tclk of the clock pulse signal, and s0-s7 are sent to the first auxiliary circuit.

[0021] The first auxiliary circuit comprises four RS flip-flops, and s0-s3 are sent to the set terminals of the four RS flip-flops respectively, and s7-s4 are sent to the reset terminals of the four RS flip-flops; the output terminals of the four RS flip-flops obtain st <m>A signal, wherein;

[0022] The second auxiliary circuit comprises eight combinational logic circuits, respectively denoted as a first combinational logic circuit to an eighth combinational logic circuit; the first four combinational logic circuits are NAND gates; the last four combinational logic circuits are combinations of NAND gates and inverters, and the NAND gate is the receiving end and the inverter is the output end; st <m>The outputs j<0>~j<3> are obtained by combining q3n with the previous four combinational logic circuits, respectively, and st <m>respectively, through the last four combinational logic circuits to obtain j4~j7; the control signals are denoted as j <f>When the q3 is in a low level state, the initial values of j<0>~j<3> are high levels, and are changed to low levels in turn at intervals of 2Tclk; when the q3 is in a high level state, the initial values of j<4>~j<7> are low levels, and are changed to high levels in turn at intervals of 2Tclk.

[0023] Optionally, the frequency dividing circuit comprises a plurality of D edge flip-flops connected in series, and for each adjacent two D edge flip-flops, a D input end of a former D edge flip-flop is connected with a reverse output end thereof, and a positive output end of the former D edge flip-flop is connected with a clock signal input end of a latter D edge flip-flop.

[0024] The positive output end of the D edge flip-flop is further connected with a frequency dividing level signal input end of the decoding circuit.

[0025] The positive output end and the reverse output end of the D edge flip-flop connected at the end of the frequency dividing circuit are connected with an input end of the second auxiliary circuit.

[0026] Optionally, the plurality of jittering resistors included in the peak voltage threshold value dividing and jittering circuit have the same resistance.

[0027] Optionally, the reference current branch of the current mirror is connected between a reference current generating circuit and the first ground end, and the current mirror is a cascode current mirror.

[0028] In a second aspect, the application provides a switching power supply, which comprises a transformer, a feedback loop and a modulation loop, the modulation loop comprising the peak voltage threshold value generating circuit according to any one of the first aspect, one end of the transformer is connected with a diode, the switching power supply output end is arranged at an end of the diode away from the secondary side of the transformer, one end of the feedback loop is connected with the output end of the switching power supply, the other end of the feedback loop is connected with one end of the peak voltage threshold value generating circuit, and the other end of the peak voltage threshold value generating circuit is connected with the primary side of the transformer.

[0029] Optionally, the switching power supply is a flyback switching power supply, and the transformer is a flyback transformer.

[0030] In a third aspect, the application provides an electronic device, which is internally provided with the switching power supply according to any one of the second aspect.

[0031] In a fourth aspect, the application provides a chip, which is provided with the peak voltage threshold value generating circuit according to any one of the first aspect.

[0032] According to the embodiments provided in the application, the following technical effects are disclosed:

[0033] The embodiment of the present application provides a peak voltage threshold generation circuit, a switching power supply, an electronic device and a chip. The peak voltage threshold generation circuit uses a resistor and a current mirror instead of an amplifier and a diode in the prior art. The resistor and the current mirror are simple in structure, small in size, low in power consumption and easy to replace. In the prior art, the amplifier and the diode used in the peak voltage threshold generation circuit are large in area resource and standby power consumption. Therefore, compared with the prior art, the circuit structure of the peak voltage threshold generation circuit provided by the present application is flexible and simple, and the circuit area occupied and the power consumption are reduced. Compared with the prior art as shown in the figure, the present application can flexibly adjust the subtraction voltage by changing the resistance value of the resistor or the size of the reference current, so as to meet the flexible control requirement of frequency hysteresis of the system. Figure 2 The embodiment of the present application provides a peak voltage threshold generation circuit, a switching power supply, an electronic device and a chip. The peak voltage threshold generation circuit uses a resistor and a current mirror instead of an amplifier and a diode in the prior art. The resistor and the current mirror are simple in structure, small in size, low in power consumption and easy to replace. In the prior art, the amplifier and the diode used in the peak voltage threshold generation circuit are large in area resource and standby power consumption. Therefore, compared with the prior art, the circuit structure of the peak voltage threshold generation circuit provided by the present application is flexible and simple, and the circuit area occupied and the power consumption are reduced. Compared with the prior art as shown in the figure, the present application can flexibly adjust the subtraction voltage by changing the resistance value of the resistor or the size of the reference current, so as to meet the flexible control requirement of frequency hysteresis of the system. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0035] Figure 1 A PWM type flyback switching power supply peak current mode control system block diagram is provided for the prior art;

[0036] Figure 2 A peak voltage threshold generation circuit is provided for the prior art;

[0037] Figure 3 Another peak voltage threshold generation circuit is provided for the prior art;

[0038] Figure 4 A peak voltage threshold generation circuit is provided for an embodiment of the present application;

[0039] Figure 5 A peak voltage threshold subtraction circuit is provided for an embodiment of the present application;

[0040] Figure 6 A frequency division circuit is provided for an embodiment of the present application;

[0041] Figure 7 A decoding circuit is provided for an embodiment of the present application;

[0042] Figure 8 A decoder schematic diagram is provided for an embodiment of the present application;

[0043] Figure 9 An embodiment of the present application provides a first auxiliary circuit.

[0044] Figure 10 An embodiment of the present application provides a second auxiliary circuit.

[0045] Figure 11 An embodiment of the present application provides a peak voltage threshold voltage division jitter circuit. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0047] The above purposes, features and advantages of the present application can be more obvious and easy to understand. The present application will be further described in detail below with reference to the drawings and specific embodiments.

[0048] Before describing the embodiments of the present application, another peak voltage threshold generation circuit in the prior art is briefly introduced, as shown in FIG. 1. Figure 3 The circuit realizes voltage subtraction by using the base-emitter saturation voltage VBE of the transistor Q2, and then obtains the peak voltage threshold VTH by resistance voltage division. VTH is as follows:

[0049]

[0050] The ideal VTH can be obtained by reasonably setting the resistance proportionality coefficient. The circuit has simple structure and low power consumption, but the VBE of the transistor is a fixed voltage, so it is difficult for the system to flexibly adjust it.

[0051] In an exemplary embodiment of the present application, as shown in FIG. 2, a peak voltage threshold generation circuit is provided, which comprises a peak voltage threshold subtraction circuit, a peak voltage threshold jitter control circuit and a peak voltage threshold voltage division jitter circuit. Figure 4 Referring to FIG. 2, the peak voltage threshold subtraction circuit comprises a first resistor R1 and a current mirror, and a mirror current branch of the current mirror is connected between an output feedback voltage end and a first ground end in sequence.

[0052] Figure 5

[0053] ​​The input end of the peak voltage threshold value dithering control circuit is connected with the output end of the clock pulse signal generator, the output end is connected with the first input end of the peak voltage threshold value voltage dividing dithering circuit, and is used for outputting a control signal, the control signal is used for adjusting the peak voltage threshold value output by the peak voltage threshold value voltage dividing dithering circuit; further, the number of resistors connected to the peak voltage threshold value voltage dividing dithering circuit is controlled by the control signal;

[0054] The second input end of the peak voltage threshold value voltage dividing dithering circuit is connected with the output end of the peak voltage threshold value subtraction circuit, and is used for outputting different peak voltage threshold values according to the subtraction voltage and the control signal; further, the second input end receives the subtraction voltage output by the peak voltage threshold value subtraction circuit, and different numbers of resistors are connected under the control of the peak voltage threshold value dithering control circuit, so that the subtraction voltage is divided to output different peak voltage threshold values.

[0055] The above-mentioned peak voltage threshold value generating circuit is part of a switching power supply, wherein the output end of the switching power supply is used for connecting other circuits, which are referred to as loads of the switching power supply in the present application.

[0056] The output feedback voltage end is used for receiving the output feedback voltage VFB fed back by the above-mentioned load, and is used for feeding back the demand of the load for electric energy, the value of the output feedback voltage VFB is larger when the demand of the load for electric energy is higher, and the value of the output feedback voltage VFB is smaller when the demand of the load for electric energy is smaller.

[0057] The current mirror includes a reference current branch and a mirror current branch, the reference current branch is a circuit connected with the reference current generating circuit, and the mirror current branch is a circuit controlled by the reference current branch.

[0058] The current in the mirror current branch is k times of the current in the reference current branch; wherein, k is determined by the ratio of the width-length ratio of the second MOS tube in the reference current branch to the width-length ratio of the second MOS tube in the mirror current branch, wherein the MOS tube in the mirror current branch is referred to as the second MOS tube, and the mirror current branch includes four second MOS tubes.

[0059] The reference current branch of the current mirror is connected between the reference current generating circuit and the first ground end. In another exemplary embodiment of the present application, still referring to Figure 5 , the current mirror is a cascode current mirror. The cascode current mirror can copy the same temperature coefficient current after copying, and can improve the accuracy of the current copying. Optionally, the MOS tube in the cascode current mirror is an NMOS tube.

[0060] Exemplarily, Figure 5 Taking the cascode current mirror as an example, the second MOS tubes in the mirror current branch are NMOS tubes, which are respectively a second NMOS tube NM2, a second NMOS tube NM3, a second NMOS tube NM4 and a second NMOS tube NM5, the width-length ratio of NM4 is a first ratio, the width-length ratio of NM5 is a second ratio, the k value is the ratio of the second ratio to the first ratio, that is, k=(W / L)5 / (W / L)4. Then the same temperature coefficient current Isub=k*Iref is obtained after the reference current Iref is copied through the cascode current mirror, and then the subtraction voltage Vsub can be expressed by the following formula (4):

[0061] Vsub=VFB-k*Iref*R1 (4)

[0062] In addition, it can be known from formula (4) that as long as the first resistance R1 and the resistance used to generate the reference current Iref are of the same type, the process, voltage and temperature (English full name: Process, Voltage and Temperature; English abbreviation: PVT) changes caused by different types of resistances can be eliminated, thereby obtaining an accurate Vsub voltage. And the resistance value of the first resistance R1 can be set to flexibly change the Vsub voltage. Compared with the circuits shown in Figure 2 and Figure 3 The circuit structure of the present application is simpler and more flexible, not only realizes high-precision subtraction operation, but also saves area resources and standby power consumption.

[0063] Here, the frequency hysteresis refers to the realization of the frequency hysteresis when the output feedback voltage VFB is subtracted by a voltage (ΔV=k*Iref*R1) and fed back to the input end of the PWM comparator. The main advantage is that ΔV can be flexibly adjusted by directly changing the resistance R1 according to system requirements, that is, the system frequency hysteresis is flexibly set, and the area resource occupation and standby power consumption are reduced.

[0064] In addition, it should be noted that the present application can adjust the subtraction voltage by changing the resistance value, or adjust the subtraction voltage by changing the size of the reference current, to meet the flexible control requirements of the system on the frequency hysteresis. In actual use, the resistance is easier to adjust, for example, multiple backup resistors of different resistance values can be replaced according to requirements.

[0065] The peak voltage threshold subtraction circuit here is mainly used to set the frequency hysteresis according to system requirements, prevent the valley bottom from jumping when the valley bottom is locked, and optimize the system efficiency.

[0066] The area resource here refers to the prior art, such as Figure 3 Two operational amplifiers are used in the prior art, Figure 2 The triode, the operational amplifier and the triode occupy a large layout area, and therefore the application saves the chip area, and compared with Figure 2 The circuit structure of the application replaces the subtraction circuit structure of the operational amplifier, and reduces the standby power consumption of the chip.

[0067] In another exemplary embodiment of the application, referring to Figure 6 and Figure 7 The peak voltage threshold value jitter control circuit comprises a frequency division circuit and a decoding circuit, a plurality of clock pulse signal output ends of the frequency division circuit are connected to a plurality of clock pulse signal input ends of the decoding circuit in a one-to-one correspondence, and a plurality of output ends of the decoding circuit are connected to a plurality of first switches of the peak voltage threshold value voltage division jitter circuit in a one-to-one correspondence.

[0068] The one-to-one correspondence in the application can be understood as that the ports of the plurality of output ends are connected to the ports of the plurality of input ends in a one-to-one correspondence, so as to ensure that the output clock pulse signal of each frequency division circuit is received by the input end of the decoding circuit, and each first switch is connected to an output end of the decoding circuit.

[0069] Optionally, referring to Figure 7 The frequency division circuit comprises a plurality of D edge flip-flops connected in series, and for each adjacent two D edge flip-flops, a D input end of a preceding D edge flip-flop is connected to an output reverse end thereof, and an output forward end of the preceding D edge flip-flop is connected to a clock pulse signal input end of a subsequent D edge flip-flop.

[0070] The output forward end of the D edge flip-flop is also connected to a frequency division level signal input end of the decoding circuit, that is, q0-q2.

[0071] The output forward end and the output reverse end of the D edge flip-flop connected at the last end in the frequency division circuit are connected to an input end of the second auxiliary circuit.

[0072] The frequency division circuit comprises a plurality of D edge flip-flops, each D edge flip-flop can divide the received clock pulse signal and output a new clock pulse signal, and send the new clock pulse signal to the next D edge flip-flop and the decoding circuit. Each D edge flip-flop comprises at least one clock pulse signal output end, so that the frequency division circuit comprises a plurality of clock pulse signal output ends.

[0073] The D input end of the D flip-flop is connected to the output reverse end Q non (that is, Qb in the figure), and the output forward end Q of the previous D flip-flop is sent to the clock pulse signal input end in the next D flip-flop, so as to achieve the effect of counting and frequency division.

[0074] For the decoding circuit, a plurality of input terminals are used to receive a plurality of clock pulse signals sent by the frequency division circuit. The plurality of clock pulse signals can be regarded as a group of clock pulse signals. For each group of different clock signals, one or more output terminals of the decoding circuit are made high, thereby controlling the number of high-level output terminals of the decoding circuit.

[0075] Further, referring to Figures 8-10 , the decoding circuit includes a decoder, a first auxiliary circuit and a second auxiliary circuit.

[0076] For the decoder, referring to Figure 8 , the decoder is taken as an example of a 3-8 decoder. The input terminal receives q0-q2 sent by the D flip-flop. The reset terminal of the 3-8 decoder is low in level and is effective, and is controlled by q0 and the clock pulse signal. The output terminal is s0-s7, which becomes high in turn at intervals of the period Tclk of the clock pulse signal. s0-s3 are sent to the set terminal of the RS flip-flop, and s7-s4 are sent to the reset terminal of the RS flip-flop. For more details of the decoder, refer to the related prior art, which will not be described herein.

[0077] For the first auxiliary circuit, referring to Figure 9 , it includes four RS flip-flops. s0-s3 are sent to the set terminal of the RS flip-flop, and s4-s7 are sent to the reset terminal of the RS flip-flop. In this way, the output terminals of the four RS flip-flops obtain st <m>signal, here 0 < m < 3.

[0078] For the second auxiliary circuit: see Figure 10 , including 8 combinational logic circuits, respectively, the first combinational logic circuit to the eighth combinational logic circuit, the first four combinational logic circuits are NAND gates, and the last four combinational logic circuits are the combination of NAND gates and inverters; st <m>The outputs j<0>~j<3> are obtained by combining q3n with the previous four combinational logic circuits, respectively, and st <m>The control signals j are obtained by passing q3 through the last four combinatorial logic circuits, respectively, to obtain j<4>~j<7> <f>, where 0≤f≤7. Among them, when q3 is low, the initial value of j<0>~j<3> is high, and it becomes low in turn every 2Tclk; when q3 is high, the initial value of j<4>~j<7> is low, and it becomes high in turn every 2Tclk. Thus, the number of low levels in j<0>~j<7> changes regularly as 4, 3, 2, 1, 0, 1, 2, 3, 4, 5, 6, 7, 8, 7, 6, 5 as a change cycle, and then the number of resistors in the peak voltage threshold voltage division jitter circuit changes regularly as 4, 3, 2, 1, 0, 1, 2, 3, 4, 5, 6, 7, 8, 7, 6, 5 as a change cycle. Thus, the first switch in the peak voltage threshold voltage division jitter circuit is controlled by j<0>~j<7>.

[0079] Further, the jittered peak voltage threshold VTH can be represented by the following formula (5):

[0080]

[0081] In formula (5), n is determined by threshold jitter signals j<0>~j<7>, and 1≤n≤8.

[0082] In another exemplary embodiment of the present application, referring to Figure 11 , the peak voltage threshold voltage division jitter circuit includes a third operational amplifier OP3, a first MOS tube NM1, a third resistor R3, a plurality of jitter resistors R4-R11 connected in series, a twelfth resistor R12, and a second ground terminal. The positive input terminal of the third operational amplifier OP3 is connected with the output terminal of the peak voltage threshold subtraction circuit, the negative input terminal of the third operational amplifier OP3 is connected with one end of the third resistor R3 close to the third operational amplifier OP3, the output terminal of the third operational amplifier OP3 is connected with the gate of the first MOS tube, and the output terminal of the peak voltage threshold voltage division jitter circuit is arranged between the twelfth resistor R12 and the plurality of jitter resistors R4-R11 connected in series. Each of the plurality of jitter resistors R4-R11 is connected in parallel with a first switch.

[0083] Among them, the third resistor R3, the plurality of jitter resistors R4-R11 connected in series, and the twelfth resistor R12 are collectively referred to as a resistor voltage division network. The third resistor and the twelfth resistor R12 are fixed resistors with fixed resistance values. The plurality of jitter resistors R4-R11 are connected to the circuit under the control of other conditions, so as to realize current and voltage jitter. Therefore, they are called jitter resistors.

[0084] The output end of the peak voltage threshold voltage dividing and jittering circuit is arranged between the twelfth resistor R12 and the jittering resistor R4-R11 which are serially connected in sequence.

[0085] Optionally, the resistors R4-R12 serially connected in sequence in the peak voltage threshold voltage dividing and jittering circuit have the same resistance.

[0086] When the resistors R4-R12 serially connected in sequence have the same resistance, the peak voltage threshold VTH can be uniformly jittered.

[0087] Optionally, the first switch is a MOS tube or a transmission gate switch.

[0088] In addition, it should be noted that the gate of the first MOS tube is connected with the output end of the third operational amplifier OP3, and the source is connected with one end of the third resistor R3. The first MOS tube can be an NMOS tube or a PMOS tube. Figure 11 Taking the NMOS tube as an example, it is denoted as NM1.

[0089] In addition, the drain of the first MOS tube NM1 is serially connected with the second resistor R2 and the power supply end VDD, and the source is connected with one end of the third resistor R3.

[0090] The resistor R2 is used to limit the current provided by the power supply end VDD, so as to prevent the first MOS tube in the circuit from being burned out due to excessive current.

[0091] The first ground end and the second ground end can be the same ground end or different ground ends.

[0092] In addition, it should be noted that the near and far in the present application are the near and far in the circuit connection relationship, and not the near and far in the spatial position.

[0093] For the convenience of description and easy understanding of the embodiments of the present application, the embodiments of the present application are described by taking the current mirror as the cascode and the eight resistors with the same resistance in the serially connected jittering resistors as an example. The working principle of the peak voltage threshold generating circuit is as follows:

[0094] The output feedback voltage VFB firstly reaches the first resistor R1, and the voltage is reduced after passing through the first resistor R1, so that the voltage subtraction is realized, and Vsub is obtained. Then, Vsub is output through the output end of the peak voltage threshold subtraction circuit.

[0095] The current size in the peak voltage threshold subtraction circuit is determined by the copy proportional coefficient k of the current mirror and the reference current Iref. The reference current Iref first reaches the reference current branch of the current mirror and then is mirrored to the mirror current branch.

[0096] The peak voltage threshold value is input to the positive input terminal of the third operational amplifier OP3, and then is output by the third operational amplifier OP3, and then is sequentially input to the first MOS transistor, the third resistor R3, the plurality of sequentially connected dithering resistors (the dithering resistors corresponding to the first switches in the off state among R4-R11) and the twelfth resistor R12, and finally is input to the second ground terminal.

[0097] The plurality of sequentially connected dithering resistors R4-R12 are not all connected to the circuit, but are controlled by the decoding circuit to turn on or off the first switches, so that the dithering resistors corresponding to the first switches in the off state are connected to the circuit, and the resistors corresponding to the first switches in the on state are not connected to the circuit, so as to dither the peak voltage, and further disperse the frequency spectrum and improve the chip EMI effect.

[0098] The peak voltage threshold value dithering control circuit: CLK is a clock signal, en is an enable signal, and the reset signal of the D edge trigger is high level effective. When the enable signal en is high, the D edge trigger normally works to divide the clock signal, so as to obtain q0-q3 and q3n, and send them to the decoding circuit, wherein q0-q2 are sent to the decoder, and q3 and q3n are sent to the second auxiliary circuit. For details, see the relevant description in the following file:

[0099] The reset end of the decoding circuit is high level effective, and reset is a reset signal. According to the value of q0-q3, the decoding circuit generates corresponding control signals j<0>-j<7>, which control the resistors connected to the circuit, that is, whether the dithering resistors R4-R11 are connected to the resistor voltage dividing network is controlled by the control signals j<0>-j<7>. By default, j<0>-j<3> are high, and j<4>-j<7> are low, that is, R4-R7 are not connected to the resistor voltage dividing network by default, and R8-R11 are connected to the resistor voltage dividing network. For example, when j<0> in j<0>-j<7> is high, the corresponding first switch is closed, and the corresponding resistor is not connected to the resistor, that is, R4 is not connected to the resistor, so as to control the dithering of the peak voltage threshold value VTH, disperse the power spectrum, and improve the electromagnetic interference (English full name: Electromagnetic Interference; English abbreviation: EMI) characteristics of the chip.

[0100] The peak voltage threshold value generating circuit provided by the present application has a flexible and simple circuit structure, and reduces the circuit area and power consumption. Further, the peak voltage threshold value VTH dithering control circuit can be used to flexibly control which dithering resistor is connected to the circuit, so that one or more dithering circuits are connected to the circuit, and the dithering is flexible. However, the VBE of the transistor used in the prior art is a fixed voltage, so it is difficult to flexibly adjust the system. In addition, the VBE of the transistor is a negative temperature coefficient voltage, which changes greatly under the PVT condition, so that the VTH changes significantly, thereby affecting the state determination of the subsequent circuit. In addition, the peak voltage threshold value dividing dithering circuit is introduced into the circuit, so that the peak voltage threshold value VTH can be adjusted by adjusting the resistance connected to the dividing network, the power spectrum of the chip is dispersed, and the EMI characteristics of the chip are improved. Therefore, the peak voltage threshold value generating circuit provided by the present application not only does not affect the subsequent circuit, but also can flexibly adjust the peak voltage, and improves the EMI performance of the switching power supply chip. In addition, compared with the prior art as shown in Figure 2 the present application has a simpler and more flexible circuit structure, not only realizes high-precision subtraction operation, meets the flexible control requirements of the system on frequency hysteresis, but also saves area resources and standby power consumption.

[0101] The present application also provides a switching power supply, which comprises a transformer, a feedback loop and a modulation loop, the modulation loop comprising the peak voltage threshold value generating circuit, one end of the transformer is connected with a diode, the diode is provided with a switching power supply output end away from the other end of the secondary side, one end of the feedback loop is connected with the output end of the switching power supply, the other end of the feedback loop is connected with one end of the peak voltage threshold value generating circuit, and the other end of the peak voltage threshold value generating circuit is connected with the primary side of the transformer.

[0102] The specific structure of the modulation loop and the specific structure of the switching power supply can be referred to the related prior art, and the present application does not make a detailed description.

[0103] Optionally, the switching power supply is a flyback switching power supply, and the transformer is a flyback transformer.

[0104] The present application also provides an electronic device, which is internally provided with the switching power supply.

[0105] The electric appliance can be a mobile phone charger, a television, or any device capable of using the switch power supply.

[0106] The application further provides a chip, and the chip is provided with the peak voltage threshold generation circuit according to any one of the above.

[0107] The technical features of the above embodiments can be combined in any manner, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combinations of the technical features do not contradict, they should be considered as the scope of the present application.

[0108] The principles and implementation modes of the present application are described by using specific examples herein, and the above embodiment descriptions are only used to help understand the method and core idea of the present application; meanwhile, for those skilled in the art, the specific implementation modes and application ranges will be changed according to the idea of the present application. In conclusion, the content of the present application should not be understood as a limitation.< / f> < / m> < / m> < / m> < / f> < / m> < / m> < / m>

Claims

1. A peak voltage threshold generation circuit, characterized in that, include: Output feedback voltage terminal, clock pulse signal generator, peak voltage threshold subtraction circuit, peak voltage threshold jitter control circuit and peak voltage threshold voltage divider jitter circuit; The peak voltage threshold subtraction circuit includes a first resistor and a current mirror. The first resistor and the mirror current branch of the current mirror are connected in series between the output feedback voltage terminal and the first ground terminal. The output terminal of the peak voltage threshold subtraction circuit is connected between the first resistor and the mirror current branch for outputting the subtraction voltage. The input terminal of the peak voltage threshold jitter control circuit is connected to the output terminal of the clock pulse signal generator, and the output terminal is connected to the first input terminal of the peak voltage threshold voltage divider jitter circuit. It is used to output a control signal, which is used to adjust the peak voltage threshold output by the peak voltage threshold voltage divider jitter circuit. The second input terminal of the peak voltage threshold voltage divider jitter circuit is connected to the output terminal of the peak voltage threshold subtraction circuit, and is used to connect different numbers of resistors under the control of the peak voltage threshold jitter control circuit, so as to divide the subtraction voltage and output different peak voltage thresholds. The peak voltage threshold jitter control circuit includes a frequency divider circuit and a decoding circuit. The input terminal of the frequency divider circuit is connected to the output terminal of the clock pulse signal generator. The multiple clock pulse signal output terminals of the frequency divider circuit are correspondingly connected to the multiple clock pulse signal input terminals of the decoding circuit. The multiple output terminals of the decoding circuit are correspondingly connected to the first input terminal of the peak voltage threshold voltage divider jitter circuit, and are used to control the number of resistors connected to the peak voltage threshold voltage divider jitter circuit through the pulse signals output by the circuit. The decoding circuit includes a decoder, a first auxiliary circuit, and a second auxiliary circuit. The decoder has the following inputs: it receives q0~q2 from the D flip-flop of the frequency divider circuit; the reset input is active low and controlled by q0 and the clock pulse signal; and the outputs are s0~s7. The first auxiliary circuit includes four RS flip-flops, and s0~s3 are respectively sent to the set terminals of the four RS flip-flops, and s7~s4 are sent to the reset terminals of the four RS flip-flops. The second auxiliary circuit includes eight combinational logic circuits, referred to as the first to the eighth combinational logic circuits respectively. The first four combinational logic circuits are NAND gates; the last four combinational logic circuits are a combination of NAND gates and inverters, with the NAND gates serving as the receiving end and the inverters serving as the output end. The receiving end of the second auxiliary circuit is connected to the decoder and the output end of the first auxiliary circuit.

2. The peak voltage threshold generation circuit according to claim 1, characterized in that, The peak voltage threshold voltage divider jittering circuit includes a third operational amplifier, a first MOSFET, a third resistor, multiple jittering resistors connected in series, a twelfth resistor, and a second ground terminal. The positive input terminal of the third operational amplifier is connected to the output terminal of the peak voltage threshold subtraction circuit, the inverting input terminal of the third operational amplifier is connected to the third resistor, and the output terminal of the third operational amplifier is connected to the gate of the first MOSFET. The output terminal of the peak voltage threshold voltage divider jittering circuit is located between the twelfth resistor and the multiple jittering resistors connected in series. Each jittering resistor in the multiple jittering resistors connected in series is connected in parallel with a first switch, which is controlled to open or close by the pulse signal to control the number of resistors connected to the peak voltage threshold voltage divider jittering circuit.

3. The peak voltage threshold generation circuit according to claim 1, characterized in that, s0~s7 sequentially change to high level with the period Tclk of the clock pulse signal as the interval, and s0~s7 are sent to the first auxiliary circuit; The outputs of the four RS flip-flops respectively receive pulse widths of 14Tclk, 10Tclk, 6Tclk, and 2Tclk. <m>Signal, in which ;< / m> st <m>The q3n signal sent by the D flip-flop in the frequency divider circuit is passed through the first four combinational logic circuits to obtain j. <0> ~j <3> , and will st <m>The q3 signal sent by the D flip-flop in the frequency divider circuit is processed through the next four combinational logic circuits to obtain j. <4> ~j <7> The control signal is denoted as j. <f>, And when q3 is in a low-level state, j <0> ~j <3> The initial value is high, and it changes to low level sequentially at intervals of 2Tclk; when q3 is in a high level state, j <4> ~j <7> The initial value is low, and it changes to high level at intervals of 2Tclk.< / f> < / m> < / m> 4. The peak voltage threshold generation circuit according to claim 3, characterized in that, The frequency divider circuit includes multiple D flip-flops connected in series. For each pair of adjacent D flip-flops, the D input terminal of the preceding D flip-flop is connected to its inverted output terminal, and the positive output terminal of the preceding D flip-flop is connected to the clock pulse signal input terminal of the following D flip-flop. The positive output of the D flip-flop is also connected to the frequency division level signal input of the decoding circuit; The positive and negative output terminals of the D flip-flop at the very end of the frequency divider circuit are connected to the input terminal of the second auxiliary circuit.

5. The peak voltage threshold generation circuit according to claim 2, characterized in that, The peak voltage threshold voltage divider dithering circuit includes multiple dithering resistors connected in series with the same resistance value.

6. The peak voltage threshold generation circuit according to any one of claims 1-5, characterized in that, The reference current branch of the current mirror is connected between the reference current generating circuit and the first ground terminal, and the current mirror is a cascode current mirror.

7. A switching power supply, characterized in that, The switching power supply includes a transformer, a feedback loop, and a modulation loop. The modulation loop includes the peak voltage threshold generation circuit according to any one of claims 1-6. A diode is connected to the secondary side of the transformer. The end of the diode away from the secondary side is provided with a switching power supply output terminal. One end of the feedback loop is connected to the output terminal of the switching power supply. The other end of the feedback loop is connected to one end of the peak voltage threshold generation circuit. The other end of the peak voltage threshold generation circuit is connected to the primary side of the transformer.

8. The switching power supply according to claim 7, characterized in that, The switching power supply is a flyback switching power supply, and the transformer is a flyback transformer.

9. An electronic device, characterized in that, The electronic device is internally equipped with the switching power supply as described in claim 7 or 8.

10. A chip, characterized in that, The chip is provided with a peak voltage threshold generation circuit as described in any one of claims 1-6.

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