An adaptive substrate potential generating circuit and its application

Abstract

The present invention discloses an adaptive substrate potential generating circuit and its application, including a state detection circuit for detecting the working state of an external pair of tubes, an output potential control circuit for adaptively providing a substrate bias potential for the external pair of tubes, a current mirror circuit for powering the state detection circuit and the output potential control circuit, and five ports connected to the outside. The state detection circuit is used to detect the drain potential and source common mode potential of the external input PMOS pair of tubes, and the precise trigger threshold of the high level output of the state detection circuit is controlled by the pull-up resistor R1; the output potential control circuit uses an operational amplifier to control the current flowing through the MP7 tube, and uses the pull-up resistor R2 to control the substrate bias potential of the external PMOS pair of tubes. The present invention can automatically detect the working state of the input pair of tubes and adaptively adjust the substrate potential of the pair of tubes. Compared with the traditional method, the minimum operating voltage of the circuit is reduced and the input common mode range of the circuit is expanded.

Description

Technical Field

[0001] The present invention relates to the selection of substrate bias potential of input pair tubes of amplifiers, comparators and the like in integrated circuits, and in particular to an adaptive substrate potential generating circuit which automatically detects the working state of the input pair tubes and adaptively gives the substrate potential and its application, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] When circuits such as operational amplifiers and comparators use MOS tubes as input pairs, it is necessary to select a suitable potential for the substrate to ensure the normal operation of the tube. The selection of substrate potential generally needs to consider two factors: First, under the lowest operating voltage condition, when at the common mode switching point, whether the input pair current mirror works normally to give a normal current; Second, under the lowest and highest common mode conditions, whether the PMOS pair and NMOS pair work in the saturation region. Usually, since the threshold voltage of the NMOS tube is lower, it is easy to be in the linear region under high common mode conditions, and a larger substrate bias is required to ensure normal operation under high common mode. In addition, the substrate potential of the NMOS tube that does not use isolation devices is grounded. Therefore, the main consideration is the connection method of the substrate potential of the PMOS pair.

[0003] The traditional structure of PMOS tube substrate potential is connected to a fixed value, generally the power supply voltage or the source voltage of the PMOS tube itself, such as Figure 1 and Figure 2 shown. Figure 1 In the circuit shown, the substrate of the PMOS pair is connected to the power supply potential. Due to the substrate bias effect, the threshold voltage (Vthp) of the first PMOS tube and the second PMOS tube is raised. The advantage is that under the condition of the lowest common mode voltage (VCM), such as VCM=VGND-0.2V, the potential between the source and drain of the pair of tubes is , Vthp increases, increases, the PMOS pair is more likely to be in the saturation region, that is However, this connection method has disadvantages. As the threshold voltage of the PMOS pair increases, when the common-mode voltage increases, the switching voltage of the NMOS pair and the PMOS pair current mirror becomes lower. Under the condition of the lowest operating voltage, it is easy to cause the NMOS pair to fail to work normally when the PMOS pair is turned off. Therefore, the lowest operating voltage of the circuit is limited. Figure 2 The circuit shown connects the substrate potential of the PMOS pair to its own source, avoiding the influence of the substrate bias effect on the threshold voltage. The advantage is that under the lowest operating voltage condition, the switching point potential of the PMOS pair is increased, and the NMOS pair near the common mode switching point is more likely to be in a normal working state. This connection method also has disadvantages. When the input common mode voltage is low, the pair will be The PMOS transistor is easy to enter the linear region, which causes the circuit to work abnormally.

[0004] In addition, there is a third substrate potential connection method, such as Figure 3 As shown. The substrate potential of the PMOS pair is composed of its own source potential plus a VGS3 of PMOS3 and a Vdiod potential, that is, the substrate bias potential VSB = VGS3 + Vdiod, which provides a substrate potential that changes with the common mode for the substrates of the PMOS1 and PMOS2 pairs, making the substrate potential higher than the common mode potential by a fixed value, but the problems that follow are similar to Figure 1 and Figure 2 If the substrate potential is set too high, the voltage power supply is low, and the common mode switching cannot guarantee that at least one pair of tubes will work normally. If the potential is set too low, the PMOS pair of tubes cannot be guaranteed to be in the normal saturation zone under low voltage and low common mode conditions. Figure 3 The structure, especially the low-voltage circuit, has a high requirement for the Vbulk potential. In addition, due to the deviation of the chip production process and the changes in the actual working environment, the Vbulk potential fluctuates within a certain range, reducing the robustness of the circuit operation.

[0005] The essential problem of the above three structures is that they cannot actively detect the working status of the input pair of tubes, so as to decide whether to apply a bias voltage and how much bias voltage to apply. Figure 1 and Figure 2 The substrate potential is completely fixed, and the common mode change and the change of the tube state VDS cannot be detected. Figure 3 The structure can detect the change of common mode voltage, but the VSB potential is fixed and still cannot give a corresponding value according to the change of VDS of the pair of tubes. Therefore, it is necessary to design a new structure to provide a suitable potential for the substrate potential of the pair of tubes, which will help reduce the minimum voltage of the circuit operation and improve the common mode input range of the circuit. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide an adaptive substrate potential generating circuit and its application, which can actively detect the working state of the tube and provide adaptive substrate potential, reduce the minimum working voltage of the circuit, and improve the common mode input range.

[0007] The present invention adopts the following technical solutions to solve the above technical problems:

[0008] An adaptive substrate potential generating circuit comprises: a state detection circuit for detecting the working state of an external pair of tubes, an output potential control circuit for adaptively providing a substrate bias potential for the external pair of tubes, a current mirror circuit for powering the state detection circuit and the output potential control circuit, and seven ports Vsense1, Vsense2, Vsense3, Vbulk, VDD, GND and IB connected to the outside;

[0009] The Vsense1 port is used to detect the change of the common mode signal input to the external pair of tubes, the Vsense2 and Vsense3 ports are used to collect the drain potential of the external pair of tubes, the Vbulk port is used to provide a substrate bias potential for the external pair of tubes, and the IB port is used to power the current mirror circuit;

[0010] The state detection circuit includes first to third PMOS tubes, a ninth PMOS tube, first to second NMOS tubes and a first pull-bias resistor; the gate of the first PMOS tube is connected to the Vsense2 port, the gate of the second PMOS tube is connected to the Vsense3 port, the source of the first PMOS tube and the second PMOS tube are connected in parallel and connected to one end of the first pull-bias resistor, the drain of the first PMOS tube and the second PMOS tube are connected in parallel and connected to the drain of the first NMOS tube, the substrate of the first PMOS tube is connected to the source, and the substrate of the second PMOS tube is connected to the source;

[0011] The gate of the first NMOS tube is connected to the gate of the second NMOS tube, the source of the first NMOS tube and the source of the second NMOS tube are connected to the GND port, and the gate and drain of the first NMOS tube are connected; the drain of the second NMOS tube is connected to the drain of the third PMOS tube as the output of the state detection circuit and connected to the output potential control circuit; the gate of the third PMOS tube is connected to the Vsense1 port, the substrate and source of the third PMOS tube are connected, the source of the third PMOS tube and the other end of the first pull-up resistor are respectively connected to the drain of the ninth PMOS tube, and the ninth PMOS tube is a current mirror of the state detection circuit, providing it with a constant current.

[0012] As a preferred solution of the present invention, the output potential control circuit includes third to fifth NMOS tubes, an eighth NMOS tube, fourth to eighth PMOS tubes, a second pull-up resistor and a compensation capacitor, wherein the fourth PMOS tube, the fifth PMOS tube, the third NMOS tube and the fourth NMOS tube constitute a first-stage operational amplifier, the fifth NMOS tube and the sixth PMOS tube constitute a second-stage operational amplifier, and the seventh PMOS tube constitutes a third-stage operational amplifier;

[0013] In the first-stage operational amplifier, the gate of the fourth PMOS tube is connected to the output of the state detection circuit, the gate of the fifth PMOS tube is connected to the Vsense1 port, the source of the fourth PMOS tube is connected in parallel with the source of the fifth PMOS tube and then connected to the drain of the eighth PMOS tube; the third NMOS tube and the fourth NMOS tube constitute a load tube of the first-stage operational amplifier, the drain of the fifth PMOS tube is connected to the drain of the fourth NMOS tube and then connected to one end of the compensation capacitor, the drain of the fourth PMOS tube is connected to the drain of the third NMOS tube, the gate of the third NMOS tube is connected to the gate of the fourth NMOS tube, the gate of the third NMOS tube is connected to the drain, and the source of the third NMOS tube and the source of the fourth NMOS tube are connected to the GND port;

[0014] In the second stage operational amplifier, the gate of the fifth NMOS tube is connected to one end of the compensation capacitor, the source is connected to the drain of the eighth NMOS tube, and the drain is connected to the drain of the sixth PMOS tube; the drain of the sixth PMOS tube is connected to the gate; the gate of the eighth NMOS tube is connected to the IB port;

[0015] In the third-stage operational amplifier, the gate of the seventh PMOS tube is connected to the gate of the sixth PMOS tube, and the drain is connected to one end of the second pull-up resistor; the other end of the second pull-up resistor is connected to the Vsense1 port and the gate of the fifth PMOS tube, and the drain of the seventh PMOS tube is connected to the Vbulk port; the source of the seventh PMOS tube, the source of the sixth PMOS tube, the source of the eighth PMOS tube and the source of the ninth PMOS tube are all connected to the VDD port, and the gate of the eighth PMOS tube is connected to the gate of the ninth PMOS tube.

[0016] As a preferred solution of the present invention, the current mirror circuit includes sixth to seventh NMOS tubes and a tenth PMOS tube; the drain of the seventh NMOS tube is connected to the IB port, the gate of the seventh NMOS tube is connected to the gate of the sixth NMOS tube, the source of the seventh NMOS tube, the source of the sixth NMOS tube and the source of the eighth NMOS tube are connected to the GND port, the drain of the sixth NMOS tube is connected to the drain of the tenth PMOS tube, the source of the tenth PMOS tube is connected to the VDD port, the gate of the tenth PMOS tube is connected to the gate of the ninth PMOS tube and the gate of the eighth PMOS tube, and the gate and drain of the tenth PMOS tube are connected.

[0017] As a preferred solution of the present invention, the external pair of tubes includes an eleventh and a twelfth PMOS tube; the sources of the eleventh PMOS tube and the twelfth PMOS tube are respectively connected to the Vsense1 port, the drain of the eleventh PMOS tube is connected to the Vsense2 port, the drain of the twelfth PMOS tube is connected to the Vsense3 port, the substrates of the eleventh PMOS tube and the twelfth PMOS tube are respectively connected to the Vbulk port, and the gates of the eleventh PMOS tube and the twelfth PMOS tube are respectively connected to the common mode signal input terminal.

[0018] As a preferred solution of the present invention, the first NMOS tube, the second NMOS tube, the sixth NMOS tube, the seventh NMOS tube and the eighth NMOS tube are all current mirror tubes, and the sixth to tenth PMOS tubes are all current mirror tubes.

[0019] As a preferred solution of the present invention, the size ratio of the first PMOS tube to the second PMOS tube is 1:1, the size ratio of the third PMOS tube to the first PMOS tube is 2:1, the size ratio of the fourth PMOS tube to the fifth PMOS tube is 1:1, the size ratio of the first NMOS tube to the second NMOS tube is 1:1, and the size ratio of the third NMOS tube to the fourth NMOS tube is 1:1.

[0020] A chip circuit comprises the adaptive substrate potential generating circuit.

[0021] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects:

[0022] 1. The present invention can automatically detect the working state of the input pair tube, and use the amplifier circuit to adaptively control the potential output, thereby reducing the circuit's minimum operating voltage and increasing the input common mode range. The traditional circuit input pair tube substrate can only be connected to a fixed potential, and a compromise needs to be made between the minimum operating voltage common mode switching and the input common mode range. In practice, the minimum operating voltage is often sacrificed. The present invention solves the problem of the difficulty in selecting the potential of the low-voltage traditional circuit substrate, and takes into account a lower operating voltage and a larger input common mode range.

[0023] 2. The comparator of the state detection part of the present invention uses a fixed resistor and a current to set the threshold of the pull-out bias. By changing the resistance value and the current, the VDS of the input pair can be controlled more flexibly.

[0024] 3. Under different voltage and common mode conditions, the present invention can independently Figure 1 , Figure 2 and Figure 3 Switching between the three structures retains the advantages of the three structures. Under low common mode conditions, the input to the tube substrate potential is pulled to the maximum, and the working state is the same as Figure 1The structure shown is the same. Under high common mode conditions, the input pair tube substrate potential is connected to its own source, and the working state of the input pair tube is the same as Figure 2 When the input pair tube VDS approaches the threshold voltage set by the state detection part, the input pair tube liner bias potential is changed by Decision, therefore the working status is Figure 3 resemblance. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is the first conventional input to tube substrate potential selection circuit diagram;

[0026] Figure 2 It is the second traditional input to tube substrate potential selection circuit diagram;

[0027] Figure 3 It is the third traditional input to tube substrate potential selection circuit diagram;

[0028] Figure 4 is an external application diagram of the adaptive substrate potential generating circuit of the present invention;

[0029] Figure 5 It is a diagram of the internal structure of the adaptive substrate potential generating circuit of the present invention. DETAILED DESCRIPTION

[0030] The embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be interpreted as limiting the present invention.

[0031] The present invention provides an adaptive substrate potential generating circuit for detecting the working state of a PMOS input pair tube, providing a suitable potential for the PMOS pair tube substrate through a feedback loop, and ensuring normal operation of the pair tube when it is in a switching or extreme common mode state.

[0032] The external application circuit of the present invention is as follows Figure 4 As shown, it includes five ports that are mainly connected to the outside. The Vsense1 port is connected to the source of MP11 and MP12 for detecting the change of the input common-mode signal; the Vsense2 and Vsense3 ports are respectively connected to the drain of MP11 and MP12 for sampling the drain potential of the tube; the Vbulk port is connected to the substrate of MP11 and MP12 to provide them with substrate bias potential; the IB port is used to power the adaptive substrate potential generation circuit.

[0033] The internal structure of the adaptive substrate potential generating circuit of the present invention is as follows: Figure 5 As shown, the following will be combined Figure 5, illustrating the control of the input to tube substrate potential by the present invention.

[0034] The adaptive substrate potential generating circuit includes three parts: a state detection circuit, an output potential control circuit and a current mirror circuit.

[0035] In the state detection circuit, the gate of MP1 is connected to Vsense2, the gate of MP2 is connected to Vsense3, and the sources of the two are connected in parallel to one end of the pull-up resistor R1, which is used to detect external signals, that is, the sampled drain potential of the pair of tubes; the drains of MP1 and MP2 are connected in parallel to provide current for MN1; the gate of MP3 is connected to Vsense1, which is used to detect external signals, that is, the input common-mode signal; the substrate of MP3 is connected to the other end of the pull-up resistor R1 and connected to the drain of the current mirror MP9; the current flowing through MP3 is equal to the current flowing through MP2, and MN1 and MN2 are set as 1:1 current mirrors, so the working principle of the state detection circuit is the same as the pull-up comparator in the open-loop state. The state detection circuit compares the potentials of Vsense1, Vsense2, and Vsense3, and outputs the comparison result to the drain of MN2. It should be noted that the areas of MP1 and MP2 are set to be equal, the area of ​​MP3 is twice that of MP1 or MP2, and the size ratio of the three is 2:1:1; the ratio of the MN2 current mirror is set to be the same as the ratio of the MN1 current mirror. MP9 provides a constant current to the tubes MP1, MP2, and MP3. The entire state detection circuit constitutes a biased comparator with a bias potential of approximately , the output node is the drain of MN2. Therefore, when the Vsense1 potential is lower than the set threshold voltage, that is, When the common-mode voltage is high, the output node potential of the comparator is raised. On the contrary, when the common-mode voltage is high, the drain potential of MN2 is close to 0 because the MP9 current flows through MN1.

[0036] The output potential control circuit includes a three-stage operational amplifier, a first-stage operational amplifier composed of MP4, MP5, NM3 and MN4; a second-stage operational amplifier composed of MN5 and MP6; and a third-stage operational amplifier composed of MP7. In the first-stage operational amplifier, the gate of MP4 is connected to the output of the state detection circuit, the gate of MP5 is connected to Vsense1, the source is connected to the drain of the current mirror MP8 after being connected in parallel with the source of MP4, MP4 and MP5 are the input pair of the first-stage operational amplifier, and MN4 and MN3 constitute the load tube of the first-stage amplifier; the output of the first-stage operational amplifier is the drain of MN4, and the compensation capacitor Cc is connected to the output stage of the first-stage amplifier to adjust the main pole of the operational amplifier to ensure the stability of the loop. In the second-stage operational amplifier, the gate of MN5 is connected to the output end of the first-stage operational amplifier, and the source is connected to the drain of MN8. MN8 is a current mirror tube, which ensures that the current flowing through MN5 has a maximum value when the gate potential of MN5 increases; MP6 is a self-biased current mirror, which is used to transmit the signal transmitted by the drain of MN5 tube to the third-stage operational amplifier MP7. MP7 can be regarded as the current generated by the mirror MP6. The drain of MP7 is connected to one end of the pull-up resistor R2. The other end of the pull-up resistor R2 is connected to the Vsense1 port and the gate of MP5. The current through MP7 flows through the pull-up resistor R2 to generate a certain voltage drop. Therefore, the entire output potential control module forms a negative feedback closed loop path. It should be noted that the aspect ratio of MP5 and MP4 is the same, and the aspect ratio of MN4 and MN3 is the same; the capacitance value is reasonably adjusted to ensure normal loop stability; and the appropriate ratio of MP6 and MP7 current mirrors is set as needed.

[0037] After the input signal is amplified by the first stage op amp and the second stage op amp MN5, the output signal controls the current through R2 through the current mirror MP7 to provide a suitable substrate potential for the external input pair. The specific value of the output substrate potential is By adjusting the width-to-length ratio of MP6 and MP7, and the resistance value of the pull-off resistor R2, it is equivalent to adjusting the feedback coefficient of the output potential control loop and the current value that needs to flow through R2. Through the entire feedback loop, the Vbulk potential is adaptively adjusted. When the output potential control circuit works in the form of an amplifier, the Vsense1 potential is controlled to be the same as the output potential of the state detection circuit to ensure that the MP3 tube works in the saturation region.

[0038] The output node of the first-stage amplifier of the output potential control circuit is connected to the compensation capacitor Cc to ensure the stability of the feedback loop during operation in the form of a three-stage operational amplifier, so that oscillation will not occur.

[0039] In the current mirror circuit, the current IB flowing through MN7 is copied to MN6, MN6 passes the current to MP10, and MP10 copies the current to MP8 and MP9, thereby supplying power to the output potential control circuit and the state detection circuit.

[0040] The working principle and process of the adaptive substrate potential generating circuit are as follows:

[0041] In the state detection circuit, the MP3 tube samples the input pair's source potential, and the MP1 and MP2 tubes sample the input pair's drain potential. Under normal circumstances, the MP3 gate potential changes with the common mode, while the MP1 and MP2 gate potential values ​​remain relatively constant.

[0042] The working process of the adaptive substrate potential generation circuit is specifically divided into three stages:

[0043] 1. When the input common mode voltage is high, the MP9 current flows through the MN1 tube, the MN2 potential is 0, the op amp of the output potential control part works as a comparator, the MP7 tube is turned off, and the Vbulk port potential is the same as the Vsense1 port potential. Figure 4 It is equivalent to connecting the input substrate potential to its own source, that is, Figure 2 The circuit shown.

[0044] 2. When the input common mode voltage is low, that is, when Figure 4 Input pair When it is slightly less than the trigger threshold voltage, the gate potential of MN2 rises, and the op amp in the output potential control circuit clamps the Vsense1 potential and the gate potential of MN2 to the same value. The current flowing through MP6 is mirrored to MP7. At this time, the potential of Vbulk terminal is So the bias potential of the tube substrate is Therefore, the Vsense1 potential is raised to ensure that there is a voltage margin on the input pair tube VDS.

[0045] 3. When the common mode voltage continues to decrease, the amplifier of the output potential control circuit works as a comparator, and the potential of the Vbulk terminal reaches the power supply voltage value, that is, the maximum value of the bias effect, and the working state is the same as Figure 1 Similar structure.

[0046] The above embodiments are only for illustrating the technical idea of ​​the present invention, and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.

Claims

1. An adaptive substrate potential generating circuit, characterized in that: include: A state detection circuit for detecting the working state of an external pair of tubes, an output potential control circuit for adaptively providing a substrate bias potential for the external pair of tubes, a current mirror circuit for powering the state detection circuit and the output potential control circuit, and seven ports Vsense1, Vsense2, Vsense3, Vbulk, VDD, GND and IB connected to the outside; The Vsense1 port is used to detect the change of the common mode signal input to the external pair of tubes, the Vsense2 and Vsense3 ports are used to collect the drain potential of the external pair of tubes, the Vbulk port is used to provide a substrate bias potential for the external pair of tubes, and the IB port is used to power the current mirror circuit; The state detection circuit includes first to third PMOS tubes, a ninth PMOS tube, first to second NMOS tubes and a first pull-bias resistor; the gate of the first PMOS tube is connected to the Vsense2 port, the gate of the second PMOS tube is connected to the Vsense3 port, the source of the first PMOS tube and the second PMOS tube are connected in parallel and connected to one end of the first pull-bias resistor, the drain of the first PMOS tube and the second PMOS tube are connected in parallel and connected to the drain of the first NMOS tube, the substrate of the first PMOS tube is connected to the source, and the substrate of the second PMOS tube is connected to the source; The gate of the first NMOS tube is connected to the gate of the second NMOS tube, the source of the first NMOS tube and the source of the second NMOS tube are connected to the GND port, and the gate and drain of the first NMOS tube are connected; the drain of the second NMOS tube is connected to the drain of the third PMOS tube and serves as the output of the state detection circuit, and is connected to the output potential control circuit; the gate of the third PMOS tube is connected to the Vsense1 port, the substrate and the source of the third PMOS tube are connected, the source of the third PMOS tube and the other end of the first pull-up resistor are respectively connected to the drain of the ninth PMOS tube, and the ninth PMOS tube is a current mirror of the state detection circuit, providing a constant current for it; The output potential control circuit includes third to fifth NMOS tubes, an eighth NMOS tube, fourth to eighth PMOS tubes, a second pull-up resistor and a compensation capacitor, wherein the fourth PMOS tube, the fifth PMOS tube, the third NMOS tube and the fourth NMOS tube constitute a first-stage operational amplifier, the fifth NMOS tube and the sixth PMOS tube constitute a second-stage operational amplifier, and the seventh PMOS tube constitutes a third-stage operational amplifier; In the first-stage operational amplifier, the gate of the fourth PMOS tube is connected to the output of the state detection circuit, the gate of the fifth PMOS tube is connected to the Vsense1 port, the source of the fourth PMOS tube is connected in parallel with the source of the fifth PMOS tube and then connected to the drain of the eighth PMOS tube; the third NMOS tube and the fourth NMOS tube constitute a load tube of the first-stage operational amplifier, the drain of the fifth PMOS tube is connected to the drain of the fourth NMOS tube and then connected to one end of the compensation capacitor, the drain of the fourth PMOS tube is connected to the drain of the third NMOS tube, the gate of the third NMOS tube is connected to the gate of the fourth NMOS tube, the gate of the third NMOS tube is connected to the drain, and the source of the third NMOS tube and the source of the fourth NMOS tube are connected to the GND port; In the second stage operational amplifier, the gate of the fifth NMOS tube is connected to one end of the compensation capacitor, the source is connected to the drain of the eighth NMOS tube, and the drain is connected to the drain of the sixth PMOS tube; the drain of the sixth PMOS tube is connected to the gate; the gate of the eighth NMOS tube is connected to the IB port; In the third-stage operational amplifier, the gate of the seventh PMOS tube is connected to the gate of the sixth PMOS tube, and the drain is connected to one end of the second pull-bias resistor; the other end of the second pull-bias resistor is connected to the Vsense1 port and the gate of the fifth PMOS tube, and the drain of the seventh PMOS tube is connected to the Vbulk port; the source of the seventh PMOS tube, the source of the sixth PMOS tube, the source of the eighth PMOS tube, and the source of the ninth PMOS tube are all connected to the VDD port, and the gate of the eighth PMOS tube is connected to the gate of the ninth PMOS tube; The current mirror circuit includes sixth to seventh NMOS tubes and a tenth PMOS tube; the drain of the seventh NMOS tube is connected to the IB port, the gate of the seventh NMOS tube is connected to the gate of the sixth NMOS tube, the source of the seventh NMOS tube, the source of the sixth NMOS tube and the source of the eighth NMOS tube are connected to the GND port, the drain of the sixth NMOS tube is connected to the drain of the tenth PMOS tube, the source of the tenth PMOS tube is connected to the VDD port, the gate of the tenth PMOS tube is connected to the gate of the ninth PMOS tube and the gate of the eighth PMOS tube, and the gate and drain of the tenth PMOS tube are connected.

2. The adaptive substrate potential generating circuit according to claim 1, characterized in that: The external pair of tubes includes an eleventh and a twelfth PMOS tube; the sources of the eleventh PMOS tube and the twelfth PMOS tube are respectively connected to the Vsense1 port, the drain of the eleventh PMOS tube is connected to the Vsense2 port, the drain of the twelfth PMOS tube is connected to the Vsense3 port, the substrates of the eleventh PMOS tube and the twelfth PMOS tube are respectively connected to the Vbulk port, and the gates of the eleventh PMOS tube and the twelfth PMOS tube are respectively connected to the common mode signal input terminal.

3. The adaptive substrate potential generating circuit according to claim 1, characterized in that: The first NMOS tube, the second NMOS tube, the sixth NMOS tube, the seventh NMOS tube and the eighth NMOS tube are all current mirror tubes, and the sixth to tenth PMOS tubes are all current mirror tubes.

4. The adaptive substrate potential generating circuit according to claim 1, characterized in that: The size ratio of the first PMOS tube to the second PMOS tube is 1:1, the size ratio of the third PMOS tube to the first PMOS tube is 2:1, the size ratio of the fourth PMOS tube to the fifth PMOS tube is 1:1, the size ratio of the first NMOS tube to the second NMOS tube is 1:1, and the size ratio of the third NMOS tube to the fourth NMOS tube is 1:

1.

5. A chip circuit, characterized in that: The chip circuit includes the adaptive substrate potential generating circuit as described in any one of claims 1-4.

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