High-speed pipelined time quantization analog-to-digital converter

Abstract

The application discloses a high-speed pipeline time quantization analog-digital converter and relates to the technical field of high-speed analog-digital converters, comprising an initial time quantization module, an N-channel multistage time quantization module and a data output module, wherein the initial time quantization module is used for sampling, converting and initially quantizing an input analog signal to obtain a first digital code and an initial time residual signal; the N-channel multistage time quantization module comprises a plurality of parallel sub-channel multistage time quantizers, the plurality of sub-channel multistage time quantizers alternately receive the initial time residual signal, each sub-channel multistage time quantizer performs multistage quantization on the received initial time residual signal to obtain a corresponding multistage digital code; and the data output module is used for integrating and outputting all the digital codes. The application adopts a time domain partial time domain interleaving structure, eliminates sampling mismatch of a traditional time domain interleaving structure, adopts an amplification and quantization parallel working mode of the time residual signal, and improves working speed.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of high-speed analog-to-digital converters, and particularly relates to a high-speed pipeline time-quantization analog-to-digital converter. BACKGROUND

[0002] High-speed ADCs (Analog to Digital Converters) are at the core of advanced technology applications, driving the innovative development of multiple fields including next-generation communication systems such as 5G and above, precision radar technology, aerospace instruments, cutting-edge medical imaging equipment, high-speed data processing centers, and frontier scientific research. In these applications, high-speed ADCs not only meet the high-precision tracking of fast-moving targets, efficient processing of wideband signals, real-time data analysis in complex environments, but also promote high-resolution image acquisition, precise measurement of high-frequency phenomena, and high-speed information transmission and processing in the era of big data.

[0003] The mainstream technology of current high-speed ADCs is voltage domain pipeline technology and time domain interleaving technology. ADCs using time domain interleaving technology make multiple sub-channel ADCs, such as SAR ADCs (Successive-Approximation Register Analog to Digital Converters) or Flash ADCs (Flash Analog to Digital Converters), work in parallel, allowing them to sequentially sample, quantize, and output the input. The overall sampling rate can be several times that of the sub-ADCs and has the precision and characteristics of the sub-ADCs. However, the precision of ADCs using time domain interleaving technology is severely affected by sampling mismatch between channels. With the evolution of technology, the reduction of intrinsic gain and power voltage increases the difficulty of designing voltage amplifiers required by pipeline technology. Moreover, ADCs using pipeline technology serially perform residual amplification and quantization, limiting the quantization speed. Traditional asynchronous pipeline SAR TDCs (Successive-Approximation Register Time to Digital Converters) are fast and low in power consumption, but due to their minimum time step reaching the femtosecond level, they are severely affected by jitter and parasitic effects, making it difficult to improve precision. SUMMARY

[0004] To solve the above problems in the prior art, the application provides a high-speed pipeline time-quantization analog-to-digital converter. The technical problem to be solved by the application is solved by the following technical scheme:

[0005] The application provides a high-speed pipeline time quantization analog-digital converter, comprising an initial time quantization module, an N-channel multi-stage time quantization module and a data output module, wherein,

[0006] The initial time quantization module is used for sampling, converting and preliminary quantizing an input analog signal to obtain a first-bit digital code and an initial time residual signal;

[0007] The N-channel multi-stage time quantization module is connected with the initial time quantization module, and comprises a plurality of parallel sub-channel multi-stage time quantizers, which alternately receive the initial time residual signal, and each sub-channel multi-stage time quantizer performs multi-stage quantization on the received initial time residual signal to obtain a corresponding multi-stage digital code;

[0008] The data output module is connected with the initial time quantization module and the N-channel multi-stage time quantization module, and is used for integrating and outputting the first-bit digital code and the multi-stage digital code.

[0009] In an embodiment of the application, the initial time quantization module comprises a sample-and-hold circuit, a voltage-time converter and a successive approximation type time-digital converter connected in sequence, wherein,

[0010] The sample-and-hold circuit is used for sampling the input analog signal to obtain a sampling signal;

[0011] The voltage-time converter is used for mapping the sampling signal to a time domain to obtain a time domain signal;

[0012] The successive approximation type time-digital converter is used for preliminary quantizing the time domain signal to obtain the first-bit digital code and the initial time residual signal.

[0013] In an embodiment of the application, the N-channel multi-stage time quantization module further comprises a multiplexer, wherein,

[0014] The input end of the multiplexer is connected with the initial time quantization module, and the output end is connected with the plurality of sub-channel multi-stage time quantizers respectively;

[0015] The multiplexer alternately transmits the initial time residual signal to the sub-channel multi-stage time quantizers according to a clock signal.

[0016] In an embodiment of the application, the multiplexer comprises a clock generator and a plurality of CMOS transmission gates connected in parallel, wherein,

[0017] The clock generator is used to generate a plurality of clock signals, each clock signal input corresponding CMOS transmission gate to control the conduction and closing of the CMOS transmission gate.

[0018] The signal input end of each CMOS transmission gate receives the initial time margin signal, and the clock signal end receives the clock signal.

[0019] In an embodiment of the present application, the number of CMOS transmission gates is consistent with the number of sub-channel multi-stage time quantizers, and the signal output end of the CMOS transmission gate is connected to the sub-channel multi-stage time quantizer one by one.

[0020] In an embodiment of the present application, the sub-channel multi-stage time quantizer comprises a plurality of time amplifiers and a plurality of successive approximation type time digital converters connected alternately.

[0021] Among them, the time amplifier and the successive approximation type time digital converter constitute a time quantization unit, the successive approximation type time digital converter of the previous time quantization unit is connected with the time amplifier of the next time quantization unit, the time amplifier of the first time quantization unit is connected with the initial time quantization module, and the successive approximation type time digital converter of the last time quantization unit is connected with the data output module.

[0022] In an embodiment of the present application, in the time quantization unit, the time amplifier amplifies the received time margin signal, and the successive approximation type time digital converter quantizes the amplified time margin signal to obtain the digital code and the time margin signal of the current stage.

[0023] In an embodiment of the present application, the time amplifier and the successive approximation type time digital converter work as separate pipeline stages respectively to realize the parallel working mode of the time amplifier and the successive approximation type time digital converter.

[0024] Compared with the prior art, the present application has the beneficial effects that:

[0025] The high-speed pipeline time quantization analog-digital converter of the present application adopts a time domain partial time domain interleaving structure, uses an N-channel multi-stage time quantization module to sequentially and alternately receive the initial time margin signal after the input analog signal is preliminarily quantized, and eliminates the sampling mismatch of the traditional time domain interleaving structure. The N-channel multi-stage time quantization module realizes the parallel working mode of amplification and quantization of the time margin signal, and improves the working speed.

[0026] The above description is only a summary of the technical solutions of the present application. In order to enable a clearer understanding of the technical means of the present application, the above and other purposes, characteristics and advantages of the present application can be more apparent and easy to understand, the following preferred embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 is a structural block diagram of a high-speed pipeline time-quantization analog-digital converter provided by an embodiment of the present application;

[0028] Figure 2 is a structural schematic diagram of a high-speed pipeline time-quantization analog-digital converter provided by an embodiment of the present application;

[0029] Figure 3 is a working timing schematic diagram of a sub-channel multi-stage time quantizer provided by an embodiment of the present application;

[0030] Figure 4 is a structural and clock signal schematic diagram of a multiplexer provided by an embodiment of the present application. DETAILED DESCRIPTION

[0031] In order to further illustrate the technical means and effects adopted by the present application to achieve the predetermined purpose, the following describes in detail a high-speed pipeline time-quantization analog-digital converter according to the present application in combination with the accompanying drawings and specific embodiments.

[0032] The foregoing and other technical contents, characteristics and effects of the present application can be clearly presented in the following detailed description of specific embodiments in combination with the accompanying drawings. Through the description of the specific embodiments, the technical means and effects adopted by the present application to achieve the predetermined purpose can be more deeply and specifically understood. However, the accompanying drawings are provided for reference and explanation only, and are not used to limit the technical solutions of the present application.

[0033] An embodiment of the present application provides a high-speed pipeline time-quantization analog-digital converter, please refer to Figure 1 , Figure 1 is a structural block diagram of a high-speed pipeline time-quantization analog-digital converter provided by an embodiment of the present application. As Figure 1As shown, the high-speed pipeline time-quantization analog-to-digital converter of the embodiment includes an initial time-quantization module, an N-channel multi-stage time-quantization module, and a data output module. The initial time-quantization module is configured to sample, convert, and preliminarily quantize an input analog signal to obtain a first-bit digital code and an initial time residual signal. The N-channel multi-stage time-quantization module is connected to the initial time-quantization module. The N-channel multi-stage time-quantization module includes a plurality of parallel sub-channel multi-stage time quantizers. The plurality of sub-channel multi-stage time quantizers alternately receive the initial time residual signal. Each sub-channel multi-stage time quantizer performs multi-stage quantization on the received initial time residual signal to obtain a corresponding multi-stage digital code. The data output module is connected to the initial time-quantization module and the N-channel multi-stage time-quantization module. The data output module is configured to integrate and output all the digital codes, i.e., the first-bit digital code and the multi-stage digital codes.

[0034] The high-speed pipeline time-quantization analog-to-digital converter of the embodiment adopts a time-domain partial time-interleaving structure. The N-channel multi-stage time-quantization module alternately receives the initial time residual signal after the input analog signal is preliminarily quantized, thereby eliminating the sampling mismatch of the conventional time-interleaving structure. Compared with the conventional voltage-domain partial time-interleaving structure, the use of sampling switches is reduced, and the overall power consumption is reduced.

[0035] Further, the specific structure of the high-speed pipeline time-quantization analog-to-digital converter of the embodiment is described in detail.

[0036] Please refer to Figure 2 , Figure 2 is a structural schematic diagram of a high-speed pipeline time-quantization analog-to-digital converter provided by the embodiment of the present application. As shown in Figure 2 , the initial time-quantization module of the embodiment includes a sample-and-hold circuit (S / H), a voltage-to-time converter (VTC), and a successive approximation register (SAR) time-to-digital converter (TDC) connected in sequence. The sample-and-hold circuit is configured to sample an input analog signal to obtain a sampling signal. The voltage-to-time converter is configured to map the sampling signal to a time domain to obtain a time-domain signal. The successive approximation register (SAR) time-to-digital converter (TDC) is configured to preliminarily quantize the time-domain signal to obtain a first-bit digital code and an initial time residual signal.

[0037] In the embodiment, the N-channel multi-stage time-quantization module further includes a multiplexer. The input end of the multiplexer is connected to the successive approximation register (SAR) time-to-digital converter (TDC) of the initial time-quantization module. The output end of the multiplexer is connected to the plurality of sub-channel multi-stage time quantizers. The multiplexer alternately transmits the initial time residual signal to the sub-channel multi-stage time quantizers according to a clock signal. Optionally, the number of the sub-channel multi-stage time quantizers can be an integer greater than or equal to 2.

[0038] In the high-speed pipeline time-quantization analog-to-digital converter of the embodiment, after an input analog signal is sampled by a sample-and-hold circuit, a voltage-to-time converter converts the analog signal into a time-domain signal, a first-bit digital code is obtained through a successive approximation type time-to-digital converter for preliminary time quantization, and an initial time residual signal is generated, which is input into a multiplexer.

[0039] Please refer to Figure 4 , Figure 4 is a structure of a multiplexer and a clock signal diagram provided by the embodiment of the application, as shown in Figure 4 In an alternative embodiment, the multiplexer includes a clock generator and a plurality of CMOS transmission gates connected in parallel, wherein the clock generator is configured to generate a plurality of clock signals, each clock signal is input into a corresponding CMOS transmission gate to control the conduction and shutdown of the CMOS transmission gate; the signal input end of each CMOS transmission gate receives the initial time residual signal, and the clock signal end receives the clock signal. In the embodiment, the number of CMOS transmission gates is consistent with the number of sub-channel multi-stage time quantizers, and the signal output end of each CMOS transmission gate is connected to the sub-channel multi-stage time quantizer one by one.

[0040] As shown in Figure 4 , CLK1 to CLK N are generated by the clock generator and are uniformly distributed, and sequentially delay the same phase by the same time to alternately receive the initial time residual signal Tin, and output N time signals, i.e., TO1 to TO N , which are transmitted to the plurality of sub-channel multi-stage time quantizers at the back end, achieving the purpose of partial time-domain interleaving.

[0041] It can be understood that the multiplexer can be generated using other logic gates including AND gate, OR gate, NOT gate, etc.

[0042] Please continue to refer to Figure 2 In the embodiment, the sub-channel multi-stage time quantizer includes a plurality of time amplifiers (TA) and a plurality of successive approximation type time-to-digital converters (SAR TDC) connected alternately; wherein the time amplifier and the successive approximation type time-to-digital converter form a time quantization unit, the successive approximation type time-to-digital converter of the previous time quantization unit is connected to the time amplifier of the next time quantization unit, the time amplifier of the first time quantization unit is connected to the initial time quantization module, and the successive approximation type time-to-digital converter of the last time quantization unit is connected to the data output module.

[0043] In the time quantization unit, the time amplifier amplifies the received time margin signal, and the successive approximation time-to-digital converter quantizes the amplified time margin signal to obtain the current-stage digital code and the time margin signal.

[0044] In this embodiment, the time amplifier and the SAR TDC are operated as separate pipeline stages, respectively, to achieve a parallel operation mode of the time amplifier and the SAR TDC.

[0045] Further, the timing process of the sub-channel multi-stage time quantizer of this embodiment is described, see Figure 3 , Figure 3 FIG. 1 is a schematic diagram of the working sequence of a sub-channel multi-stage time quantizer provided by an embodiment of the present invention. Figure 3 As shown, taking the first two time quantization units in a subchannel multi-stage time quantizer as an example, the first-stage (Stage 1) TA has two states: reset and time amplification. In the reset state, the TA output is reset. After the time amplification state, the TA outputs a differential time signal. The differential time signal consists of two pulse signals, and the difference between the two pulse widths is the time information to be quantized. The two differential time signals are passed to the second-stage (Stage 2) SAR TDC for quantization. Quantization results in the ADC's second-bit output code and the current-stage time margin signal. The time quantization process reduces the high-level pulse widths of the two time signals. If the pulse widths are too low, the next stage cannot quantize. Therefore, the quantized current-stage time margin signal is stored in a trigger to obtain a longer pulse width. It is then sent to the third-stage (Stage 3) TA for further time amplification. After amplification, it is quantized in the fourth-stage (Stage 4) SAR TDC to produce the third-bit digital code.

[0046] In this embodiment's sub-channel multi-stage time quantizer, the TA serves as a separate pipeline stage to amplify the time margin signal and transmit it to the SAR TDC for quantization to generate a digital code. The TA and SAR TDC each perform time margin amplification and quantization in a pipelined manner, enabling parallel amplification and quantization of the time margin signal. This significantly improves operating speed compared to the traditional time-domain pipeline ADC, which performs margin amplification and quantization serially. Furthermore, compared to the traditional asynchronous pipeline SARTDC, using the TA as a separate pipeline stage to amplify the time margin signal increases the minimum delay step size and reduces the impact of jitter and parasitics on overall ADC accuracy.

[0047] It is understandable that, in this embodiment, the SAR TDC in the initial time quantization module and the N-channel multi-stage time quantization module may also be replaced with a combination structure of other types of TDC plus a digital-to-time converter (DTC).

[0048] The high-speed pipeline time-quantization analog-digital converter of the embodiment of the application adopts a time-domain partial time-domain interleaving structure, uses N-channel multi-stage time-quantization modules to sequentially and alternately receive initial time-quantization signals of the input analog signals after preliminary quantization, and eliminates the sampling mismatch of the traditional time-domain interleaving structure. The N-channel multi-stage time-quantization modules realize the parallel working mode of amplification and quantization of the time-quantization signals, and improve the working speed.

[0049] It should be noted that, in this document, the terms such as first and second are used merely to distinguish one entity or operation from another, and do not necessarily require or imply that these entities or operations exist in any such actual relationship or order. Moreover, the terms "include", "contain" or any other variants are intended to cover non-exclusive inclusion, so that the article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed. Without more limitations, the element defined by the statement "including a" does not exclude the presence of other identical elements in the article or device including the element. The terms "connected" or "connected" and the like are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The orientations or positional relationships indicated by the terms "upper", "lower", "left", "right", and the like are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0050] The above is a further detailed description of the present application in combination with specific preferred embodiments, and the specific implementation of the present application cannot be limited to these descriptions. For ordinary skilled persons in the technical field to which the present application belongs, a number of simple deductions or substitutions can be made without departing from the concept of the present application, and all should be considered within the protection scope of the present application.

Claims

1. A high-speed pipeline time quantization analog-to-digital converter, characterized in that: include: Initial time quantization module, N-channel multi-level time quantization module and data output module, among which, The initial time quantization module is used to sample, convert and preliminarily quantize the input analog signal to obtain the first digital code and the initial time margin signal; the initial time quantization module includes a sample-and-hold circuit, a voltage-to-time converter and a successive approximation time-to-digital converter connected in sequence, wherein: The sample-and-hold circuit is used to sample the input analog signal to obtain a sampled signal; The voltage-to-time converter is used to map the sampling signal to the time domain to obtain a time domain signal; The successive approximation time-to-digital converter is used to perform preliminary quantization on the time domain signal to obtain the first digital code and the initial time margin signal; The N-channel multi-level time quantization module is connected to the initial time quantization module, and the N-channel multi-level time quantization module includes a plurality of parallel sub-channel multi-level time quantizers, the plurality of sub-channel multi-level time quantizers alternately receiving the initial time margin signal, and each sub-channel multi-level time quantizer performs multi-level quantization on the received initial time margin signal to obtain a corresponding multi-level digital code; the sub-channel multi-level time quantizer includes a plurality of time amplifiers and a plurality of successive approximation time-to-digital converters alternately connected; The time amplifier and the successive approximation time-to-digital converter form a time quantization unit, the successive approximation time-to-digital converter of the preceding time quantization unit is connected to the time amplifier of the succeeding time quantization unit, the time amplifier of the first time quantization unit is connected to the initial time quantization module, and the successive approximation time-to-digital converter of the last time quantization unit is connected to the data output module; The data output module is connected to the initial time quantization module and the N-channel multi-level time quantization module, and is used to integrate and output the first-bit digital code and the multi-level digital code.

2. The high-speed pipeline time quantization analog-to-digital converter according to claim 1, characterized in that: The N-channel multi-level time quantization module also includes a multiplexer, wherein: The input end of the multiplexer is connected to the initial time quantization module, and the output end is connected to the multiple sub-channel multi-stage time quantizers respectively; The multiplexer transmits the initial time margin signal alternately to the sub-channel multi-stage time quantizer according to the clock signal.

3. The high-speed pipeline time quantization analog-to-digital converter according to claim 2, characterized in that: The multiplexer includes a clock generator and a plurality of CMOS transmission gates connected in parallel, wherein: The clock generator is used to generate a plurality of clock signals, each clock signal is input into a corresponding CMOS transmission gate to control the conduction and closing of the CMOS transmission gate; The signal input terminal of each CMOS transmission gate receives the initial time margin signal, and the clock signal terminal receives the clock signal.

4. The high-speed pipeline time quantization analog-to-digital converter according to claim 3, characterized in that: The number of the CMOS transmission gates is consistent with the number of the sub-channel multi-stage time quantizers, and the signal output ends of the CMOS transmission gates are connected to the sub-channel multi-stage time quantizers one by one.

5. The high-speed pipeline time quantization analog-to-digital converter according to claim 1, characterized in that: In the time quantization unit, the time amplifier amplifies the received time margin signal, and the successive approximation time-to-digital converter quantizes the amplified time margin signal to obtain a digital code of a current stage and a time margin signal.

6. The high-speed pipeline time quantization analog-to-digital converter according to claim 1, characterized in that: The time amplifier and the SAR TDC are operated as separate pipeline stages respectively, so as to realize a parallel operation mode of the time amplifier and the SAR TDC.

Images