An adaptive analog-to-digital conversion device and a nanopore biological detection system

Abstract

The application discloses an adaptive analog-digital conversion device and a nanopore biological detection system, and is applied to the technical field of signal processing, and aims at solving the problems of power consumption waste and data redundancy of an analog-digital converter in reading biological signals in the prior art. Specifically, the analog-digital conversion module collects biological detection signals input by a nanopore sensor and converts the biological detection signals into digital signals; the adaptive control module detects biological analog signals or biological digital signals, judges whether a signal difference between the biological analog signals or the biological digital signals detected in two adjacent times is greater than a preset threshold value, if yes, outputs a first sampling signal to a sampling rate adjustment module, so that the sampling rate adjustment module controls the analog-digital conversion module to perform high-frequency sampling; if not, outputs a second sampling signal to the sampling rate adjustment module, so that the sampling rate adjustment module controls the analog-digital conversion module to perform low-frequency sampling, thereby effectively reducing power consumption waste and reducing redundant signal quantity.

Description

Technical Field

[0001] The present application relates to the field of signal processing technology, and in particular to an adaptive analog-to-digital conversion device and a nanopore biological detection system. Background Art

[0002] An analog-to-digital converter (ADC) is an electronic component that converts analog signals into digital signals. Since various physical quantities in real-world production and life are analog signals, and powerful CPUs and DSPs can only process digital signals, in order to collect real-world analog signals, analog circuits must be used to convert these signals into digital signals for processing and control by digital circuits. As a type of analog-to-digital converter, the SAR ADC (Successive Approximation Register Analog-to-Digital Converter) has a simple structure, with only the comparator and sample-and-hold circuit forming the analog portion. Only one comparator is required, eliminating the need for a complex operational amplifier structure and resulting in low power consumption and chip area. These characteristics make the SAR ADC suitable for a wide range of applications requiring medium-to-high precision, medium speed, and low power consumption, meeting the performance requirements of ADCs for nanopore single-molecule detection.

[0003] At present, nanopore biological detection signals are characterized by strong sparsity, burstiness, and long periods of silence. Faced with the biological signals that may be transmitted by nanopores, the existing SAR ADC architecture cannot well identify and selectively detect them, resulting in power consumption waste and data redundancy when reading biological signals. Summary of the Invention

[0004] The embodiments of the present application provide an adaptive analog-to-digital conversion device and a nanopore biological detection system to solve the problems of power consumption waste and data redundancy in the prior art analog-to-digital converter when reading biological signals.

[0005] The technical solutions provided in the embodiments of this application are as follows:

[0006] On the one hand, an embodiment of the present application provides an adaptive analog-to-digital conversion device, comprising: an analog-to-digital conversion module, an adaptive control module, and a sampling rate adjustment module;

[0007] The first input end of the analog-to-digital conversion module is connected to the output end of the external nanopore sensor, and the output end of the analog-to-digital conversion module is connected to the data receiving end of the external data processing device; the analog-to-digital conversion module is used to collect the biological analog signal input by the external nanopore sensor and convert the biological analog signal into a biological digital signal;

[0008] The input end of the adaptive control module is connected to the first input end of the analog-to-digital conversion module, and the output end of the adaptive control module is connected to the input end of the sampling rate adjustment module. The adaptive control module is used to detect the biological analog signal input to the analog-to-digital conversion module, determine the signal difference between two adjacent biological analog signals detected, and judge whether the signal difference is greater than a preset threshold value. If so, the first sampling signal is output to the sampling rate adjustment module, and if not, the second sampling signal is output to the sampling rate adjustment module; or, the input end of the adaptive control module is connected to the output end of the analog-to-digital conversion module, and the output end of the adaptive control module is connected to the input end of the sampling rate adjustment module. The adaptive control module is used to detect the biological digital signal output by the analog-to-digital conversion module, determine the signal difference between two adjacent biological digital signals detected, and judge whether the signal difference is greater than a preset threshold value. If so, the first sampling signal is output to the sampling rate adjustment module, and if not, the second sampling signal is output to the sampling rate adjustment module; wherein the frequency of the first sampling signal is higher than the frequency of the second sampling signal;

[0009] The output end of the sampling rate adjustment module is connected to the second input end of the analog-to-digital conversion module; the sampling rate adjustment module is used to provide a sampling clock signal to the analog-to-digital conversion module based on the first sampling signal so that the analog-to-digital conversion module performs high-frequency sampling, or to provide a sampling clock signal to the analog-to-digital conversion module based on the second sampling signal so that the analog-to-digital conversion module performs low-frequency sampling.

[0010] In one possible implementation, the analog-to-digital conversion module includes: a first sample-and-hold circuit, a DAC capacitor array, a comparator circuit, and a SAR logic circuit;

[0011] The first input terminal and the second input terminal of the first sample-and-hold circuit are connected to the first output terminal and the second output terminal of the external nanopore sensor, and the first output terminal and the second output terminal of the first sample-and-hold circuit are connected to the first input terminal and the second input terminal of the DAC capacitor array.

[0012] The first output terminal of the DAC capacitor array is connected to the positive input terminal of the comparator circuit, and the second output terminal of the DAC capacitor array is connected to the negative input terminal of the comparator circuit;

[0013] The output terminal of the comparator circuit is connected to the first input terminal of the SAR logic circuit;

[0014] A first output terminal of the SAR logic circuit is connected to a first control terminal of the DAC capacitor array, and a second output terminal of the SAR logic circuit is connected to a second control terminal of the DAC capacitor array;

[0015] The third output terminal of the SAR logic circuit is connected to the input terminal of the adaptive control module, or the output terminal of the first sample and hold circuit is connected to the input terminal of the adaptive control module;

[0016] The clock signal input terminals of the first sample-and-hold circuit, the comparator circuit and the SAR logic circuit are respectively connected to the corresponding output terminals of the sampling rate adjustment module.

[0017] In a possible implementation, the DAC capacitor array includes: a first capacitor array, a second capacitor array, a first switch array, and a second switch array;

[0018] The first capacitor array includes a plurality of first sampling capacitors, the second capacitor array includes a plurality of second sampling capacitors, the first switch array includes a plurality of first sampling switches, and the second switch array includes a plurality of second sampling switches;

[0019] The first end of each first sampling capacitor is connected to the first output end of the first sample-and-hold circuit and the positive input end of the comparator circuit, respectively; the second end of each first sampling capacitor is connected to the movable contact of the corresponding first sampling switch; the first static contact of each first sampling switch is connected to ground; the second static contact of each first sampling switch is connected to an external third power supply; and the control end of each first sampling switch is connected to the first output end of the SAR logic circuit;

[0020] A first end of each second sampling capacitor is connected to the second output end of the first sample-and-hold circuit and the negative input end of the comparator circuit, respectively; a second end of each second sampling capacitor is connected to the moving contact of the corresponding second sampling switch; a first static contact of each second sampling switch is connected to ground; a second static contact of each second sampling switch is connected to an external third power supply; and a control end of each second sampling switch is connected to the second output end of the SAR logic circuit.

[0021] In a possible implementation, the adaptive control module includes: a register, a subtractor, a first comparator, a first D flip-flop, a first data selector, and a first delay module;

[0022] The input terminal of the register is connected to the third output terminal of the SAR logic circuit, and the output terminal of the register is connected to the first input terminal of the subtractor;

[0023] The second input terminal of the subtractor is connected to the third output terminal of the SAR logic circuit, the output terminal of the subtractor is connected to the positive input terminal of the first comparator, and the clock input terminal of the subtractor is connected to the external low-frequency clock signal source;

[0024] The negative input terminal of the first comparator is connected to the external first power supply, and the output terminal of the first comparator is connected to the input terminal of the first D flip-flop;

[0025] An output terminal of the first D flip-flop is connected to a selection control terminal of the first data selector;

[0026] The first data input terminal of the first data selector is connected to the external high-frequency clock signal source, the second data input terminal of the first data selector is connected to the external low-frequency clock signal source, and the output terminal of the first data selector is connected to the input terminal of the sampling rate adjustment module;

[0027] The input end of the first delay module is connected to the external low-frequency clock signal source, the first output end of the first delay module is connected to the clock input end of the register, the second output end of the first delay module is connected to the clock input end of the first comparator, and the third output end of the first delay module is connected to the clock input end of the first D flip-flop.

[0028] In a possible implementation, the first delay module includes: a first delay circuit, a second delay circuit, and a third delay circuit;

[0029] The input end of the first delay circuit is connected to an external low-frequency clock signal source, the output end of the first delay circuit is connected to the input end of the second delay circuit and the clock input end of the register respectively, the output end of the second delay circuit is connected to the input end of the third delay circuit and the clock input end of the first comparator respectively, and the output end of the third delay circuit is connected to the clock input end of the first D flip-flop.

[0030] In one possible implementation, the adaptive control module includes: a charge redistribution module, a second comparator, a third comparator, an OR gate, a second D flip-flop, a second data selector, and a second delay module;

[0031] A first input terminal of the charge redistribution module is connected to the output terminal of the first sample and hold circuit, a second input terminal of the charge redistribution module is connected to an external second power supply, a first output terminal of the charge redistribution module is connected to the positive input terminal of the second comparator, and a second output terminal of the charge redistribution module is connected to the positive input terminal of the third comparator;

[0032] The negative input terminal of the second comparator is connected to the external first power supply, and the output terminal of the second comparator is connected to the first input terminal of the OR gate; the negative input terminal of the third comparator is connected to the external first power supply, and the output terminal of the third comparator is connected to the second input terminal of the OR gate;

[0033] The output terminal of the OR gate is connected to the input terminal of the second D flip-flop;

[0034] The output terminal of the second D flip-flop is connected to the selection control terminal of the second data selector;

[0035] The first data input terminal of the second data selector is connected to the external high-frequency clock signal source, the second data input terminal of the second data selector is connected to the external low-frequency clock signal source, and the output terminal of the second data selector is connected to the input terminal of the sampling rate adjustment module;

[0036] The input end of the second delay module is connected to the external low-frequency clock signal source, the first output end of the second delay module is connected to the clock input end of the second comparator and the clock input end of the third comparator respectively, the second output end of the second delay module is connected to the clock input end of the second D flip-flop, and the third output end of the second delay module is connected to the clock input end of the charge redistribution module.

[0037] In a possible implementation, the charge redistribution module includes: a first capacitor, a second capacitor, a first switch, and a second switch;

[0038] A first end of the first capacitor is connected to the first output end of the first sample-and-hold circuit, and a second end of the first capacitor is connected to the first end of the first switch and the positive input end of the second comparator respectively; a second end of the first switch is connected to the external second power supply, and a control end of the first switch is connected to the third output end of the second delay module;

[0039] The first end of the second capacitor is connected to the second output end of the first sample and hold circuit, and the second end of the second capacitor is respectively connected to the first end of the second switch and the positive input end of the third comparator; the second end of the second switch is connected to the external second power supply, and the control end of the second switch is connected to the third output end of the second delay module.

[0040] In a possible implementation, the analog-to-digital conversion module further includes: a second sample-and-hold circuit;

[0041] The input end of the second sample-and-hold circuit is connected to the output end of the external nanopore sensor, and the output end of the second sample-and-hold circuit is connected to the first input end of the charge redistribution module.

[0042] In one possible implementation, the sampling rate adjustment module includes: a clock generator;

[0043] The input end of the clock generator is connected to the output end of the adaptive control module, and the output end of the clock generator is connected to the second input end of the analog-to-digital conversion module.

[0044] On the other hand, an embodiment of the present application provides a nanopore biological detection system, comprising: a nanopore sensor, a data processing device, and an adaptive analog-to-digital conversion device as provided in an embodiment of the present application; an input end of the adaptive analog-to-digital conversion device is connected to the nanopore sensor, and an output end of the adaptive analog-to-digital conversion device is connected to the data processing device;

[0045] The nanopore sensor is used to perform biological detection on the nanopore, generate a biological simulation signal, and send the biological simulation signal to the adaptive analog-to-digital conversion device;

[0046] The adaptive analog-to-digital conversion device is used to receive the biological analog signal sent by the nanopore sensor, convert the biological analog signal into a biological digital signal, and send the biological digital signal to the data processing device;

[0047] The data processing device is used for receiving and storing the biological digital signal sent by the adaptive analog-to-digital conversion device, and performing biological analysis based on the biological digital signal.

[0048] The beneficial effects of the embodiments of the present application are as follows:

[0049] In an embodiment of the present application, an adaptive control module is set to detect the biological analog signal input to the analog-to-digital conversion module or the biological digital signal output by the analog-to-digital conversion module, and the signal difference between two adjacent detected biological analog signals or biological digital signals is determined. When the signal difference is greater than a preset threshold, it is determined that the biological analog signal or biological digital signal is in a mutation period, and a first sampling signal is output to the sampling rate adjustment module so that the sampling rate adjustment module controls the analog-to-digital conversion module to perform high-frequency sampling; when the signal difference is less than the preset threshold, it is determined that the biological analog signal or biological digital signal is in a rest period, and a second sampling signal is output to the sampling rate adjustment module so that the sampling rate adjustment module controls the analog-to-digital conversion module to perform low-frequency sampling, thereby effectively reducing power consumption waste and reducing the amount of redundant signals.

[0050] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description or be understood by practicing the present application. The purposes and other advantages of the present application can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0052] Figure 1 This is a schematic diagram of a first circuit structure of the adaptive analog-to-digital conversion device in an embodiment of the present application;

[0053] Figure 2 This is a schematic diagram of a second circuit structure of the adaptive analog-to-digital conversion device in an embodiment of the present application;

[0054] Figure 3 This is a schematic diagram of a third circuit structure of the adaptive analog-to-digital conversion device in an embodiment of the present application;

[0055] Figure 4 This is a schematic diagram of a fourth circuit structure of the adaptive analog-to-digital conversion device in an embodiment of the present application;

[0056] Figure 5 This is a schematic diagram of a fifth circuit structure of the adaptive analog-to-digital conversion device in an embodiment of the present application;

[0057] Figure 6 This is a schematic diagram of a sixth circuit structure of the adaptive analog-to-digital conversion device in an embodiment of the present application;

[0058] Figure 7 This is a seventh circuit structure diagram of the adaptive analog-to-digital conversion device in the embodiment of the present application;

[0059] Figure 8 Schematic diagram of the nanopore biological detection system framework in the embodiment of this application. DETAILED DESCRIPTION

[0060] In order to make the purpose, technical solutions and beneficial effects of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0061] It should be noted that the terms "first," "second," etc., mentioned in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that such terms are interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein.

[0062] First, the application scenarios and design concepts of the embodiments of the present application are briefly introduced.

[0063] Currently, SAR ADC (Successive Approximation Register Analog-to-Digital Converter), as a type of analog-to-digital converter, has a simple structure that does not require a complex operational amplifier structure, and has low power consumption and chip area. These characteristics make SAR ADCs suitable for a wide range of applications under the requirements of medium to high precision, medium speed, and low power consumption, meeting the performance requirements of ADCs for nanopore single-molecule detection. Nanopore biological detection signals are sparse, bursty, and accompanied by long periods of rest. When faced with the biological signals that may be transmitted by nanopores, the existing SAR ADC architecture cannot effectively identify and selectively detect them, resulting in problems of power consumption waste and data redundancy when reading biological signals.

[0064] To this end, in an embodiment of the present application, an adaptive control module is set to detect the biological analog signal input to the analog-to-digital conversion module or the biological digital signal output by the analog-to-digital conversion module, and the signal difference between two adjacent detected biological analog signals or biological digital signals is determined. When the signal difference is greater than a preset threshold, it is determined that the biological analog signal or biological digital signal is in a mutation period, and a first sampling signal is output to the sampling rate adjustment module so that the sampling rate adjustment module controls the analog-to-digital conversion module to perform high-frequency sampling; when the signal difference is less than the preset threshold, it is determined that the biological analog signal or biological digital signal is in a rest period, and a second sampling signal is output to the sampling rate adjustment module so that the sampling rate adjustment module controls the analog-to-digital conversion module to perform low-frequency sampling, thereby effectively reducing power consumption waste and reducing the amount of redundant signals.

[0065] After introducing the application scenarios and design concepts of the embodiments of the present application, the technical solutions provided by the embodiments of the present application are described in detail below.

[0066] The present application embodiment provides an adaptive analog-to-digital conversion device, see Figure 1 As shown, an adaptive analog-to-digital conversion device 100 provided in an embodiment of the present application includes at least: an analog-to-digital conversion module 110, an adaptive control module 120 and a sampling rate adjustment module 130;

[0067] The first input terminal of the analog-to-digital conversion module 110 is connected to the output terminal of the external nanopore sensor, and the output terminal of the analog-to-digital conversion module 110 is connected to the data receiving terminal of the external data processing device; the analog-to-digital conversion module 110 is used to collect the biological analog signal input by the external nanopore sensor and convert the biological analog signal into a biological digital signal;

[0068] The input end of the adaptive control module 120 is connected to the first input end of the analog-to-digital conversion module 110, and the output end of the adaptive control module 120 is connected to the input end of the sampling rate adjustment module 130. The adaptive control module 120 is used to detect the bio-analog signal input to the analog-to-digital conversion module 110, determine the signal difference between two adjacent detected bio-analog signals, and determine whether the signal difference is greater than a preset threshold. If so, the first sampling signal is output to the sampling rate adjustment module 130, and if not, the second sampling signal is output to the sampling rate adjustment module 130; or, the adaptive control module 120 The input end of the adaptive control module 120 is connected to the output end of the analog-to-digital conversion module 110, and the output end of the adaptive control module 120 is connected to the input end of the sampling rate adjustment module 130. The adaptive control module 120 is used to detect the biological digital signal output by the analog-to-digital conversion module 110, determine the signal difference between two adjacent biological digital signals detected, and judge whether the signal difference is greater than a preset threshold. If so, it outputs a first sampling signal to the sampling rate adjustment module 130; if not, it outputs a second sampling signal to the sampling rate adjustment module 130; wherein the frequency of the first sampling signal is higher than the frequency of the second sampling signal;

[0069] The output end of the sampling rate adjustment module 130 is connected to the second input end of the analog-to-digital conversion module 110; the sampling rate adjustment module 130 is used to provide a sampling clock signal to the analog-to-digital conversion module 110 based on the first sampling signal so that the analog-to-digital conversion module 110 performs high-frequency sampling, or to provide a sampling clock signal to the analog-to-digital conversion module 110 based on the second sampling signal so that the analog-to-digital conversion module 110 performs low-frequency sampling.

[0070] exist Figure 1In the illustrated adaptive analog-to-digital conversion device 100, the analog-to-digital conversion module 110 defaults to low-frequency sampling. The analog-to-digital conversion module 110 collects the bioanalog signal input from the external nanopore sensor at a relatively low sampling frequency and converts the bioanalog signal into a biodigital signal. The bioanalog signal is a biosignal detected by the nanopore sensor in the form of an analog signal, and the biodigital signal is a biosignal detected in the form of a digital signal. Different access methods for the adaptive control module 120 correspond to different signal differences. The input end of the adaptive control module 120 is connected to the first input end of the analog-to-digital conversion module 110. The adaptive control module 120 detects the bioanalog signal, and the signal difference is the signal difference between two adjacent bioanalog signals. The input end of the adaptive control module 120 is connected to the output end of the analog-to-digital conversion module 110. The adaptive control module 120 detects the biodigital signal, and the signal difference is the signal difference between two adjacent biodigital signals. When the signal difference is greater than a preset threshold, the adaptive control module 120 indicates that the biological detection signal is in a mutation phase. At this time, the adaptive control module 120 outputs a first sampling signal to the sampling rate adjustment module 130, causing the adaptive control module 120 to control the analog-to-digital conversion module 110 to perform high-frequency sampling. When the signal difference is less than the preset threshold, the biological detection signal is in a rest phase. At this time, the adaptive control module 120 outputs a second sampling signal to the sampling rate adjustment module 130, causing the adaptive control module 120 to control the analog-to-digital conversion module 110 to perform low-frequency sampling. The frequency of the first sampling signal is higher than the frequency of the second sampling signal; the first sampling signal is a high-frequency signal, while the second sampling signal is a low-frequency signal. The biological detection signal is a biological analog signal or a biological digital signal.

[0071] In specific implementation, the analog-to-digital conversion module 110 in the adaptive analog-to-digital conversion device has various structures to achieve its functions. Figure 2 As shown, the analog-to-digital conversion module 110 includes: a first sample-and-hold circuit 111, a DAC capacitor array 112, a comparator circuit 113 and a SAR logic circuit 114;

[0072] The first input terminal and the second input terminal of the first sample and hold circuit 111 are connected to the first output terminal and the second output terminal of the external nanopore sensor, and the first output terminal and the second output terminal of the first sample and hold circuit 111 are connected to the first input terminal and the second input terminal of the DAC capacitor array 112.

[0073] The first output terminal of the DAC capacitor array 112 is connected to the positive input terminal of the comparator circuit 113 , and the second output terminal of the DAC capacitor array 112 is connected to the negative input terminal of the comparator circuit 113 ;

[0074] The output terminal of the comparator circuit 113 is connected to the first input terminal of the SAR logic circuit 114;

[0075] A first output terminal of the SAR logic circuit 114 is connected to a first control terminal of the DAC capacitor array 112 , and a second output terminal of the SAR logic circuit 114 is connected to a second control terminal of the DAC capacitor array 112 ;

[0076] The third output terminal of the SAR logic circuit 114 is connected to the input terminal of the adaptive control module 120 , or the output terminal of the first sample and hold circuit 111 is connected to the input terminal of the adaptive control module 120 ;

[0077] The clock signal input terminals of the first sample and hold circuit 111 , the comparator circuit 113 and the SAR logic circuit 114 are respectively connected to corresponding output terminals of the sampling rate adjustment module 130 .

[0078] exist Figure 2 In the adaptive analog-to-digital conversion device shown, the output end of the external nanopore sensor outputs two differential signals, Vin and Vip, to the first sample-and-hold circuit 111. The first sample-and-hold circuit 111 adopts a differential structure. During the sampling phase of the adaptive analog-to-digital conversion device, the first sample-and-hold circuit performs two operations, sampling and holding, on the two analog signals, Vin and Vip, being input. The sampling operation is performed during the sampling phase, when the switch in the first sample-and-hold circuit is closed, and the first sample-and-hold circuit obtains an instantaneous value from the input analog signal. During the holding phase, the switch in the first sample-and-hold circuit is opened, and the capacitor is isolated from the input signal, maintaining this instantaneous value at a fixed voltage level until the analog-to-digital conversion process is completed. The first sample-and-hold circuit 111 is the first step in the analog-to-digital conversion module 110 in processing the input signal, and its performance determines the upper limit of the performance of the entire analog-to-digital conversion device. The comparator circuit 113 includes at least one comparator. Taking the comparator circuit 113 including one comparator as an example, after the sampling phase of the adaptive analog-to-digital conversion device 100 ends, the differential input signals Vin and Vip are directly compared in the comparator circuit 113 to obtain the digital value of the most significant bit (MSB). If the positive input signal of the comparator circuit 113 is greater than the negative input signal at this time, the comparator output is "1". If the positive input signal of the comparator circuit 113 is less than the negative input signal at this time, the comparator output is "0". The SAR logic circuit 114 structure controls the switches in the DAC capacitor array 112 according to the comparison result. The comparison cycle is repeated until the least significant bit (LSB) is determined, and the final converted biological digital signal will be output from the SAR logic circuit 114.

[0079] In specific implementation, the DAC capacitor array 112 in the analog-to-digital conversion module 110 includes a variety of structures to achieve its functions. Figure 3 As shown, the DAC capacitor array 112 includes: a first capacitor array 115, a second capacitor array 116, a first switch array 117 and a second switch array 118;

[0080] The first capacitor array 115 includes a plurality of first sampling capacitors, the second capacitor array 116 includes a plurality of second sampling capacitors, the first switch array 117 includes a plurality of first sampling switches, and the second switch array 118 includes a plurality of second sampling switches;

[0081] The first end of each first sampling capacitor is connected to the first output end of the first sample-and-hold circuit 111 and the positive input end of the comparator circuit 113, respectively. The second end of each first sampling capacitor is connected to the movable contact of the corresponding first sampling switch. The first static contact of each first sampling switch is connected to ground. The second static contact of each first sampling switch is connected to the external third power supply. The control end of each first sampling switch is connected to the first output end of the SAR logic circuit 114.

[0082] The first end of each second sampling capacitor is connected to the second output end of the first sample-and-hold circuit 111 and the negative input end of the comparator circuit 113, respectively. The second end of each second sampling capacitor is connected to the movable contact of the corresponding second sampling switch. The first static contact of each second sampling switch is connected to ground. The second static contact of each second sampling switch is connected to the external third power supply. The control end of each second sampling switch is connected to the second output end of the SAR logic circuit 114.

[0083] exist Figure 3In the adaptive analog-to-digital conversion device 100 shown, the first capacitor array 115 and the second capacitor array 116 are mirror-image capacitor arrays. The first sampling capacitors in the first capacitor array 115 are arranged in sequence, and their capacitance values ​​are halved in sequence. In addition, the capacitance values ​​of the last two first sampling capacitors in the first capacitor array 115 are the same. Similarly, the second sampling capacitors in the second capacitor array 116 are arranged in sequence, and their capacitance values ​​are halved in sequence. In addition, the capacitance values ​​of the last two second sampling capacitors in the second capacitor array 116 are the same. In addition, the capacitance values ​​of the mirror-image first sampling capacitor and the second sampling capacitor are the same. When the differential signal Vip is greater than the differential signal Vin, the MSB output by the comparator circuit 113 is "1". After being controlled by the SAR logic circuit 114, the switch S1p will be switched, and the capacitor C1 on the positive input end will be connected to GND. After the switch is switched, the next comparison is entered. For a 12-bit analog-to-digital converter, the above comparison process will be repeated 12 times until the LSB is determined. The number of sampling capacitors connected to the positive input and negative input of the comparator circuit 113 is 12 each, for a total of 24. The final converted digital signal will be output from the SAR logic circuit 114.

[0084] In practical applications, both the first sampling capacitor and the second sampling capacitor utilize a metal-oxide-metal (MOM) capacitor unit structure, with two high-layer metal layers used for the top and bottom layers of the first and second sampling capacitors. The capacitance between the metal layers is provided, and the top layer surrounds the bottom layer. The top layers of all capacitor components are connected together to form the DAC capacitor array 112, making the capacitor array more compact and minimizing the capacitance area and gradient effect.

[0085] In specific implementations, the adaptive control module 120 in the adaptive analog-to-digital conversion device 100 has various structures to achieve its functions. The adaptive analog-to-digital conversion device 100 can be divided into a digital circuit structure and a charge redistribution structure. The charge redistribution structure corresponds to the input terminal of the adaptive control module 120, which is connected to the first input terminal of the analog-to-digital conversion module 110, detecting and processing biological analog signals. The digital circuit structure corresponds to the input terminal of the adaptive control module 120, which is connected to the output terminal of the analog-to-digital conversion module 110, detecting and processing biological digital signals.

[0086] First, the adaptive control module 120 using a digital circuit structure is introduced. Figure 4 As shown, the adaptive control module 120 using a digital circuit structure includes: a register 121, a subtractor 122, a first comparator 123, a first D flip-flop 124, a first data selector 125 and a first delay module 126;

[0087] An input terminal of the register 121 is connected to the third output terminal of the SAR logic circuit 114 , and an output terminal of the register 121 is connected to the first input terminal of the subtractor 122 ;

[0088] The second input terminal of the subtractor 122 is connected to the third output terminal of the SAR logic circuit 114, the output terminal of the subtractor 122 is connected to the positive input terminal of the first comparator 123, and the clock input terminal of the subtractor 122 is connected to the external low-frequency clock signal source;

[0089] The negative input terminal of the first comparator 123 is connected to the external first power supply Vth, and the output terminal of the first comparator 123 is connected to the input terminal of the first D flip-flop 124;

[0090] The output terminal of the first D flip-flop 124 is connected to the selection control terminal of the first data selector 125;

[0091] The first data input terminal of the first data selector 125 is connected to the external high-frequency clock signal source, the second data input terminal of the first data selector 125 is connected to the external low-frequency clock signal source, and the output terminal of the first data selector 125 is connected to the input terminal of the sampling rate adjustment module 130;

[0092] The input end of the first delay module 126 is connected to the external low-frequency clock signal source, the first output end of the first delay module 126 is connected to the clock input end of the register 121, the second output end of the first delay module 126 is connected to the clock input end of the first comparator 123, and the third output end of the first delay module 126 is connected to the clock input end of the first D flip-flop 124.

[0093] exist Figure 4 In the adaptive analog-to-digital conversion device 100 shown in FIG, the clock signal output by the external low-frequency clock signal source is f L , the first clock signal f outputted from the first output terminal of the first delay module 126 L1 The clock signal f L The second clock signal f is obtained by delaying the first time and outputted from the second output terminal of the first delay module 126. L2 The first clock signal f L1 The third clock signal f is obtained by delaying the second time and outputted from the third output terminal of the first delay module 126. L3 The second clock signal f L2The biological digital signal output by the SAR logic circuit 114 is used as the input signal of the register 121 and the subtractor 122. Since there is a delay between the first clock signal fL1 input to the register 121 and the clock signal fL input to the subtractor 122, the register 121 stores the biological digital signal output by the SAR logic circuit 114 in the previous cycle and outputs it to the subtractor 122. The other input signal of the subtractor 122 is the biological digital signal output by the SAR logic circuit 114 in the current cycle. The subtractor 122 is used to perform a difference between the biological digital signal output by the SAR logic circuit 114 in the previous cycle and the biological digital signal output by the SAR logic circuit 114 in the current cycle, and obtains the signal difference V of the two adjacent digital signals at the output end of the subtractor 122. diff The first comparator 123 starts working when the rising edge of the second clock signal fL2 arrives. The first comparator 123 is used to convert the signal difference V diff Compared with the first voltage of the preset external first power supply Vth input, the signal difference V diff When the signal difference V diff When the voltage is less than the first voltage, the first comparator 123 outputs a low level. The first D flip-flop 124 starts working when the rising edge of the third clock signal fL3 arrives. The first D flip-flop 124 is used to output a high level to the selection control terminal of the first data selector 125 when the first comparator 123 outputs a high level to the first D flip-flop 124; and output a low level to the selection control terminal of the first data selector 125 when the first comparator 123 outputs a low level to the first D flip-flop 124. The first data selector 125 is a 2:1 data selector. The external high-frequency clock signal source outputs a high-frequency clock signal fL2. H , to the first data input terminal of the first data selector 125, the external low-frequency clock signal source outputs a low-frequency clock signal f L To the second data input terminal of the first data selector 125. The first data selector 125 is used to select the high frequency clock signal f when the first D flip-flop 124 outputs a high level to the selection control terminal of the first data selector 125. H As the first sampling signal, the first sampling signal is output to the sampling rate adjustment module 130; when the first D flip-flop 124 outputs a low level to the selection control terminal of the first data selector 125, the low frequency clock signal f is selected. L As the second sampling signal, the second sampling signal is output to the sampling rate adjustment module 130.

[0094] In specific implementation, the first delay module 126 has various structures to achieve its function. Figure 5 As shown, the first delay module 126 includes: a first delay circuit 127, a second delay circuit 128 and a third delay circuit 129;

[0095] The input end of the first delay circuit 127 is connected to the external low-frequency clock signal source, the output end of the first delay circuit 127 is respectively connected to the input end of the second delay circuit 128 and the clock input end of the register 121, the output end of the second delay circuit 128 is respectively connected to the input end of the third delay circuit 129 and the clock input end of the first comparator 123, and the output end of the third delay circuit 129 is connected to the clock input end of the first D flip-flop 124.

[0096] exist Figure 5 In the adaptive analog-to-digital conversion device 100 shown in FIG, the first delay module 126 outputs different clock signals by setting multiple delay circuits. The clock signal output by the external low-frequency clock signal source is f L The first clock signal f is delayed by the first time through the first delay circuit 127 to obtain the first clock signal f L1 And output, the first clock signal f L1 The second clock signal f is delayed by a second time through the second delay circuit 128 to obtain the second clock signal f L2 And output, the second clock signal f L2 The third clock signal f is delayed by a third time through the third delay circuit 129 to obtain a third clock signal f L3 And output.

[0097] Next, the adaptive control module 120 using the charge redistribution structure is introduced. Figure 6 As shown, the adaptive control module 120 using the charge redistribution structure includes: a charge redistribution module 140, a second comparator 141, a third comparator 142, an OR gate 143, a second D flip-flop 144, a second data selector 145 and a second delay module 146;

[0098] A first input terminal of the charge redistribution module 140 is connected to the output terminal of the first sample and hold circuit 111, a second input terminal of the charge redistribution module 140 is connected to the external second power supply Vcm, a first output terminal of the charge redistribution module 140 is connected to the positive input terminal of the second comparator 141, and a second output terminal of the charge redistribution module 140 is connected to the positive input terminal of the third comparator 142;

[0099] The negative input terminal of the second comparator 141 is connected to the external first power supply Vth, and the output terminal of the second comparator 141 is connected to the first input terminal of the OR gate 143; the negative input terminal of the third comparator 142 is connected to the external first power supply Vth, and the output terminal of the third comparator 142 is connected to the second input terminal of the OR gate 143;

[0100] The output terminal of the OR gate 143 is connected to the input terminal of the second D flip-flop 144;

[0101] The output terminal of the second D flip-flop 144 is connected to the selection control terminal of the second data selector 145;

[0102] A first data input terminal of the second data selector 145 is connected to an external high-frequency clock signal source, a second data input terminal of the second data selector 145 is connected to an external low-frequency clock signal source, and an output terminal of the second data selector 145 is connected to an input terminal of the sampling rate adjustment module 130;

[0103] The input end of the second delay module 146 is connected to the external low-frequency clock signal source, the first output end of the second delay module 146 is connected to the clock input end of the second comparator 141 and the clock input end of the third comparator 142 respectively, the second output end of the second delay module 146 is connected to the clock input end of the second D flip-flop 144, and the third output end of the second delay module 146 is connected to the clock input end of the charge redistribution module 140.

[0104] exist Figure 6 In the adaptive analog-to-digital conversion device 100 shown in FIG, the second delay module 146 outputs different clock signals by setting multiple delay circuits. The structure of the second delay module 146 is the same as that of the first delay circuit. Specifically, the clock signal output by the external low-frequency clock signal source is f L The fourth clock signal f is delayed by a fourth time through the fourth delay circuit to obtain a fourth clock signal f L4 And output, the fourth clock signal f L4 The fifth clock signal f is delayed by a fifth time through the fifth delay circuit to obtain a fifth clock signal f L5 And output, the fifth clock signal f L5 The sixth clock signal f is delayed by a sixth time through the sixth delay circuit to obtain a sixth clock signal f L6 The biological analog signal output by the first sampling and holding circuit 111 is used as the input signal of the charge redistribution module 140. The charge redistribution module 140 is used to control the plate delay reset of the internal capacitor at the beginning of the sampling phase to obtain the signal difference Vdiffp and Vdiffn of two adjacent analog signals. The second comparator 141 and the third comparator 142 are both based on the fourth clock signal f L4The second comparator 141 starts working when the rising edge of the clock signal f arrives. The second comparator 141 is used to compare the signal difference Vdiffp with the first voltage of the preset external first power supply Vth input. When the signal difference Vdiffp is greater than the first voltage, the second comparator 141 outputs a high level; when the signal difference Vdiffp is less than the first voltage, the second comparator 141 outputs a low level. The third comparator 142 is used to compare the signal difference Vdiffn with the first voltage of the preset external first power supply Vth input. When the signal difference Vdiffn is greater than the first voltage, the third comparator 142 outputs a high level; when the signal difference Vdiffn is less than the first voltage, the third comparator 142 outputs a low level. When at least one of the second comparator 141 and the third comparator 142 outputs a high level, the OR gate 143 outputs a high level to the second D flip-flop 144; when both the second comparator 141 and the third comparator 142 output a low level, the OR gate 143 outputs a low level to the second D flip-flop 144. The second D flip-flop 144 is turned on when the fifth clock signal f L5 The second D flip-flop 144 is used to output a high level to the selection control terminal of the second data selector 145 when the OR gate 143 outputs a high level to the second D flip-flop 144; and output a low level to the selection control terminal of the second data selector 145 when the OR gate 143 outputs a low level to the second D flip-flop 144. The second data selector 145 is a 2:1 data selector. The external high-frequency clock signal source outputs a high-frequency clock signal f H To the first data input terminal of the second data selector 145, the external low-frequency clock signal source outputs a low-frequency clock signal f L The second data selector 145 is used to select the high-frequency clock signal f when the second D flip-flop 144 outputs a high level to the selection control terminal of the second data selector 145. H As the first sampling signal, the first sampling signal is output to the sampling rate adjustment module 130; when the second D flip-flop 144 outputs a low level to the selection control terminal of the second data selector 145, the low frequency clock signal f is selected. L As the second sampling signal, the second sampling signal is output to the sampling rate adjustment module 130.

[0105] In specific implementation, the charge redistribution module 140 has various structures to achieve its functions. Figure 6 As shown, the charge redistribution module 140 includes: a first capacitor C1, a second capacitor C2, a first switch S1 and a second switch S2;

[0106] A first end of the first capacitor C1 is connected to the first output end of the first sample-and-hold circuit 111, and a second end of the first capacitor C1 is connected to the first end of the first switch S1 and the positive input end of the second comparator 141, respectively. A second end of the first switch S1 is connected to the external second power supply Vcm, and a control end of the first switch S1 is connected to the third output end of the second delay module.

[0107] A first end of the second capacitor C2 is connected to the second output end of the first sample and hold circuit 111, and a second end of the second capacitor C2 is connected to the first end of the second switch S2 and the positive input end of the third comparator 142, respectively; a second end of the second switch S2 is connected to the external second power supply Vcm, and a control end of the second switch S2 is connected to the third output end of the second delay module.

[0108] exist Figure 6 In the adaptive analog-to-digital conversion device 100 shown, a capacitor and a controllable switch are added to the first output terminal and the second output terminal of the first sample-and-hold circuit 111, respectively. Taking the first switch S1 and the first capacitor C1 corresponding to the first output terminal of the first sample-and-hold circuit 111 as an example, during the first sampling, the charge Q1 carried by the first capacitor C1 is: Q1 = (V cm -V in1 )C t , where Q1 is the charge carried by the first capacitor C1 during the first sampling, Ct is the capacitance of the first capacitor C1, Vcm is the voltage of the external second power supply Vcm, V in1 is the input voltage of the first sampling. At the second sampling, the charge Q2 carried by the first capacitor C1 is: Q2=(V diff -V in1 )C t , where Q2 is the charge carried by the first capacitor C1 during the second sampling, Ct is the capacitance of the first capacitor C1, Vcm is the voltage of the external second power supply Vcm, V in2 is the input voltage of the second sampling. According to the law of conservation of charge, Q2=Q1, then we can get V diff =V in2 -V in1 +V cm, that is, the voltage input to the positive input terminal of the second comparator 141 is the sum of the difference between the voltage signals obtained by the two samples and the external second power supply Vcm. Since the first sample and hold circuit 111 adopts a differential structure, the input signal of the first sample and hold circuit 111 is differential, that is, the sum of the two differential signals Vin and Vip input to the first sample and hold circuit 111 is a constant value. For the differential signal Vip input from the first input terminal of the first sample and hold circuit 111 and the differential signal Vip input from the second input terminal of the first sample and hold circuit 111, if the second sampling voltage Vin2 of the differential signal Vip is greater than the first sampling voltage Vin1, then the second sampling voltage Vin2 of the differential signal Vin must be less than the first sampling voltage Vin1, that is, for the V of the differential signals Vin and Vip in2 -V in1 , there must be a V in2 -V in1 greater than 0, and the other V in2 -V in1 Less than 0. Then according to the above V diff =V in2 -V in1 +V cm From the formula, we can see that the signal differences Vdiffn and Vdiffp must be one greater than Vcm and one less than Vcm. Therefore, after detecting the voltage difference between the two sampling signals, two comparators are needed to determine the size of the difference.

[0109] In one possible implementation, see Figure 7 As shown, the analog-to-digital conversion module 110 further includes: a second sample-and-hold circuit 119;

[0110] An input terminal of the second sample and hold circuit 119 is connected to an output terminal of the external nanopore sensor, and an output terminal of the second sample and hold circuit 119 is connected to a first input terminal of the charge redistribution module 140 .

[0111] exist Figure 7 In the illustrated adaptive analog-to-digital conversion device 100, to reduce interference from the operation of the charge redistribution module 140 on the analog-to-digital conversion process in the analog-to-digital conversion module 110, a second sample-and-hold circuit 119 is additionally provided between the external nanopore sensor and the charge redistribution module 140. The structure and operation of the second sample-and-hold circuit 119 are identical to those of the first sample-and-hold circuit 111. The second sample-and-hold circuit 119 is used to replicate the analog signal output by the first sample-and-hold circuit 111.

[0112] In specific implementation, the sampling rate adjustment module in the adaptive analog-to-digital conversion device has various structures to achieve its functions. The sampling rate adjustment module includes: a clock generator;

[0113] The input end of the clock generator is connected to the output end of the adaptive control module, and the output end of the clock generator is connected to the second input end of the analog-to-digital conversion module.

[0114] In practical applications, a clock generator is used to provide sampling clock signals for the first sampling and holding circuit, the comparator circuit, and the SAR logic circuit in the analog-to-digital conversion module, respectively. The sampling clock signals for the first sampling and holding circuit, the comparator circuit, and the SAR logic circuit are different and require different logic processing to obtain. When the clock generator receives a first sampling signal, it performs logic processing on the first sampling signal to obtain a high-frequency sampling clock signal for the first sampling and holding circuit, a high-frequency sampling clock signal for the comparator circuit, and a high-frequency sampling clock signal for the SAR logic circuit, respectively, and inputs these signals into corresponding circuits. When the clock generator receives a second sampling signal, it performs logic processing on the second sampling signal to obtain a low-frequency sampling clock signal for the first sampling and holding circuit, a low-frequency sampling clock signal for the comparator circuit, and a low-frequency sampling clock signal for the SAR logic circuit, respectively, and inputs these signals into corresponding circuits.

[0115] After introducing the adaptive analog-to-digital conversion device 100 provided in the embodiment of the present application, the nanopore biological detection system provided in the embodiment of the present application is briefly introduced next.

[0116] See Figure 8 As shown, the nanopore biological detection system 200 provided in the embodiment of the present application at least includes: a nanopore sensor 210, a data processing device 220, and the adaptive analog-to-digital conversion device 100 provided in the above embodiment of the present application; the input end of the adaptive analog-to-digital conversion device 100 is connected to the nanopore sensor 210, and the output end of the adaptive analog-to-digital conversion device 100 is connected to the data processing device 220;

[0117] The nanopore sensor 210 is used to perform biological detection on the nanopore, generate a biological simulation signal, and send the biological simulation signal to the adaptive analog-to-digital conversion device 100;

[0118] The adaptive analog-to-digital conversion device 100 is used to receive the bioanalog signal sent by the nanopore sensor 210, convert the bioanalog signal into a biodigital signal, and send the biodigital signal to the data processing device 220;

[0119] The data processing device 220 is used to receive and store the biological digital signal sent by the adaptive analog-to-digital conversion device 100, and perform biological analysis based on the biological digital signal.

[0120] It should be noted that, although several units or sub-units of the apparatus are mentioned in the above detailed description, such division is merely exemplary and not mandatory. Indeed, according to an embodiment of the present application, the features and functions of two or more units described above can be embodied in one unit. Conversely, the features and functions of one unit described above can be further divided into several units to be embodied.

[0121] Moreover, although the operations of the method(s) herein are described in a particular, sequential order, this order is not meant to be a limitation and is not intended to imply that

[0122] Although preferred embodiments of the application have been described herein, with reference to the accompanying drawings, it is to be understood that the application is not limited to those preferred embodiments. Rather, additional modifications and changes can be made by one skilled in the art, which modifications are also within the spirit and scope of the application. It is therefore intended that the appended claims encompass all such modifications and changes as fall within the scope of the application.

[0123] Obviously, numerous modifications and variations of the present embodiments are possible in light of the above teachings. It is therefore to be understood that within the scope of the claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. An adaptive analog-to-digital conversion device, characterized in that: include: Analog-to-digital conversion module, adaptive control module and sampling rate adjustment module; The first input end of the analog-to-digital conversion module is connected to the output end of the external nanopore sensor, and the output end of the analog-to-digital conversion module is connected to the data receiving end of the external data processing device; the analog-to-digital conversion module is used to collect the biological analog signal input by the external nanopore sensor and convert the biological analog signal into a biological digital signal; The input end of the adaptive control module is connected to the first input end of the analog-to-digital conversion module, and the output end of the adaptive control module is connected to the input end of the sampling rate adjustment module. The adaptive control module is used to detect the biological analog signal input to the analog-to-digital conversion module, determine the signal difference between two adjacent biological analog signals detected, and judge whether the signal difference is greater than a preset threshold. If so, the first sampling signal is output to the sampling rate adjustment module, and if not, the second sampling signal is output to the sampling rate adjustment module; or, the input end of the adaptive control module is connected to the output end of the analog-to-digital conversion module, and the output end of the adaptive control module is connected to the input end of the sampling rate adjustment module. The adaptive control module is used to detect the biological digital signal output by the analog-to-digital conversion module, determine the signal difference between two adjacent biological digital signals detected, and judge whether the signal difference is greater than a preset threshold. If so, the first sampling signal is output to the sampling rate adjustment module, and if not, the second sampling signal is output to the sampling rate adjustment module; wherein the frequency of the first sampling signal is higher than the frequency of the second sampling signal; The output end of the sampling rate adjustment module is connected to the second input end of the analog-to-digital conversion module; the sampling rate adjustment module is used to provide a sampling clock signal to the analog-to-digital conversion module based on the first sampling signal so that the analog-to-digital conversion module performs high-frequency sampling, or to provide a sampling clock signal to the analog-to-digital conversion module based on the second sampling signal so that the analog-to-digital conversion module performs low-frequency sampling.

2. The adaptive analog-to-digital conversion device according to claim 1, wherein: The analog-to-digital conversion module includes: a first sample-and-hold circuit, a DAC capacitor array, a comparator circuit and a SAR logic circuit; The first input terminal and the second input terminal of the first sample-and-hold circuit are connected to the first output terminal and the second output terminal of the external nanopore sensor, and the first output terminal and the second output terminal of the first sample-and-hold circuit are connected to the first input terminal and the second input terminal of the DAC capacitor array; The first output terminal of the DAC capacitor array is connected to the positive input terminal of the comparator circuit, and the second output terminal of the DAC capacitor array is connected to the negative input terminal of the comparator circuit; The output terminal of the comparator circuit is connected to the first input terminal of the SAR logic circuit; The first output terminal of the SAR logic circuit is connected to the first control terminal of the DAC capacitor array, and the second output terminal of the SAR logic circuit is connected to the second control terminal of the DAC capacitor array; The third output terminal of the SAR logic circuit is connected to the input terminal of the adaptive control module, or the output terminal of the first sample and hold circuit is connected to the input terminal of the adaptive control module; The clock signal input terminals of the first sample-and-hold circuit, the comparator circuit, and the SAR logic circuit are respectively connected to corresponding output terminals of the sampling rate adjustment module.

3. The adaptive analog-to-digital conversion device according to claim 2, wherein: The DAC capacitor array includes: a first capacitor array, a second capacitor array, a first switch array and a second switch array; The first capacitor array includes a plurality of first sampling capacitors, the second capacitor array includes a plurality of second sampling capacitors, the first switch array includes a plurality of first sampling switches, and the second switch array includes a plurality of second sampling switches; The first end of each first sampling capacitor is connected to the first output end of the first sample-and-hold circuit and the positive input end of the comparator circuit, respectively; the second end of each first sampling capacitor is connected to the movable contact of the corresponding first sampling switch; the first static contact of each first sampling switch is connected to ground; the second static contact of each first sampling switch is connected to an external third power supply; and the control end of each first sampling switch is connected to the first output end of the SAR logic circuit; A first end of each second sampling capacitor is connected to the second output end of the first sample-and-hold circuit and the negative input end of the comparator circuit, respectively; a second end of each second sampling capacitor is connected to the moving contact of a corresponding second sampling switch; a first static contact of each second sampling switch is connected to ground; a second static contact of each second sampling switch is connected to an external third power supply; and a control end of each second sampling switch is connected to the second output end of the SAR logic circuit.

4. The adaptive analog-to-digital conversion device according to claim 2, wherein: The adaptive control module includes: a register, a subtractor, a first comparator, a first D flip-flop, a first data selector and a first delay module; The input end of the register is connected to the third output end of the SAR logic circuit, and the output end of the register is connected to the first input end of the subtractor; The second input terminal of the subtractor is connected to the third output terminal of the SAR logic circuit, the output terminal of the subtractor is connected to the positive input terminal of the first comparator, and the clock input terminal of the subtractor is connected to an external low-frequency clock signal source; The negative input terminal of the first comparator is connected to an external first power supply, and the output terminal of the first comparator is connected to the input terminal of the first D flip-flop; The output terminal of the first D flip-flop is connected to the selection control terminal of the first data selector; The first data input terminal of the first data selector is connected to an external high-frequency clock signal source, the second data input terminal of the first data selector is connected to an external low-frequency clock signal source, and the output terminal of the first data selector is connected to the input terminal of the sampling rate adjustment module; The input end of the first delay module is connected to the external low-frequency clock signal source, the first output end of the first delay module is connected to the clock input end of the register, the second output end of the first delay module is connected to the clock input end of the first comparator, and the third output end of the first delay module is connected to the clock input end of the first D flip-flop.

5. The adaptive analog-to-digital conversion device according to claim 4, wherein: The first delay module includes: a first delay circuit, a second delay circuit and a third delay circuit; The input end of the first delay circuit is connected to an external low-frequency clock signal source, the output end of the first delay circuit is connected to the input end of the second delay circuit and the clock input end of the register respectively, the output end of the second delay circuit is connected to the input end of the third delay circuit and the clock input end of the first comparator respectively, and the output end of the third delay circuit is connected to the clock input end of the first D flip-flop.

6. The adaptive analog-to-digital conversion device according to claim 2, wherein: The adaptive control module includes: a charge redistribution module, a second comparator, a third comparator, an OR gate, a second D flip-flop, a second data selector and a second delay module; A first input terminal of the charge redistribution module is connected to the output terminal of the first sample and hold circuit, a second input terminal of the charge redistribution module is connected to an external second power supply, a first output terminal of the charge redistribution module is connected to the positive input terminal of the second comparator, and a second output terminal of the charge redistribution module is connected to the positive input terminal of the third comparator; The negative input terminal of the second comparator is connected to the external first power supply, and the output terminal of the second comparator is connected to the first input terminal of the OR gate; the negative input terminal of the third comparator is connected to the external first power supply, and the output terminal of the third comparator is connected to the second input terminal of the OR gate; The output end of the OR gate is connected to the input end of the second D flip-flop; The output terminal of the second D flip-flop is connected to the selection control terminal of the second data selector; The first data input terminal of the second data selector is connected to an external high-frequency clock signal source, the second data input terminal of the second data selector is connected to an external low-frequency clock signal source, and the output terminal of the second data selector is connected to the input terminal of the sampling rate adjustment module; The input end of the second delay module is connected to an external low-frequency clock signal source, the first output end of the second delay module is connected to the clock input end of the second comparator and the clock input end of the third comparator respectively, the second output end of the second delay module is connected to the clock input end of the second D flip-flop, and the third output end of the second delay module is connected to the clock input end of the charge redistribution module.

7. The adaptive analog-to-digital conversion device according to claim 6, wherein: The charge redistribution module includes: a first capacitor, a second capacitor, a first switch and a second switch; A first end of the first capacitor is connected to the first output end of the first sample-and-hold circuit, and a second end of the first capacitor is connected to the first end of the first switch and the positive input end of the second comparator, respectively; a second end of the first switch is connected to an external second power supply, and a control end of the first switch is connected to the third output end of the second delay module; The first end of the second capacitor is connected to the second output end of the first sample and hold circuit, and the second end of the second capacitor is respectively connected to the first end of the second switch and the positive input end of the third comparator; the second end of the second switch is connected to the external second power supply, and the control end of the second switch is connected to the third output end of the second delay module.

8. The adaptive analog-to-digital conversion device according to claim 7, wherein: The analog-to-digital conversion module further includes: a second sampling and holding circuit; The input end of the second sample-and-hold circuit is connected to the output end of the external nanopore sensor, and the output end of the second sample-and-hold circuit is connected to the first input end of the charge redistribution module.

9. The adaptive analog-to-digital conversion device according to any one of claims 1 to 8, wherein: The sampling rate adjustment module includes: a clock generator; The input end of the clock generator is connected to the output end of the adaptive control module, and the output end of the clock generator is connected to the second input end of the analog-to-digital conversion module.

10. A nanopore biological detection system, characterized in that: include: A nanopore sensor, a data processing device, and the adaptive analog-to-digital conversion device according to any one of claims 1 to 9, wherein the input end of the adaptive analog-to-digital conversion device is connected to the nanopore sensor, and the output end of the adaptive analog-to-digital conversion device is connected to the data processing device; The nanopore sensor is used to perform biological detection on the nanopore, generate a biological simulation signal, and send the biological simulation signal to the adaptive analog-to-digital conversion device; The adaptive analog-to-digital conversion device is used to receive the biological analog signal sent by the nanopore sensor, convert the biological analog signal into a biological digital signal, and send the biological digital signal to the data processing device; The data processing device is used to receive and store the biological digital signal sent by the adaptive analog-to-digital conversion device, and perform biological analysis based on the biological digital signal.

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