Pixel structure, pre-charging operation method and display panel

Abstract

The present invention proposes a pixel structure, a pre-charging operation method and a display panel. By adopting a special sub-pixel design, selective control of sub-pixel pre-charging is achieved, the pixel charging effect is improved, and poor image quality caused by insufficient charging is reduced. According to different pre-charging conditions, pixel pre-charging is performed by adopting a method of redistributing charges of adjacent pixels. The technical solution of the present invention realizes selective pre-charging of pixels, improves the pixel charging capacity, and improves the image quality in high refresh rate and high resolution applications.

Description

Technical Field

[0001] The present invention relates to the field of liquid crystal display panel design, process and driving technology, and in particular to a pixel structure, a pre-charging operation method and a display panel. Background Art

[0002] The current mainstream active displays (such as active liquid crystal AMLCD, micro-LED, AMOLED, etc., AMLCD is used as an example for discussion below) have reduced the charging time of each row of storage capacitors in high refresh rate and high resolution applications. The display screen adopts a line-by-line scanning method to transmit the voltage signal corresponding to the pixel grayscale of the current screen to the pixel, that is, starting from the first row at the farthest end (or the nearest end) of the Data driver IC of the panel with a vertical resolution of n, the storage capacitor voltage is written, followed by the second row, the third row, and so on, the nth row. At the end of the panel far from the Data driver IC, due to the effect of signal delay, the charging effect of the pixel storage capacitor is further reduced, and the problem of insufficient pixel charging may occur. Since the pixel storage capacitor directly determines the final brightness (grayscale) of the pixel, the situation where the entire row of pixels at the far end of the Data driver IC or even several adjacent rows are insufficiently charged is manifested in the macroscopic form that the set grayscale cannot be achieved, that is, the appearance of light or heavy horizontal stripes of poor image quality, such as gradient gray bars in a pure white picture.

[0003] In response to this situation, related fields use different panel, signal design and process solutions to improve, such as reducing the data line (Data electrode) load related to storage capacitor charging as much as possible in panel design, setting a pre-charging process in the Data signal, using Data lines with lower resistance or PVX, GI insulation layers with lower dielectric constants, etc. However, the existing technology cannot achieve selective pre-charging, resulting in poor overall pre-charging effect, which causes poor image quality. Summary of the invention

[0004] In order to solve the above technical problems, the present invention proposes a pixel structure, a pre-charging operation method and a display panel. By designing TFT1 and TFT2 with pre-charging function in the pixel structure, the effect of selectively pre-charging the pixels that need to be charged is achieved. If pre-charging does not improve the image quality, no pre-charging is performed. In hydrogenated amorphous silicon TFT products, the realization of the pre-charging module requires the use of special processes, based on the design of thin film transistors (TFTs) with different threshold voltages (Vth), so as to realize the formation of a selectable pre-charging mode.

[0005] In a first aspect, the present invention proposes a pixel structure, wherein the pixel structure includes a plurality of pixel units arranged in an array, each pixel unit includes a driving circuit of a corresponding sub-pixel, the driving circuit includes a signal electrode Di, a gate electrode Gj, a pixel electrode Pixelk, and a thin film transistor TFT0, the driving circuit also includes a thin film transistor TFT1 and a thin film transistor TFT2 for precharging, and each sub-pixel is connected to a common electrode COM;

[0006] The gate electrode of the TFT1 is connected to the gate electrode G0 corresponding to a row of sub-pixels, the drain electrode d of the TFT1 is connected to the pixel electrode Pixel0 of a row of pixels in the same column, and the source electrode s of the TFT1 is connected to the drain electrode of the TFT2;

[0007] The gate of the TFT2 is connected to the signal electrode D1 or the signal electrode D2 corresponding to the sub-pixel in the second column, and the drain d and the source s of the TFT2 are connected to the source of the TFT1 and the pixel electrode Pixel1 respectively;

[0008] Among them, i=1,2,3; j=0,1,2; k=0,1.

[0009] Furthermore, the thin film transistor TFT1 and the thin film transistor TFT2 used for precharging are obtained by the following process:

[0010] A gate electrode signal line and a gate electrode are formed on a glass substrate. After deposition, exposure, development, etching, photoresist stripping and dry etching, part of the active layer in the channel is removed to form two grooves. After a baffle shielding operation, oxygen ion bombardment is performed to form a thin film transistor TFT2 subjected to oxygen ashing treatment and a thin film transistor TFT1 not subjected to oxygen ashing treatment, and corresponding threshold voltages Vtha and Vthb are formed respectively, wherein Vtha is greater than Vthb.

[0011] In a second aspect, the present invention provides a pre-charging operation method based on the pixel structure of the first aspect, comprising:

[0012] A first condition that the pixel electrode Pixel0 and the pixel electrode Pixel1 need to be precharged is set. If the first condition is met, the pixel electrode Pixel0 or the pixel electrode Pixel1 needs to be precharged, and at this time, the thin film transistor TFT1 and the thin film transistor TFT2 in the corresponding sub-pixel are enabled for precharging, otherwise they are not enabled;

[0013] The first condition is that the maximum grayscale difference between the pixel electrodes Pixel0 and Pixel1 when precharging is not used is greater than the maximum grayscale difference when precharging is used, which is expressed by the following formula:

[0014]

[0015] Wherein, m0, n0, p0 represent the initial voltages of the pixel electrodes Pixel0, Pixel1, Pixel2 respectively; m1, n1, p1 represent the voltages after power-on in this frame respectively.

[0016] Further, the step of enabling the thin film transistor TFT1 and the thin film transistor TFT2 in the corresponding sub-pixel for pre-charging includes:

[0017] A second condition is set, and the thin film transistor TFT1 and the thin film transistor TFT2 are precharged when the second condition is met, wherein the second condition is: the gate electrode G0 is at a high voltage greater than Vthb, and the signal electrode D2 is at a high voltage greater than Vtha;

[0018] Before the display screen scans the G0 row and the conventional gate electrode of the G0 row is a high voltage signal greater than Vtha, the total charging time t of the G0 row and the pre-charging time t1 of the G1 row are set, where t1<total charging time t;

[0019] Given a high voltage of D2 greater than Vtha and a low voltage of D3 less than Vtha, Pixel0 and Pixel1 are turned on, Pixel0 and Pixel1 are pre-charged at the same time, and within time t1, the voltage of Pixel0 and Pixel1 is stabilized within a set value;

[0020] After time t1, the G0 row starts the normal charging process. At this time, D2 turns to a low voltage less than Vtha, and G0 turns to a normal pixel TFT turn-on voltage greater than Vtha. At this time, TFT2 is turned off, TFT1 is turned on, and Pixel0 is not connected to Pixel1;

[0021] After the G0 scan is completed and before the G1 scan is performed, the above steps are repeated to pre-charge Pixel1 and Pixel2.

[0022] In a third aspect, the present invention proposes a pixel structure, wherein the pixel structure includes a plurality of pixel units arranged in an array, each pixel unit includes a driving circuit of a corresponding sub-pixel, the driving circuit includes a signal electrode Di, a gate electrode Gj, a pixel electrode Pixelk, and a thin film transistor TFT0, the driving circuit also includes thin film transistors TFT1, TFT2, and TFT3 for precharging, and each sub-pixel is connected to a common electrode COM;

[0023] The gate electrode of the TFT1 is connected to the gate electrode G0 corresponding to a row of sub-pixels, the drain electrode d of the TFT1 is connected to the pixel electrode Pixel0 of a row and a column of pixels, and the source electrode s of the TFT1 is connected to the drain electrode of the TFT3;

[0024] The gate of the TFT2 is connected to the signal electrode D2 corresponding to the second column of sub-pixels, and the drain d and source s of the TFT2 are connected to the source of the TFT3 and the pixel electrode Pixel1 respectively;

[0025] The gate of the TFT3 is connected to the signal electrode D1;

[0026] Among them, i=1,2,3; j=0,1,2; k=0,1.

[0027] Furthermore, the thin film transistors TFT1, TFT2 and TFT3 used for precharging enter the precharging state when the following conditions are met:

[0028] G0>Vthb;

[0029] And D1,D2>Vtha

[0030] Wherein, D1 or D2 is converted from a negative grayscale voltage to a positive grayscale voltage.

[0031] In a fourth aspect, the present invention further proposes a display panel, comprising the pixel structure as described in the first aspect or the third aspect.

[0032] The present invention proposes a pixel structure, a pre-charging operation method and a display panel. By adopting a special sub-pixel design, selective control of sub-pixel pre-charging is achieved, the pixel charging effect is improved, and poor image quality caused by insufficient charging is reduced. In terms of manufacturing process, an oxygen ashing process with a baffle is adopted to achieve the differentiation of a-Si-based AMLCD TFT Vth. According to different pre-charging conditions, pixel pre-charging is performed by adopting a method of redistributing charges of adjacent pixels. The present invention effectively enhances the overall effect of pre-charging, improves the charging rate of pixels at the far end of the data line, and improves the image quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is a cross-sectional diagram of conventional deposition process of each film layer on a TFT substrate.

[0034] Figure 2 This is a cross-sectional view of the film layer after Half-tone mask PR glue coating, exposure and development.

[0035] Figure 3 This is the cross-sectional view of the film layer after SD etching and PR peeling.

[0036] Figure 4 This is the cross-sectional view of the film layer after Active dry etching.

[0037] Figure 5 This is a schematic diagram of the cross-section of the film layer after oxygen ashing treatment with the baffle added.

[0038] Figure 6This is a cross-sectional view of the film layer after oxygen ashing treatment with baffles.

[0039] Figure 7 This is a schematic diagram of a sub-pixel circuit of the first embodiment of the pixel structure proposed by the present invention.

[0040] Figure 8 This is a timing diagram of gate and data signals during precharging of the first embodiment of the pixel structure proposed by the present invention.

[0041] Fig. 9 This is a timing diagram of the signals of the electrodes related to Pixel0 when pre-charging is performed in the first embodiment of the pixel structure proposed in the present invention.

[0042] Fig.10 This is a schematic diagram of a sub-pixel circuit of the second embodiment of the pixel structure proposed by the present invention. DETAILED DESCRIPTION

[0043] The present application is further described in detail below in conjunction with the accompanying drawings. It is necessary to point out here that the following specific implementation methods are only used to further illustrate the present application and cannot be understood as limiting the scope of protection of the present application. Technical personnel in this field can make some non-essential improvements and adjustments to the present application based on the above application content.

[0044] The pre-charging process set in the Data signal means that when the mth row of pixels is scanned, that is, the storage capacitor voltage is written to the mth row of pixels, the same Data voltage is used to write the voltage to the (m+1)th row, (m+2)th row...(m+a)th row. Since this voltage is not the voltage actually required to be written to the (m+1)th row, (m+2)th row...(m+a)th row, it is called "pre-charging" of the (m+1)th row, (m+2)th row...(m+a)th row of pixels. For a single pixel in the mth row, let its initial voltage before pre-charging be V0, the pre-charging voltage be V1, the voltage to be written be V2, and the actual voltage after the scanning of the mth row is V3. Since V1-V0 and V2-V0 may be of the same or different signs, the use of pre-charging may cause V3≥V2 or V3>V2, that is, pre-charging may promote charging and improve image quality, or it may have the opposite effect. However, for the entire row, the entire area, and even the entire display screen, the overall effect is generally to improve image quality.

[0045] The pre-charging strategy in this application adopts the method of setting a pre-charging module in the pixel. The pre-charging module will achieve the effect of selectively pre-charging the pixels that need to be pre-charged. If the pre-charging does not improve the image quality, no pre-charging will be performed. In hydrogenated amorphous silicon TFT products, the implementation of the pre-charging module requires the use of special processes to achieve the design of thin film transistors (TFTs) with different threshold voltages (Vth), thereby forming a workable pre-charging module.

[0046] In this embodiment, to realize the function of the pre-charging module, it is necessary to perform it on the basis of the set process. a. For hydrogenated amorphous silicon (H: a-Si) based devices, it is necessary to adopt process means to perform different process treatments on the active layer of different parts of the array substrate to achieve different Vth effects in different parts.

[0047] The process means include but are not limited to oxygen ashing (O2 ashing) after the active layer photoresist is stripped. The Vth of the part where O2 ashing is performed is increased. Specifically, the following steps can be taken: (The attached figure is a cross-sectional view of each film layer of the TFT substrate, and the film layer plane design details cannot be shown)

[0048] like Figure 1 As shown, the Gate / GI layer of the TFT substrate is manufactured according to the conventional process (deposition + etching), and the Active / SD layer is deposited according to the conventional process;

[0049] like Figure 2 As shown, SD photoresist (PR) deposition, exposure, and development;

[0050] like Figure 3 As shown, the SD layer is wet etched and the PR adhesive is stripped;

[0051] like Figure 4 As shown, the channel active layer (Active) is dry-etched. The dry-etching needs to cut off the n+ layer on the upper part of the active layer, but the intrinsic a-Si should be retained as much as possible. The two grooves form TFT1 (right) and TFT2 (left) respectively;

[0052] like Figure 5 As shown, a mask is used to expose a specific area to block the surface and perform oxygen ion bombardment (oxygen ashing). In the figure, the area near TFT2 is bombarded, but the TFT1 area on the right is protected by the mask and is not bombarded;

[0053] like Figure 6 As shown, after the baffle is removed, TFT2 with Vth a is formed on the left, and TFT1 with Vth b is formed on the right. Generally, a>b, that is, TFT2 requires a higher gate (G) voltage than TFT to be turned on.

[0054] Through the above steps, TFTs with different threshold voltages can be obtained, namely, TFT2 with a normal threshold voltage and TFT 1 with a lower gate voltage.

[0055] b. For NMOS / PMOS active display devices, similar processing techniques can be adopted, or converted to CMOS technology to achieve selective pre-charging.

[0056] c. For CMOS devices, no additional process is required.

[0057] It should be noted that TFT1 and TFT2 obtained by the above process are used to precharge the sub-pixels, so it can be understood that TFT1 and TFT2 are the aforementioned pre-charging modules. Next, the pixel structure, pre-charging operation method and display panel proposed in this application are specifically described in conjunction with the accompanying drawings.

[0058] Example

[0059] In this embodiment, a pixel structure is involved. The pixel structure includes a plurality of pixel units arranged in an array. Each pixel unit includes a driving circuit of a corresponding sub-pixel. The driving circuit includes a signal electrode Di, a gate electrode Gj, a pixel electrode Pixelk, and a thin film transistor TFT0. In a conventional TFT-LCD pixel design, Figure 7 As shown, the electrodes associated with each sub-pixel include 1 signal electrode (data, D1 / D2 / D3 in the figure), 1 gate electrode (gate, G0 / G1 / G2 in the figure), 1 pixel electrode (Pixel0 / 1), and 1 TFT (TFT0). Each sub-pixel is connected to a common electrode COM, which may not be graphed in the plane (it may cover the entire display area), so it is only marked with a ground symbol. In this embodiment, in order to realize the pre-charging function, the thin film transistors TFT1 and TFT2 obtained above are added as shown in FIG. Figure 7 In the circuit shown.

[0060] like Figure 7 As shown, the gate of TFT1 is connected to the gate electrode G0 corresponding to the sub-pixel in the previous row, the drain d of TFT1 is connected to the pixel electrode Pixel0 of the same column of pixels in the previous row, and the source s of TFT1 is connected to the drain of TFT2; the gate of TFT2 is connected to the signal electrode D1 or the signal electrode D2 corresponding to the sub-pixel in the second column, and the drain d and source s of TFT2 are connected to the source of TFT1 and the pixel electrode Pixel1 respectively.

[0061] A gate electrode signal line and a gate electrode are formed on a glass substrate. After deposition, exposure, development, etching, photoresist stripping and dry etching, part of the active layer in the channel is removed to form two grooves. After a baffle shielding operation, oxygen ion bombardment is performed to form a thin film transistor TFT2 subjected to oxygen ashing treatment and a thin film transistor TFT1 not subjected to oxygen ashing treatment, and corresponding threshold voltages Vtha and Vthb are formed respectively, wherein Vtha is greater than Vthb.

[0062] The above content constructs a pre-charging module. The following specifically describes the pre-charging operation mechanism and signal setting process of the pre-charging module using the thin film transistor TFT1 and the thin film transistor TFT2.

[0063] During the pre-charging operation, it is necessary to determine whether each sub-pixel needs to be pre-charged, so a determination condition based on the maximum grayscale difference is set, which can also be considered as the first condition, specifically:

[0064] Assume that the initial voltages of Pixel0 / 1 / 2 are m0 / n0 / p0 respectively, and after charging in this frame, they are m1 / n1 / p1. To ensure that pre-charging improves the overall image quality, only the sub-pixel pre-charging process with improved maximum grayscale difference is used. Without pre-charging, the maximum grayscale difference between Pixel0 and 1 is Max(|n0-n1|,|m0-m1|), and after pre-charging, the maximum grayscale difference is The display driver chip performs calculations to determine the relationship between the two numbers, as shown below:

[0065]

[0066] If it is established, it is decided to enable the sub-pixel pre-charging, otherwise it is not enabled.

[0067] The following example illustrates the difference between enabling and disabling precharge:

[0068] exist Figure 8 , 9 In the example, the initial voltages of Pixel0 / 1 / 2 are V255 / V127 / V127, and the preset voltages of the three in this frame are V63 / V0 / V127. Let the preset voltage V63 of Pixel0 in this frame be Vx(x∈N, 0≤x≤255), then the left and right sides of inequality (1) become

[0069] Max(127-0,255-x)=Max(127,255-x) (2)

[0070]

[0071] It is easy to understand that when 0≤x<96, Pixel0 needs to be pre-charged, but when 96≤x≤255, it does not need to be pre-charged.

[0072] Similarly, when the initial voltages of Pixel0 / 1 / 2 are V255 / V0 / V0 respectively, and the preset voltages of the three in this frame are Vx / V127 / V0, it can be solved that when 1≤x≤255, Pixel0 needs to be pre-charged, and only when x=0, it is not needed. By comparison, it can be seen that the pre-charging strategy involved in this application is more effective when the charging directions of adjacent sub-pixels are opposite.

[0073] When pre - charging is required, it is also necessary to determine whether the TFT1 and TFT2, which serve as the pre - charging module, can perform pre - charging. Therefore, a second condition is set, that is: when and only when the gate electrode G0 is at a high voltage greater than Vthb and the signal electrode D2 is at a high voltage greater than Vtha, the two are jointly turned on to connect Pixel0 and Pixel1. When pre - charging Pixel1 is required, its operating mechanism is as follows:

[0074] When the display screen scans row G0, before the regular gate high - voltage (greater than Vtha) signal of row G0, a pre - charging time of row G1 with a length of t1 is set, where t1 < the total charging time t of this row.

[0075] The sub - pixel Pixel1 needs to be pre - charged, while its adjacent sub - pixel Pixel1' in the same row does not. Therefore, at this time, a high voltage (greater than Vtha) is given to D2 and a low voltage (less than Vtha) is given to D3. At this time, Pixel0 and Pixel1 are turned on, and both are pre - charged simultaneously. For example, if Pixel0 was originally 0V and Pixel1 was originally 6V, when t1 is long enough, both will stabilize at 3V.

[0076] After t1, the regular charging process of row G0 starts. At this time, D2 turns into a low voltage less than Vtha, and G0 turns into a regular pixel TFT turn - on voltage greater than Vtha. At this time, TFT2 is turned off and TFT1 is turned on, and Pixel0 and Pixel1 are not connected. Since the voltage of Pixel0 in the next frame is higher than 0V, the pre - charging process will help it quickly reach the preset voltage and prevent related defects caused by insufficient charging.

[0077] After the scan of G0 is completed and before the scan of G1, if necessary, the above steps can be repeated to pre - charge Pixel1 and Pixel2.

[0078] In this embodiment, during the above process, the signal timings of each gate and data electrode are as Figure 8 shown.

[0079] As Figure 8 shown, for each gate signal:

[0080] In each frame, it is at a high voltage VGH1 or VGH2 (Vthb < VGH1 < Vtha < VGH2) only for t time, and the rest is at VGL < Vtha; the gate signals reach the high voltage in sequence, and the time difference between the start times of the voltage rise of adjacent gate signals is t;

[0081] In the case of the pre - charging enabled state of the sub - pixels in the lower row, each high - voltage time is divided into a lower - row pre - charging time t1 and a regular charging time t2;

[0082] When the pre-charging of the lower sub-pixels is in the off state, the high-voltage time is all VGH2.

[0083] For each data signal:

[0084] When the pre-charging of the sub-pixels in the previous column is off (as in the case of D1 in the figure, that is, all sub-pixels in column D0 do not require pre-charging), the data signal voltage changes with a period of t, and each plateau corresponds to a preset voltage for a certain row (i.e., the target voltage for normal pixel charging);

[0085] When the pre-charging of the sub-pixels in the previous column is on (such as Figure 8 in the case of D2 in the figure, the sub-pixels Pixel1 and Pixel2 in D1 require pre-charging), the data signal voltage still changes with a period of t, but there are two target voltages within each period, the on-state time t1' of the pre-charging in the previous column and the normal charging time t2;

[0086] Within the t1 time, the data voltage is VP > Vtha > V255, that is, VP is a specially set voltage for turning on TFT2 and is not within the voltage range for displaying gray levels 0 - 255;

[0087] Within the remaining t2 time of each row's charging, the data signal is the target voltage for the sub-pixels in the corresponding row in the normal case.

[0088] The timing of each electrode signal related to the pre-charging of Pixel0 is as Fig. 9 shown.

[0089] a. From Vthb < VGH1 < Vtha < VGH2, it can be known that TFT1 remains in the on state throughout the high-voltage time period (with a length of t) of G0;

[0090] b. From VP > Vtha > V255, it can be known that within each data change period t, the on state time of TFT2 is t1 (or 0);

[0091] c. The pre-charging signal of Pixel0 is jointly determined by G0 and D2, and pre-charging is carried out only when both signals give corresponding high voltages (VGH1 and VGH2), where the former lasts for a time t1 and the latter lasts for a time t1';

[0092] d. Since the rising time of the gate signal must be earlier than the rising time of the data signal by a time period (GOE time), so t1 = GOE + t1', and the co-on time of TFT1 and TFT2 is t1', that is, the actual effective pre-charging time is t1';

[0093] e. Assuming that the initial voltage of Pixel0 (i.e., the preset voltage of the previous frame) is 255 grayscale voltage V255, and the preset voltage of this frame is V63, then Pixel0 will drop to V191 briefly during the pre-charging stage, and then reach V63 before the end of time t under the action of the normal pixel charging of row G0;

[0094] f. Assuming that the initial voltage of Pixel 1 is V127 and the preset voltage of this frame is V0, the pre-charge of Pixel 0 will pull it up to V191, and then the pre-charge of Pixel 1 will pull it back to V159 (assuming that the preset voltage of the sub-pixels in the next row is always V127), and finally it will drop to V0 during the regular charging of G1 row;

[0095] g. The effect of the entire Pixel0 and Pixel1 pixel pre-charging is to change the two processes of V255→V63&V127→V0 into V191→V63&V159→V0. Although the voltage difference in the second process is slightly increased and the charging time is slightly increased, the shortest charging time required for the entire block is determined by the charging status of the sub-pixel with the largest voltage difference. The maximum voltage difference before pre-charging is V255→V63 with a difference of 192 gray levels, while the maximum voltage difference after pre-charging is V159→V0 with a total of 159 gray levels, an improvement of about 16.7%.

[0096] Since TFT charging is not linear, the closer to the target voltage, the slower the charging, so the last few grayscale charging processes are actually crucial to the overall effect. In this example, the charging of Pixel0 and Pixel1 is significantly improved. If extended to the entire screen, the overall image quality will be greatly improved.

[0097] Example 2.

[0098] In this embodiment, the pixel design may also be Fig.10 The scheme, namely in the aforementioned Figure 7On the basis of pixel design, TFT3 with the same structure as TFT2 is added. TFT3 is connected in series with TFT1&2, and its gate is connected to the D1 signal line. In AMLCD display, in order to avoid polarization of liquid crystal materials, frame inversion, column inversion or other methods are generally adopted to drive sub-pixels, among which column inversion is the most commonly used, that is, D(2n+1) adopts negative grayscale voltage (such as -V255 and V255 can have almost the same optical effect), and D(2n) adopts positive grayscale voltage. In the next frame, D(2n+1) adopts positive grayscale voltage, and D(2n) adopts negative grayscale voltage. Based on the above mechanism, in the alternative scheme, G0, D1, and D2 signals are used to jointly determine the activation of the pre-charge state, that is, the pre-charge state is entered only when G0>b and D1, D2>a. At this time, D1 or D2 is converted from the original negative grayscale voltage to the positive grayscale voltage, and the D1 signal can be operated on the D2 signal line without adding the VP high voltage signal to the data line. This solution has little impact on the Pixel1' sub-pixel charging, but when Pixel1 pre-charging is turned on, Pixel1' or Pixel" pre-charging must be turned on at the same time, and further switching TFTs need to be added to achieve complete single sub-pixel pre-charging selective control.

[0099] Example 3.

[0100] This embodiment provides a display panel, which includes any one of the pixel structures provided in Embodiment 1 or 2 of the present disclosure. The display panel may include a plurality of display units surrounded by adjacent gate lines and adjacent data lines, and each display unit includes the pixel structure. Regarding other structures of the display panel, this embodiment is not limited, and reference may be made to conventional designs in the art. For example, the display panel may be a liquid crystal display panel, an organic light-emitting display panel, etc.

[0101] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0102] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0103] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A pixel structure, comprising a plurality of pixel units arranged in an array, each pixel unit comprising a driving circuit of a corresponding sub-pixel, the driving circuit comprising a signal electrode Di, a gate electrode Gj, a pixel electrode Pixelk, and a thin film transistor TFT0, characterized in that: The driving circuit further includes a thin film transistor TFT1 and a thin film transistor TFT2 for precharging, and each sub-pixel is connected to a common electrode COM; The gate of the TFT1 is connected to the gate electrode G0 corresponding to a row of sub-pixels, the drain of the TFT1 is connected to the pixel electrode Pixel0 of a row of pixels in the same column, and the source of the TFT1 is connected to the drain of the TFT2; The gate of the TFT2 is connected to the signal electrode D1 or the signal electrode D2 corresponding to the sub-pixel in the second column, and the drain and source of the TFT2 are connected to the source of the TFT1 and the pixel electrode Pixel1 respectively; Among them, i=1,2,3; j=0,1,2; k=0,1.

2. The pixel structure according to claim 1, characterized in that: The thin film transistor TFT1 and the thin film transistor TFT2 for precharging are obtained by the following process: A gate electrode signal line and a gate electrode are formed on a glass substrate. After deposition, exposure, development, etching, photoresist stripping and dry etching, part of the active layer in the channel is removed to form two grooves. After a baffle shielding operation, oxygen ion bombardment is performed to form a thin film transistor TFT2 subjected to oxygen ashing treatment and a thin film transistor TFT1 not subjected to oxygen ashing treatment, and corresponding threshold voltages Vtha and Vthb are formed respectively, wherein Vtha is greater than Vthb.

3. A pre-charging operation method of a pixel structure as claimed in claim 2, characterized in that: The method comprises: A first condition that the pixel electrode Pixel0 and the pixel electrode Pixel1 need to be precharged is set. If the first condition is met, the pixel electrode Pixel0 or the pixel electrode Pixel1 needs to be precharged, and at this time, the thin film transistor TFT1 and the thin film transistor TFT2 in the corresponding sub-pixel are enabled for precharging, otherwise they are not enabled; The first condition is that the maximum grayscale difference between the pixel electrodes Pixel0 and Pixel1 when precharging is not used is greater than the maximum grayscale difference when precharging is used, which is expressed by the following formula: Wherein, m0, n0, p0 represent the initial voltages of the pixel electrodes Pixel0, Pixel1, Pixel2 respectively; m1, n1, p1 represent the voltages after power-on in this frame respectively.

4. The pre-charging operation method according to claim 3, characterized in that: The step of enabling the thin film transistor TFT1 and the thin film transistor TFT2 in the corresponding sub-pixel for pre-charging includes: A second condition is set, and the thin film transistor TFT1 and the thin film transistor TFT2 are precharged when the second condition is met, wherein the second condition is: the gate electrode G0 is at a high voltage greater than Vthb, and the signal electrode D2 is at a high voltage greater than Vtha; Before the display screen scans the G0 row and the conventional gate electrode of the G0 row is a high voltage signal greater than Vtha, the total charging time t of the G0 row and the pre-charging time t1 of the G1 row are set, where t1<total charging time t; Given a high voltage of D2 greater than Vtha and a low voltage of D3 less than Vtha, Pixel0 and Pixel1 are turned on, Pixel0 and Pixel1 are pre-charged at the same time, and within time t1, the voltage of Pixel0 and Pixel1 is stabilized within a set value; after time t1, G0 starts the normal charging process, at which time D2 turns to a low voltage less than Vtha, G0 turns to a normal pixel TFT turn-on voltage greater than Vtha, at which time TFT2 is turned off, TFT1 is turned on, and Pixel0 and Pixel1 are not connected; After the G0 scan is completed and before the G1 scan is performed, the above steps are repeated to pre-charge Pixel1 and Pixel2.

5. A pixel structure, comprising a plurality of pixel units arranged in an array, each pixel unit comprising a driving circuit of a corresponding sub-pixel, the driving circuit comprising a signal electrode Di, a gate electrode Gj, a pixel electrode Pixelk, and a thin film transistor TFT0, characterized in that: The driving circuit further includes thin film transistors TFT1, TFT2 and TFT3 for precharging, each sub-pixel is connected to a common electrode COM; the gate of TFT1 is connected to the gate electrode G0 corresponding to a row of sub-pixels, the drain of TFT1 is connected to the pixel electrode Pixel0 of a row and a column of pixels, and the source of TFT1 is connected to the drain of TFT3; The gate of the TFT2 is connected to the signal electrode D2 corresponding to the sub-pixel in the second column, and the drain and source of the TFT2 are connected to the source of the TFT3 and the pixel electrode Pixel1 respectively; The gate of the TFT3 is connected to the signal electrode D1; Among them, i=1,2,3; j=0,1,2; k=0,1.

6. The pixel structure according to claim 5, characterized in that: The thin film transistors TFT1, TFT2 and TFT3 used for precharging enter the precharging state when the following conditions are met: G0>Vthb; And D1,D2>Vtha Wherein, D1 or D2 is converted from a negative grayscale voltage to a positive grayscale voltage.

7. A display panel comprising the pixel structure according to claim 2 or claim 6.

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