A state machine inference method and system based on Retimer chip

Abstract

The present invention discloses a state machine inference method and system based on a Retimer chip, the method comprising: the Retimer chip determines whether it is currently in a link training or test mode state; the first processing module infers the training state jump of the link training state machine of the devices connected on both sides of the Retimer chip; the second processing module infers the specific category of the test mode and records key test information; the third processing module analyzes the abnormal jump and the most likely cause of the jump according to the inferred link training state machine jump and related electrical characteristics, and outputs to a storage module; the storage module stores the input information, and outputs an interrupt signal when it is full or stops storing through a register. The present invention can restore the link training state jump of the devices on both sides of the Retimer chip under any circumstances, especially when there is a problem with the link training, and can assist in accurately locating the link training state machine jump of the device with the problem and the cause of the problem.

Description

Technical Field

[0001] The present invention relates to the technical field of state inference, and in particular to a state machine inference method and system based on a Retimer chip. Background Art

[0002] With the development of PCIe protocol, link loss is becoming more and more serious. The emergence of Retimer chip solves such problems. However, after Retimer chip is added to PCIe link, problems involving PCIe physical layer appear. However, the state machine of Retimer in PCIe specification is not standard LTSSM (Link Training State Machine). Therefore, when there is a problem in physical layer, it will be difficult to find the problem because the state of Retimer itself does not correspond to LTSSM. At present, the industry usually needs an external analysis device to capture the OS (Ordered Set) code stream or service message on the relevant link to assist in positioning. However, this method has limitations. On the one hand, after inserting the external analysis device, the current link state will be changed, and more unknown factors will be introduced, such as increasing the current link loss, and the resistance of the analysis device itself will be released and the maximum width will be released, which will affect the detection result of PCIe device, and then some unpredictable problems will occur; on the other hand, the price of this analysis device itself is very expensive, which increases a lot of expenses.

[0003] As the PCIe protocol speed increases, signal quality degradation becomes more serious. PCIe 4.0 introduces the Retimer chip to compensate for link loss. As the link scenarios become more and more complex, more and more problems will be encountered on the PCIe physical layer, and they will be more difficult to locate. It costs a lot to use analysis equipment to locate them. Summary of the invention

[0004] In view of the problems that PCIe physical layer related problems occurring in a link with a Retimer chip are difficult to locate, external analysis equipment will introduce more uncertain factors, and the cost of purchasing analysis equipment is high, the present invention provides a state machine inference method and system based on a Retimer chip. When a link with a Retimer chip encounters a problem, the Retimer state machine can be mapped to the LTSSM, thereby making it easier to find the problem without using an external analysis device.

[0005] The present invention discloses a state machine inference method based on a Retimer chip, which comprises:

[0006] Step 1, the Retimer chip determines whether it is currently in link training or test mode according to its own logic function and code stream information; if it is currently in link training state, it outputs the captured and processed physical layer signal to the first processing module and jumps to step 2; if it is currently in test mode, it outputs the signal to the second processing module and jumps to step 3;

[0007] Step 2: The first processing module performs secondary processing according to the received physical layer information, and infers the training state jump of the link training state machine of the devices on both sides of the Retimer chip; if an abnormality occurs during the inference process, it is output to the third processing module and jumps to step 4; otherwise, it is output to the storage module to store the secondary processing information and jumps to step 5;

[0008] Step 3, the second processing module performs secondary processing according to the received information, infers the specific category of the test mode, and records the key test information; if the test mode cannot be exited normally, it is output to the third processing module and jumps to step 4, otherwise it is output to the storage module to store the secondary processing information and jumps to step 5;

[0009] Step 4: The third processing module further performs judgment processing based on the inferred link training state machine jump conditions of the devices on both sides and the relevant electrical characteristics, analyzes the abnormal jump conditions and the most likely causes of the abnormal jump conditions, and outputs them to the storage module;

[0010] Step 5: The storage module stores the input information and outputs an interrupt signal when the storage is full or the storage is stopped through the register.

[0011] Furthermore, after step 5, the method further includes:

[0012] The software interface reads the data in the storage module according to the interruption and parses and outputs it to the graphical interface.

[0013] Furthermore, the step 2 comprises:

[0014] Step 21: For the link training state machine state that the Retimer chip cannot directly infer through its own digital logic, the first processing module compares the Retimer chip with the maximum link width supported by the devices connected to the two sides of the Retimer chip based on its own maximum link width when the devices connected to the two sides of the Retimer chip start to send an ordered set. If the maximum link width of the Retimer chip itself is less than the maximum link width supported by the devices connected to the two sides of the Retimer chip, it is inferred that the devices connected to the two sides of the Retimer chip have performed two resistance tests, which are recorded in the register for subsequent software analysis and identification;

[0015] Step 22, when the devices connected on both sides of the Retimer chip are in the training and configuration state, the first processing module determines the specific link training state machine sub-state of the devices connected on both sides of the Retimer chip according to the ordered set type; captures the key information in the ordered set and stores it in the register; the key information includes the maximum supported public rate, the behavior of the subsequent link and the maximum negotiated link width;

[0016] Step 23, when the devices connected to both sides of the Retimer chip are in a balanced state, the first processing module directly obtains the sub-state of the balanced devices connected to both sides of the Retimer chip according to the obtained state machine information of the Retimer itself; and obtains the coefficient information negotiated during the balanced process from the ordered set and stores it in the register; identifies the error information that may occur during the balanced process and stores it in the register;

[0017] Step 24: For the link training state machines of the devices connected on both sides of the Retimer chip, the first processing module determines the expected jump state of the link training state machine according to the specification. If it is found that the current link training state machine is not in the expected jump state, it is inferred that an abnormal jump occurs in the LTSSM, and the abnormal jump is output to the third processing module, and the process goes to step 25.

[0018] Step 25, the first processing module sends the information and timestamp related to the link training state machine inferred to be normal and the link training state machine with recoverable errors to the storage module; wherein the relevant information includes the bit stream type and the number of state jumps for error recovery.

[0019] Furthermore, the step 3 comprises:

[0020] Step 31, if the second processing module infers that the link training state machine is to be guided into the test mode to test the consistency of the electrical signal according to the domain segment and timeout of the OS information, a specific branch for entering the consistency of the electrical signal will be obtained; if a consistency test mode is inferred, the corresponding test code stream number will be output together; if it is inferred that the consistency test is entered directly or the consistency test is entered by receiving the code stream, it will be determined whether the current test code stream type is a modified consistency test code pattern or a standard consistency test code pattern;

[0021] Step 32: If the second processing module enters the test mode for loopback test according to the link training state machine of the domain segment of the ordered set information, the data path of the loopback is determined according to the state machine information of the second processing module to obtain whether the loopback is in the forwarding loopback test mode or the independent loopback test mode; and whether the speed cut and balancing are required for entering the mode according to the bit stream information of the second processing module;

[0022] Step 33: When the second processing module infers that the test mode cannot be entered or exited normally, the information is output to the third processing module;

[0023] Step 34: The second processing module outputs each set of information obtained previously to the storage module according to the timestamp relationship.

[0024] Furthermore, the step 4 comprises:

[0025] Step 41, when the third processing module processes the received information and infers that the abnormal situation at this time is an abnormal speed drop scenario of link training or an abnormal jump occurs in the test mode or the test mode cannot be exited normally, it infers and distinguishes the detection and recovery speed states according to the rate change and the number of electrical idle times;

[0026] Step 43: The third processing module infers the link training state machine jump of the unrecoverable error based on all the information it receives, and analyzes and determines the most likely cause of the abnormality;

[0027] Step 44: The third processing module outputs each set of inferred abnormal jump state machine information, key code stream information and abnormal cause to the storage module according to the timestamp relationship.

[0028] Furthermore, in step 41, the detection state and the speed recovery state will not send any ordered set and are both in electrical idle state.

[0029] Furthermore, the step 4 comprises:

[0030] Step 42: When the third processing module processes the received information and infers that the test mode cannot be entered or exited normally, it processes the key information of the relevant code stream or test pattern again, and infers the subsequent link training state machine jump situation according to the electrical characteristics;

[0031] Step 43: The third processing module infers the link training state machine jump of the unrecoverable error based on all the information it receives, and analyzes and determines the most likely cause of the abnormality;

[0032] Step 44: The third processing module outputs each set of inferred abnormal jump state machine information, key code stream information and abnormal cause to the storage module according to the timestamp relationship.

[0033] Furthermore, the step 5 comprises:

[0034] Step 51, configuring the storage module with the required triggering conditions;

[0035] Step 52: The storage module identifies the received information and writes it into the built-in memory when the received information meets the trigger condition;

[0036] Step 53: When the memory is full or the software configuration register stops storing, an interrupt signal is output.

[0037] Further, the step 6 comprises:

[0038] Step 61, the software interface starts to read the information in the storage module according to the output interrupt signal; after reading, the link training state machine information is decoded to obtain the corresponding link training state machine jump;

[0039] Step 62: for the link training state machine state in which the link training state machine is in electrical idle state, the time in which the link training state machine is in electrical idle state is calculated according to the timestamp information; for the detection state, the number of detections performed by the link training state machine is decoded and recorded according to the information of the number of detections;

[0040] Step 63: When the Retimer state machine is in forwarding mode, the link training state machine provides the key information domain of the forwarding mode; when the Retimer state machine is in execution mode for balancing, the coefficients of the Retimer state machine evaluating the opposite end and the coefficients of the opposite end evaluating itself are provided; when the Retimer state machine is in a related test mode, the key test information parameters are provided;

[0041] Step 64: After the interpretation is completed, it is displayed in a graphical interface according to the timestamp for the user to view.

[0042] The present invention also discloses a state machine inference system based on a Retimer chip, which implements any of the above-mentioned state machine inference methods based on a Retimer chip, and includes a Retimer state machine, a first processing module, a second processing module, a third processing module, and a storage module; the Retimer state machine is connected to the third processing module through the first processing module and the second processing module respectively, and the third processing module is connected to the storage module; the first processing module and the second processing module are both connected to the storage module; the storage module is connected to an external display terminal, and the external display terminal has a graphical interface.

[0043] Due to the adoption of the above technical solution, the present invention has the following advantages:

[0044] 1. The present invention combines and organizes the corresponding link information (OS code stream, etc.), and outputs it through the built-in storage block, which can accurately diagnose problems related to PCIe link training. And further analyzes and outputs a graphical interface through software to help users effectively and simply locate problems.

[0045] 2. The present invention can infer all LTSSM jump conditions defined in the PCIe specification, including but not limited to link training, test mode and low power consumption mode.

[0046] 3. The present invention can realize real-time monitoring of PCIe link scenarios through the Retimer chip, and can effectively and accurately locate general PCIe physical layer problems.

[0047] 4. The present invention can realize a simple PCIe analyzer function at the system level, replacing the traditional external analysis equipment, greatly reducing the cost of locating PCIe link problems and improving the accuracy.

[0048] 5. The present invention can restore the link training state jump of the devices on both sides of the Retimer chip under any circumstances. Especially when there is a problem with the link training, it can help accurately locate the link training state machine jump of the problematic device and the cause of the problem. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments recorded in the embodiments of the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0050] Figure 1 A schematic flow chart of a state machine inference method based on a Retimer chip according to an embodiment of the present invention;

[0051] Figure 2 A schematic diagram of a state machine inference system based on a Retimer chip according to an embodiment of the present invention;

[0052] Figure 3 The figure is a schematic diagram of the network of the root connector, Retimer and endpoint devices according to an embodiment of the present invention. DETAILED DESCRIPTION

[0053] The present invention is further described in conjunction with the accompanying drawings and embodiments, and the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field should fall within the scope of protection of the embodiments of the present invention.

[0054] In order to clearly display the LTSSM jumps on both sides of the Retimer chip and more efficiently locate the problems related to the link with the Retimer chip, the state machine inference function is implemented. Figure 1 The present invention provides a state machine inference method based on a Retimer chip, which comprises:

[0055] S1, the Retimer state machine determines whether it is currently in link training or test mode based on its own logical function and code stream information. If it is currently in normal power-on training state, it outputs the captured and processed physical layer signal to the first processing module and jumps to S2. Otherwise, it outputs the signal to the second processing module and jumps to S3.

[0056] S2, the first processing module performs secondary processing according to the received information to infer the training status jump of the LTSSM on both sides. If an abnormal situation occurs during the process, it is output to the third processing module and jumps to S4. Otherwise, it is output to the storage module to store the secondary processing information and jumps to S5.

[0057] S3, the second processing module performs secondary processing based on the received information to infer the specific category of the test mode and record the key test information. If the test mode cannot be exited normally, it is output to the third processing module and jumps to S4. Otherwise, it is output to the storage module to store the secondary processing information and jumps to S5.

[0058] S4. The third processing module needs to perform further judgment processing based on the inferred LTSSM jump situation and related electrical characteristics, analyze the abnormal jump situation and the most likely cause of this situation, and output it to the storage module.

[0059] S5. The storage module stores the input information and outputs an interrupt signal when it is full or storage stops through the register.

[0060] S6. The software interface reads the data in the storage module according to the interrupt signal and parses and outputs it to the graphical interface.

[0061] In one embodiment, S2 includes the following steps:

[0062] S21. For the LTSSM state that the Retimer chip cannot directly infer through its own digital logic, such as the resistance detection state, the first processing module compares the maximum link width of the Retimer chip with the maximum link width supported by the link partner when the link partner (the device connected on both sides of the Retimer chip) starts to send an OS (ordered set). If the maximum link width of the Retimer chip itself is smaller than the maximum link width supported by the link partner, it is inferred that the link partner has performed two resistance tests, which are recorded in the register for subsequent software analysis and identification.

[0063] S22, when the link partner is in the rotation training and configuring these LTSSM states, the first processing module first determines the specific link training state machine sub-state of the link partner according to the OS type; then it captures the key information in the OS, such as the maximum supported public rate, the behavior of the subsequent link, the maximum negotiated link width and other information and stores them in the register;

[0064] S23, when the link partner performs balancing, the first processing module directly obtains the sub-state of the link partner balancing according to the obtained state machine information of the Retimer itself; and obtains the coefficient information negotiated during the balancing process from the OS and stores it in the register; finally, it is also necessary to identify the error information that may occur during the balancing and store it in the register;

[0065] S24. For the link training state machine of the link partner, the first processing module defines the expected jump state of the link training state machine according to the specification. If it is found that the current link training state machine is not in the expected jump state, it is inferred that an abnormal jump occurs in the LTSSM, and the abnormal jump is output to the third processing module, and the process jumps to step 25.

[0066] S25. The first processing module sends information and timestamps related to the link training state machine inferred to be normal and the link training state machine with recoverable errors to the storage module; wherein the relevant information includes the bit stream type and the number of state jumps for error recovery.

[0067] Through the above technical solution, if the link training state machine does not match the expected jump state, it is determined that the link training state machine has a problem, otherwise it is normal. The approximate time when the link training state machine has a problem can be obtained through the timestamp information.

[0068] In one embodiment, S3 includes the following steps:

[0069] S31. If the second processing module infers that the link training state machine is to be guided into the test mode to test the consistency of the electrical signal based on the domain segment and timeout of the OS information, it will derive the specific branch for entering the electrical signal consistency; if the consistency test mode is inferred, the corresponding test code stream number will be output together; if it is inferred that the consistency test is to be entered directly or the consistency test is to be entered by receiving the code stream, it will be determined whether the current test code stream type is a modified consistency test code pattern or a standard consistency test code pattern.

[0070] S32. If the second processing module enters the test mode for loopback test according to the link training state machine of the domain segment of the OS information, it first determines the data path passed by the loopback according to its own state machine information to obtain whether the loopback is in the forward loopback test mode or the follower loopback test mode; then, according to the code stream information for entering this mode, it determines whether it is necessary to cut the speed and perform balancing when entering this mode.

[0071] S33: When the second processing module infers that the test mode cannot be entered or exited normally, the information is output to the third processing module.

[0072] S34, the second processing module outputs each set of information obtained previously to the storage module according to the timestamp relationship.

[0073] In one embodiment, S4 includes the following steps:

[0074] S41. When the third processing module processes the received information and infers that the abnormal situation is an abnormal speed drop scenario in link training or an abnormal jump in the test mode or an inability to exit the test mode normally, it will infer and distinguish between resistance detection and speed recovery (these two states will not send any OS and are both in electrical idle) state according to the rate change and the number of electrical idle times.

[0075] S43, the third processing module outputs each set of inferred abnormal jump state machine information, key code stream information and abnormal cause to the storage module according to the timestamp relationship.

[0076] S44. The third processing module outputs each set of inferred abnormal jump information to the storage module according to the timestamp relationship.

[0077] Alternatively, S4 comprises the following steps:

[0078] S42: The third processing module infers the unrecoverable erroneous link training state machine jump situation based on all the information it receives, and analyzes and determines the most likely cause of the abnormality.

[0079] S43, the third processing module outputs each set of inferred abnormal jump state machine information, key code stream information and abnormal cause to the storage module according to the timestamp relationship.

[0080] S44. The third processing module outputs each set of inferred abnormal jump information to the storage module according to the timestamp relationship.

[0081] Generally, there are two types of link problems: one is recoverable (corresponding to S2); the other is currently unrecoverable (corresponding to S4); the recoverable one will not affect the final result of link training, while the unrecoverable one needs to restart from the resistance detection state or from a certain state (for example, unable to enter or exit normally). Therefore, the present invention can restore the link training state jump of the devices on both sides of the Retimer chip under any circumstances, especially when there is a problem with the link training, it can help accurately locate the link training state machine jump of the device with the problem and the cause of the problem.

[0082] In one embodiment, S5 includes the following steps:

[0083] S51, configuring the storage module with the required triggering conditions;

[0084] S52, identifying the received information, and when the received information meets the trigger condition, writing it into the built-in SRAM (static random access memory);

[0085] S53: When the SRAM is full or the software configuration register stops storing, an interrupt signal is output.

[0086] In one embodiment, S6 includes the following steps:

[0087] S61, the software interface starts to read the information in the storage module according to the output interrupt signal;

[0088] S62, after reading the blank, decode the LTSSM state machine information to obtain the corresponding LTSSM state machine jump;

[0089] S63, for the link partner in the LTSSM state of electrical idleness, calculate the time in which the link partner is in the electrical idleness according to the timestamp information;

[0090] S64, for resistance detection, according to the information of resistance detection times, decode the resistance detection times performed by the link partner and record it;

[0091] S65. When the Retimer state machine is in the forwarding mode, in the specific LTSSM state machine state of the link partner, identify the key information fields of this state, such as how many OSs are sent and received, and whether the OS type changes in this state.

[0092] S66. When the Retimer is in execution mode for balancing, a coefficient for the Retimer state machine to evaluate the peer end and a coefficient for the peer end to evaluate itself are given.

[0093] S67. When the Retimer is in a related test mode, key test information parameters are provided.

[0094] S68. After the interpretation is completed, it is displayed in a graphical interface according to the timestamp for the user to view.

[0095] The present invention can infer all LTSSM jump situations defined in the PCIe specification, and is applicable not only to link training and test modes, but also to low power consumption modes and the like.

[0096] See also Figure 2 The present invention also provides an embodiment of a state machine inference system based on a Retimer chip, which implements a state machine inference method based on a Retimer chip described in the above embodiment, which includes a Retimer state machine, a first processing module, a second processing module, a third processing module, and a storage module; the Retimer state machine is connected to the third processing module through the first processing module and the second processing module respectively, and the third processing module is connected to the storage module; the first processing module and the second processing module are both connected to the storage module; the storage module is connected to an external display terminal, and the external display terminal has a graphical interface.

[0097] For ease of understanding, the present invention provides the following specific implementation examples:

[0098] Implementation Example 1:

[0099] See also Figure 3 Taking the networking of the root connector (RC), Retimer and endpoint device (EP) as an example, all three support the PCIeGen5 rate (i.e. 64GT / s). At this time, RC and EP are the link partners of the Retimer.

[0100] Involving the Retimer state machine, the first processing module, the storage module and the software interface, the scenario is RC / Retimer / EP normal link training to the Gen5 rate.

[0101] 1. After the electrolytic reset on the chip, when the Retimer state machine receives the RC bit stream for the first time, this information will be passed to the first processing module. After analysis, the first processing module can infer that the LTSSM of the RC is in the rotation training state. Similarly, when the Retimer state machine receives the EP bit stream for the first time, the information will be passed to the first processing module. After analysis, the first processing module can infer that the LTSSM of the EP is in the rotation training state.

[0102] 2. The Retimer state machine continuously transmits the code stream information and its own state machine jump status to the first processing module.

[0103] 3. When the first processing module finds that the link number field in the received code stream has changed, it is inferred that the LTSSM of the RC / EP is in the sub-state of negotiating the link number in the configuration state.

[0104] 4. When the first processing module finds that the channel number field in the received code stream has changed, it is inferred that the LTSSM of the RC / EP is in the sub-state of negotiating the channel number under the configuration state.

[0105] 5. When the code stream type sent by the first processing module changes, it is inferred that the LTSSM of the RC / EP is in the final handshake state under the configuration state.

[0106] 6. When the type of the code stream received by the first processing module changes from a training code stream to a data code stream, it is inferred that the LTSSM of the RC / EP is in a working state with a rate of Gen1.

[0107] 7. When the first processing module finds that the received code stream changes from a data code stream to a training code stream, and the rate domain segment in the code stream changes to the decoding corresponding to Gen5, it is inferred that the LTSSM of RC / EP is in a recovery state and is ready to switch to the Gen5 rate.

[0108] 8. When the first processing module obtains that RC / EP stops sending code streams and enters the idle state machine, and the Retimer state machine informs itself that it is also in the speed cutting state, it is inferred that RC / EP is in the speed cutting sub-state of the recovery state at this time.

[0109] 9. When the first processing module can again obtain the received code stream information sent by the Retimer state machine, it is inferred that RC / EP is now in the recovery state of GEN5 rate.

[0110] 10. When the code stream type received by the first processing module changes from training code stream to data code stream, it is inferred that the LTSSM of RC / EP is in the working state of rate Gen5 at this time, and the link training is completed. The first processing module sends all the above inference information to the storage module.

[0111] 11. After the storage module completes the storage, it pulls the interrupt low, and the data is read out by the software interface for processing, and finally displayed graphically to the user.

[0112] The above technical solution can accurately diagnose problems related to PCIe link training. The software can further analyze and output a graphical interface to help users effectively and simply see the link building process.

[0113] Implementation Example 2:

[0114] See also Figure 3Taking the networking of the root connector (RC), Retimer and endpoint device (EP) as an example, all three support the PCIeGen5 rate (i.e. 64GT / s). At this time, RC and EP are the link partners of the Retimer.

[0115] It involves the Retimer state machine, the first processing module, the third processing module, the storage module and the software interface. The scenario is that the RC / Retimer / EP link is trained to the Gen5 rate and the EP abnormally drops back to the Gen1 rate.

[0116] 1. Similar to steps 1-9 of implementation example 1, the first processing module finds that after a period of time, the Retimer state machine does not provide the code stream information to the EP side, and the Retimer state machine informs the first processing module that RC / EP is in an idle state and does not send a code stream. When its own state machine is ready to switch back to Gen1, the first processing module sends the inference information before this to the storage module, and transfers the relevant code stream information from this time on to the third processing module.

[0117] 2. The third processing module starts working. According to the previous information, it is concluded that it is an abnormal rate drop scenario. And because the bitstream information on the EP side has not been received before, it can be inferred that there is a problem with the link between the Retimer and the EP.

[0118] 3. The third processing module checks whether there is a problem with the receiving side of the Retimer connected to the EP through the information sent by the first processing module. If there is only no code stream information, but the electrical layer tells that the EP was not in an idle state at that time, it is inferred that the receiving side of the Retimer is abnormal and cannot lock the information sent by the EP; if the EP was in an idle state at the electrical layer, it is inferred that there is a problem with the EP in this speed cut.

[0119] 4. The third processing module continues to obtain information from the first module. When it is found that the code stream type has changed to a data code stream and the Retimer rate is Gen1, it is concluded that the link training is completed at this time and abnormal training is performed to the Gen1 rate.

[0120] 5. The third processing module sends the relevant inference information to the storage module, and when the storage module has completed the storage, it outputs an interrupt signal.

[0121] 6. The software interface sees the interruption and starts to read the relevant data. After processing, it displays the data graphically to the customer and informs the cause of the abnormality.

[0122] Through the above technical solution, it is possible to accurately infer whether there is a problem with the link between the Retimer and the EP, to achieve real-time monitoring of the PCIe link scenario, and to effectively locate general PCIe physical layer problems.

[0123] Implementation Example 3:

[0124] See also Figure 3 Taking the networking of the root connector (RC), Retimer and endpoint device (EP) as an example, all three support the PCIeGen5 rate (i.e. 64GT / s). At this time, RC and EP are the link partners of the Retimer.

[0125] Involving the Retimer state machine, the second processing module, the storage module and the software interface, the scenario is the RC / Retimer / EP forwarding loopback test mode.

[0126] 1. After the normal link training is completed, the RC side actively requests to enter the forwarding loopback test. After the Retimer state machine receives the corresponding code stream, it notifies the second processing module to start working.

[0127] 2. The second processing module determines that the forwarding loopback test mode is about to be entered according to the RC side code stream information. At this time, it can be inferred that the RC enters the preparation sub-state of the loopback state.

[0128] 3. When the second processing module first obtains the code stream on the EP side carrying the information of entering the forwarding loopback test mode, it infers that the EP is in the preparation sub-state of the loopback state. When the second processing module finds that multiple such code streams are received continuously from the EP side, it infers that the EP enters the active sub-state of the loopback state.

[0129] 4. When the second processing module obtains from the Retimer state machine that the EP side has sent multiple code streams with information of entering the forwarding loopback test mode, it infers that the RC enters the active sub-state of the loopback state. At this time, the link is in the forwarding loopback test mode.

[0130] 5. When the second processing module obtains from the Retimer state machine that RC begins to enter electrical idle, it means that the loopback test is over, and it is inferred that RC enters the exit sub-state of the loopback state. Similarly, when the second processing module obtains from the Retimer state machine that EP begins to enter electrical idle, it means that the loopback test is over, and it is inferred that EP enters the exit sub-state of the loopback state. At this time, the forwarding loopback test mode ends, and the second processing module sends the information to the storage module.

[0131] 6. The storage module stores the relevant information and outputs an interrupt signal.

[0132] 7. The software interface starts reading relevant information based on the interrupt, and after processing, it graphically displays the test process.

[0133] Through the above technical solution, the sub-state jump situation of the EP when entering the loopback state can be inferred, which can help accurately locate the link training state machine jump situation of the problematic device and the cause of the problem.

[0134] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A state machine inference method based on a Retimer chip, characterized in that: include: Step 1: The Retimer chip determines whether it is currently in link training or test mode based on its own logic function and bit stream information; If the link is currently in the training state, the captured physical layer signal is output to the first processing module, and the process goes to step 2; If the current state is in the test mode, the signal is output to the second processing module and the process goes to step 3; Step 2: The first processing module performs secondary processing according to the received physical layer information to infer the training state jump of the link training state machine of the devices on both sides of the Retimer chip; If an abnormality occurs during the inference process, it is output to the third processing module and jumps to step 4; otherwise, it is output to the storage module to store the secondary processing information and jumps to step 5; Step 3, the second processing module performs secondary processing according to the received information, infers the specific category of the test mode, and records the key test information; if the test mode cannot be exited normally, it is output to the third processing module and jumps to step 4, otherwise it is output to the storage module to store the secondary processing information and jumps to step 5; Step 4: The third processing module further performs judgment processing based on the inferred link training state machine jump conditions of the devices on both sides and the relevant electrical characteristics, analyzes the abnormal jump conditions and the most likely causes of the abnormal jump conditions, and outputs them to the storage module; Step 5: The storage module stores the input information, and outputs an interrupt signal when the storage is full or the storage is stopped through the register; Step 6: The software interface reads the data in the storage module according to the interruption and parses and outputs it to the graphical interface; The step 2 comprises: Step 21: For the link training state machine state that the Retimer chip cannot directly infer through its own digital logic, the first processing module compares the Retimer chip with the maximum link width supported by the devices connected to the two sides of the Retimer chip based on its own maximum link width when the devices connected to the two sides of the Retimer chip start to send an ordered set. If the maximum link width of the Retimer chip itself is less than the maximum link width supported by the devices connected to the two sides of the Retimer chip, it is inferred that the devices connected to the two sides of the Retimer chip have performed two resistance tests, which are recorded in the register for subsequent software analysis and identification; Step 22, when the devices connected on both sides of the Retimer chip are in the training and configuration state, the first processing module determines the specific link training state machine sub-state of the devices connected on both sides of the Retimer chip according to the ordered set type; captures the key information in the ordered set and stores it in the register; the key information includes the maximum supported public rate, the behavior of the subsequent link and the maximum negotiated link width; Step 23, when the devices connected to both sides of the Retimer chip are in a balanced state, the first processing module directly obtains the sub-state of the balanced devices connected to both sides of the Retimer chip according to the obtained state machine information of the Retimer itself; and obtains the coefficient information negotiated during the balanced process from the ordered set and stores it in the register; identifies the error information that may occur during the balanced process and stores it in the register; Step 24: For the link training state machines of the devices connected on both sides of the Retimer chip, the first processing module determines the expected jump state of the link training state machine according to the specification. If it is found that the current link training state machine is not in the expected jump state, it is inferred that an abnormal jump occurs in the LTSSM, and the abnormal jump is output to the third processing module, and the process goes to step 25. Step 25, the first processing module sends the information and timestamp related to the link training state machine inferred to be normal and the link training state machine with recoverable errors to the storage module; wherein the relevant information includes the bit stream type and the number of state jumps for error recovery.

2. The state machine inference method based on the Retimer chip according to claim 1, characterized in that: The step 3 comprises: Step 31, if the second processing module infers that the link training state machine is to be guided into the test mode to test the consistency of the electrical signal according to the domain segment and timeout of the OS information, a specific branch for entering the consistency of the electrical signal will be obtained; if a consistency test mode is inferred, the corresponding test code stream number will be output together; if it is inferred that the consistency test is entered directly or the consistency test is entered by receiving the code stream, it will be determined whether the current test code stream type is a modified consistency test code pattern or a standard consistency test code pattern; Step 32: If the second processing module enters the test mode for loopback test according to the link training state machine of the domain segment of the ordered set information, the data path of the loopback is determined according to the state machine information of the second processing module to obtain whether the loopback is in the forwarding loopback test mode or the independent loopback test mode; and whether the speed cut and balancing are required for entering the mode according to the bit stream information of the second processing module; Step 33: When the second processing module infers that the test mode cannot be entered or exited normally, the information is output to the third processing module; Step 34: The second processing module outputs each set of information obtained previously to the storage module according to the timestamp relationship.

3. The state machine inference method based on the Retimer chip according to claim 1, characterized in that: The step 4 comprises: Step 41, when the third processing module processes the received information and infers that the abnormal situation at this time is an abnormal speed drop scenario of link training or an abnormal jump occurs in the test mode or the test mode cannot be exited normally, it infers and distinguishes the detection and recovery speed states according to the rate change and the number of electrical idle times; Step 43: The third processing module infers the link training state machine jump of the unrecoverable error based on all the information it receives, and analyzes and determines the most likely cause of the abnormality; Step 44: The third processing module outputs each set of inferred abnormal jump state machine information, key code stream information and abnormal cause to the storage module according to the timestamp relationship.

4. The state machine inference method based on the Retimer chip according to claim 3 is characterized in that: In step 41, the detection state and the speed recovery state do not send any ordered set and are both in electrical idle state.

5. The state machine inference method based on the Retimer chip according to claim 1, characterized in that: The step 4 comprises: Step 42: When the third processing module processes the received information and infers that the test mode cannot be entered or exited normally, it processes the key information of the relevant code stream or test pattern again, and infers the subsequent link training state machine jump situation according to the electrical characteristics; Step 43: The third processing module infers the link training state machine jump of the unrecoverable error based on all the information it receives, and analyzes and determines the most likely cause of the abnormality; Step 44: The third processing module outputs each set of inferred abnormal jump state machine information, key code stream information and abnormal cause to the storage module according to the timestamp relationship.

6. The state machine inference method based on the Retimer chip according to claim 1, characterized in that: The step 5 comprises: Step 51, configuring the storage module with the required triggering conditions; Step 52: The storage module identifies the received information and writes it into the built-in memory when the received information meets the trigger condition; Step 53: When the memory is full or the software configuration register stops storing, an interrupt signal is output.

7. The state machine inference method based on the Retimer chip according to claim 1, characterized in that: The step 6 comprises: Step 61, the software interface starts to read the information in the storage module according to the output interrupt signal; after reading, the link training state machine information is decoded to obtain the corresponding link training state machine jump; Step 62: for the link training state machine state in which the link training state machine is in electrical idle state, the time in which the link training state machine is in electrical idle state is calculated according to the timestamp information; for the detection state, the number of detections performed by the link training state machine is decoded and recorded according to the information of the number of detections; Step 63: When the Retimer state machine is in forwarding mode, the link training state machine provides the key information domain of the forwarding mode; when the Retimer state machine is in execution mode for balancing, the coefficients of the Retimer state machine evaluating the opposite end and the coefficients of the opposite end evaluating itself are provided; when the Retimer state machine is in a related test mode, the key test information parameters are provided; Step 64: After the interpretation is completed, it is displayed on the graphical interface according to the timestamp for the convenience of users.

8. A state machine inference system based on a Retimer chip, implementing a state machine inference method based on a Retimer chip as claimed in any one of claims 1 to 7, characterized in that: It includes a Retimer state machine, a first processing module, a second processing module, a third processing module, and a storage module; the Retimer state machine is connected to the third processing module through the first processing module and the second processing module respectively, and the third processing module is connected to the storage module; the first processing module and the second processing module are both connected to the storage module; the storage module is connected to an external display terminal, and the external display terminal has a graphical interface.

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