Method for controlling chip layout, electronic device and computer-readable storage medium

Abstract

The present application discloses a method for managing and controlling chip layout, an electronic device, and a computer-readable storage medium. The method includes: obtaining a mask layer layout of a chip in a mask manufacturing process, wherein the mask layer layout is obtained by logical operation of an initial layout of the chip; detecting process weakness problems on the mask layer layout; and preparing the mask based on the mask layer layout that has passed the detection. Through the scheme of the present application, based on the detection of process weakness problems of the mask layer layout, the process weaknesses in the layout can be detected to the greatest extent, thereby ensuring the effectiveness of the prepared mask, and then improving the yield of the chips subsequently prepared using the mask.

Description

Technical Field

[0001] The present application generally relates to the field of semiconductor manufacturing processes. More specifically, the present application relates to a method for managing chip layout, an electronic device, and a computer-readable storage medium. Background Art

[0002] Tape-out (TO) originally means the "offline" of wafers, and usually refers to the stage between the final step of integrated circuit (IC) design and the delivery to manufacturing. Simply put, the designer delivers the final GDSII format file (Data Base, DB) to the manufacturing plant to produce wafers. Before the wafer is off the line, the customer's DB needs to go through a series of processes to verify and process, and then deliver it to the manufacturing plant to make a mask, and then use the layout defined by the mask for wafer processing. Therefore, TO is a necessary process in the final stage of the integrated circuit design process.

[0003] However, in the actual mask preparation process, the layout provided by the customer and the converted intermediate layout may not meet the process conditions and have weaknesses, resulting in low yield of the subsequently manufactured chips.

[0004] In view of this, there is an urgent need to provide a solution for managing chip layout so as to effectively detect weak issues in the layout and improve chip yield. Summary of the invention

[0005] In order to at least solve one or more of the technical problems mentioned above, the present application proposes a solution for managing chip layout in multiple aspects.

[0006] In a first aspect, the present application provides a method for managing and controlling chip layout, comprising: obtaining a mask layer layout of a chip in a mask manufacturing process, wherein the mask layer layout is obtained by logical operation of an initial layout of the chip; detecting process weakness issues on the mask layer layout; and preparing the mask based on the detected mask layer layout.

[0007] In some embodiments, detecting process weakness issues on the mask layer layout includes: detecting process weakness issues on the mask layer layout using preset layout detection rules, wherein the layout detection rules are constructed based on design rules combined with process adjustment parameters.

[0008] In some embodiments, using preset layout detection rules to detect process weakness problems on the mask layer layout includes cyclically executing the following steps: determining whether the mask layer layout violates the layout detection rules, and when determining that the mask layer layout violates the layout detection rules, detecting the risk level of the mask layer layout violating the layout detection rules; and in response to the risk level of the mask layer layout violating the layout detection rules being high risk, improving the mask layer layout, and continuing to detect whether the improved mask layer layout violates the layout detection rules until it passes the detection of the layout detection rules.

[0009] In some embodiments, determining whether the layout detection rule has been passed includes: in response to the mask layer layout not violating the layout detection rule, determining that the layout detection rule has been passed; or in response to the risk level of the mask layer layout violating the layout detection rule being low risk, determining that the layout detection rule has been passed.

[0010] In some embodiments, detecting the risk level of the mask layer layout violating the layout detection rules includes: in response to obtaining a target highlighted layout with process weaknesses from the mask layer layout, wherein the target highlighted layout is obtained by highlighting the mask layer layout with process weaknesses, classifying the target highlighted layout; detecting the risk level of the process weaknesses in the target highlighted layout in combination with the category of the target highlighted layout; and storing the detection results of the target highlighted layout, the category of the target highlighted layout, and the risk level of the target highlighted layout in a database.

[0011] In some embodiments, wherein the database pre-stores different categories of highlighted layouts and corresponding risk level detection results, in combination with the category of the target highlighted layout, detecting the risk level of process weaknesses in the target highlighted layout includes: detecting whether there is a highlighted layout of the same category as the target highlighted layout in the database; in response to the existence of a highlighted layout of the same category as the target highlighted layout, determining the risk level detection result corresponding to the found highlighted layout as the risk level detection result of the target highlighted layout; or in response to the absence of a highlighted layout of the same category as the target highlighted layout, acquiring the process technology and defect standards related to the target highlighted layout, and determining the risk level of the target highlighted layout based on the acquired process technology and defect standards.

[0012] In some embodiments, the method also includes: monitoring feedback information of process weaknesses detected by the layout detection rules in actual process technology; evaluating the risk level of the detected process weaknesses based on the feedback information to obtain an evaluation result; and selectively adjusting the layout detection rules according to the evaluation result.

[0013] In a second aspect, the present application provides an electronic device, comprising: a processor; and a memory, which stores computer instructions for controlling a chip layout, wherein when the computer instructions are executed by the processor, the electronic device executes the method described in the foregoing and following embodiments.

[0014] In a third aspect, the present application proposes a computer-readable storage medium, comprising program instructions for managing a chip layout, and when the program instructions are executed by a processor, the method described in the foregoing and following embodiments is implemented.

[0015] The unexpected beneficial technical effect of the present application is: through the method, electronic device and computer-readable storage medium for controlling chip layout provided above, the embodiment of the present application obtains the mask layer layout output by logical operation in the process of mask preparation, and detects process weakness problems for these mask layer layouts, so that the mask can be prepared using the mask layer layout that has passed the detection. Since the process weaknesses existing in the initial layout and the intermediate layout obtained by logical operation can basically be presented on the mask layer layout, by detecting the process weakness problems of the mask layer layout, the process weaknesses in the layout can be detected to the greatest extent, thereby ensuring the effectiveness of the prepared mask, and then improving the yield of the chip prepared using the mask in the future.

[0016] Furthermore, in some embodiments, the layout detection rules can be updated cyclically to detect process weakness problems by utilizing the layout detection rules, thereby making the process platform healthier and ensuring a significant improvement in the chip yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] By reading the detailed description below with reference to the accompanying drawings, the above and other purposes, features and advantages of the exemplary embodiments of the present application will become easy to understand. In the accompanying drawings, several embodiments of the present application are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0018] Figure 1 A schematic diagram showing a flow chart of a method for managing and controlling chip layout according to an embodiment of the present application;

[0019] Figure 2 A schematic flow chart showing a method for managing and controlling chip layout according to another embodiment of the present application is shown;

[0020] Figure 3 A schematic flow chart of a method for managing and controlling chip layout according to another embodiment of the present application is shown;

[0021] Figure 4A schematic diagram showing a flow chart of a method for updating layout detection rules according to an embodiment of the present application; and

[0022] Figure 5 A schematic structural block diagram of an electronic device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0024] It should be understood that the terms "include" and "comprising" used in the specification and claims of the present application indicate the presence of described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or collections thereof.

[0025] It should also be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in this application specification and claims, unless the context clearly indicates otherwise, the singular forms of "a", "an" and "the" are intended to include plural forms. It should also be further understood that the term "and / or" used in this application specification and claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0026] The specific implementation of the present application is described in detail below with reference to the accompanying drawings.

[0027] Figure 1 A schematic flow chart of a method 100 for managing and controlling chip layout according to an embodiment of the present application is shown.

[0028] like Figure 1As shown, at step S101, the mask layer layout of the chip in the mask process can be obtained. Among them, the mask layer layout is obtained by logical operation of the initial layout of the chip. In this embodiment, the initial layout of the chip can be understood as the layout of all layers of the chip designed by the layout designer, for example, it can include a layout DB in GDSII format. In some embodiments, after obtaining the initial layout of the chip, the mask layer layout of the chip can be output after performing a logical operation (AutoGeneration, referred to as AG) on the initial layout. In practical applications, the logical operations performed on the initial layout may include some operations such as or operations, and operations, and not operations. Some intermediate layouts obtained by processing the initial layout through these operations have a high probability of having process weakness problems. For example, the initial layout will be drawn according to the design rules during the drawing process, but the above-mentioned intermediate layout after the logical operation contains content obtained by operation rather than manual drawing, and this part of the content may have some process weakness problems. In addition, it should be noted that although the initial layout will contain the layouts of all layers of the chip, not all layers of the layout will necessarily be used during the logic operation process. The layout of the required layer can be automatically selected for operation based on actual needs.

[0029] At step S102, the mask layer layout can be tested for process weaknesses. The process weaknesses that may exist in the initial layout and the above-mentioned intermediate layout can be fully presented through the mask layer layout, so by testing the mask layer layout for process weaknesses, it can be ensured that the process weaknesses in the layout are effectively detected.

[0030] In some embodiments, the detection of process weakness problems of the mask layer layout can be performed by automatic detection. For example, a pre-set layout detection rule can be obtained and the process weakness problem can be detected using the layout detection rule.

[0031] At step S103, the photomask can be prepared based on the mask layer layout that has passed the test. In this embodiment, it can be detected through the process weakness problem that the mask layer layout does not contain process weaknesses or contains process weaknesses with a lower risk level. That is, the contents in the mask layer layout that has passed the test can meet the process conditions, and preparing the photomask based on the mask layer layout that has passed the test is conducive to improving the yield of the chip.

[0032] The unexpected beneficial technical effect of the present application is: unlike the traditional technology of only performing design rule detection on the chip layout, the solution of the present application takes into account that the process weaknesses existing in the initial layout and the intermediate layout obtained by logical operation can basically be presented on the mask layer layout. Therefore, by obtaining the mask layer layout output by logical operation in the mask preparation process, and detecting process weakness problems on these mask layer layouts, the process weaknesses in the layout can be detected to the greatest extent, thereby ensuring the effectiveness of the prepared mask, and then improving the yield rate of chips prepared subsequently using the mask.

[0033] Figure 2 FIG. 2 is a flow chart of a method 200 for managing and controlling chip layout according to another embodiment of the present application. It should be noted that: Figure 2 It can be understood as Figure 1 The specific limitation and further extension of method 100, therefore Figure 1 The relevant instructions in also apply to the following.

[0034] like Figure 2 As shown, at step S201, the initial layout of the chip can be obtained, wherein the initial layout of the chip can be understood as the layout of all layers of the chip designed by the layout designer.

[0035] At step S202, the aforementioned initial layout may be subjected to a design rule check. Design Rule Check (DRC) is a part of physical verification of integrated circuit design. Usually, wafer foundries formulate geometric dimension constraints between the same process layer and different process layers that meet the chip manufacturing yield for their respective different process parameters. The set of these dimension plans is the layout design rules. In this embodiment, these design rules can be used to perform a preliminary check on the initial layout to detect layouts that violate DRC, thereby facilitating timely adjustments and interventions.

[0036] Further, in some embodiments, when there is an initial layout that violates DRC, the risk level of the initial layout that violates DRC can continue to be judged. For example, the initial layout that violates DRC can be visually displayed to combine manual work to determine whether the risk level of the initial layout that violates DRC is high or low. Of course, some initial layouts that violate DRC and their corresponding high and low risk levels can also be stored in the database in advance, and the automatic detection of the risk level of the initial layout that violates DRC can be achieved by searching the database. In practical applications, when it is determined that the risk level of the initial layout that violates DRC is low risk, it means that although DRC is violated, the risk level is small and it can meet the subsequent process conditions. At this time, the subsequent process can be performed on the initial layout that does not violate DRC and the initial layout with a low risk level. When it is determined that the risk level of the initial layout that violates DRC is high risk, it is necessary to promptly feedback to the relevant personnel so that the initial layout can be adjusted so that it can pass the design rule detection.

[0037] At step S203, a logical operation may be performed on the initial layout that passes the design rule detection to obtain a mask layer layout. In some embodiments, a logical operation may be performed on the initial layout that does not violate the DRC or the initial layout with low risk, and then the mask layer layout may be output. It should be noted that in the traditional chip tape-out process, the mask layer layout is automatically output by using the logical operation of the layout. This embodiment does not involve further improvements to the process, and will not be described in detail here.

[0038] After the mask layer layout is obtained, at step S204, the mask layer layout can be inspected for process weakness using a preset layout inspection rule, wherein the layout inspection rule can be constructed based on design rules combined with process adjustment parameters.

[0039] In some embodiments, the aforementioned design rules can be understood as the design rules involved in DRC, and the layout detection rules (Post Layer Rule Check, referred to as PLRC) can be evolved through the design rules. For example, some process adjustment parameters such as lithography deviation, etching deviation or shrinkage value can be integrated with the design rules involved in DRC to obtain new detection rules (i.e., PLRC). It should be noted that the description of the acquisition process of PLRC here is only an exemplary description, for example, the process adjustment parameters are not limited to the parameters listed above.

[0040] Furthermore, the aforementioned layout detection rules PLRC can be updated as needed. For example, feedback information of the process weaknesses detected by the layout detection rules in the actual process technology (such as critical dimension information after lithography, critical dimension information after etching, defective process window, multi-stroke through-focus exposure matrix window, etc.) can be monitored. Then, the risk level of the detected process weaknesses can be evaluated based on the feedback information to obtain an evaluation result. Then, the layout detection rules are selectively adjusted according to the evaluation results. For example, when the risk level of the process weakness detected based on the feedback information is low risk, the safety of PLRC can be re-evaluated and PLRC can be appropriately adjusted within the safety range. In particular, when the process window of the process weakness is sufficient, adaptive adjustment of PLRC can be considered to avoid the appearance of redundant layouts containing process weaknesses within the safety range, and the adjustment is repeated in a cycle to make the entire process window more reasonable. When the risk level of the process weakness detected based on the feedback information is high risk, the weak process can be removed. For example, the process weakness can be removed by modifying the design layout, logical operations, or improving the process.

[0041] In a specific application, the following process can be executed cyclically to realize the detection of process weakness problems of the mask layer layout: First, it can be detected whether the mask layer layout violates the aforementioned layout detection rules. In response to the existence of a mask layer layout violating the layout detection rules, the risk level of the mask layer layout violating the layout detection rules can be continued to be detected. In response to the high risk level of the mask layer layout violating the layout detection rules, the mask layer layout can be improved, and the improved mask layer layout can be continued to be detected whether it violates the layout detection rules until it passes the detection of the layout detection rules. Among them, the improvement of the mask layer layout can specifically include the modification of logical operations, the modification of the initial layout, etc. to achieve the improvement of the mask layer layout. In this detection process, considering the existence of a low-risk mask layer layout, its risk level is small and it can also meet the requirements of subsequent process conditions. Therefore, combining the judgment of risk level can avoid false detection of some "process weaknesses" that may actually meet the process conditions, thereby being able to more accurately detect process weaknesses that do not actually meet the process conditions.

[0042] The above detection process can be understood as a cyclic process, and the cycle is not terminated until the mask layer layout passes the detection of the layout detection rules. In some embodiments, in response to the aforementioned mask layer layout not violating the layout detection rules, it can be determined that the detection of the layout detection rules has been passed. In other embodiments, in response to the risk level of the mask layer layout violating the layout detection rules being low risk, it is determined that the detection of the layout detection rules has been passed. It should be noted that the mask layer layout here can be the mask layer layout that is initially tested for the layout detection rules, and can also include an improved mask layer layout.

[0043] Of course, in the actual detection process, it is also possible to only detect whether the mask layer layout violates the aforementioned layout detection rules without judging the risk level. When it is determined that the aforementioned layout detection rules are not violated, the subsequent steps can be executed. When it is determined that the aforementioned layout detection rules are violated, relevant prompts are output to improve the mask layer layout until it passes the layout detection rules. In this way, process weaknesses that do not meet the process condition requirements can also be effectively detected.

[0044] Furthermore, the aforementioned detection of the risk level of the mask layer layout violating the layout detection rules can be implemented in a variety of ways. In some embodiments, it can be set that when the mask layer layout violates the layout detection rules, it needs to be marked out.

[0045] For example, the mask layer layout that violates the layout detection rules can be marked by highlighting. In this scenario, in response to obtaining a target highlighted layout with process weaknesses from the mask layer layout, the target highlighted layout can be classified. Then, the risk level of the process weaknesses in the target highlighted layout can be detected in combination with the category of the target highlighted layout. Specifically, different categories of highlighted layouts and corresponding risk level detection results can be pre-stored in the database, and it is detected whether there is a highlighted layout with the same category as the target highlighted layout in the database. In response to the presence of a highlighted layout with the same category as the target highlighted layout, the detection result of the risk level corresponding to the found highlighted layout is determined as the detection result of the risk level of the target highlighted layout. In response to the absence of a highlighted layout with the same category as the target highlighted layout, the process technology and defect standards related to the target highlighted layout can be obtained, and the risk level of the target highlighted layout can be determined based on the obtained process technology and defect standards. Thus, an accurate assessment of the risk level of the target highlighted layout is achieved.

[0046] Finally, the aforementioned target highlight map, target highlight map category, and target highlight map risk level detection results can be stored in the database. Of course, if the target highlight map and the related risk level detection results are already stored in the database, there is no need to store them repeatedly. Thus, by continuously updating the data in the database, the efficiency of risk level judgment can be improved by utilizing the rich data in the database.

[0047] After completing the detection of the process weakness problem of the mask layer layout, at step S205, a mask can be prepared based on the mask layer layout that has passed the detection. In some embodiments, optical proximity correction (OPC) can be performed on some key mask layers in the mask layer layout that has passed the detection, the cutting road and the mask layer layout can be merged to generate a mask tooling table, a JDV (Job Deck View) diagram can be generated, and it can be determined whether the JDV diagram meets the process requirements, etc., so as to finally generate a mask.

[0048] The unexpected beneficial technical effect of the present application is: in the process of preparing the mask, after the logic operation, additional layout detection can be added to the mask layer layout to detect the process weakness problems in the mask layer layout, so that the mask layer layout can be effectively improved in time, thereby ensuring that the prepared mask meets the requirements of the subsequent process, so as to improve the yield of the chip prepared using the mask. In addition, in this process, layout detection rules are also set, and the layout detection rules can be cyclically updated. The long-term detection of process weakness problems through the layout detection rules can make the process platform healthier and ensure that the yield of the chip is greatly improved.

[0049] Figure 3 FIG. 3 is a flow chart of a method 300 for controlling chip layout according to another embodiment of the present application. It should be noted that: Figure 3 It can be understood that Figure 1 Method 100 or Figure 2 A specific implementation process of method 200, therefore Figure 1 and Figure 2 The relevant instructions in also apply to the following.

[0050] like Figure 3 As shown, at step S301, the layout designed by the customer can be obtained. In some embodiments, after the customer designs the layout (that is, the initial layout mentioned above), the layout can be handed over to a wafer foundry (FAB for short). In this embodiment, the layout here includes the final file in, for example, GDSII format, which can cover the layout of all layers of the chip.

[0051] At step S302, it can be detected whether the above layout violates the DRC. If it is determined that the above layout violates the DRC, step S304 can be executed. If it is determined that the above layout does not violate the DRC, step S303 can be executed.

[0052] At step S303, the layout that has passed the DRC inspection will output the mask layer layout after undergoing a logical operation (ie, AG). When the layout undergoes a logical operation, it will contain some non-manually drawn or designed content. Once this part of the content has a process weakness, it cannot be detected using traditional DRC technology.

[0053] At step S304, the risk level of the layout violating the DRC is determined. If the risk level is determined to be high, the customer needs to be prompted to adjust the design layout in a timely manner. If the risk level is determined to be low, it means that the low-risk layout is likely to meet the process requirements and can be determined to have passed the DRC test, and step S303 is continued.

[0054] At step S305, the mask layer layout may be subjected to PLRC detection to determine whether it violates PLRC. If it is determined that the mask layer layout violates PLRC, step S306 may be performed. If it is determined that the mask layer layout does not violate PLRC, step S307 may be performed.

[0055] At step S306, the risk level of the mask layer layout that violates the PLRC can be further determined. If the risk level is high, the mask layer layout needs to be improved. For example, the logical operation can be modified, or the layout designed by the customer can be modified to improve the mask layer layout. If the risk level is low, it means that the risk of the mask layer layout is small, and it is likely to meet the subsequent process conditions, and it can continue to be used, and step S307 is executed. Among them, the specific judgment process of the risk level of the mask layer layout that violates the PLRC can be referred to in the previous text combined with Figure 2 The relevant description will not be repeated here.

[0056] In some embodiments, the aforementioned PLRC may be updated as needed. For example, Figure 4 A specific method 400 for updating layout check rules (PLRC) is shown. Specifically, Figure 4 As shown, at step S401, the design rules involved in the DRC can be obtained. At step S402, the design rules involved in the DRC can be evolved to obtain layout detection rules (PLRC). For example, parameters such as light / etching deviation or shrinkage value are integrated into the design rules involved in the DRC to obtain PLRC rules. At step S403, process weaknesses detected based on PLRC can be obtained. At step S404, the obtained process weaknesses can be fed back to the actual process to collect ADI (After Dry Inspection, generally refers to the critical dimension size after photolithography) / AEI (After Etch Inspection, generally refers to the critical dimension after etching) / Defect FEM (Focus Exposure Matrix, multi-pen focus exposure matrix) windows, etc. At step S405, the above-collected information can be used to evaluate the risk level of the process weakness. If the risk level is low, step S406 is executed to re-evaluate the safety of PLRC and adaptively adjust PLRC. If the risk level is high, step S407 is executed to remove the process weakness by modifying the GDS layout, logical operation or improving the process, etc. GDS is usually a binary file format used for semiconductor chip design, and the GDS layout mainly describes the chip layout and is used for mask production.

[0057] After passing the above PLRC test, return Figure 3In step S307, optical proximity correction (OPC) may be performed on some key mask layer layouts. Generally speaking, when the line width on the wafer is less than a certain value (e.g., less than the exposure wavelength), optical proximity correction is required for the pattern on the mask. Optical proximity correction can correct errors by moving the edge of the pattern on the mask or adding additional polygons. In some embodiments, the mask layer layout that has undergone optical proximity correction can continue to be tested for some corresponding rules, and of course, the rule detection of this part can be omitted.

[0058] In step S308, a layout diagram of the cutting paths is obtained, and in step S309, the mask layer layout and the cutting paths are merged to generate a mask tooling table.

[0059] At step S310, a JDV map is generated, and it is determined whether the JDV map meets the process conditions. If it meets the process conditions, step S311 is executed. If it does not meet the process conditions, the optical correction model used in the optical proximity correction process can be adjusted, or the logical operation can be modified, or the layout designed by the customer can be adjusted until the JDV map obtained meets the process conditions.

[0060] In step S311 , a mask may be finally obtained, thereby completing the preparation of the mask.

[0061] Figure 5 Schematically shows a schematic block diagram of an electronic device 500 according to an embodiment of the present disclosure. Figure 5 As shown, the electronic device 500 may include a processor 501 and a memory 502. The memory 502 stores computer instructions for controlling chip layout. When the computer instructions are executed by the processor 501, the electronic device 500 performs: obtaining the mask layer layout of the chip in the mask manufacturing process, wherein the mask layer layout is obtained by logical operation of the initial layout of the chip; detecting process weakness problems on the mask layer layout; and preparing the mask based on the mask layer layout that passes the detection.

[0062] Optionally, detecting process weakness issues on the mask layer layout includes: detecting process weakness issues on the mask layer layout using preset layout detection rules, wherein the layout detection rules are constructed based on design rules combined with process adjustment parameters.

[0063] Optionally, using preset layout detection rules to detect process weakness problems in the mask layer layout includes cyclically executing the following steps: judging whether the mask layer layout violates the layout detection rules, and when determining that the mask layer layout violates the layout detection rules, detecting the risk level of the mask layer layout violating the layout detection rules; and in response to the risk level of the mask layer layout violating the layout detection rules being high risk, improving the mask layer layout, and continuing to detect whether the improved mask layer layout violates the layout detection rules until it passes the detection of the layout detection rules.

[0064] Optionally, determining whether the layout detection rule has been passed includes: in response to the mask layer layout not violating the layout detection rule, determining that the layout detection rule has been passed; or in response to the risk level of the mask layer layout violating the layout detection rule being low risk, determining that the layout detection rule has been passed.

[0065] Optionally, detecting the risk level of the mask layer layout violating the layout detection rules includes: in response to obtaining a target highlighted layout with process weaknesses from the mask layer layout, classifying the target highlighted layout, wherein the target highlighted layout is obtained by highlighting the mask layer layout with process weaknesses; detecting the risk level of the process weaknesses in the target highlighted layout in combination with the category of the target highlighted layout; and storing the detection results of the target highlighted layout, the category of the target highlighted layout and the risk level of the target highlighted layout in a database.

[0066] Optionally, the database pre-stores different categories of highlighted layouts and corresponding risk level detection results. In combination with the category of the target highlighted layout, detecting the risk level of process weaknesses in the target highlighted layout includes: detecting whether there is a highlighted layout of the same category as the target highlighted layout in the database; in response to the existence of a highlighted layout of the same category as the target highlighted layout, determining the risk level detection result corresponding to the found highlighted layout as the risk level detection result of the target highlighted layout; or in response to the absence of a highlighted layout of the same category as the target highlighted layout, acquiring the process technology and defect standards related to the target highlighted layout, and determining the risk level of the target highlighted layout based on the acquired process technology and defect standards.

[0067] Optionally, the method also includes: monitoring feedback information of process weaknesses detected by the layout detection rules in actual process technology; evaluating the risk level of the detected process weaknesses based on the feedback information to obtain an evaluation result; and selectively adjusting the layout detection rules according to the evaluation result.

[0068] Optionally, obtaining the mask layer layout of the chip in the mask process includes: obtaining an initial layout of the chip; performing a design rule check on the initial layout; and performing a logical operation on the initial layout that passes the design rule check to obtain the mask layer layout.

[0069] The unexpected beneficial technical effect of the present application is that the electronic device obtains the mask layer layout output by logical operation in the process of preparing the mask, and detects the process weakness problems for these mask layer layouts, so that the mask can be prepared using the mask layer layout that has passed the detection. Since the process weaknesses existing in the initial layout and the intermediate layout obtained by logical operation can basically be presented on the mask layer layout, by detecting the process weakness problems of the mask layer layout, the process weaknesses in the layout can be detected to the greatest extent, thereby ensuring the effectiveness of the prepared mask, and then improving the yield of the chip prepared using the mask in the future.

[0070] It should be noted that the specific contents of the method steps of the electronic device are combined with the above Figure 1~Figure 3 The specific implementation methods of the described methods for managing chip layout are the same or similar, so they will not be repeated here.

[0071] In addition, the present disclosure also provides a computer-readable storage medium in which program instructions are stored, and the program instructions are configured to be executed at runtime. Figure 1~Figure 3 The method of controlling chip layout is shown.

[0072] Specifically, in this embodiment, the above-mentioned storage medium may include but is not limited to: a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other media that can store computer programs.

[0073] It should be noted that although the operations of the method of the present application are described in a specific order in the accompanying drawings, this does not require or imply that the operations must be performed in this specific order, or that all the operations shown must be performed to achieve the desired results. On the contrary, the steps depicted in the flow chart can be performed in a different order. Additionally or alternatively, some steps can be omitted, multiple steps can be combined into one step, and / or one step can be decomposed into multiple steps.

[0074] Although multiple embodiments of the present application have been shown and described herein, it is obvious to those skilled in the art that such embodiments are provided only by way of example. Those skilled in the art can think of many changes, modifications and alternatives without departing from the thought and spirit of the present application. It should be understood that in the process of practicing the present application, various alternatives to the embodiments of the present application described herein can be adopted. The attached claims are intended to limit the scope of protection of the present application, and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A method for managing chip layout, characterized in that: include: Acquiring a mask layer layout of a chip in a mask manufacturing process, wherein the mask layer layout is obtained by a logic operation on an initial layout of the chip, specifically, acquiring the initial layout of the chip, performing a design rule detection on the initial layout, and performing a logic operation on the initial layout that passes the design rule detection to obtain the mask layer layout; The mask layer layout is tested for process weakness problems, and a preset layout detection rule is used to test the mask layer layout for process weakness problems, wherein the layout detection rule is constructed based on the design rule combined with the process adjustment parameter, and further, feedback information of the process weakness detected by the layout detection rule in the actual process technology is monitored, and the risk level of the detected process weakness is evaluated based on the feedback information to obtain an evaluation result, and the layout detection rule is selectively adjusted according to the evaluation result. The detection of process weakness problems of the mask layer layout using a preset layout detection rule includes cyclically executing the following steps: determining whether the mask layer layout violates the layout detection rule, and when determining that the mask layer layout violates the layout detection rule, detecting the risk level of the mask layer layout violating the layout detection rule; In response to the risk level of the mask layer layout violating the layout detection rule being high risk, improving the mask layer layout, and continuing to detect whether the improved mask layer layout violates the layout detection rule until it passes the detection of the layout detection rule; as well as The photomask is prepared based on the detected mask layer pattern.

2. The method according to claim 1, characterized in that Determining whether the layout detection rule is passed includes: In response to the mask layer layout not violating the layout detection rule, determining that the layout detection rule has been passed; or In response to the risk level of the mask layer layout violating the layout detection rule being low risk, it is determined that the layout has passed the detection of the layout detection rule.

3. The method according to claim 1, characterized in that Detecting the risk level of the mask layer layout violating the layout detection rule includes: In response to obtaining a target highlighted layout with a process weakness from the mask layer layout, classifying the target highlighted layout, wherein the target highlighted layout is obtained by highlighting the mask layer layout with the process weakness; In combination with the category of the target highlighted layout, detecting the risk level of process weaknesses in the target highlighted layout; and The detection results of the target highlighted layout, the category of the target highlighted layout and the risk level of the target highlighted layout are stored in a database.

4. The method according to claim 3, characterized in that The database pre-stores different types of highlighted layouts and corresponding risk level detection results. In combination with the type of the target highlighted layout, detecting the risk level of the process weakness in the target highlighted layout includes: Detecting whether there is a highlighted layout of the same category as the target highlighted layout in the database; In response to the presence of a highlighted layout of the same category as the target highlighted layout, determining the risk level detection result corresponding to the found highlighted layout as the risk level detection result of the target highlighted layout; or In response to the absence of a highlighted layout of the same category as the target highlighted layout, a process technology and a defect standard related to the target highlighted layout are obtained, and the risk level of the target highlighted layout is determined based on the obtained process technology and defect standard.

5. An electronic device, characterized in that: include: processor; as well as A memory storing computer instructions for controlling chip layout, wherein when the computer instructions are executed by the processor, the electronic device executes the method according to any one of claims 1 to 4.

6. A computer-readable storage medium, characterized in that: The invention comprises program instructions for controlling the chip layout, and when the program instructions are executed by a processor, the method according to any one of claims 1 to 4 is implemented.

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