Fabrication method of semiconductor processing tray and semiconductor device

Abstract

A manufacturing method of a semiconductor processing tray and a semiconductor device. The semiconductor processing tray includes a tray bottom plate and a tray side wall; the tray side wall surrounds the tray bottom plate and is connected to the edge of the tray bottom plate; the tray bottom plate includes a bearing part and an anti-adhesion part, the bearing part is configured to bear the semiconductor device, the anti-adhesion part surrounds the bearing part and is located between the bearing part and the tray side wall, and the average height of the anti-adhesion part is less than the average height of the bearing part. Thus, the anti-adhesion part can prevent the edge part of the semiconductor device from adhering to the tray bottom plate during the high-temperature reflow process and the cooling process after the high-temperature reflow process ends, thereby preventing defects such as fragmentation and corner chipping of the semiconductor device or the tray bottom plate.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor processing, and more particularly, to a semiconductor processing tray and a method for manufacturing a semiconductor device. Background Art

[0002] Boro-phospho-silicate-glass (BPSG) is a boron-doped SiO2 glass. BPSG has good fluidity at high temperatures and is therefore widely used as an interlayer insulating film with high flatness in semiconductor devices.

[0003] In the method for manufacturing a semiconductor device, after growing BPSG, a high-temperature reflow process is usually required to improve the flatness and hole filling ability of the BPSG film layer, thereby improving the performance of the semiconductor device and also contributing to improving the product yield. Summary of the Invention

[0004] The present disclosure provides a semiconductor processing tray, which includes: a tray bottom plate; and a tray side wall surrounding the tray bottom plate and connected to the edge of the tray bottom plate. The tray bottom plate includes a bearing portion and an anti-adhesion portion. The bearing portion is configured to bear a semiconductor device. The anti-adhesion portion surrounds the bearing portion and is located between the bearing portion and the tray side wall. The average height of the anti-adhesion portion is less than the average height of the bearing portion.

[0005] For example, in the semiconductor processing tray provided by the present disclosure, the value range of the difference between the minimum height of the anti-adhesion portion and the maximum height of the bearing portion is 0.3 mm - 0.5 mm.

[0006] For example, in the semiconductor processing tray provided by the present disclosure, the tray side wall includes at least one access notch.

[0007] For example, in the semiconductor processing tray provided by the present disclosure, the tray side wall includes a plurality of the access notches, which are arranged circumferentially along the edge of the tray bottom plate.

[0008] For example, in the semiconductor processing tray provided by the present disclosure, the anti-adhesion portion includes a groove structure to make the average height of the anti-adhesion portion less than the average height of the bearing portion.

[0009] For example, in the semiconductor processing tray provided by the present disclosure, the groove structure is a first annular groove surrounding the bearing portion.

[0010] For example, in the semiconductor processing tray provided by the present disclosure, the groove structure includes a plurality of first grooves arranged circumferentially along the edge of the bearing portion, and the plurality of first grooves are arranged at intervals.

[0011] For example, in the semiconductor processing tray provided by the present disclosure, the groove structure includes a plurality of second grooves sequentially arranged along the direction from the bearing portion to the side wall of the tray, and the anti-sticking portion includes a serrated portion located between the plurality of second grooves.

[0012] For example, in the semiconductor processing tray provided by the present disclosure, each of the second grooves is a second annular groove surrounding the bearing portion.

[0013] For example, in the semiconductor processing tray provided by the present disclosure, the bearing portion includes a plurality of protruding structures, so that the average height of the anti-sticking portion is less than the average height of the bearing portion.

[0014] For example, in the semiconductor processing tray provided by the present disclosure, the value range of the difference between the maximum height of the side wall of the tray and the maximum height of the bearing portion is 0.5 mm - 0.7 mm.

[0015] The present disclosure also provides a method for manufacturing a semiconductor device, which includes: growing borophosphosilicate glass on a quartz substrate to form a semiconductor device; placing the semiconductor device on a semiconductor processing tray; performing a high-temperature reflow process on the semiconductor processing tray and the semiconductor device; and separating the semiconductor device after the high-temperature reflow process from the semiconductor processing tray, where the semiconductor processing tray is the semiconductor processing tray provided in any of the above examples, and the value range of the temperature of the high-temperature reflow process is 1100°C - 1300°C.

[0016] In the semiconductor processing tray provided by the present disclosure, since the average height of the anti-sticking portion is less than the average height of the bearing portion, when carrying a semiconductor device, there is a non-contact part between the anti-sticking portion and the edge part of the semiconductor device. Therefore, the anti-sticking portion can prevent the edge part of the semiconductor device from adhering to the tray bottom plate during the high-temperature reflow process and the cooling process after the high-temperature reflow process ends, thereby preventing defects such as fragmentation and corner chipping of the semiconductor device or the tray bottom plate. On the other hand, since the side wall of the tray can also limit the displacement of the semiconductor device, it can prevent the semiconductor device from shifting. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0018] Figure 1 It is a plan view of a semiconductor processing tray provided by an embodiment of the present disclosure;

[0019] Figure 2 For Figure 1Schematic cross-sectional view of the semiconductor processing tray shown along line AB;

[0020] Figure 3 Planar schematic view of another semiconductor processing tray provided by an embodiment of the present disclosure;

[0021] Figure 4 is Figure 3 Schematic cross-sectional view of the semiconductor processing tray shown along line AB;

[0022] Figure 5 Planar schematic view of yet another semiconductor processing tray provided by an embodiment of the present disclosure;

[0023] Figure 6 is Figure 5 Schematic cross-sectional view of the semiconductor processing tray shown along line AB;

[0024] Figure 7 Planar schematic view of yet another semiconductor processing tray provided by an embodiment of the present disclosure;

[0025] Figure 8 is Figure 7 Schematic cross-sectional view of the semiconductor processing tray shown along line AB; and

[0026] Figure 9 Flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present disclosure. Detailed implementation manners

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art without creative efforts based on the described embodiments of the present disclosure fall within the scope of protection of the present disclosure.

[0028] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings understood by those of ordinary skill in the art belonging to the field of the present disclosure. The "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms such as "including" or "comprising" mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items.

[0029] In the manufacturing method of semiconductor devices (such as PLC optical module chips), after growing borophosphosilicate glass on a quartz substrate, a high-temperature reflow process at 1100°C - 1300°C is usually required. Since the above temperature is already close to the melting point of the quartz material, deformation, warping, and other defects of the quartz substrate are likely to occur. In response to this, the quartz substrate can be placed on a tray, and then the above high-temperature reflow process can be carried out.

[0030] However, when growing a relatively thick boron-doped phosphosilicate glass (i.e., borophosphosilicate glass) on a quartz substrate by chemical vapor deposition (PECVD), due to the too-thick film layer of the boron-doped phosphosilicate glass and the characteristics of the PECVD equipment, it is extremely easy to grow boron-doped phosphosilicate glass on the back edge of the quartz substrate as well. In this case, when the quartz substrate is placed face-up on the tray and sent into a vertical furnace for the high-temperature reflow process, the boron-doped phosphosilicate glass on the back of the quartz substrate will melt simultaneously and adhere to the processing tray; after the high-temperature reflow is completed and the temperature is lowered and taken out of the furnace, the boron-doped phosphosilicate glass cools and solidifies. Due to the different expansion coefficients of the quartz material and the tray material (silicon), the quartz substrate or the tray will have defects such as fragmentation and corner chipping during the cooling process. Moreover, even if no defects such as fragmentation and corner chipping occur fortunately during the cooling process, the quartz substrate cannot be removed due to the adhesion between the two during subsequent manual wafer picking.

[0031] In response to this, the embodiments of the present disclosure provide a semiconductor processing tray, which includes a tray bottom plate and a tray side wall; the tray side wall surrounds the tray bottom plate and is connected to the edge of the tray bottom plate; the tray bottom plate includes a bearing part and an anti-adhesion part. The bearing part is configured to bear a semiconductor device, the anti-adhesion part surrounds the bearing part and is located between the bearing part and the tray side wall, and the average height of the anti-adhesion part is less than the average height of the bearing part. Thus, since the average height of the anti-adhesion part is less than the average height of the bearing part, when bearing a semiconductor device, there is a non-contact part between the anti-adhesion part and the edge part of the semiconductor device. Therefore, the anti-adhesion part can prevent the edge part of the semiconductor device from adhering to the tray bottom plate during the high-temperature reflow process and the cooling process after the high-temperature reflow process is completed, thereby preventing defects such as fragmentation and corner chipping of the semiconductor device or the tray bottom plate. On the other hand, since the tray side wall can also limit the displacement of the semiconductor device and prevent the semiconductor device from shifting.

[0032] An embodiment of the present disclosure also provides a method for manufacturing a semiconductor device, which includes: growing borophosphosilicate glass on a quartz substrate to form a semiconductor device; placing the semiconductor device on a semiconductor processing tray; performing a high-temperature reflow process on the semiconductor processing tray and the semiconductor device; and separating the semiconductor device after the high-temperature reflow process from the semiconductor processing tray. The semiconductor processing tray is the semiconductor processing tray provided in the above embodiment, and the temperature range of the high-temperature reflow process is 1100°C - 1300°C. Thus, by placing the semiconductor device on the semiconductor processing tray and then performing the high-temperature reflow process, the method for manufacturing the semiconductor device can prevent abnormal conditions such as deformation or warping of the semiconductor device. On the other hand, since the semiconductor processing tray is the semiconductor processing tray provided in any of the above examples, and the average height of the anti-adhesion portion is less than the average height of the bearing portion, when bearing the semiconductor device, there is a non-contact portion between the anti-adhesion portion and the edge portion of the semiconductor device. Therefore, the anti-adhesion portion can prevent the edge portion of the semiconductor device from adhering to the tray bottom plate during the high-temperature reflow process and the cooling process after the high-temperature reflow process, thereby preventing defects such as fragmentation or corner chipping of the semiconductor device or the tray bottom plate. On the other hand, since the tray sidewall can also limit the displacement of the semiconductor device and prevent the semiconductor device from shifting.

[0033] Next, with reference to the accompanying drawings, a detailed description will be given of the semiconductor processing tray and the method for manufacturing a semiconductor device provided in the embodiments of the present disclosure.

[0034] Figure 1 A plan view of a semiconductor processing tray provided in an embodiment of the present disclosure; Figure 2 is Figure 1 a cross-sectional view of the semiconductor processing tray shown along line AB.

[0035] As Figure 1 and Figure 2 shown, the semiconductor processing tray 100 includes a tray bottom plate 110 and a tray sidewall 120; the tray sidewall 120 surrounds the tray bottom plate 110 and is connected to the edge of the tray bottom plate 110; the tray bottom plate 110 includes a bearing portion 112 and an anti-adhesion portion 114. The bearing portion 112 is configured to bear the semiconductor device 200, the anti-adhesion portion 114 surrounds the bearing portion 112, and is located between the bearing portion 112 and the tray sidewall 120; the average height of the anti-adhesion portion 114 is less than the average height of the bearing portion 112.

[0036] In the semiconductor processing tray provided by the embodiments of the present disclosure, the anti-sticking portion is located around the bearing portion. Therefore, when the processing tray bears a semiconductor device, the bearing portion corresponds to the main body portion of the semiconductor device, and the anti-sticking portion corresponds to the edge portion of the semiconductor device. Since the average height of the anti-sticking portion is less than the average height of the bearing portion, when bearing the semiconductor device, there is a non-contact portion between the anti-sticking portion and the edge portion of the semiconductor device. Therefore, the anti-sticking portion can prevent the edge portion of the semiconductor device from adhering to the tray bottom plate during the high-temperature reflow process and the cooling process after the high-temperature reflow process, thereby preventing defects such as fragmentation and corner chipping of the semiconductor device or the tray bottom plate. On the other hand, since the tray sidewall can also limit the displacement of the semiconductor device, it can prevent the semiconductor device from shifting.

[0037] It should be noted that the average height of the anti-sticking portion mentioned above refers to the average value of the heights at different positions of the anti-sticking portion, and the height of the anti-sticking portion refers to the distance between the anti-sticking portion and the back surface of the tray bottom plate. The average height of the bearing portion mentioned above refers to the average value of the heights at different positions of the bearing portion, and the height of the bearing portion refers to the distance between the bearing portion and the back surface of the tray bottom plate. That is to say, the embodiments of the present disclosure can use the back surface of the tray bottom plate as a reference surface to calculate the heights of the anti-sticking portion and the bearing portion.

[0038] For example, the above-mentioned semiconductor device 200 can be a semiconductor device including borophosphosilicate glass.

[0039] In some examples, such as Figure 1 and Figure 2 shown, the value range of the difference between the minimum height of the anti-sticking portion 114 and the maximum height of the bearing portion 112 is 0.3 mm - 0.5 mm. That is to say, the value range of the height difference between the bottom of the anti-sticking portion and the top of the bearing portion is 0.3 mm - 0.5 mm. Thus, a certain accommodation space can be formed between the anti-sticking portion and the edge portion of the semiconductor device, avoiding adhesion between the anti-sticking portion and the edge portion of the semiconductor device.

[0040] In some examples, such as Figure 1 and Figure 2 shown, the value range of the difference between the maximum height of the tray sidewall 120 and the maximum height of the bearing portion 112 is 0.5 mm - 0.7 mm. Thus, the tray sidewall 120 can better limit the displacement of the semiconductor device and prevent the semiconductor device from shifting.

[0041] In some examples, such as Figure 1 and Figure 2 shown, the tray sidewall 120 includes at least one access notch 125. The access notch can facilitate the operator to separate the processing tray from the semiconductor device, thereby improving efficiency.

[0042] In some examples, such asFigure 1 and Figure 2 As shown in Figure 2 , the side wall 120 of the tray includes a plurality of access notches 125, which are circumferentially spaced along the edge of the tray bottom plate 110, so as to facilitate the operator to separate the processing tray from the semiconductor device in different directions.

[0043] For example, as Figure 1 and Figure 2 shown, the side wall 120 of the tray includes four access notches 125; the included angle between the connection lines of the centers of two adjacent access notches 125 and the center of the tray bottom plate 110 is 90 degrees.

[0044] In some examples, as Figure 1 and Figure 2 shown, the above-mentioned anti-adhesion portion 114 includes a groove structure 1140, so that the average height of the anti-adhesion portion 114 is less than the average height of the bearing portion 112. Thus, the anti-adhesion portion makes the average height of the anti-adhesion portion less than the average height of the bearing portion by setting the groove structure. In this case, the groove structure does not contact the edge portion of the semiconductor device, so the anti-adhesion portion can prevent the edge portion of the semiconductor device from adhering to the tray bottom plate during the high-temperature reflow process and the cooling process after the high-temperature reflow process, thereby preventing defects such as fragmentation and corner chipping of the semiconductor device or the tray bottom plate.

[0045] In some examples, as Figure 1 and Figure 2 shown, the above-mentioned groove structure 1140 can be a first annular groove 131 surrounding the bearing portion 112. At this time, the anti-adhesion portion 114 is the first annular groove 131. In this case, the first annular groove makes the anti-adhesion portion not contact the edge portion of the semiconductor device at all, so the anti-adhesion portion can better prevent the edge portion of the semiconductor device from adhering to the tray bottom plate during the high-temperature reflow process and the cooling process after the high-temperature reflow process, thereby preventing defects such as fragmentation and corner chipping of the semiconductor device or the tray bottom plate.

[0046] In some examples, the value range of the dimension of the anti-adhesion portion 114 in the direction from the center of the bearing portion 112 to the side wall 120 of the tray is 15 mm - 30 mm; that is to say, the value range of the width of the anti-adhesion portion 114 is 15 mm - 30 mm. Through this dimension design, the anti-adhesion portion can better prevent the edge portion of the semiconductor device from adhering to the tray bottom plate during the high-temperature reflow process and the cooling process after the high-temperature reflow process.

[0047] For example, the dimension of the anti-adhesion portion 114 in the direction from the center of the bearing portion 112 to the side wall 120 of the tray can be 18 mm, 19 mm, 20 mm, 21 mm or 22 mm.

[0048] For example, the planar shape of the tray bottom plate 110 can be circular, the planar shape of the bearing portion 112 can be circular, and at this time, the planar shape of the anti-adhesion portion 114 can be circular. Of course, the embodiments of the present disclosure include but are not limited to this, and the planar shapes of the tray bottom plate, the bearing portion, and the anti-adhesion portion can also be other shapes.

[0049] For example, the value range of the diameter of the tray bottom plate 110 can be 100 mm - 200 mm, such as 152.5 mm. The value range of the diameter of the bearing portion 112 can be 80 mm - 180 mm, such as 130 mm. The thickness of the above-mentioned tray side wall 120 can be 1 mm - 3 mm, such as 2 mm.

[0050] In some examples, the material of the above-mentioned semiconductor processing tray can include silicon; that is to say, the above-mentioned semiconductor processing tray can be a silicon tray. Of course, the embodiments of the present disclosure include but are not limited to this, and the above-mentioned semiconductor processing tray can be made of other suitable materials.

[0051] Figure 3 A plan view of another semiconductor processing tray provided by an embodiment of the present disclosure; Figure 4 is Figure 3 A cross-sectional view of the shown semiconductor processing tray along line AB.

[0052] As Figure 3 and Figure 4 shown, the semiconductor processing tray 100 includes a tray bottom plate 110 and a tray side wall 120; the tray side wall 120 surrounds the tray bottom plate 110 and is connected to the edge of the tray bottom plate 110; the tray bottom plate 110 includes a bearing portion 112 and an anti-adhesion portion 114, the bearing portion 112 is configured to carry the semiconductor device 200, the anti-adhesion portion 114 surrounds the bearing portion 112 and is located between the bearing portion 112 and the tray side wall 120; the average height of the anti-adhesion portion 114 is less than the average height of the bearing portion 112.

[0053] As Figure 3 and Figure 4 shown, the above-mentioned anti-adhesion portion 114 includes a groove structure 1140, so that the average height of the anti-adhesion portion 114 is less than the average height of the bearing portion 112. The above-mentioned groove structure 1140 includes a plurality of first grooves 141 arranged circumferentially along the edge of the bearing portion 112, and the plurality of first grooves 141 are arranged at intervals.

[0054] In the semiconductor processing tray provided by the embodiments of the present disclosure, the anti-sticking portion is located around the bearing portion. Therefore, when the processing tray bears a semiconductor device, the bearing portion corresponds to the main body portion of the semiconductor device, and the anti-sticking portion corresponds to the edge portion of the semiconductor device. Since the anti-sticking portion includes a plurality of first grooves, the average height of the anti-sticking portion is less than the average height of the bearing portion. When bearing the semiconductor device, the plurality of first grooves do not contact the edge portion of the semiconductor device. Therefore, the anti-sticking portion can prevent the edge portion of the semiconductor device from adhering to the tray bottom plate during the high-temperature reflow process and the cooling process after the high-temperature reflow process ends, thereby preventing defects such as fragmentation and corner chipping of the semiconductor device or the tray bottom plate. On the other hand, since the tray sidewall can also limit the displacement of the semiconductor device, it can prevent the semiconductor device from shifting.

[0055] In some examples, such as Figure 3 and Figure 4 shown, the value range of the difference between the minimum height of the anti-sticking portion 114 and the maximum height of the bearing portion 112 is 0.3 mm - 0.5 mm. That is to say, the value range of the height difference between the bottom of the anti-sticking portion and the top of the bearing portion is 0.3 mm - 0.5 mm. Thus, a certain accommodation space can be formed between the anti-sticking portion and the edge portion of the semiconductor device, avoiding adhesion between the anti-sticking portion and the edge portion of the semiconductor device.

[0056] In some examples, such as Figure 3 and Figure 4 shown, the value range of the difference between the maximum height of the tray sidewall 120 and the maximum height of the bearing portion 112 is 0.5 mm - 0.7 mm. Thus, the tray sidewall 120 can better limit the displacement of the semiconductor device and prevent the semiconductor device from shifting.

[0057] In some examples, such as Figure 3 and Figure 4 shown, the tray sidewall 120 includes at least one access notch 125. The access notch can facilitate the operator to separate the processing tray from the semiconductor device, thereby improving efficiency.

[0058] In some examples, such as Figure 3 and Figure 4 shown, the tray sidewall 120 includes a plurality of access notches 125, which are arranged at intervals along the circumference of the edge of the tray bottom plate 110, so as to facilitate the operator to separate the processing tray from the semiconductor device in different directions.

[0059] For example, as Figure 3 and Figure 4 shown, the tray sidewall 120 includes four access notches 125; the included angle between the connecting lines of the centers of two adjacent access notches 125 and the center of the tray bottom plate 110 is 90 degrees.

[0060] Figure 5 Another plan view of a semiconductor processing tray provided by an embodiment of the present disclosure; Figure 6 is Figure 5 A cross-sectional view of the semiconductor processing tray shown along line AB.

[0061] As Figure 5 and Figure 6 shown, the semiconductor processing tray 100 includes a tray bottom plate 110 and a tray side wall 120; the tray side wall 120 surrounds the tray bottom plate 110 and is connected to the edge of the tray bottom plate 110; the tray bottom plate 110 includes a bearing portion 112 and an anti-adhesion portion 114, the bearing portion 112 is configured to bear semiconductor devices, the anti-adhesion portion 114 surrounds the bearing portion 112 and is located between the bearing portion 112 and the tray side wall 120; the average height of the anti-adhesion portion 114 is less than the average height of the bearing portion 112.

[0062] As Figure 5 and Figure 6 shown, the above anti-adhesion portion 114 includes a groove structure 1140, so that the average height of the anti-adhesion portion 114 is less than the average height of the bearing portion 112. The above groove structure 1140 includes a plurality of second grooves 142 sequentially arranged in the direction from the bearing portion 112 to the tray side wall 120, and the anti-adhesion portion 114 includes a sawtooth portion 143 located between the plurality of second grooves 142.

[0063] In the semiconductor processing tray provided by the embodiment of the present disclosure, the anti-adhesion portion is located around the bearing portion. Therefore, when the processing tray bears semiconductor devices, the bearing portion corresponds to the main body portion of the semiconductor device, and the anti-adhesion portion corresponds to the edge portion of the semiconductor device. Since the anti-adhesion portion includes a plurality of second grooves, the average height of the anti-adhesion portion is less than the average height of the bearing portion. When bearing semiconductor devices, the sawtooth portion contacts the edge portion of the semiconductor device, and the sawtooth portion can play a role in supporting the semiconductor device, but the contact area with the semiconductor device is very small, and the plurality of second grooves do not contact the edge portion of the semiconductor device. Therefore, the anti-adhesion portion can prevent the edge portion of the semiconductor device from adhering to the tray bottom plate during the high-temperature reflow process and the cooling process after the high-temperature reflow process while playing a supporting role, thereby preventing defects such as fragmentation and corner chipping of the semiconductor device or the tray bottom plate. On the other hand, since the tray side wall can also limit the displacement of the semiconductor device and prevent the semiconductor device from shifting.

[0064] In some examples, as Figure 5 and Figure 6 shown, each second groove 142 is a second annular groove 132 surrounding the bearing portion 112, so as to form an annular sawtooth portion 143 between the plurality of second annular grooves 132.

[0065] In some examples, such as Figure 5 and Figure 6 shown, the value range of the difference between the minimum height of the anti-sticking portion 114 and the maximum height of the bearing portion 112 is 0.3 mm - 0.5 mm. That is to say, the value range of the height difference between the bottom of the anti-sticking portion and the top of the bearing portion is 0.3 mm - 0.5 mm. Thus, a certain accommodation space can be formed between the anti-sticking portion and the edge portion of the semiconductor device, avoiding adhesion between the anti-sticking portion and the edge portion of the semiconductor device.

[0066] In some examples, such as Figure 5 and Figure 6 shown, the value range of the difference between the maximum height of the tray side wall 120 and the maximum height of the bearing portion 112 is 0.5 mm - 0.7 mm. Thus, the tray side wall 120 can better limit the displacement of the semiconductor device and prevent the semiconductor device from shifting.

[0067] In some examples, such as Figure 5 and Figure 6 shown, the tray side wall 120 includes at least one access notch 125. This access notch can facilitate the operator to separate the processing tray from the semiconductor device, thereby improving efficiency.

[0068] In some examples, such as Figure 5 and Figure 6 shown, the tray side wall 120 includes a plurality of access notches 125, which are circumferentially spaced along the edge of the tray bottom plate 110, so as to facilitate the operator to separate the processing tray from the semiconductor device in different directions.

[0069] Figure 7 FIG. is a plan view of another semiconductor processing tray provided by an embodiment of the present disclosure; Figure 8 is Figure 7 a cross-sectional view of the semiconductor processing tray shown along line AB.

[0070] As Figure 7 and Figure 8 shown, the semiconductor processing tray 100 includes a tray bottom plate 110 and a tray side wall 120; the tray side wall 120 surrounds the tray bottom plate 110 and is connected to the edge of the tray bottom plate 110; the tray bottom plate 110 includes a bearing portion 112 and an anti-sticking portion 114, the bearing portion 112 is configured to carry the semiconductor device, the anti-sticking portion 114 surrounds the bearing portion 112 and is located between the bearing portion 112 and the tray side wall 120; the average height of the anti-sticking portion 114 is less than the average height of the bearing portion 112.

[0071] As Figure 7 and Figure 8As shown, the above-mentioned bearing part 112 includes a plurality of convex structures 1120, so that the average height of the anti-adhesion part 114 is less than the average height of the bearing part 112.

[0072] In the semiconductor processing tray provided by the embodiment of the present disclosure, the anti-adhesion part is located around the bearing part. Therefore, when the processing tray bears a semiconductor device, the bearing part corresponds to the main body part of the semiconductor device, and the anti-adhesion part corresponds to the edge part of the semiconductor device. Since the bearing part includes a plurality of convex structures, the average height of the anti-adhesion part is less than the average height of the bearing part. When bearing a semiconductor device, the plurality of convex structures play a role in supporting the semiconductor device, so that the edge part of the semiconductor device does not contact the anti-adhesion part. Therefore, the anti-adhesion part can prevent the edge part of the semiconductor device from adhering to the tray bottom plate during the high-temperature reflow process and the cooling process after the high-temperature reflow process is completed, thereby preventing defects such as fragmentation and corner chipping of the semiconductor device or the tray bottom plate. On the other hand, since the tray side wall can also limit the displacement of the semiconductor device, it can prevent the semiconductor device from shifting.

[0073] In some examples, as Figure 7 and Figure 8 shown, the value range of the difference between the minimum height of the anti-adhesion part 114 and the maximum height of the bearing part 112 is 0.3 mm - 0.5 mm. That is to say, the value range of the height difference between the bottom of the anti-adhesion part and the top of the bearing part is 0.3 mm - 0.5 mm. Thus, a certain accommodation space can be formed between the anti-adhesion part and the edge part of the semiconductor device, avoiding adhesion between the anti-adhesion part and the edge part of the semiconductor device.

[0074] In some examples, as Figure 7 and Figure 8 shown, the value range of the difference between the maximum height of the tray side wall 120 and the maximum height of the bearing part 112 is 0.5 mm - 0.7 mm. Thus, the tray side wall 120 can better limit the displacement of the semiconductor device and prevent the semiconductor device from shifting.

[0075] In some examples, as Figure 7 and Figure 8 shown, the tray side wall 120 includes at least one access notch 125. The access notch can facilitate the operator to separate the processing tray from the semiconductor device, thereby improving efficiency.

[0076] In some examples, as Figure 7 and Figure 8 shown, the tray side wall 120 includes a plurality of access notches 125, which are arranged at intervals along the circumferential direction of the edge of the tray bottom plate 110, so as to facilitate the operator to separate the processing tray from the semiconductor device in different directions.

[0077] An embodiment of the present disclosure also provides a method for manufacturing a semiconductor device. Figure 9 It is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present disclosure. As Figure 9 shown, the method for manufacturing the semiconductor device includes the following steps S101 - S104:

[0078] Step S101: Grow borophosphosilicate glass on a quartz substrate to form a semiconductor device.

[0079] For example, the above-mentioned borophosphosilicate glass can be used as an interlayer insulating film in the semiconductor device.

[0080] Step S102: Place the semiconductor device on a semiconductor processing tray. The semiconductor processing tray is the semiconductor processing tray provided in any of the above examples.

[0081] Step S103: Perform a high-temperature reflow process on the semiconductor processing tray and the semiconductor device. The temperature range of the high-temperature reflow process is 1100°C - 1300°C.

[0082] For example, the semiconductor processing tray and the semiconductor device can be placed in a vertical furnace together to perform the high-temperature reflow process.

[0083] Step S104: Separate the semiconductor device after being processed by the high-temperature reflow process from the semiconductor processing tray.

[0084] In the method for manufacturing a semiconductor device provided by the embodiment of the present disclosure, by placing the semiconductor device on the semiconductor processing tray and then performing the high-temperature reflow process, the method for manufacturing the semiconductor device can prevent abnormal conditions such as deformation or warping of the semiconductor device. On the other hand, since the semiconductor processing tray is the semiconductor processing tray provided in any of the above examples, and the average height of the anti-adhesion part is less than the average height of the bearing part, there is a non-contact part between the anti-adhesion part and the edge part of the semiconductor device when carrying the semiconductor device. Therefore, the anti-adhesion part can prevent the edge part of the semiconductor device from adhering to the tray bottom plate during the high-temperature reflow process and the cooling process after the high-temperature reflow process ends, thereby preventing defects such as fragmentation or corner chipping of the semiconductor device or the tray bottom plate. On the other hand, since the tray side wall can also limit the displacement of the semiconductor device and prevent the semiconductor device from shifting.

[0085] In some examples, the step of growing borophosphosilicate glass on the quartz substrate to form a semiconductor device may further include: forming a semiconductor layer on the quartz substrate; patterning the semiconductor layer to form a chip pattern; depositing borophosphosilicate glass on the chip pattern by a chemical vapor deposition (such as PECVD) process.

[0086] For example, the semiconductor layer described above may be germanium-doped silica glass (Ge-SiO2) for transmitting optical signals.

[0087] The following points need to be explained:

[0088] (1) In the accompanying drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0089] (2) Without conflict, the features in the same embodiment and different embodiments of the present disclosure can be combined with each other.

[0090] The above description is only an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A semiconductor processing tray, comprising: Pallet bottom plate; as well as The side wall of the pallet surrounds the bottom plate of the pallet and is connected to the edge of the bottom plate of the pallet, It is characterized in that the tray bottom plate comprises a bearing portion and an anti-adhesion portion, and the average height of the anti-adhesion portion is smaller than the average height of the bearing portion. The anti-adhesion portion surrounds the load-bearing portion and is located between the load-bearing portion and the side wall of the tray, and does not overlap with the side wall of the tray in a direction perpendicular to the bottom plate of the tray. The carrying portion is configured to carry a semiconductor device, the semiconductor device includes borophosphosilicate glass, the carrying portion includes a carrying surface in contact with the semiconductor device, the carrying surface is a plane, and the side wall of the tray includes at least one access notch, The size of the anti-adhesion portion in the direction from the center of the bearing portion to the side wall of the tray ranges from 15 mm to 30 mm.

2. The semiconductor processing tray according to claim 1, characterized in that: The difference between the minimum height of the anti-adhesion portion and the maximum height of the bearing portion ranges from 0.3 mm to 0.5 mm.

3. The semiconductor processing tray according to claim 1, characterized in that: The tray side wall includes a plurality of access notches, which are arranged along the circumference of the edge of the tray bottom plate.

4. The semiconductor processing tray according to any one of claims 1 to 3, characterized in that: The anti-adhesion portion includes a groove structure, so that an average height of the anti-adhesion portion is smaller than an average height of the supporting portion.

5. The semiconductor processing tray according to claim 4, characterized in that: The groove structure is a first annular groove surrounding the bearing portion.

6. The semiconductor processing tray according to claim 4, characterized in that: The groove structure includes a plurality of first grooves arranged along the circumference of the edge of the bearing portion, and the plurality of first grooves are arranged at intervals.

7. The semiconductor processing tray according to claim 4, characterized in that: The groove structure includes a plurality of second grooves sequentially arranged along a direction from the bearing portion to the side wall of the tray, and the anti-adhesion portion includes a serration portion located between the plurality of second grooves.

8. The semiconductor processing tray according to claim 7, characterized in that: Each of the second grooves is a second annular groove surrounding the bearing portion.

9. The semiconductor processing tray according to any one of claims 1 to 3, characterized in that: The bearing portion includes a plurality of protruding structures, so that an average height of the anti-adhesion portion is smaller than an average height of the bearing portion.

10. The semiconductor processing tray according to any one of claims 1 to 3, characterized in that: The difference between the maximum height of the tray side wall and the maximum height of the bearing portion ranges from 0.5 mm to 0.7 mm.

11. A method for manufacturing a semiconductor device, characterized in that: include: Growing borophosphosilicate glass on a quartz substrate to form a semiconductor device; placing the semiconductor device on a semiconductor processing tray; performing a high temperature reflow process on the semiconductor processing tray and the semiconductor device; as well as Separating the semiconductor device after the high temperature reflow process from the semiconductor processing tray, Wherein, the semiconductor processing tray is the semiconductor processing tray according to any one of claims 1 to 10, and the temperature of the high-temperature reflow process ranges from 1100° C. to 1300° C.

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