An interleaving and deinterleaving method suitable for Turbo decoding of 4G 802.16m protocol

Abstract

An interleaving and deinterleaving method suitable for Turbo decoding of 4G 802.16m protocol, aiming at 39 groups of Turbo interleaving parameters supported by 4G 802.16m protocol, the method uses grouped interleaving initial address table Itab_init and fixed interleaving step Istep at each level to realize simplified calculation of interleaving address; uses grouped deinterleaving initial address table Dtab_init and fixed deinterleaving step Dstep at each level to realize simplified calculation of deinterleaving address; uses the mapping relationship between interleaving and deinterleaving to process the interleaver and deinterleaver of Turbo iterative decoding and replace the deinterleaving table and interleaving table between iteration of component decoders. The present application reduces the calculation complexity based on the simplified Turbo decoding interleaving and deinterleaving calculation method, and replaces the interleaving and deinterleaving tables between two component encoders to realize parallel processing of interleaving and deinterleaving processing and Turbo component decoder external information calculation, which reduces the interleaving and deinterleaving delay to equivalent only one processing time slot, is irrelevant to interleaving depth, and improves the decoding rate of Turbo decoding.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of channel coding and decoding, and particularly relates to an interleaving and deinterleaving method suitable for Turbo decoding of 4G 802.16m protocol. BACKGROUND

[0002] The IEEE 802.16m protocol is an upgrade of the 4G WiMax technology, aiming at higher wireless transmission rate and improved network performance. The IEEE 802.16m can support a wireless transmission rate of up to 1 Gbps, which is a significant performance improvement over the previous standard, thus meeting the higher data transmission and multimedia application requirements.

[0003] In the field of channel coding, Turbo code uses two component decoders for iterative decoding, and has a decoding performance approaching the Shannon limit, and is widely used. However, the decoding scheme has a large decoding delay, mainly including three parts: the decoding delay of the component decoder, the interleaving and deinterleaving delay, and the iteration number delay. In terms of interleaving and deinterleaving delay, the factors affecting the delay mainly include the interleaving depth and the interleaving calculation complexity. The IEEE 802.16m protocol uses dual-binary Turbo coding, and in order to support various service requirements, it supports 39 groups of Turbo interleaving parameters, and the maximum interleaving depth is 4800. For the implementation of the interleaver and the deinterleaver, there are usually two schemes: 1. Direct storage method, which directly stores the interleaving and deinterleaving table. This scheme reduces the calculation complexity and the interleaving delay, but requires additional storage resources. 2. Non-storage method of direct calculation, the dual-binary Turbo interleaver of the 802.16m protocol uses two-stage interleaving, and the calculation of the second-stage interleaving index P[j] requires one multiplication, three additions, and two remainder operations, which is relatively complex, and there is no direct deinterleaving calculation formula, so the interleaver calculation is complex and still needs to store the deinterleaving table. At the same time, the protocol clearly specifies the interleaving processing method, which requires the completion of the storage of the data to be interleaved before starting the interleaving processing, which introduces interleaving delay, and the interleaving delay increases by a multiple with the increase of the iteration number.

[0004] It should be noted that the information disclosed in the above background section is only for understanding the background of the present application, and therefore can include information that does not constitute the prior art known to those of ordinary skill in the art. SUMMARY

[0005] The main purpose of the present application is to solve the problems existing in the above background technology, and to provide an interleaving and deinterleaving method suitable for Turbo decoding of 4G 802.16m protocol.

[0006] To achieve the above purpose, the present application adopts the following technical scheme:

[0007] An interleaving and deinterleaving method suitable for Turbo decoding of 4G 802.16m protocol, comprising:

[0008] (1) using grouped interleaving initial address table Itab_init and fixed interleaving step length Istep at each stage to realize simplified calculation of interleaving address;

[0009] (2) using grouped deinterleaving initial address table Dtab_init and fixed deinterleaving step length Dstep at each stage to realize simplified calculation of deinterleaving address;

[0010] (3) using the mapping relationship between interleaving and deinterleaving to process interleaver and deinterleaver of Turbo iterative decoding, and replacing the deinterleaving table and interleaving table between component decoders to realize interleaving and deinterleaving scheme with random access characteristics, and realize parallel processing of preceding stage extrinsic information calculation and interleaver or deinterleaver.

[0011] Further, in the (1), the grouped interleaving initial address Itab_init and fixed interleaving step length Istep are used, and the interleaving groups have the following characteristics: the interleaving address calculation uses grouped processing, the group index i = mod(j, 4), and the index j with the same remainder has the same interleaving, wherein the group index i = 0, 1, 2, 3, and the interleaving address index j = 0, 1, … N-1, N being the interleaving depth.

[0012] Further, in the (1), the grouped interleaving initial address Itab_init and fixed interleaving step length Istep are used, and the group parameter calculation has the following characteristics:

[0013] Based on the interleaving length N and the interleaving address P[j] calculation rule specified in 802.16m, the interleaving parameters P0, P1, P2, P3 are configured by table lookup, the interleaving initial address Itab_init[i] and the step length Istep within the group are calculated, and the group index i = 0, 1, 2, 3.

[0014]

[0015] Further, in the (1), the interleaver uses the grouped interleaving initial address table Itab_init and the fixed interleaving step length Istep at each stage to realize simplified calculation of interleaving address, and has the following characteristics: the interleaving index Intlv_Indx[i] of the group is initially assigned as Itab_init[i]; based on parallel iteration increment, four interleaving indexes Intlv_Idx[i] of the qth iteration are calculated: q q-1 ​+Istep; This simplifies the modulo operation based on a conditional logic. If Intlv_Idx[i]... q If N >= N, then Intlv_Idx[i] q =Intlv_Idx[i] q -N, the internal index of the group i = 0, 1, 2, 3, the number of interleaved index iterations q = 0, 1, ..., N / 4-1.

[0016] Furthermore, in step (2), the deinterleaving initial address table Dtab_init and the step-by-step fixed interleaving step size Dstep are used in a grouped manner. The calculation of its grouping parameters has the following characteristics: In the iterative calculation of the interleaving index, the parameters Dtab_init and Dstep are calculated based on simplified judgment logic: if Intlv_Idx[i] q If == j, then Dtab_init[j] = i + SIdx; if Intlv_Idx[i]... q =5, then DStep = i + SIdx; in the above formula, the internal index of the group i,j = 0,1,2,3; the number of interleaving iterations q = 0,1,…N / 4-1; the starting index of this iteration SIdx = q*4.

[0017] Furthermore, in step (2), the deinterleaver uses the initial deinterleaving address table Dtab_init and the step-by-step fixed interleaving step size Dstep to simplify the calculation of the deinterleaving address, wherein: the deinterleaving index Dintlv_Idx[i] of the initial assignment group is Dtab_init[i]; the four deinterleaving indices for the qth iteration are calculated based on parallel iterative increment: Dintlv_Idx[i] q =Dintlv_Idx[i] q +Dstep simplifies the modulo operation based on judgment logic; if Ditlv_Idx[i]... q If N >= N, then Dintlv_Idx[i] q =Dintlv_Idx[i] q -N, grouping index i = 0, 1, 2, 3, interleaving iteration count q = 0, 1, ..., N / 4-1.

[0018] Furthermore, in step (3), the interleaving and deinterleaving are mapped to each other to process the interleaver and deinterleaver of Turbo iterative decoding, and the deinterleaving table and interleaving table of the component decoders are replaced, thus realizing an interleaving and deinterleaving scheme with sequential random placement characteristics, wherein:

[0019] For the external information output by the component decoder DEC1 of Turbo decoding, an interleaving process is implemented using a deinterleaving table;

[0020]

[0021] wherein the iteration number of the group deinterleaver is q = floor(k / 4), the time of the turbo extrinsic information is k = 0, 1, … N-1, the group index of the group interleaving is i = 0, 1, 2, 3, when k++ processing, i++, if i equals 4, i is assigned 0, thus i adopts the counting mode with the cycle length of 4.

[0022] Further, in the (3), the interleaver and deinterleaver processing of the turbo iteration decoding is processed by using the mapping relationship of the interleaving and deinterleaving, the deinterleaving table and the interleaving table between the component decoders are replaced, and the interleaving and deinterleaving scheme with the pick-up disorder feature is realized, wherein:

[0023] For the extrinsic information output by the component decoder DEC2 of the turbo decoding, the deinterleaving processing is realized by using the interleaving table.

[0024]

[0025] wherein the iteration number of the group interleaver is q = floor(k / 4), the time of the turbo extrinsic information is k = 0, 1, … N-1, the group index of the group interleaving is i = 0, 1, 2, 3, when k++ processing, i++, if i equals 4, i is assigned 0, thus i adopts the counting mode with the cycle length of 4.

[0026] Further, in the (3), for the component decoders DEC1 and DEC2 of the turbo decoding, after the calculation and output of the first group of extrinsic information are completed, two-step parallel processing is immediately started: (1) the calculation corresponding to the interleaving or deinterleaving of the current index is calculated, and the extrinsic information at the current time k is stored in the interleaving index or deinterleaving index position of the corresponding a priori information ; (2) the extrinsic information calculation at the next time is calculated synchronously, the present method is aimed at the extrinsic information output in turn, and the replacement processing is immediately completed to achieve the pick-up disorder effect, the calculation of the extrinsic information and the interleaving or deinterleaving processing are calculated in parallel, and the equivalent interleaving or deinterleaving delay only needs one processing time slot, which is irrelevant to the interleaving depth.

[0027] A computer program product comprising a computer program which, when executed by a processor, implements the interleaving and deinterleaving method suitable for the turbo decoding of the 4G 802.16m protocol.

[0028] In some embodiments, the method has the following features:

[0029] (1) Based on the calculation rules of interleaving length N and interleaving address P[j] specified in 802.16m, configure interleaving parameters: P0, P1, P2, P3 by looking up the table, and calculate the interleaving initial address Itab_init[i] and the group step Istep, where i = 0, 1, 2, 3;

[0030]

[0031] (2) Initial assignment of interleaving index Intlv_Indx[i] = Itab_init[i]. The four interleaving indices for the q-th iteration are calculated using parallel iterative incrementing. Simultaneously, during the iterative calculation of the interleaving indices, the parameters Dtab_init and Dstep are calculated based on simplified judgment logic:

[0032] Intlv_Idx[i] q =Intlv_Idx[i] q-1 +Istep. Simplify the modulo operation based on the conditional logic; if Intlv_Idx[i]... q If N >= N, then Intlv_Idx[i] q =Intlv_Idx[i] q -N;

[0033] If Intlv_Idx[i] q If == j, then Dtab_init[j] = i + SIdx; if Intlv_Idx[i]... q =5, then DStep = i + SIdx; in the above formula, the internal index of the group i,j = 0,1,2,3; the number of interleaving iterations q = 0,1,…N / 4-1; the starting index of this iteration SIdx = q*4.

[0034] (3) Calculate the four interleaved indices of the solution in the q-th iteration based on parallel iterative increment: Dintlv_Idx[i] q =Dintlv_Idx[i] q +Dstep simplifies the modulo operation based on judgment logic; if Ditlv_Idx[i]... q If N >= N, then Dintlv_Idx[i] q =Dintlv_Idx[i] q -N, grouping index i = 0, 1, 2, 3, interleaving iteration count q = 0, 1, ..., N / 4-1;

[0035] (4) By utilizing the mapping relationship between interleaving and deinterleaving, the interleaver and deinterleaver of Turbo iterative decoding are processed, and the deinterleaving table and interleaving table of the component decoders are replaced, thus realizing an interleaving and deinterleaving scheme with sequential random placement characteristics:

[0036] extrinsic information output by the component decoder DEC1 for Turbo decoding The interleaving processing is realized by using the deinterleaving table to obtain the a priori information

[0037]

[0038] extrinsic information output by the component decoder DEC2 for Turbo decoding The deinterleaving processing is realized by using the interleaving table

[0039]

[0040] wherein the iteration number q of the packet interleaver is equal to floor (k / 4), the time k of the extrinsic information for Turbo decoding is equal to 0, 1, …, N-1, the group index i of the packet interleaving is equal to 0, 1, 2, 3, when the processing of k++ is performed, i++ is performed, if i is equal to 4, i is assigned to 0, therefore, i is counted in a cyclic length of 4.

[0041] (5) for the component decoders DEC1 and DEC2 for Turbo decoding, after the output of the calculation of the first group of extrinsic information is completed, two-step parallel processing is started immediately: (1) the calculation corresponding to the interleaving or deinterleaving of the current index is calculated, and the extrinsic information at the current time k is stored in the interleaving index or deinterleaving position of the corresponding a priori information ; (2) the extrinsic information calculation at the next time is calculated synchronously, this method is aimed at the extrinsic information output in sequence, and the permutation processing is completed immediately to achieve the effect of taking disorderly and placing orderly, the calculation of the extrinsic information is realized in parallel with the interleaving or deinterleaving processing, and the equivalent interleaving or deinterleaving delay only needs one processing time slot, which is irrelevant to the interleaving depth.

[0042] The present application has the following beneficial effects:

[0043] The present application proposes a simplified calculation method of interleaving and deinterleaving, which is realized by using the addition of the packet initial address and incremental step, and the operation complexity is simplified. Meanwhile, this aspect is completely suitable for the 39-group Turbo interleaving parameters supported by 4G 802.16m, based on the simplified calculation method, the calculation complexity of the interleaving is simplified, the storage requirement of the deinterleaving table is solved, and the memory is reduced.

[0044] The application utilizes the mapping relationship between interleaving and deinterleaving, and proposes the deinterleaving table and interleaving table between permutation component decoders to realize the interleaving and deinterleaving function in the interleaver and deinterleaver processing in the iteration of Turbo decoding, so that the interleaving and deinterleaving processing is realized in parallel with the outer information calculation of Turbo component decoder, and the interleaving and deinterleaving delay is reduced to equivalent only one processing time slot, which is irrelevant to the interleaving depth, and the decoding throughput of Turbo decoding is improved.

[0045] Other beneficial effects of the embodiments of the application will be further described below. BRIEF DESCRIPTION OF DRAWINGS

[0046] Figure 1 The step flow chart of the interleaving and deinterleaving method suitable for the Turbo decoding of 4G 802.16m protocol of the embodiments of the application.

[0047] Figure 2 The structure block diagram of the dual-binary Turbo encoder of 802.16m protocol of the embodiments of the application.

[0048] Figure 3 The theoretical block diagram of the dual-binary Turbo iteration decoding process of 802.16m protocol of the embodiments of the application.

[0049] Figure 4 The iteration decoding block diagram of the dual-binary Turbo of 802.16m protocol using permutation interleaving and deinterleaving table of the embodiments of the application. DETAILED DESCRIPTION

[0050] The embodiments of the application are described in detail below. It should be emphasized that the following description is only exemplary, and is not intended to limit the scope of the application and its applications.

[0051] In addition, the terms "first", "second" are only used for description purpose, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0052] This invention proposes an interleaving and deinterleaving method suitable for Turbo decoding of the 4G 802.16m protocol. This method targets the 39 sets of Turbo interleaving parameters supported by the 4G 802.16m protocol. It employs a grouped interleaving initial address table (Itab_init) and a progressively fixed interleaving step size (Istep) to simplify the calculation of interleaving addresses; it also employs a grouped deinterleaving initial address table (Dtab_init) and a progressively fixed deinterleaving step size (Dstep) to simplify the calculation of deinterleaving addresses. Utilizing the mapping relationship between interleaving and deinterleaving, the method processes the interleaver and deinterleaver in Turbo iterative decoding, replacing the deinterleaving and interleaving tables iteratively between component decoders. This achieves an interleaving and deinterleaving scheme with sequential and random placement characteristics, enabling parallel processing of front-end external information calculation and the interleaver or deinterleaver. This invention is based on a simplified Turbo decoding interleaving and deinterleaving calculation method, which reduces computational complexity. At the same time, by replacing the interleaving and deinterleaving tables between the two component encoders, the interleaving and deinterleaving processes can be paralleled with the external information calculation of the Turbo component decoder. The interleaving and deinterleaving delays are reduced to an equivalent processing time slot, which is independent of the interleaving depth, thereby improving the decoding rate of Turbo decoding.

[0053] To more clearly illustrate the implementation and optimization effects of the interleaving and deinterleaving methods of the present invention, based on... Figure 2 The diagram shows the block structure of an 802.16m protocol dual-binary Turbo encoder. Briefly describe the encoding and interleaving related rules. Let the input dual-binary bit sequence be (A,B)=(a0,b0),(a1,b1),…,(a…b1…b2 ... N-1 ,b N-1 ), where N is the length of the bit pair, and 2N is the length of the information bits to be encoded. The encoded output consists of six sub-blocks, namely: A, B, Y1, Y2, W1, W2 = {a0, a1, ..., a N-1 ,b0,b1,…,b N-1 ,y 1,0 ,y 1,1 ,…,y 1,N-1 ,y 2,0 ,y 2,1 ,…,y 2,N-1 ,w 1,0 ,w 1,1 ,…,w 1,N-1 ,w 2,0 ,w 2,1 ,…,w 2,N-1} Turbo-coded interleavers use two-stage interleaving:

[0054] 1) Bit interleaving. This involves swapping the bits with odd-numbered sequences (a, b, c) within the input encoder's binary bit sequence. 2i-1 ,b 2i-1) internal elements, resulting in (b 2i-1 2i-1 ), i = 0, 1,... N-1.

[0055] 2) Interleaving between bit groups. That is, the first level interleaving result is rearranged in sequence elements, and P[j] represents the address index of the dual binary sequence after the second level interleaving. The second level interleaving uses quadratic congruence method, and the specific calculation method is as shown in the following formula.

[0056]

[0057] Where mod is the modulus operation, P0, P1, P1, P3 are interleaving parameters, and N is the information bit pair length. Therefore, the address mapping P[j] is used for the specific implementation algorithm of Turbo coding interleaving, as shown in the following formula:

[0058]

[0059] In the formula, a[], b[] are the information bit sequences before interleaving, aInt[], bInt[] are the information bit sequences after interleaving, and different interleaving parameters are configured for different information bit lengths in the protocol, as shown in the following table 1:

[0060] Table 1 Interleaving parameter table of 802.16m protocol Turbo

[0061]

[0062]

[0063] From table 1, it can be seen that the interleaving parameters of 802.316m protocol support 39 groups, and the interleaving depth is as high as 2400. For the implementation of interleaver and deinterleaver, there are usually two schemes:

[0064] One is to use the direct storage method, and the storage size required by the interleaving table is: 2400*ceil(log2(2400)) = 28800 Bit. Combined with the decoding block diagram of dual binary Turbo coding shown in Figure 3 During the decoding process, in order to reduce the decoding delay, two component decoders are usually used for parallel processing, so the interleaving and deinterleaving tables need to be stored at the same time, so the required interleaving and deinterleaving storage size is 57600 Bit. This scheme reduces the calculation complexity, but increases the storage resources.

[0065] ​II. The second level interleaving of the turbo interleaver in the non-storage mode of direct calculation requires one multiplication, three additions, and two remainder operations for the calculation of the interleaving index P[j], which is relatively complex and has no direct de-interleaving calculation formula, thus having the problems of complex interleaver calculation and the need for storage of the de-interleaving table. Meanwhile, the interleaving mode of the interleaving processing Intx[i]=x[P[i]] given in formula (2) needs to complete the storage of x before starting the interleaving processing, and the interleaving scheme is here referred to as disorderly taking and orderly placing, which introduces interleaving delay.

[0066] In view of the problems of the above two schemes, the present application utilizes the mapping relationship between interleaving and de-interleaving to process the interleaver and de-interleaver of Turbo iterative decoding, and to replace the de-interleaving table and interleaving table between iterations of the component decoder, as shown in formula (1). Figure 4 The present application will be described in detail below with the Turbo decoding length as an example, where the index table Index is 4 and the interleaving length N is 40. The specific implementation steps are as follows:

[0067] (S1) Based on the interleaving length N being 40, the interleaving parameters are configured by table lookup: P0=7, P1=4, P2=32, and P3=36. The interleaving initial address Itab_init[i] and the intra-group step Istep are calculated based on the calculation of the interleaving address P(j) (formula-1), where i=0, 1, 2, 3.

[0068]

[0069] (S2) The decoding input information bit soft information {y ka , y kb} is interleaved to obtain the interleaved information part where the time k=0, 1…N-1. The de-interleaving initial address Dtab_init[i] and the intra-group step Dstep of de-interleaving are obtained. The specific implementation steps are as follows:

[0070] (S2.1) Let the current group initial address be SIdx=0, the iteration number q=0, and the interleaving index of the group be assigned the initial value Intlv_Idx[i]=Itab_init[i], i=0, 1, 2, 3.

[0071] (S2.2) Based on the four interleaving indexes Intlv_Idx[i] of the current iteration group, Intlv_Idx[i]=Intlv_Idx[i]+Istep, based on the judgment logic simplification mod operation, if Intlv_Idx[i]>=N, then Intlv_Idx[i]=Intlv_Idx[i]-N, i=0, 1, 2, 3, and the y ka , ykb The interweaving, output

[0072] (S2.3) The deinterleaving initial address Dtab_init[i] is found based on the comparator, and the specific implementation is as follows:

[0073] If Intlv_Idx[i] <= 5, then proceed to step (2.4) after the subsequent judgment; otherwise, proceed directly to step (2.4).

[0074] If Intlv_Idx[i] == j, then Dtab_init[j] = i + SIdx;

[0075] If Intlv_Idx[i] = 5, then DStep = i + SIdx;

[0076] In the above formula, i,j=0,1,2,3. In this implementation case, Dtab_init=[25 0 15 30],DStep=12; (S2.4) Counting process: SIdx=SIdx+4, iteration number q++, and determine q. If it is less than N / 4, return to step (S2.2), otherwise end the interleaving process. Table 2 gives the four interleaving indices Intlv_Idx that are computed in parallel in different iteration numbers.

[0077] Table 2. Interleaved Lookup Table for Parallel Group Computation Based on Iteration

[0078]

[0079]

[0080] S3: Set the component decoder iteration count DecIter=0, the current decoder component decoder IDEC=0, and the maximum iteration count threshold InterThr=6;

[0081] S4: When the Turbo component decoder completes sub-decoding, the posterior log-likelihood ratio L of the output information bits is... i (u k External information At that time, based on the interleaving or deinterleaving table, the extrinsic information at each time step is immediately stored in the prior information of the corresponding sub-decoder. The storage address enables parallel processing of the pre-processing and interleaving or deinterleaving. This invention focuses on optimizing the interleaving and deinterleaving processes during turbo decoding; therefore, the decoding process of the sub-decoder is simplified here. The specific implementation steps are as follows:

[0082] (S4.1) Let the cycle count Cnt = 0, the current time K = 0, and select the interleaving or deinterleaving parameters based on the current Turbo component decoder DEC1 or DEC2.

[0083] If IDEC = = 0 is component decoder DEC1, select the deinterleaving parameters PIdx[i] = Dtab_int[i], and deinterleaving step Step = Dstep, to realize the interleaving function in turbo decoding.

[0084] If IDEC = = 1 is component decoder DEC2, select the interleaving parameters PIdx[i] = Itab_init[i], and interleaving step Step = Istep, to realize the deinterleaving processing in turbo decoding.

[0085] In the present application, the tables for replacing the interleaving and deinterleaving between two component encoders are used to realize the interleaving and deinterleaving processing in parallel with the output timing of the extrinsic information of the Turbo component decoder, thereby reducing the interleaving and deinterleaving delay.

[0086] (S4.2) Calculate the extrinsic information at time k based on the calculation formula of the extrinsic information.

[0087]

[0088] (S4.3) Calculate the interleaving or deinterleaving index PIdx based on the iterative increment calculation:

[0089] PIdx[Cnt] = PIdx[Cnt] + step, and if PIdx[Cnt] >= N, then PIdx[Cnt] = -N.

[0090] (S4.4) Realize the replacement processing of the extrinsic information based on the replacement index Paddr[Cnt], to obtain the a priori information:

[0091] If IDEC = = 0 is component decoder DEC1:

[0092]

[0093] If IDEC = = 1 is component decoder DEC2:

[0094]

[0095] (S4.5) Increase the cycle count Cnt by 1, and increase k by 1, if Cnt = = 4, then Cnt = 0, if k = = N, then enter step S5, otherwise enter step (S4.2). Table 3 shows four interleaving indexes DIntlv_Idx calculated in parallel in different iteration numbers in the present embodiment.

[0096] Table 3 Iteration-based parallel-grouping computation deinterleaving lookup table

[0097]

[0098] (S5) Iteration number DecIter++ processing, if DecIter == 2*InterThr, end iteration decoding, enter step S6, otherwise IDEC = mod(IDEC+1,2) enter (S4.1)

[0099] (S6) When the maximum iteration number is reached, the a posteriori likelihood ratio L i (u k ) of the component decoder DEC2 is hard-decision, the decoding bit pair u k is obtained, and deinterleaving processing is realized using interleaving parameters. The specific implementation steps are:

[0100] (S6.1) Select interleaving parameters PIdx[i] = Itab_init[i], interleaving step Step = Istep, realize deinterleaving processing in Turbo decoding, and let k = 0, Cnt = 0.

[0101] (S6.2) The a posteriori likelihood ratio L i (u k ) of the component decoder DEC2 is hard-decision, the hard-decision bit pair u k is obtained:

[0102]

[0103] (S6.2) Interleaving index PIdx based on iteration increment calculation:

[0104] PIdx[Cnt] = PIdx[Cnt] + step, if PIdx[Cnt] >= N, then PIdx[Cnt] = -N;

[0105] (S6.3) Based on the permutation index Paddr[Cnt], the permutation processing of the hard-decision information is realized, and the decoding output information bit is obtained:

[0106]

[0107] (S6.5) The loop counter Cnt++ is obtained, k++, if Cnt == 4, Cnt = 0, if k == N, enter step S7, otherwise enter step (S6.2).

[0108] (S7) Output DecData[2N-2], DecData[2N-1], and end the entire Turbo decoding iteration.

[0109] The embodiment of the present application further provides a storage medium for storing a computer program, which is executed to perform at least the method described above.

[0110] The embodiment of the present application further provides a control device, comprising a processor and a storage medium for storing a computer program; wherein the processor is configured to execute the computer program to perform at least the method described above.

[0111] The embodiment of the present application further provides a processor, which executes a computer program to perform at least the method described above.

[0112] The storage medium can be implemented by any type of nonvolatile storage device, or a combination thereof. The nonvolatile storage device can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a ferromagnetic random access memory (FRAM), a flash memory, a magnetic surface storage, an optical disc, or a compact disc read-only memory (CD-ROM). The magnetic surface storage can be a disk storage or a tape storage. The storage medium described in the embodiment of the present application is intended to include, but is not limited to, these and any other suitable types of storage.

[0113] In several embodiments of the present application, it should be understood that the disclosed system and method can be implemented in other manners. The described device embodiments are merely illustrative, for example, the division of the units is only a logical function division, and there can be another division manner in actual implementation, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed coupling, or direct coupling or communication connection between the components can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or in other forms.

[0114] The units described as separate components above can or can not be physically separate, and the components shown as units can or can not be physical units, that is, can be located in one place or distributed on multiple network units; part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0115] In addition, each functional unit in each embodiment of the present application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be realized in the form of hardware or in the form of hardware plus software functional unit.

[0116] Those skilled in the art can understand that all or part of the steps of the above-mentioned method embodiments can be completed by program instruction related hardware, and the foregoing program can be stored in a computer readable storage medium, and the program executes the steps including the above-mentioned method embodiments when executed; and the foregoing storage medium includes: mobile storage device, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and various storage program codes.

[0117] Alternatively, the integrated unit of the present application, if implemented in the form of a software function module and sold or used as an independent product, can also be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the embodiments of the present application can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the various embodiments of the present application. The foregoing storage medium includes: mobile storage device, ROM, RAM, magnetic disk or optical disk, and various storage program codes.

[0118] The methods disclosed in the several method embodiments of the present application can be combined arbitrarily without conflict to obtain new method embodiments.

[0119] The features disclosed in the several product embodiments of the present application can be combined arbitrarily without conflict to obtain new product embodiments.

[0120] The features disclosed in the several method or device embodiments of the present application can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

[0121] The above is further detailed description of the present application in combination with specific preferred embodiments, and cannot be deemed as limitation of the specific implementation of the present application to these descriptions. For those skilled in the art to which the present application belongs, without departing from the concept of the present application, a number of equivalent substitutions or obvious variations can be made, and the performance or use is the same, which should be deemed as falling within the protection scope of the present application.

Claims

1. An interleaving and deinterleaving method for Turbo decoding of the 4G 802.16m protocol, characterized in that, include: (1) The interleaving initial address table Itab_init and the step-by-step fixed interleaving step size Istep are used to simplify the calculation of the interleaving address; (2) The deinterleaving initial address table Dtab_init and the step-by-step fixed deinterleaving step size Dstep are used to simplify the calculation of the deinterleaving address; (3) By utilizing the mutual mapping relationship between interleaving and deinterleaving, the interleaver and deinterleaver of Turbo iterative decoding are processed, and the deinterleaving table and interleaving table of the component decoders are replaced, thus realizing an interleaving and deinterleaving scheme with sequential random placement characteristics, and realizing the parallel processing of the front-end external information calculation and the interleaver or deinterleaver; among them, for the component decoders DEC1 and DEC2 of Turbo decoding, after completing the first set of external information After the calculation output, immediately initiate two parallel processing steps: (a) calculate the corresponding interleaving or deinterleaving index and input the external information at the current time k. Stored in the corresponding prior information (a) The interleaving index or deinterleaving index position; (b) Simultaneously calculate the external information calculation at the next moment, and perform the permutation process for the external information output in sequence, so as to realize the parallel calculation of external information calculation and interleaving or deinterleaving processing.

2. The interleaving and deinterleaving method for Turbo decoding of the 4G 802.16m protocol as described in claim 1, characterized in that, In (1), the grouped interleaving initial address table Itab_init and the step-by-step fixed interleaving step size Istep are used. The interleaving group has the following characteristics: the interleaving address calculation adopts group processing, and its group index i=mod(j,4) realizes that the index j with the same remainder has the same interleaving, where the group index i=0,1,2,3, the interleaving address index j=0,1,…N-1, and N is the interleaving depth.

3. The interleaving and deinterleaving method for Turbo decoding of the 4G 802.16m protocol as described in claim 1, characterized in that, In (1), the grouped interleaving initial address table Itab_init and the step-by-step fixed interleaving step size Istep are used. The calculation of its grouping parameters has the following characteristics: Based on the interleaving depth N and interleaving address P[j] calculation rules specified in the 802.16m protocol, where j is the interleaving address index, the interleaving parameters are configured by looking up the table: P0, P1, P2, P3; the initial interleaving address Itab_init[i] and the intra-group step size Istep are calculated, with group index i=0,1,2,3: 。 4. The interleaving and deinterleaving method for 4G 802.16m protocol Turbo decoding as described in claim 1, characterized in that, In (1), the interleaver uses a grouped interleaving initial address table Itab_init and a progressively fixed interleaving step size Istep to simplify the calculation of the interleaving address. It has the following characteristics: the initial assignment of the grouped interleaving index Intlv_Indx[i] = the interleaving initial address Itab_init[i]; and the calculation of the four interleaving indices for the q-th iteration based on parallel iterative increments: Intlv_Idx[i] q = Intlv_Idx [i] q-1 + Istep; Simplifies modulo operations based on conditional logic, if Intlv_Idx[i]... q If N >= N, then Intlv_Idx[i] q = Intlv_Idx[i] q - N, grouping index i=0,1,2,3, interleaving index iteration count q=0,1,…,N / 4-1, N is the interleaving depth.

5. The interleaving and deinterleaving method for 4G 802.16m protocol Turbo decoding as described in claim 4, characterized in that, In (2), the deinterleaving initial address table Dtab_init and the step-by-step fixed deinterleaving step size Dstep are used in a grouped manner. The calculation of its grouping parameters has the following characteristics: In the iterative calculation of the interleaving index, the parameters Dtab_init and Dstep are calculated based on simplified judgment logic: if Intlv_Idx[i] q If == j, then Dtab_init[j] = i + SIdx; if Intlv_Idx[i]... q ==5, then DStep = i+SIdx; In the above formula, the internal indexes of the group i,j=0,1,2,3; The number of interleaving iterations is q = 0, 1, ..., N / 4-1; the starting index of this iteration is SIdx = q * 4.

6. The interleaving and deinterleaving method for 4G 802.16m protocol Turbo decoding as described in claim 1, characterized in that, In (2), the deinterleaver uses a deinterleaving initial address table Dtab_init and a progressively fixed deinterleaving step size Dstep to simplify the calculation of the deinterleaving address, wherein: the deinterleaving index Dintlv_Idx[i] of the initial assignment group = the deinterleaving initial address Dtab_init[i]; the four deinterleaving indices of the qth iteration are calculated based on parallel iterative increment: Dintlv_Idx[i] q =Dintlv_Idx [i] q + Dstep, simplifies the modulo operation based on judgment logic; if Dintlv_Idx [i]... q If >= N, then Dintlv_Idx[i] q = Dintlv_Idx [i] q -N, grouping index i=0,1,2,3, interleaving iteration count q=0,1,…,N / 4-1, N is the interleaving depth.

7. The interleaving and deinterleaving method for 4G 802.16m protocol Turbo decoding as described in claim 1, characterized in that, In (3), the interleaving and deinterleaving relationships are used to process the interleaver and deinterleaver of Turbo iterative decoding, and the deinterleaving table and interleaving table of the component decoders are replaced, thus realizing an interleaving and deinterleaving scheme with sequential and random placement characteristics, wherein: For the external information output by the component decoder DEC1 of Turbo decoding, an interleaving process is implemented using a deinterleaving table; ； Where Dintlv_Idx [i] q Let q be the deinterleaving index of the deinterleaving unit with iteration number q, where q = floor(k / 4). The timing of Turbo decoding of external information is k = 0, 1, ..., N-1, where N is the interleaving depth. The group index of the deinterleaving unit is i = 0, 1, 2, 3. When k++ is processed, i++. If i equals 4, i is assigned the value 0. Therefore, i adopts a counting method with a loop length of 4.

8. The interleaving and deinterleaving method for 4G 802.16m protocol Turbo decoding as described in claim 1, characterized in that, In (3), the interleaving and deinterleaving relationships are used to process the interleaver and deinterleaver of Turbo iterative decoding, and the deinterleaving table and interleaving table of the component decoders are replaced, thus realizing an interleaving and deinterleaving scheme with sequential and random placement characteristics, wherein: For the external information output by the component decoder DEC2 in Turbo decoding, an interleaving table is used to implement deinterleaving: ； Where Intlv_Idx[i] q Let q be the interleaving index of the interleaving circuit with iteration number q, where q = floor(k / 4). The timing of Turbo decoding of external information is k = 0, 1, ..., N-1, where N is the interleaving depth. The group index of the interleaving circuit is i = 0, 1, 2, 3. When k++ is processed, i++. If i equals 4, i is assigned the value 0. Therefore, i adopts a counting method with a loop length of 4.

9. The interleaving and deinterleaving method for 4G 802.16m protocol Turbo decoding as described in claim 1, characterized in that, In (3), the replacement process is completed immediately for the sequentially output external information to achieve the effect of sequential take-and-place. The equivalent interleaving or deinterleaving delay only requires one processing time slot, which is independent of the interleaving depth.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the interleaving and deinterleaving method for Turbo decoding of the 4G 802.16m protocol as described in any one of claims 1-9.

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