OPC modeling method and OPC correction method

By designing test patterns with different pattern densities and fitting the relationship between pattern density and size difference, an OPC standard model was established and the OPC model was adjusted using a modulation function. This solved the problem that the influence of pattern density on OPC correction was not considered, improved the accuracy of OPC correction, and reduced the computational load.

CN119065192BActive Publication Date: 2025-10-28SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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Patent Information

Application Number
CN202411098822.8
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2024-08-12
Publication Date
2025-10-28
Estimated Expiration
2044-08-12

AI Technical Summary

Technical Problem

Existing OPC correction methods fail to effectively consider the impact of pattern density on pattern accuracy, resulting in the inability to meet OPC accuracy requirements when the lithography process approaches its resolution limit. Furthermore, using pattern density as a calculation variable in the OPC model leads to an exponential increase in computational complexity.

Method used

Design multiple test patterns with different pattern densities, transfer them onto wafers using photolithography to form wafer test patterns, compare the size difference, fit the relationship between pattern density and size difference, establish an OPC standard model, and adjust the OPC model using a pattern density-related modulation function to reflect the influence of pattern density.

Benefits of technology

It improves the accuracy of OPC correction, reduces computational load, lowers modeling difficulty, and ensures that OPC accuracy requirements are met when the lithography process approaches its resolution limit.

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Abstract

This invention discloses an OPC modeling method comprising the following steps: designing two or more layout test patterns with different pattern densities; transferring each set of layout test patterns onto a wafer to form a wafer test pattern; comparing the size difference between the wafer test pattern and the layout test pattern at each pattern density; selecting one of the layout test patterns as the layout standard test pattern based on each size difference, and using the size difference corresponding to the layout standard test pattern as the standard size difference; establishing an OPC standard model using the standard size difference; fitting a modulation function related to the pattern density using the size difference deviation between the size difference at each pattern density and the standard size difference; and multiplying the modulation function at each pattern density with the OPC standard model to obtain the corresponding OPC modulation model. This invention also discloses an OPC correction method. This invention can reflect the actual impact of pattern density on pattern accuracy, thereby improving the accuracy of OPC correction, reducing computational load, and lowering modeling difficulty.
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Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an OPC modeling method. This invention also relates to an OPC correction method. Background Technology

[0002] Current OPC corrections do not consider the impact of pattern density; neither the corrected model nor the recipe reflects the actual effect of pattern density on pattern accuracy. Because neither the model nor the recipe considers pattern density, existing methods do not require pattern density in the data collected during modeling. However, when lithography processes approach their resolution limits, the impact of pattern density, especially local pattern density, cannot be ignored.

[0003] like Figure 1 The image shown is a layout pattern of an existing metal layer; Figure 1 The figures 101a, 101b, 101c, 101d, and 101e are the same figures, but they are in different positions, namely P1, P2, P3, P4, and P5, respectively.

[0004] Figure 1 It also includes large graphic blocks 102, such as large graphic block 102 being a graphic of the MIM capacitor region. Figure 1 The MIM capacitor area is also represented by the Large MIM area.

[0005] It can be seen that the spacing between P1, P2, P3, P4 and P5 and the large block 102 becomes larger and larger, which will make the density of graphics 101a, 101b, 101c, 101d and 101e different.

[0006] As commonly understood, patterns 101a, 101b, 101c, 101d, and 101e are the same pattern, and therefore, after being transferred to the wafer through photolithography, the wafer pattern should also be identical. However, in reality, the wafer patterns corresponding to patterns 101a, 101b, 101c, 101d, and 101e are not identical; rather, they are affected by the pattern density. For example... Figure 2 As shown, is Figure 1 The bar chart of DOF distribution with position for wafer patterns corresponding to 5 identical layout patterns, and the curve of critical dimension distribution with position; Figure 2 In the diagram, the horizontal axis represents the position, the vertical axis on the left represents the DOF (Domain of Dimension), and the vertical axis on the right represents the critical dimension. Figure 2 The chart displays two bar charts and two curves, where:

[0007] The bar chart corresponding to mark 201 is a DOF bar chart of the DARC layer pattern of the wafer pattern, using the left vertical axis; it can be seen that the DOF bar size of the DARC layer pattern is not consistent at different locations.

[0008] The bar chart corresponding to mark 202 is a DOF bar chart of the BARC layer pattern of the wafer pattern, using the left vertical axis; it can be seen that the DOF bar size of the BARC layer pattern is not consistent at different locations.

[0009] The curve corresponding to mark 203 is the critical dimension curve of the DARC layer pattern of the wafer pattern, using the right vertical axis; it can be seen that the critical dimension of the DARC layer pattern is not consistent at different locations.

[0010] The curve corresponding to marker 204 is the critical dimension curve of the BARC layer pattern of the wafer pattern, expressed on the right-hand vertical axis. It can be seen that the critical dimension of the BARC layer pattern is not consistent at different locations.

[0011] It can be seen that the parameters change accordingly with the change in pattern density. If this change related to pattern density is ignored in OPC correction, the OPC accuracy requirements will inevitably be unmet when the photolithography process approaches its resolution limit. Therefore, it is necessary to consider the influence of pattern density in OPC correction. For example, the applicant previously disclosed an OPC correction method based on pattern density in publication number CN115598922A.

[0012] However, existing OPC correction methods based on graph density require incorporating graph density as a dimension into the OPC model for calculation, which leads to an exponential increase in computational cost. This is further explained below:

[0013] The OPC algorithm posits that the mask pattern of a layout is transformed into a photoresist-simulated pattern through the cross-transfer matrix (TCC) of the OPC model. The TCC mathematically represents the deformation of the original mask pattern caused by optical diffraction, chemical diffusion, and development processes.

[0014] The OPC modeling method involves designing test patterns corresponding to numerous photomask patterns used in the product. These test patterns are then transferred onto a wafer using photolithography to form the actual photoresist pattern. Next, the actual photoresist pattern is measured, and the dimensional differences between the test pattern and the actual photoresist pattern, such as the critical dimension (CD), are obtained. These dimensional differences, along with optical system parameters, are then used to calculate the critical dimension (TCC). This establishes a mathematical model based on the TCC, predicting a simulated photoresist pattern that matches the actual photoresist pattern. This calculation typically cannot be solved analytically; instead, a numerical solution is obtained using a computer to determine all components of the TCC and minimize the root mean square difference and maximum (size difference) of all dimensional differences. Optical system parameters include dozens of process-related parameters such as D (dose), NA (numerical aperture), σ (coherence coefficient), L (diffusion length), and Eth (reaction threshold energy).

[0015] like Figure 3 The diagram shown is a schematic of layout graphic transformation using the cross-transfer matrix of the existing OPC model. Figure 3 The diagram shows the relationship between the changes and formula (1). If M(x,y) represents the structure of the test pattern or photomask pattern 301, and M'(x,y) represents the structure of the photoresist simulation pattern 303, then the OPC model 302 between the two has the transformation formula in TCC:

[0016] M'(x,y)=TCC*M(x,y) (1).

[0017] The TCC transfer matrix includes at least the following components: optical imaging (4F imaging system Fourier transform / Abel transform / Hopkins transform); photoacid generation (PAG); chemical diffusion (Gaussian equivalent diffusion); chemical threshold reaction (LPM Model...).

[0018] If we directly introduce graph density into the TCC transfer matrix and add graph density variables to M(x,y) and M'(x,y), then M(x,y) and M'(x,y) become M(x,y,η) and M'(x,y,η) respectively. This will cause the TCC matrix to change from two dimensions to three dimensions, and the computational cost of OPC modeling will increase exponentially. η represents graph density. Formula (1) will then become:

[0019] M' (x, y, η)=TCC*M (x, y, η) (2).

[0020] The theoretical basis for decomposing TCC into a product of optical and chemical components is the Abel approximation and the Hopkins approximation, as well as the Hermitian symmetry and conjugate preservation of the multiplication of the Gaussian function and the TCC optical matrix. Once a function related to the graph density is introduced, it is necessary to find a functional form that satisfies all the above approximation conditions, which is currently very difficult mathematically. Summary of the Invention

[0021] The technical problem to be solved by this invention is to provide an OPC modeling method that can reflect the actual impact of graphic density on graphic accuracy, thereby improving the accuracy of OPC correction and reducing computational load and modeling difficulty. To this end, this invention also provides an OPC correction method.

[0022] To solve the above-mentioned technical problems, the OPC modeling method provided by this invention includes the following steps:

[0023] Design two or more test layout patterns with different pattern densities.

[0024] The aforementioned layout test patterns are transferred onto the wafer to form wafer test patterns.

[0025] Compare the dimensional differences between the wafer test pattern and the layout test pattern at each of the specified pattern densities.

[0026] Based on the size difference of each of the graphic densities, one of the graphic test graphics is selected as the standard test graphic, and the size difference corresponding to the standard test graphic is taken as the standard size difference.

[0027] The standard size difference is used to establish the OPC standard model corresponding to the layout test pattern.

[0028] A modulation function related to the pattern density is obtained by fitting the size difference deviation between the size difference and the standard size difference under each pattern density.

[0029] The modulation function for each of the aforementioned pattern densities is multiplied by the OPC standard model to obtain the OPC modulation model for the corresponding pattern density.

[0030] A further improvement is that the structures of each of the layout test patterns are identical, and the pattern density of each of the layout test patterns is defined by layout redundancy test patterns placed around the corresponding layout test pattern. The layout test pattern and the corresponding layout redundancy test pattern form a layout test pattern group.

[0031] A further improvement is that the step of adjusting the graphic density of the layout test graphic includes:

[0032] Each of the aforementioned layout test patterns uses a corresponding redundant test pattern.

[0033] In each of the layout test pattern groups, the layout test pattern and the corresponding redundant test pattern are arranged in one dimension.

[0034] The pattern density of the corresponding layout test pattern is adjusted by adjusting the spacing between each of the layout test patterns and the corresponding redundant test patterns.

[0035] A further improvement is that the step of adjusting the graphic density of the layout test graphic includes:

[0036] A two-dimensional redundant test pattern setting area is set around each of the aforementioned test patterns.

[0037] The redundant test patterns corresponding to each of the layout test patterns include multiple ones and are set in the redundant test pattern setting area. The pattern density of the corresponding layout test pattern is adjusted by adjusting the area of ​​the redundant test patterns set in the redundant test pattern setting area.

[0038] A further improvement is that the step of selecting the standard test pattern for the layout includes:

[0039] After obtaining the size difference corresponding to each of the graphic densities, a relationship curve or fitting function between the graphic density and the size difference is formed by fitting.

[0040] In the relationship curve or by taking the derivative or differential of the fitting function, one or more sets of graphic densities are obtained as selected graphic densities, and each of the selected graphic densities meets the first requirement and the second requirement.

[0041] The first requirement is that the size difference of the selected graphic density meets the modeling accuracy requirements of the OPC standard model.

[0042] The second requirement is met when the change in the size difference between each selected graphic density and the adjacent graphic densities is gradual, and the gradual change is obtained by the curvature of the relationship curve or by the derivative or differential value of the fitting function.

[0043] Among the selected graphic densities obtained, one of the layout test graphics corresponding to the selected graphic density is selected as the layout standard test graphic.

[0044] A further improvement is that the parameters of the modulation function include a series of multiple process parameters, and the expression of the modulation function is different when the pattern density is different.

[0045] A further improvement is that the expression for the modulation function is the sum of all the process parameter terms, and each of the process parameter terms is expressed by the formula: Bi*Pi di .

[0046] Wherein, P represents the process parameter, B represents the fitting constant, d represents the exponential fitting value; i represents the number of the process parameter, Pi represents the i-th process parameter, Bi represents the i-th fitting constant, and di represents the i-th exponential fitting value.

[0047] A further improvement is that the process parameters include NA, Dose, Focus, σ, EL, and η.

[0048] NA represents numerical aperture, Dose represents exposure dose, Focus represents focal plane position, σ represents spatial coherence coefficient, EL represents exposure process latitude, and η represents the pattern density.

[0049] A further improvement is that the fitting step of the modulation function includes:

[0050] Adjust the values ​​of B and d for each of the aforementioned process parameters so that the root mean square error and the absolute value of the second size difference between the simulated and actual values ​​of the test pattern with the selected pattern density are both less than the OPC accuracy.

[0051] A further improvement is that, in the fitting step of the modulation function, the optimal solutions for B and d of each of the process parameter terms are obtained by conforming to the least squares method.

[0052] A further improvement is that the OPC accuracy is 1% to 5% of the minimum critical size of the corresponding graphics layer.

[0053] A further improvement is that the OPC standard model includes OPC model A with a standard cross-transmission matrix.

[0054] The OPC modulation model has a modulation cross-transmission matrix, which is obtained by multiplying the modulation function and the standard cross-transmission matrix.

[0055] To solve the above-mentioned technical problems, the OPC correction method provided by the present invention includes the following steps:

[0056] The OPC modulation model corresponding to each of the aforementioned graphic densities is formed using the OPC modeling method.

[0057] Query the graphic density of the target layout graphic to be corrected, and select the corresponding OPC modulation model based on the graphic density of the target layout graphic.

[0058] The target layout pattern is modified by using the selected OPC modulation model to obtain the modified target layout pattern.

[0059] A further improvement is that the step of querying the graphic density of the target layout graphic to be corrected includes:

[0060] The setting includes the scanning area of ​​the target layout graphic.

[0061] The target layout graphic density is obtained by performing graphic scanning on the scanned area.

[0062] The OPC modulation model obtained by this invention reflects the actual impact of pattern density on pattern accuracy. Therefore, this invention can reflect the actual impact of pattern density on pattern accuracy, thereby improving the accuracy of OPC correction.

[0063] The OPC modulation model of this invention is obtained by multiplying the modulation function related to the graph density with the standard OPC model. The standard OPC model itself does not need to be related to the graph density. Therefore, the computational workload related to the graph density is only the calculation of the modulation function. It is not necessary to use the graph density as a computational variable in the standard OPC model. However, if the graph density is used as a computational variable in the standard OPC model, the computational workload of OPC modeling will inevitably increase exponentially. Therefore, this invention can reduce the computational workload and reduce the modeling difficulty. Attached Figure Description

[0064] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0065] Figure 1 It is a layout pattern of an existing metal layer;

[0066] Figure 2 yes Figure 1 The bar chart of DOF distribution with position for wafer patterns corresponding to 5 identical layout patterns, and the curve of critical dimension distribution with position;

[0067] Figure 3 This is a schematic diagram of layout graphic transformation using the cross-transfer matrix of the existing OPC model;

[0068] Figure 4 This is a flowchart of the OPC modeling method according to an embodiment of the present invention;

[0069] Figure 5 This is a schematic diagram of a layout test pattern with different pattern densities in the OPC modeling method of this invention.

[0070] Figure 6 This is a schematic diagram of another layout test pattern with different pattern densities in the OPC modeling method of this invention;

[0071] Figure 7 yes Figure 5 The bar charts of DOF distribution with position and the curves of critical dimension distribution with position for wafer test patterns corresponding to 5 identical layout test patterns. Detailed Implementation

[0072] like Figure 4 The diagram shows a flowchart of the OPC modeling method according to an embodiment of the present invention; the OPC modeling method according to an embodiment of the present invention includes the following steps:

[0073] Step S101: Design two or more test layout patterns with different pattern densities.

[0074] In this embodiment of the invention, the layout test patterns have the same structure, but different pattern densities. The pattern density of each layout test pattern is defined by redundant layout test patterns placed around it. The layout test patterns and their corresponding redundant test patterns form a layout test pattern group. Any existing method capable of adjusting the pattern density can be used to set the layout test patterns in this embodiment of the invention.

[0075] In some implementation methods, such as Figure 5 The diagram shown is a schematic of a layout test pattern with different pattern densities in the OPC modeling method of this invention; a step of adjusting the pattern density of the layout test pattern includes:

[0076] Each of the aforementioned layout test patterns uses a corresponding redundant test pattern 402. Figure 5 The diagram displays five layout test patterns, labeled 401a, 401b, 401c, 401d, and 401e, respectively. The layout test patterns corresponding to labels 401a, 401b, 401c, 401d, and 401e are sequentially combined with the redundant test pattern 402.

[0077] In each of the layout test pattern groups, the layout test pattern and the corresponding redundant test pattern are arranged in a one-dimensional arrangement. In some embodiments, each layout test pattern can also share the redundant test pattern, so that each layout test pattern and the redundant test pattern together form a one-dimensional arrangement structure. Figure 5As shown, the layout test patterns and the redundant test patterns 402 corresponding to labels 401a, 401b, 401c, 401d, and 401e are arranged in one dimension. In some embodiments, the layout test pattern groups can also be set separately, so that the layout test patterns and the corresponding redundant test patterns in each layout test pattern group are arranged on different one-dimensional straight lines.

[0078] The pattern density of the corresponding layout test pattern is adjusted by adjusting the spacing between each of the layout test patterns and the corresponding redundant test patterns. Figure 5 As shown, the spacing between the layout test patterns and the redundant test pattern 402 corresponding to the marks 401a, 401b, 401c, 401d and 401e is different, which makes the pattern density of the layout test patterns corresponding to the marks 401a, 401b, 401c, 401d and 401e different, thereby enabling the adjustment and definition of the pattern density of the layout test patterns.

[0079] In some implementation methods, such as Figure 6 The diagram shown is a schematic of another layout test pattern with different pattern densities in the OPC modeling method of this invention; another step of adjusting the pattern density of the layout test pattern includes:

[0080] A two-dimensional redundant test pattern setting area is set around each of the aforementioned test patterns. Figure 6 The diagram displays three test patterns, labeled 401f, 401g, and 401h, respectively. The redundant test pattern setting areas corresponding to labels 401f, 401g, and 401h are labeled 403a, 403b, and 403c, respectively.

[0081] The redundant test patterns corresponding to each of the layout test patterns include multiple ones and are set in the redundant test pattern setting area. The pattern density of the corresponding layout test pattern is adjusted by adjusting the area of ​​the redundant test patterns set in the redundant test pattern setting area. Figure 6 The redundant test pattern is not displayed in the diagram. The redundant test pattern is set in the corresponding redundant test pattern setting area, so that the pattern density of the corresponding layout test pattern can be adjusted.

[0082] Step S102: Transfer each of the layout test patterns onto the wafer to form a wafer test pattern.

[0083] The wafer test pattern is formed by transferring the various layout test patterns onto the wafer through a photolithography process. The wafer test pattern is usually a photoresist pattern, and when a DARC layer or a BARC layer is used, it also includes a DARC layer pattern or a BARC layer pattern.

[0084] Step S103: Compare the size difference between the wafer test pattern and the layout test pattern at each of the specified pattern densities.

[0085] In some embodiments, the size difference is typically the size difference between the critical dimension of the wafer test pattern and the critical dimension of the layout test pattern.

[0086] When OPC correction is not performed, and the critical dimensions of the layout test patterns are the same, different pattern densities will result in different critical dimensions of the wafer test patterns.

[0087] like Figure 7 As shown, is Figure 5 The bar charts of DOF distribution with position and the curves of critical dimension distribution with position for wafer test patterns corresponding to 5 identical layout test patterns. Figure 5 In the diagram, the positions of the test patterns corresponding to 401a, 401b, 401c, 401d and 401e are marked with P1, P2, P3, P4 and P5 respectively; Figure 7 In the diagram, the horizontal axis represents the position, the vertical axis on the left represents the DOF (Domain of Dimension), and the vertical axis on the right represents the critical dimension.

[0088] Figure 7 The chart displays two bar charts and two curves, where:

[0089] The bar chart corresponding to mark 501 is a DOF bar chart of the DARC layer pattern of the wafer test pattern, using the left vertical axis;

[0090] The bar chart corresponding to mark 502 is a DOF bar chart of the BARC layer pattern of the wafer test pattern, using the left vertical axis;

[0091] The curve corresponding to mark 503 is the critical dimension curve of the DARC layer pattern of the wafer test pattern, using the right vertical axis;

[0092] The curve corresponding to marker 504 is the critical dimension curve of the BARC layer pattern of the wafer test pattern, using the right-hand vertical axis.

[0093] As can be seen, the parameters change accordingly with the change in pattern density. If this change related to pattern density is ignored in OPC correction, it will inevitably fail to meet OPC accuracy requirements when the photolithography process approaches its resolution limit.

[0094] Step S104: Select one of the layout test patterns as the layout standard test pattern from among the layout test patterns according to the size difference of each of the pattern densities, and take the size difference corresponding to the layout standard test pattern as the standard size difference.

[0095] In some embodiments, the step of selecting the layout standard test pattern includes:

[0096] After obtaining the size difference corresponding to each of the graphic densities, a relationship curve between the graphic density and the size difference is fitted.

[0097] The relationship curve yields a set of above-mentioned graphic densities as selected graphic densities, and each of the selected graphic densities meets the first requirement and the second requirement.

[0098] The first requirement is that the size difference of the selected graphic density meets the modeling accuracy requirements of the OPC standard model.

[0099] The second requirement is that the change in the size difference between each selected graphic density and its adjacent graphic densities is gradual, and this gradual change is determined by the curvature of the relationship curve. Those skilled in the art have specified that the smaller the curvature of the relationship curve, the more gradual the change in the size difference at the corresponding position. Therefore, the curvature of the relationship curve can be used to determine whether the change in the size difference between each selected graphic density and its adjacent graphic densities is gradual, and based on the calculated curvature, the desired gradually changing graphic density can ultimately be selected.

[0100] Among the selected graphic densities obtained, one of the layout test graphics corresponding to the selected graphic density is selected as the layout standard test graphic.

[0101] In some embodiments, the step of selecting the layout standard test pattern may also include:

[0102] After obtaining the size difference corresponding to each of the graphic densities, a fitting function is formed for the graphic density and the size difference.

[0103] By taking the derivative or differential of the fitting function, one or more sets of graphic densities are obtained as selected graphic densities, and each selected graphic density meets the first requirement and the second requirement.

[0104] The first requirement is that the size difference of the selected graphic density meets the modeling accuracy requirements of the OPC standard model.

[0105] The second requirement is that the change in the size difference between each selected graphic density and its adjacent graphic densities is gradual, and this gradual change is obtained by taking the derivative or differential value of the fitting function. The derivative of the fitting function corresponds to the curvature of the relationship curve described above, so the desired gradually changing graphic density can also be selected by taking the derivative or differential value of the fitting function.

[0106] Among the selected graphic densities obtained, one of the layout test graphics corresponding to the selected graphic density is selected as the layout standard test graphic.

[0107] The following combination Figure 7 Further explanation of the selected graphic density:

[0108] Since the position and the density of the graphic are in one-to-one correspondence Figure 7 The graph density is divided into four range regions: η1, η2, η3, and η4. The relationship curve or fitting function can be obtained by combining η1, η2, η3, and η4 with curve 503 or 504.

[0109] from Figure 7 It can be seen that within the range of η4, the values ​​of the critical dimensions corresponding to curves 503 and 504 are relatively stable, and the changes between the size differences corresponding to adjacent positions are gradual. Therefore, the size differences of each graphic density within the range of η4 are small, thus meeting the modeling accuracy requirements of the OPC standard model. The range of η4 includes two layout test graphics at positions P4 and P5. Therefore, the graphic densities corresponding to the two layout test graphics at positions P4 and P5 can be set as the selected graphic densities. Then, one or two of the selected graphic densities can be selected as the layout standard test graphics. For example, in some embodiments, the layout test graphics at position P4 are selected as the layout standard test graphics, and the size differences corresponding to the layout test graphics at position P4 are all the standard size differences. In some embodiments, the layout test graphics at position P5 can also be selected as the layout standard test graphics, and the size differences corresponding to the layout test graphics at position P5 are the standard size differences. In some embodiments, the layout test patterns at positions P4 and P5 can be selected together as the layout standard test patterns. In this case, the average value of the size difference corresponding to the layout test patterns at positions P4 and P5 is used as the standard size difference.

[0110] Step S105: Establish the OPC standard model corresponding to the layout test graphic using the standard size difference.

[0111] In this embodiment of the invention, the OPC standard model includes OPC model A with a standard cross-transmission matrix, and the standard cross-transmission matrix is ​​represented by TCC.

[0112] In this embodiment of the invention, the modeling method for the OPC standard model using the standard size difference is the same as the existing modeling method when not considering graphic density. Therefore, in this embodiment of the invention, the computational load of modeling the OPC standard model, especially TCC, is exactly the same as that of existing methods, and no additional computational load is added.

[0113] Step S106: Use the size difference deviation between the size difference and the standard size difference under each of the pattern densities to fit a modulation function related to the pattern density.

[0114] In this embodiment of the invention, the parameters of the modulation function include a series of multiple process parameters, and the expression of the modulation function is different when the pattern density is different.

[0115] The modulation function is expressed as the sum of all the process parameter terms, and each of the process parameter terms is expressed by the formula: Bi*Pi di .

[0116] Wherein, P represents the process parameter, B represents the fitting constant, d represents the exponential fitting value; i represents the number of the process parameter, Pi represents the i-th process parameter, Bi represents the i-th fitting constant, and di represents the i-th exponential fitting value.

[0117] In some embodiments, the process parameters include NA, Dose, Focus, σ, EL, and η;

[0118] NA represents numerical aperture, Dose represents exposure dose, Focus represents focal plane position, σ represents spatial coherence coefficient, EL represents exposure process latitude, and η represents the pattern density.

[0119] The expression for the modulation function is given by the formula:

[0120]

[0121]

[0122] In formula (3), f(η) represents the modulation function;

[0123] The expression of the modulation function is not fixed, but varies with the density of the pattern. In formula (3), C1, C2 to Cn represent the expressions corresponding to the range of n patterns.

[0124] The ranges of the n graphic densities are: 0 < η < η1, η1 < η < η2, up to ηn < η < 100, where 0 represents the minimum value of the graphic density (0%) and 100 represents the maximum value of the graphic density (100%).

[0125] In formula (4), Ck is an expression among C1, C2 to Cn, 1≤k≤n; k and n correspond to the numbering of the range of the described graphic densities.

[0126] f(NA, σ, Dose, EL......η) also represents the Ck expression, with the process parameters shown in parentheses; ∑Bi*Pi di This indicates the sum of all the process parameters mentioned.

[0127] As can be seen from formula (4), the modulation function is the same within the same range of the k-th pattern density, i.e., Ck is used; the modulation function is different between different ranges of pattern densities, mainly reflected in the different corresponding B and d. The B and d corresponding to each process parameter P of the range of pattern density are obtained by fitting.

[0128] The fitting steps for the modulation function include:

[0129] Adjust the values ​​of B and d for each of the aforementioned process parameters so that the root mean square error and the absolute value of the second size difference between the simulated and actual values ​​of the test pattern with the selected pattern density are both less than the OPC accuracy.

[0130] In some embodiments, the OPC accuracy is 1% to 5% of the minimum critical dimension of the corresponding pattern layer. For example, at the 130nm node, the CD of the gate pattern is 130nm, requiring an OPC accuracy of less than 5nm; at the 55nm node, the CD of the gate pattern is 65nm, requiring an OPC accuracy of less than 3nm.

[0131] In some preferred embodiments, in the fitting step of the modulation function, the optimal solutions for B and d of each of the process parameter terms are obtained by conforming to the least squares method, that is, by minimizing the sum of the mean square errors.

[0132] Step S107: Multiply the modulation function under each of the graphic densities and the OPC standard model to obtain the corresponding OPC modulation model.

[0133] At this point, multiplying the modulation function by the TCC in the OPC standard model yields the modulation cross-transmission matrix in the OPC modulation model. The modulation cross-transmission matrix is ​​denoted by TCC', and the corresponding formula for multiplication is:

[0134] TCC'=f(η)*TCC (5).

[0135] In this embodiment of the invention, based on obtaining f(η), TCC, or TCC', OPC correction can be further performed. The OPC correction method in this embodiment of the invention includes the following steps:

[0136] The OPC modulation model corresponding to each of the aforementioned graphic densities is formed using the OPC modeling method; that is, TCC' is obtained.

[0137] The method involves querying the pattern density of the target layout pattern to be corrected, and selecting the corresponding OPC modulation model based on the pattern density of the target layout pattern. In some embodiments, the step of querying the pattern density of the target layout pattern to be corrected includes:

[0138] The scanning area includes the target layout graphic;

[0139] The target layout graphic is obtained by performing a graphic scan on the scanned area.

[0140] The target layout pattern is modified by using the selected OPC modulation model to obtain the modified target layout pattern.

[0141] The OPC modulation model obtained in this embodiment reflects the actual impact of pattern density on pattern accuracy. Therefore, this embodiment can reflect the actual impact of pattern density on pattern accuracy, thereby improving the accuracy of OPC correction.

[0142] In this embodiment of the invention, the OPC modulation model is obtained by multiplying the modulation function related to the graph density with the OPC standard model. The OPC standard model itself does not need to be related to the graph density. Therefore, the computational workload related to the graph density is only the calculation of the modulation function. It is not necessary to use the graph density as a computational variable in the OPC standard model. However, if the graph density is used as a computational variable in the OPC standard model, the computational workload of OPC modeling will inevitably increase exponentially. Therefore, this embodiment of the invention can reduce the computational workload and reduce the modeling difficulty.

[0143] Directly transforming the graphic density into a third dimension is not feasible. Therefore, in this embodiment of the invention, a modulation function f(η) related to the graphic density is used to modulate the TCC, combining the influence of the graphic density with the numerical solution, thus simplifying the calculation.

[0144] In the modeling process of this invention, test patterns with different pattern densities are used to measure the deviation value of OPC under different pattern densities, i.e., the size difference, and to establish the size difference deviation value under different pattern densities.

[0145] f(η) is fitted using the dimensional difference deviation value.

[0146] During OPC correction, the density of surrounding graphics is first queried, and then the correction is performed based on TCC' and OPC.

[0147] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. An OPC modeling method, characterized in that, Including the following steps: Design two or more test layout patterns with different pattern densities; The aforementioned layout test patterns are transferred onto the wafer to form wafer test patterns; Compare the dimensional differences between the wafer test pattern and the layout test pattern at each of the specified pattern densities; Based on the size difference of each of the pattern densities, one of the pattern test patterns is selected as the pattern standard test pattern, and the size difference corresponding to the pattern standard test pattern is taken as the standard size difference. The standard size difference is used to establish the OPC standard model corresponding to the layout test pattern; A modulation function related to the pattern density is obtained by fitting the size difference deviation between the size difference and the standard size difference under each pattern density; The modulation function for each of the aforementioned pattern densities is multiplied by the OPC standard model to obtain the OPC modulation model for the corresponding pattern density.

2. The OPC modeling method as described in claim 1, characterized in that: The layout test patterns have the same structure, and the pattern density of each layout test pattern is defined by the layout redundancy test patterns placed around the corresponding layout test pattern. The layout test pattern and the corresponding layout redundancy test pattern form a layout test pattern group.

3. The OPC modeling method as described in claim 2, characterized in that: The steps for adjusting the density of the test pattern in the layout include: Each of the aforementioned layout test patterns uses a corresponding redundant test pattern; In each of the layout test pattern groups, the layout test pattern and the corresponding redundant test pattern are arranged in one dimension. The pattern density of the corresponding layout test pattern is adjusted by adjusting the spacing between each of the layout test patterns and the corresponding redundant test patterns.

4. The OPC modeling method as described in claim 2, characterized in that: The steps for adjusting the density of the test pattern in the layout include: A two-dimensional redundant test pattern setting area is set around each of the aforementioned test patterns; The redundant test patterns corresponding to each of the layout test patterns include multiple ones and are set in the redundant test pattern setting area. The pattern density of the corresponding layout test pattern is adjusted by adjusting the area of ​​the redundant test patterns set in the redundant test pattern setting area.

5. The OPC modeling method as described in claim 2, characterized in that: The steps for selecting the standard test graphic of the layout include: After obtaining the size difference corresponding to each of the graphic densities, a relationship curve or fitting function between the graphic density and the size difference is formed by fitting. In the relationship curve or by taking the derivative or differential of the fitting function, one or more sets of graphic densities are obtained as selected graphic densities, and each of the selected graphic densities meets the first requirement and the second requirement; The first requirement is that the size difference of the selected graphic density meets the modeling accuracy requirements of the OPC standard model; The second requirement is met when the change in the size difference between each selected graphic density and the adjacent graphic densities is gradual, and the gradual change is obtained by the curvature of the relationship curve or by the derivative or differential value of the fitting function; Among the selected graphic densities obtained, one of the layout test graphics corresponding to the selected graphic density is selected as the layout standard test graphic.

6. The OPC modeling method as described in claim 1, characterized in that: The modulation function has a series of multiple process parameters, and the expression of the modulation function is different when the pattern density is different.

7. The OPC modeling method as described in claim 6, characterized in that: The modulation function is expressed as the sum of all the process parameter terms, and each of the process parameter terms is expressed by the formula: Bi*Pi di ; Wherein, P represents the process parameter, B represents the fitting constant, d represents the exponential fitting value; i represents the number of the process parameter, Pi represents the i-th process parameter, Bi represents the i-th fitting constant, and di represents the i-th exponential fitting value.

8. The OPC modeling method as described in claim 7, characterized in that: The process parameters include NA, Dose, Focus, σ, EL, and η; NA represents numerical aperture, Dose represents exposure dose, Focus represents focal plane position, σ represents spatial coherence coefficient, EL represents exposure process latitude, and η represents the pattern density.

9. The OPC modeling method as described in claim 7, characterized in that: The fitting steps for the modulation function include: Adjust the values ​​of B and d for each of the aforementioned process parameters so that the root mean square error and the absolute value of the second size difference between the simulated and actual values ​​of the test pattern with the selected pattern density are both less than the OPC accuracy.

10. The OPC modeling method as described in claim 9, characterized in that: In the fitting step of the modulation function, the optimal solutions for B and d of each process parameter are obtained by conforming to the least squares method.

11. The OPC modeling method as described in claim 9, characterized in that: The OPC accuracy is 1% to 5% of the minimum critical size of the corresponding graphics layer.

12. The OPC modeling method as described in claim 1, characterized in that: The OPC standard model includes OPC model A with a standard cross-transmission matrix; The OPC modulation model has a modulation cross-transmission matrix, which is obtained by multiplying the modulation function and the standard cross-transmission matrix.

13. An OPC correction method, characterized in that, Includes the following steps: The OPC modulation model corresponding to each of the said graphic densities is formed using the OPC modeling method described in any one of claims 1 to 12; Query the graphic density of the target layout graphic to be corrected, and select the corresponding OPC modulation model based on the graphic density of the target layout graphic; The target layout pattern is modified by using the selected OPC modulation model to obtain the modified target layout pattern.

14. The OPC correction method as described in claim 13, characterized in that: The steps for querying the graphic density of the target layout graphic to be corrected include: The scanning area includes the target layout graphic; The target layout graphic density is obtained by performing graphic scanning on the scanned area.

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