A system and method for designing integrated circuits based on register control

Abstract

The present application provides an integrated circuit design system and method based on register control. The integrated circuit includes a chip. A controlled module, an instruction execution module, an instruction storage module, an internal bus arbitration module and an external bus arbitration module are respectively arranged inside the chip. An external instruction storage module is arranged outside the chip. The external bus arbitration module is connected to the external instruction storage module through a first bus, the internal bus arbitration module is connected to the external bus arbitration module through a second bus, the internal bus arbitration module is connected to the instruction storage module through a third bus, the internal bus arbitration module is connected to the instruction execution module through a fourth bus, and the instruction execution module is connected to the controlled module through a fifth bus. At the same time, the controlled module and the external instruction storage module can also be directly accessed from outside the system through a seventh bus. The present invention can realize highly flexible integration for some reusable circuit modules, save R&D and verification costs, and can be applied to the design of various chips and IPs.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design, and in particular to an integrated circuit design system and method based on register control. Background Art

[0002] Integrated circuits, also known as microcircuits, microchips, and chips, are a way of miniaturizing circuits (mainly semiconductor devices, but also passive components, etc.) in electronics, and are usually manufactured on the surface of semiconductor wafers. Using a certain process, the transistors, resistors, capacitors, inductors and other components and wiring required in a circuit are interconnected and made on a small piece or several small pieces of semiconductor wafers or dielectric substrates, and then packaged in a tube shell to become a microstructure with the required circuit function; all the components have formed a whole in structure, making electronic components a big step towards miniaturization, low power consumption, intelligence and high reliability. Integrated circuits have the advantages of small size, light weight, few lead wires and welding points, long life, high reliability, good performance, etc., and low cost, which is convenient for large-scale production. It is not only widely used in industrial and civilian electronic equipment such as recorders, televisions, computers, etc., but also in military, communications, remote control, etc. The assembly density of electronic equipment assembled with integrated circuits can be increased by dozens to thousands of times compared with transistors, and the stable working time of the equipment can also be greatly improved.

[0003] In chip design, the design of circuit modules is usually applied in certain scenarios. During design, only a few parameters may be reserved for configuration by software. However, some circuit modules can be reused in multiple application scenarios or in a series of chips, such as some algorithm modules. However, different parameter configurations may be required in different application scenarios. If these reusable circuit modules are designed as configurable modules, they can be reused in other chips after tape-out verification. Only the configuration instructions need to be changed, which can greatly save R&D and verification costs. In addition, an external storage circuit is reserved. Even if some parameters are not configured ideally during tape-out, they can be updated after tape-out. This increases the flexibility of chip design and reduces tape-out risks. This method is implemented by hardware circuits, which has faster execution and response speeds than software methods. If such a design method is applied to IP design, the application flexibility of IP can be greatly increased. Therefore, a register-controlled integrated circuit design system is designed. Summary of the invention

[0004] The present application provides an integrated circuit design system and method based on register control to solve the problem of high integrated circuit cost in the prior art, and realizes highly flexible integration of some reusable circuit modules, saving R&D and verification costs.

[0005] The present application provides an integrated circuit design system based on register control, wherein the integrated circuit includes a chip;

[0006] The chip is internally provided with a controlled module, an instruction execution module, an instruction storage module, an internal bus arbitration module and an external bus arbitration module;

[0007] An external instruction storage module is arranged outside the chip;

[0008] The external bus arbitration module is connected to the external instruction storage module via the first bus, and the external instruction storage module is used to update the configuration instructions pre-stored in the internal storage module;

[0009] The internal bus arbitration module is connected to the external bus arbitration module via a second bus;

[0010] The internal bus arbitration module is connected to the instruction storage module via a third bus, and the instruction storage module stores instruction codes encoded according to a certain encoding logic;

[0011] The internal bus arbitration module is connected to the instruction execution module via a fourth bus;

[0012] The instruction execution module is connected to the controlled module via a fifth bus; the instruction execution module reads instructions from the instruction storage module and decodes the instructions according to a preset decoding logic;

[0013] The user accesses the external instruction storage module and the controlled module through the seventh bus.

[0014] Preferably, the present application provides an integrated circuit design system based on register control, wherein a functional circuit, a configuration circuit and an access bus arbitration circuit are arranged in the controlled module, the functional circuit is used to realize a specific circuit function, the configurable parameters of the functional circuit are all from the configuration circuit, the configuration circuit and the functional circuit are interconnected by hardware wiring, and the access bus arbitration circuit is connected to the configuration circuit.

[0015] Preferably, the present application provides an integrated circuit design system based on register control, wherein a plurality of registers with unique addresses are set in the configuration circuit, and the registers are accessed by the instruction execution module through the fifth bus, or accessed through the seventh bus through an external register configuration.

[0016] Preferably, the present application provides an integrated circuit design system based on register control, wherein the access bus arbitration circuit is used to process access requests of the seventh bus and the fifth bus, and convert the access request information into an address line reg_addr, a read enable signal rd_en, a write enable signal wr_en and write data wr_data for accessing the register module of the configuration circuit, and translates the rd_data read from the register into the standard format of the fifth bus and the seventh bus.

[0017] Preferably, the present application provides an integrated circuit design system based on register control, wherein the instruction execution module is implemented by a state machine, the state machine loads instructions from the instruction storage module, decodes the loaded instructions, and finally transmits the decoded instructions to the controlled module through the fifth bus.

[0018] Preferably, the present application provides an integrated circuit design system based on register control, wherein the instruction storage module uses a read-only memory, and the instruction storage module stores algorithm configuration instructions pre-compiled according to certain coding rules. After the circuit starts working, the instruction execution module reads instructions from the instruction storage module and decodes and executes them.

[0019] Preferably, the present application provides an integrated circuit design system based on register control, wherein the external instruction storage module uses a readable and writable memory. When in the debugging stage, the logic of the external instruction storage module is retained. When it is desired to modify the configuration instructions for the internal controlled module, the initial configuration instructions are first loaded from the internal instruction storage block through the sixth bus. After the loading is completed, the configuration instructions stored in the external instruction storage block are modified through the seventh bus, and the instruction execution module is notified to read instructions from the external instruction storage block.

[0020] Preferably, a method for using an integrated circuit design system based on register control comprises the following steps:

[0021] A. When the chip is powered on and exits from the reset state, and the enable signal fsm_en of the instruction execution module is 1, that is, after the instruction execution state machine is set, determine whether the external instruction storage module needs to be enabled;

[0022] B. Set the flag signal sram_bypass. When the sram_bypass signal is 0, it is considered that the external instruction storage module needs to be enabled. Otherwise, the external instruction storage module is disabled. If the external instruction storage module is disabled, the internal execution state machine of the instruction execution module starts to call the controlled module to implement the corresponding function by executing the configuration instructions in the internal storage module.

[0023] C. If the external instruction storage module is enabled, firstly, the initial configuration instructions stored in the internal storage block are loaded into the external instruction storage block from the internal instruction storage module through the sixth bus. After the loading is completed, the loading completion flag sram_ini_done signal is set to 1;

[0024] D. When the execution state machine detects that sram_ini_done is 1, it is allowed to modify the initial configuration instructions stored in the external instruction storage block through the seventh bus;

[0025] E. After the modification is completed, the flag sram_cha_done is set to 1 to indicate that the modification is completed. When the execution state machine detects that sram_cha_done is 1, it can start to call the controlled module to implement the corresponding function by executing the configuration instructions in the external storage module.

[0026] Beneficial effects: The design principle of the present invention is simple. The controlled module can be any circuit module that needs to be reused. The changeable parameters of these circuit modules are designed to adopt a register configuration mode. Each register defines an access address, and the instruction execution module continuously reads instructions from the instruction storage module and decodes the instructions according to the preset decoding logic, and then configures the functional circuit modules in the controlled module through the access interface. For some reusable circuit modules, highly flexible integration can be achieved, saving R&D and verification costs, and can be applied to the design of various chips and IPs.

[0027] The above description is only an overview of the technical solution of the embodiment of the present application. In order to more clearly understand the technical means of the embodiment of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiment of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present application, a brief introduction will be given below to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 This is a block diagram of the system principle of the present invention;

[0030] Figure 2 This is a structural block diagram of a controlled module of the present invention;

[0031] Figure 3 It is a schematic diagram of the jump of the instruction execution state machine of the present invention;

[0032] Figure 4 It is the work flow chart of the present invention;

[0033] In the figure: chip 1, controlled module 2, instruction execution module 3, instruction storage module 4, internal bus arbitration module 5, external bus arbitration module 6, external instruction storage module 7, functional circuit 8, configuration circuit 9, access bus arbitration circuit 10. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used in the specification of the application are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification, claims and drawings of this application are intended to cover non-exclusive inclusions.

[0036] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiments" in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0037] In addition, the terms "first", "second", etc. in the specification and claims of this application or the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0038] In the description of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, the "connection" or "connection" of a mechanical structure may refer to a physical connection. For example, the physical connection may be a fixed connection, such as a fixed connection through a fixing member, such as a fixed connection through a screw, bolt or other fixing member; the physical connection may also be a detachable connection, such as a mutual snap-on or snap-fit ​​connection; the physical connection may also be an integral connection, such as a connection formed by welding, bonding or integral molding. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0039] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0040] See also Figure 1-Figure 4 , the present application discloses an integrated circuit design system based on register control, the integrated circuit comprising a chip 1;

[0041] The chip 1 is internally provided with a controlled module 2, an instruction execution module 3, an instruction storage module 4, an internal bus arbitration module 5 and an external bus arbitration module 6;

[0042] An external instruction storage module 7 is arranged outside the chip 1;

[0043] The external bus arbitration module 6 is connected to the external instruction storage module 7 via the first bus, and the external instruction storage module 7 is used to update the configuration instructions pre-stored in the internal storage module;

[0044] The internal bus arbitration module 5 is connected to the external bus arbitration module 6 via a second bus;

[0045] The internal bus arbitration module 5 is connected to the instruction storage module 4 via the third bus, and the instruction storage module 4 stores instruction codes encoded according to a certain encoding logic;

[0046] The internal bus arbitration module 5 is connected to the instruction execution module 3 via the fourth bus;

[0047] The instruction execution module 3 is connected to the controlled module 2 via a fifth bus; the instruction execution module reads instructions from the instruction storage module and decodes the instructions according to a preset decoding logic;

[0048] The user accesses the external instruction storage module 7 and the controlled module 2 through the seventh bus.

[0049] The controlled module in the present invention can be any circuit module that needs to be reused. The changeable parameters of these circuit modules are designed to adopt a register configuration mode. Each register defines an access address, and the instruction execution module continuously reads instructions from the instruction storage module and decodes the instructions according to the preset decoding logic, and then configures the functional circuit module in the controlled module through the access interface. The instruction storage module stores instruction codes encoded according to a certain encoding logic. The external instruction storage module is used to update the configuration instructions pre-stored in the internal storage module. The external instruction storage module is an optional circuit. When the algorithm solution is immature or the application scenario is not fixed, this logic can be retained to update the internal execution instructions. After the solution is mature, this memory can be removed to reduce costs.

[0050] Among them, a function circuit 8, a configuration circuit 9 and an access bus arbitration circuit 10 are set in the controlled module 2, the function circuit 8 is used to realize a specific circuit function, the configurable parameters of the function circuit 8 are all from the configuration circuit 9, the configuration circuit 9 and the function circuit 8 are interconnected by hardware wiring, and the access bus arbitration circuit 10 is connected to the configuration circuit 9; a plurality of registers with unique addresses are set in the configuration circuit 9, and the registers are accessed by the instruction execution module through the fifth bus, or accessed by configuring the seventh bus through an external register. Since the present invention does not define the type of the first bus-the seventh bus, the first bus-the seventh bus can be a bus of any standard protocol or a custom bus, the access bus arbitration circuit 10 is used to process the access request of the seventh bus and the fifth bus, and convert the access request information into the address line reg_addr, the read enable signal rd_en, the write enable signal wr_en and the write data wr_data of the register module for accessing the configuration circuit, and translate the rd_data read from the register into the standard format of the fifth bus and the seventh bus.

[0051] In the present invention, the instruction execution module 3 is implemented by a state machine, and the state machine used to access the register mainly completes three functions: the state machine loads instructions from the instruction storage module, decodes the loaded instructions, and finally transmits the decoded instructions to the controlled module through the fifth bus. Figure 3 This is a most basic instruction execution module state machine jump diagram. In actual implementation, states can be added according to actual needs. For example, in some cases, it may be necessary to perform some calculations in this module and store the calculation results. In this case, some states for calculating and storing the calculation results can be added.

[0052] In the present invention, the instruction storage module 4 uses a read-only memory, which stores algorithm configuration instructions pre-compiled according to certain coding rules. These configuration instructions are defined according to different project requirements. After the circuit starts working, the instruction execution module reads instructions from the instruction storage module and decodes and executes them.

[0053] In the present invention, the external instruction storage module 7 adopts a readable and writable memory, which is an optional circuit. When in the debugging stage, the logic of the external instruction storage module is retained. When it is desired to modify the configuration instructions for the internal controlled module, the initial configuration instructions are first loaded from the internal instruction storage block through the sixth bus. After the loading is completed, the configuration instructions stored in the external instruction storage block are modified through the seventh bus, and the instruction execution module is notified to read the instructions from the external instruction storage block.

[0054] In the present invention, since both the external instruction storage and the registers inside the controlled module can be accessed through the seventh bus, when allocating addresses, these two memories should be allocated in different address segments.

[0055] Working principle: A method for using an integrated circuit design system based on register control, comprising the following steps:

[0056] A. When the chip is powered on and exits from the reset state, and the enable signal fsm_en of the instruction execution module is 1, that is, after the instruction execution state machine is set, determine whether the external instruction storage module needs to be enabled;

[0057] B. Set the flag signal sram_bypass. When the sram_bypass signal is 0, it is considered that the external instruction storage module needs to be enabled. Otherwise, the external instruction storage module is disabled. If the external instruction storage module is disabled, the internal execution state machine of the instruction execution module starts to call the controlled module to implement the corresponding function by executing the configuration instructions in the internal storage module.

[0058] C. If the external instruction storage module is enabled, firstly, the initial configuration instructions stored in the internal storage block are loaded into the external instruction storage block from the internal instruction storage module through the sixth bus. After the loading is completed, the loading completion flag sram_ini_done signal is set to 1;

[0059] D. When the execution state machine detects that sram_ini_done is 1, it is allowed to modify the initial configuration instructions stored in the external instruction storage block through the seventh bus;

[0060] E. After the modification is completed, the flag sram_cha_done is set to 1 to indicate that the modification is completed. When the execution state machine detects that sram_cha_done is 1, it can start to call the controlled module to implement the corresponding function by executing the configuration instructions in the external storage module.

[0061] To sum up, the design principle of the present invention is simple. The controlled module can be any circuit module that needs to be reused. The changeable parameters of these circuit modules are designed to adopt a register configuration mode. Each register defines an access address, and the instruction execution module continuously reads instructions from the instruction storage module and decodes the instructions according to the preset decoding logic, and then configures the functional circuit module in the controlled module through the access interface. For some reusable circuit modules, highly flexible integration can be achieved, saving R&D and verification costs, and can be applied to the design of various chips and IPs.

[0062] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. An integrated circuit design system based on register control, characterized in that: The integrated circuit design system comprises a chip (1); The chip (1) is internally provided with a controlled module (2), an instruction execution module (3), an instruction storage module (4), an internal bus arbitration module (5) and an external bus arbitration module (6); An external instruction storage module (7) is provided outside the chip (1); The external bus arbitration module (6) is connected to the external instruction storage module (7) via a first bus, and the external instruction storage module (7) is used to update the configuration instructions pre-stored in the internal storage module; The internal bus arbitration module (5) is connected to the external bus arbitration module (6) via a second bus; The internal bus arbitration module (5) is connected to the instruction storage module (4) via a third bus, and the instruction storage module (4) stores instruction codes encoded according to a certain encoding logic; The internal bus arbitration module (5) is connected to the instruction execution module (3) via a fourth bus; The instruction execution module (3) is connected to the controlled module (2) via a fifth bus; the instruction execution module reads instructions from the instruction storage module and decodes the instructions according to a preset decoding logic; The user accesses the external instruction storage module (7) and the controlled module (2) via the seventh bus; The controlled module (2) is provided with a functional circuit (8), a configuration circuit (9) and an access bus arbitration circuit (10); the functional circuit (8) is used to realize a specific circuit function; the configurable parameters of the functional circuit (8) are all from the configuration circuit (9); the configuration circuit (9) and the functional circuit (8) are interconnected by hardware wiring; and the access bus arbitration circuit (10) is connected to the configuration circuit (9); The configuration circuit (9) is provided with a plurality of registers with unique addresses, and the registers are accessed by the instruction execution module through the fifth bus, or are accessed through the seventh bus configured by an external register.

2. The integrated circuit design system based on register control according to claim 1, characterized in that: The access bus arbitration circuit (10) is used to process access requests of the seventh bus and the fifth bus, and convert the access request information into an address line reg_addr, a read enable signal rd_en, a write enable signal wr_en and write data wr_data for accessing a register module of the configuration circuit, and translate the rd_data read from the register into a standard format of the fifth bus and the seventh bus.

3. The integrated circuit design system based on register control according to claim 1, characterized in that: The instruction execution module (3) is implemented by a state machine, which loads instructions from the instruction storage module, decodes the loaded instructions, and finally transmits the decoded instructions to the controlled module via a fifth bus.

4. The integrated circuit design system based on register control according to claim 1, characterized in that: The instruction storage module (4) uses a read-only memory, and the instruction storage module stores algorithm configuration instructions pre-compiled according to certain coding rules. After the circuit starts working, the instruction execution module reads instructions from the instruction storage module and decodes and executes them.

5. The integrated circuit design system based on register control according to claim 1, characterized in that: The external instruction storage module (7) uses a readable and writable memory. When in the debugging stage, the logic of the external instruction storage module is retained. When it is desired to modify the configuration instructions for the internal controlled module, the initial configuration instructions are first loaded from the internal instruction storage block through the sixth bus via the external bus arbitration module through the first bus. After the loading is completed, the configuration instructions stored in the external instruction storage block are modified through the seventh bus, and the instruction execution module is notified to read the instructions from the external instruction storage block.

6. A method for using the register-controlled integrated circuit design system according to claim 1, characterized in that: The method of use includes the following steps: A. When the chip is powered on and exits from the reset state, and the enable signal fsm_en of the instruction execution module is 1, that is, after the instruction execution state machine is set, determine whether the external instruction storage module needs to be enabled; B. Set the flag signal sram_bypass. When the sram_bypass signal is 0, it is considered that the external instruction storage module needs to be enabled. Otherwise, the external instruction storage module is disabled. If the external instruction storage module is disabled, the internal execution state machine of the instruction execution module starts to call the controlled module to implement the corresponding function by executing the configuration instructions in the internal storage module. C. If the external instruction storage module is enabled, firstly, the initial configuration instructions stored in the internal storage block are loaded into the external instruction storage block from the internal instruction storage module through the sixth bus. After the loading is completed, the loading completion flag sram_ini_done signal is set to 1; D. When the execution state machine detects that sram_ini_done is 1, it is allowed to modify the initial configuration instructions stored in the external instruction storage block through the seventh bus; E. After the modification is completed, the flag sram_cha_done is set to 1 to indicate that the modification is completed. When the execution state machine detects that sram_cha_done is 1, it can start to call the controlled module to implement the corresponding function by executing the configuration instructions in the external storage module.

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