Display panel and electronic device

Abstract

The present application provides a display panel and electronic device, relating to the field of display technology. An auxiliary gate is provided on the side of the channel layer away from the gate dielectric layer, thereby improving the ability of the multiplexer to transmit data signals. The main gate and the auxiliary gate jointly control the flow of current in the channel, thereby improving the response speed of the selection transistor and reducing the threshold voltage of the selection transistor. This increases the current transmitted from the selection transistor to the data line and improves the charging effect of the data line on the pixel unit connected to it, ultimately achieving the purpose of optimizing the display effect of the display panel. In addition, the auxiliary gate can also act as an electrostatic shield, suppressing the problem of characteristic drift of the selection transistor due to static electricity.

Description

Technical Field

[0001] The present application relates to the field of display technology, and more specifically, to a display panel and an electronic device. Background Art

[0002] With the development of display technology, display panels have been applied in various fields. A display panel includes a display area and a non-display area. The display area includes multiple data lines, and the non-display area includes multiple multiplexers. The input port of the multiplexer is electrically connected to the data signal terminal, and the multiple output ports of the multiplexer are each connected to a data line. During the operation of the display panel, the multiplexer selects the data signal output from the data signal terminal and transmits it to one of the data lines to provide the data signal to the corresponding pixel unit via the data line. Therefore, the multiplexer's ability to transmit data signals directly affects the display effect of the display panel. Summary of the Invention

[0003] In view of this, the present application provides a display panel and an electronic device, which effectively solve the technical problems existing in the prior art, improve the ability of the multiplexer to transmit data signals, and improve the display effect of the display panel.

[0004] To achieve the above objectives, the technical solutions provided by this application are as follows:

[0005] A display panel includes a substrate and a plurality of multiplexers located on the substrate, the multiplexers including a plurality of selection transistors, wherein the source and drain of the selection transistors are electrically connected to a data signal terminal and a data line, respectively, and the selection transistors include: a channel layer located on the substrate, a gate dielectric layer located on one side of the channel layer, and a main gate located on a side of the gate dielectric layer away from the channel layer, the main gate receiving a selection control signal;

[0006] At least one of the channel layers includes an auxiliary gate on the side facing away from the gate dielectric layer, an auxiliary insulating layer is included between the auxiliary gate and the channel layer, the auxiliary gate and the orthographic projection of the channel layer on the substrate have at least a partially overlapping area, and the auxiliary gate is connected to a reference voltage.

[0007] Based on the same inventive concept, the present application also provides an electronic device, which includes the above-mentioned display panel.

[0008] Compared with the existing technology, the technical solution provided by this application has at least the following advantages:

[0009] The present application provides a display panel and an electronic device, wherein the display panel includes a substrate and a plurality of multiplexers located on the substrate, the multiplexers including a plurality of selection transistors, the source electrodes and the drain electrodes of the selection transistors being electrically connected to a data signal terminal and a data line, respectively, the selection transistors including: a channel layer located on the substrate, a gate dielectric layer located on one side of the channel layer, and a main gate located on a side of the gate dielectric layer facing away from the channel layer, the main gate being connected to a selection control signal; at least one of the channel layers including an auxiliary gate on a side facing away from the gate dielectric layer, an auxiliary insulating layer being included between the auxiliary gate and the channel layer, the auxiliary gate having an at least partially overlapping area with an orthographic projection of the channel layer on the substrate, and the auxiliary gate being connected to a reference voltage.

[0010] As can be seen from the above, the technical solution provided by this application, which provides an auxiliary gate on the side of the channel layer facing away from the gate dielectric layer, improves the multiplexer's ability to transmit data signals. The main gate and the auxiliary gate jointly control the flow of current in the channel, thereby improving the response speed of the selection transistor and reducing the threshold voltage of the selection transistor. This increases the current transmitted by the selection transistor to the data line, improving the charging effect of the data line on the pixel unit connected to it, and ultimately achieving the purpose of optimizing the display effect of the display panel. In addition, the auxiliary gate can also act as an electrostatic shield, suppressing the problem of characteristic drift of the selection transistor caused by static electricity. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0012] Figure 1 is a structural schematic diagram of a display panel;

[0013] Figure 2 A circuit diagram of a pixel driving circuit;

[0014] Figure 3 It is a timing diagram;

[0015] Figure 4 A schematic structural diagram of a display panel provided in an embodiment of the present application;

[0016] Figure 5 A schematic structural diagram of another display panel provided in an embodiment of the present application;

[0017] Figure 6 A schematic structural diagram of another display panel provided in an embodiment of the present application;

[0018] Figure 7 A schematic structural diagram of another display panel provided in an embodiment of the present application;

[0019] Figure 8 A schematic structural diagram of another display panel provided in an embodiment of the present application;

[0020] Figure 9 A schematic structural diagram of another display panel provided in an embodiment of the present application;

[0021] Figure 10 A schematic structural diagram of another display panel provided in an embodiment of the present application;

[0022] Figure 11 A schematic structural diagram of another display panel provided in an embodiment of the present application;

[0023] Figure 12 A schematic structural diagram of another display panel provided in an embodiment of the present application;

[0024] Figure 13 A schematic structural diagram of another display panel provided in an embodiment of the present application;

[0025] Figure 14 A schematic structural diagram of another display panel provided in an embodiment of the present application;

[0026] Figure 15 A schematic structural diagram of another display panel provided in an embodiment of the present application;

[0027] Figure 16 A schematic structural diagram of another display panel provided in an embodiment of the present application;

[0028] Figure 17 A schematic structural diagram of another display panel provided in an embodiment of the present application;

[0029] Figure 18 A schematic structural diagram of another display panel provided in an embodiment of the present application;

[0030] Figure 19 A schematic structural diagram of another display panel provided in an embodiment of the present application;

[0031] Figure 20 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0033] As described in the background technology, during the operation of the display panel, the multiplexer selects and transmits the data signal output from the data signal terminal to one of the data lines to which it is connected, so as to provide the data signal to the corresponding pixel unit through the data line. Therefore, the ability of the multiplexer to transmit data signals directly affects the display effect of the display panel. Figure 1 Figure 1 is a schematic diagram of the structure of a display panel. The display panel includes a plurality of pixel units arranged in an array along the row direction X and the column direction Y. Each pixel unit includes a pixel driving circuit 10 and a light-emitting element DL electrically connected to the pixel driving circuit 10. The pixel driving circuit 10 is electrically connected to a data line 20. The light-emitting element DL can be a light-emitting diode. When the display panel is in operation, the pixel units are scanned row by row. During the scanning process, a multiplexer selects and transmits data signals to corresponding data lines 20. The data lines 20 provide the pixel driving circuit 10 with data signals for charging.

[0034] Further integration Figure 2 and Figure 4 As shown, Figure 2 is a circuit diagram of a pixel driving circuit, Figure 3This is a timing diagram, in which a pixel driving circuit is described using the example of a pixel driving circuit in which all transistors are P-type transistors. The pixel driving circuit includes a driving transistor M0, a reset transistor M1, a data writing transistor M2, a threshold compensation transistor M3, a first emission control transistor M4, a second emission control transistor M5, and a storage capacitor C. The first terminal of the reset transistor M1 is connected to the reset signal Vref, the second terminal of the reset transistor M1 is electrically connected to the gate of the driving transistor M0, and the gate of the reset transistor M1 is connected to the reset control signal S1. The first terminal of the data writing transistor M2 is electrically connected to a data line and connected to the data signal Vdata, the second terminal of the data writing transistor M2 is electrically connected to the first terminal of the driving transistor M0, and the gate of the data writing transistor M2 is connected to the data writing control signal S2. The first terminal of the threshold compensation transistor M3 is electrically connected to the second terminal of the driving transistor M0, the second terminal of the threshold compensation transistor M3 is electrically connected to the gate of the driving transistor M0, and the gate of the threshold driving transistor M3 is connected to the threshold compensation control signal S3. A first terminal of the first emission control transistor M4 is connected to an anode voltage PVDD, a second terminal of the first emission control transistor M4 is electrically connected to a first terminal of the driving transistor M0, a first terminal of the second emission control transistor M5 is electrically connected to a second terminal of the driving transistor M0, a second terminal of the second emission control transistor M5 is electrically connected to an anode of the light-emitting element DL, gates of the first emission control transistor M4 and the second emission control transistor M5 are both connected to an emission control signal Emit, and a cathode of the light-emitting element DL is connected to a cathode voltage PVEE. Furthermore, a first terminal of the storage capacitor C is connected to an anode voltage PVDD, and a second terminal of the storage capacitor C is electrically connected to the gate of the driving transistor M0.

[0035] The data write transistor M2 is electrically connected to a data line and receives the data signal Vdata. The driving of the pixel driving circuit includes a reset phase T1, a compensation write phase T2, and a light-emitting phase T3, which are performed in sequence. In the reset phase T1, the reset transistor M1 is turned on in response to the low level control of the reset control signal S1, and the threshold compensation transistor M3 is turned on in response to the low level control of the threshold compensation control signal S3, so as to transmit the reset signal Vref to the gate of the driving transistor M0 and the second end of the driving transistor M0 for resetting. In the compensation write phase T2, the data write transistor M2 is turned on in response to the low level control of the data write control signal S2, and the threshold compensation transistor M3 is turned on in response to the low level control of the threshold compensation control signal S3. The data write transistor M2 transmits the data signal Vdata to the first end of the driving transistor M0. The data signal Vdata is then transmitted to the gate of the driving transistor M0 through the driving transistor M0 and the threshold compensation transistor M3 to charge the storage capacitor C. During the light-emitting phase T3, the first light-emitting control transistor M4 and the second light-emitting control transistor M5 are turned on in response to the low-level control of the light-emitting control signal Emit, transmitting the driving current generated by the driving transistor M0 to the light-emitting element DL, which is then illuminated in response to the driving current. It can be seen that the data signal Vdata has a significant impact on the illumination of the light-emitting element DL. Therefore, the ability of the multiplexer to transmit the data signal Vdata directly affects the display quality of the display panel. In particular, as the resolution of the display panel increases, the driver of the existing display panel usually compresses the pulse width time of the compensation writing phase T2, which correspondingly compresses the pulse width time of the data signal Vdata output by the multiplexer. If the multiplexer has a poor ability to transmit the data signal Vdata, the data line 20 cannot fully transmit the data signal Vdata to the pixel driving circuit 10, significantly affecting the charging effect of the data line 20 on the pixel driving circuit 10, further deteriorating the display quality of the display panel, such as the vertical stripes caused by the difference in the data signal transmission ability of different data lines 20.

[0036] It should be noted that the pixel driving circuit shown above is only a specific device composition and connection among all pixel driving circuits applicable to the display panel, and no specific restrictions are imposed on this. As long as the data signal connected to the pixel driving circuit is output by the multiplexer, the multiplexer's ability to transmit data signals affects the display effect of the display panel. Related technical issues.

[0037] Based on this, the embodiments of the present application provide a display panel and an electronic device, which effectively solve the technical problems existing in the prior art, improve the ability of the multiplexer to transmit data signals, and improve the display effect of the display panel.

[0038] To achieve the above purpose, the technical solutions provided in the embodiments of the present application are as follows, specifically combined with Figures 4 to 20 The technical solutions provided in the embodiments of the present application are described in more detail.

[0039] Combine Figure 4 and Figure 5 As shown, Figure 4 A schematic structural diagram of a display panel provided in an embodiment of the present application is shown in FIG. Figure 5 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present application, wherein: Figure 4 The line connection in the display panel is used as an example. Figure 5 The cross-sectional composition of the display panel is used for illustration. The display panel provided in the embodiment of the present application includes a substrate 100 and a data circuit located on the substrate 100. The data circuit includes a plurality of multiplexers 200, a plurality of data lines 20 and a plurality of data signal terminals VD. The multiplexer 200 includes a plurality of selection transistors 210. The source of the selection transistor 210 and the drain of the selection transistor are electrically connected to the data signal terminal and the data line 20, respectively. The source of the selection transistor 210 can be electrically connected to the data signal terminal, while the drain of the selection transistor 210 is electrically connected to the data line 20; or, the source of the selection transistor 210 can be electrically connected to the data line 20, while the drain of the selection transistor 210 is electrically connected to the data signal terminal. This application does not impose any specific restrictions on this, and specific analysis and design are required based on parameters such as the conduction type of the selection transistor 210.

[0040] The select transistor 210 includes a channel layer 211 located on the substrate 100, a gate dielectric layer 212 located on one side of the channel layer 211, and a main gate 213 located on a side of the gate dielectric layer 212 facing away from the channel layer 211. The main gate 213 is connected to a selection control signal MUX. At least one channel layer 211 includes an auxiliary gate 310 on a side facing away from the gate dielectric layer 212. An auxiliary insulating layer 320 is provided between the auxiliary gate 310 and the channel layer 211. The orthographic projection of the auxiliary gate 310 on the substrate 100 at least partially overlaps with the orthographic projection of the channel layer 211 on the substrate 100. The auxiliary gate 310 is connected to a reference voltage VF.

[0041] It can be understood that the technical solution provided by the embodiment of the present application provides an auxiliary gate 310 on the side of the channel layer 211 away from the gate dielectric layer 212, thereby improving the ability of the multiplexer 200 to transmit data signals. Among them, the main gate 213 and the auxiliary gate 310 jointly control the flow of current in the channel, thereby improving the response speed of the selection transistor 210 and reducing the threshold voltage of the selection transistor 210. This increases the current transmitted from the selection transistor 210 to the data line 20, improves the charging effect of the data line 20 on the pixel drive circuit connected to it, and ultimately achieves the purpose of optimizing the display effect of the display panel. In addition, the auxiliary gate 310 can also act as an electrostatic shield, suppressing the problem of characteristic drift of the selection transistor 210 due to static electricity.

[0042] Specific reference Figure 4 As shown, a display panel including two multiplexers and two data signal terminals is described as an example, and the selection transistor 210 is a P-type transistor. The first multiplexer 201 includes two selection transistors 210, namely a first selection transistor 2101 and a second selection transistor 2102, and the second multiplexer 202 includes two selection transistors 210, namely a third selection transistor 2103 and a fourth selection transistor 2104. The first selection transistor 2101 and the second selection transistor 2102 are both electrically connected to the first data signal terminal VD1, and the third selection transistor 2103 and the fourth selection transistor 2104 are both electrically connected to the second data signal terminal VD2. Furthermore, the main gates 213 of the first selection transistor 2101 and the main gates 213 of the third selection transistor 2103 are both connected to the first selection control signal MUX1, and the main gates 213 of the second selection transistor 2102 and the main gates 213 of the fourth selection transistor 2104 are both connected to the second selection control signal MUX2. The main gate 213 of the first selection transistor 2101 is provided with a first auxiliary gate 311 relative to the main gate 213 of the second selection transistor 2102, the main gate 213 of the third selection transistor 2103 is provided with a third auxiliary gate 313 relative to the main gate 213, and the main gate 213 of the fourth selection transistor 2104 is provided with a fourth auxiliary gate 314 relative to the main gate 213, and the auxiliary gate 310 at least partially overlaps with the channel layer 211 of the selection transistor 210, wherein the first auxiliary gate 311 is connected to the reference voltage VF1, the second auxiliary gate 312 is connected to the reference voltage VF2, the third auxiliary gate 313 is connected to the reference voltage VF3, and the fourth auxiliary gate 314 is connected to the reference voltage VF4.

[0043] During the process of the first selection control signal MUX1 controlling the conduction of the first selection transistor 2101 and the third selection transistor 2103, the first auxiliary gate 311 and the third auxiliary gate 313 are respectively connected to the first reference voltage VF1 and the third reference voltage VF3, thereby reducing the threshold voltage of the first selection transistor 2101 and the third selection transistor 2103, increasing the current of the data signal passing through the first selection transistor 2101 and the third selection transistor 2103, and thereby improving the charging effect of the data line 20 on the pixel driving circuit connected thereto, thereby achieving the purpose of optimizing the display effect of the display panel. Similarly, when the second selection control signal MUX2 controls the conduction of the second selection transistor 2102 and the fourth selection transistor 2104, the second auxiliary gate 312 and the fourth auxiliary gate 314 are connected to the second reference voltage VF2 and the fourth reference voltage VF4, respectively. This lowers the threshold voltage of the second selection transistor 2102 and the fourth selection transistor 2104, increases the current of the data signal passing through the second selection transistor 2102 and the fourth selection transistor 2104, and thereby improves the charging effect of the data line 20 on the pixel driving circuit connected thereto, thereby optimizing the display effect of the display panel. In addition, the first auxiliary gate 311 to the fourth auxiliary gate 314 can also act as an electrostatic shield, suppressing the problem of characteristic drift of the first selection transistor 2101 to the fourth selection transistor 2104 caused by static electricity.

[0044] refer to Figure 6As shown, it is a structural schematic diagram of another display panel provided by an embodiment of the present application, wherein the display panel includes a plurality of pixel units, and the plurality of pixel units are arranged in an array along the row direction X and the column direction Y. The pixel unit includes a pixel driving circuit 10 electrically connected to the data line 20 and a light-emitting element DL electrically connected to the pixel driving circuit 10. The light-emitting element DL is a red light-emitting element DLR, a green light-emitting element DLG or a blue light-emitting element DLB, wherein the selection transistor 210 corresponding to the red light-emitting element DLR is defined as a red light selection transistor 210R, the selection transistor 210 corresponding to the green light-emitting element DLG is defined as a green light selection transistor 210G, and the selection transistor 210 corresponding to the blue light-emitting element DLB is defined as a blue light selection transistor 210B; the channel layer 211 of at least one of the red light selection transistors 210R is away from the gate dielectric layer 212 One side includes an auxiliary gate 310R, and the auxiliary gate 310R and the orthographic projection on the substrate 100 and the orthographic projection of the channel layer 211 on the substrate 100 have at least a partially overlapping area; and / or, the channel layer 211 of at least one of the blue light selection transistors 210B includes an auxiliary gate 310B on the side facing away from the gate dielectric layer 212, and the auxiliary gate 310B and the orthographic projection on the substrate 100 and the orthographic projection of the channel layer 211 on the substrate 100 have at least a partially overlapping area.

[0045] It is understood that at least one red light selection transistor 210R in the display panel may be provided with an auxiliary gate 310R; or at least one blue light selection transistor 210B in the display panel may be provided with an auxiliary gate 310B; or at least one red light selection transistor 210R in the display panel may be provided with an auxiliary gate 310R, and at least one blue light selection transistor 210B may be provided with an auxiliary gate 310B. This application does not impose any specific restrictions on this. Preferably, at least one red light selection transistor 210R in the display panel may be provided with an auxiliary gate 310R, and at least one blue light selection transistor 210B may be provided with an auxiliary gate 310B. Since the inherent luminous efficiency of the green light emitting element DLG is greater than the inherent luminous efficiency of the red light emitting element DLR and the blue light emitting element DLB, the red light emitting element DLR and the blue light emitting element DLB are more dependent on the charging effect of the data line 20 on the pixel driving circuit 10 than the green light emitting element DLG. Therefore, an auxiliary gate 310 is set at the red light selection transistor 210R and the blue light selection transistor 210B, while the auxiliary gate 310 is no longer set at the green light selection transistor 210G. During the operation of the display panel, the threshold voltages of the red light selection transistor 210R and the blue light selection transistor 210B can be reduced, thereby improving the charging effect of the data line 20 on the corresponding pixel driving circuits of the red light emitting element DLR and the blue light emitting element DLB, improving the luminous efficiency of the red light emitting element DLR and the blue light emitting element DLB, and balancing the luminous efficiency of the red light emitting element DLR, the blue light emitting element DLB and the green light emitting element DLG, thereby improving the display brightness uniformity of the display panel and optimizing the display effect of the display panel.

[0046] Specific as Figure 6In the display panel shown, an example is shown in which the display panel includes two multiplexers and two data signal terminals, and the select transistor 210 is a P-type transistor. The two multiplexers 200 are respectively a third multiplexer 203 and a fourth multiplexer 204, and the two data signal terminals are respectively a third data signal terminal VD3 and a fourth data signal terminal VD4. The third multiplexer 203 and the fourth multiplexer 204 each include four select transistors 210. All select transistors 210 in the third multiplexer 203 are electrically connected to the third data signal terminal VD3, and all select transistors 210 in the fourth multiplexer 204 are electrically connected to the fourth data signal terminal VD4. The main gate 213 of the red light selection transistor 210R in the third multiplexer 203 and the fourth multiplexer 204 is connected to the red light selection control signal MUXR, the main gate 213 of the blue light selection transistor 210B in the third multiplexer 203 and the fourth multiplexer 204 is connected to the blue light selection control signal MUXB, the main gate 213 of the green light selection transistor 210G in the third multiplexer 203 and the fourth multiplexer 204 that is scanned in the same row as the red light emitting element DLR is connected to the first green light selection control signal MUXG1, and the main gate 213 of the green light selection transistor 210G in the third multiplexer 203 and the fourth multiplexer 204 that is scanned in the same row as the blue light emitting element DLB is connected to the second green light selection control signal MUXG2.

[0047] During the process of the red light selection control signal MUXR controlling the red light selection transistor 210R to be turned on, the auxiliary gate 310R is connected to the corresponding reference voltage, thereby reducing the threshold voltage of the red light selection transistor 210R and increasing the current of the data signal passing through the red light selection transistor 210R, thereby improving the charging effect of the data line 20 on the corresponding pixel driving circuit 10 of the red light emitting element DLR, and improving the luminous efficiency of the red light emitting element DLR; and, during the process of the blue light selection control signal MUXB controlling the blue light selection transistor 210B to be turned on, the auxiliary gate 310B is connected to the corresponding reference voltage, thereby reducing the threshold voltage of the blue light selection transistor 210B and increasing the current of the data signal passing through the blue light selection transistor 210B, thereby improving the charging effect of the data line 20 on the corresponding pixel driving circuit 10 of the blue light emitting element DLB, and improving the luminous efficiency of the blue light emitting element DLB. During the process of controlling the green light selection transistor 210G to be turned on by the first green light selection control signal MUXG1 and the second green light selection control signal MUXG2, there is no need to increase the charging effect of the data line 20 on the pixel driving circuit 10 corresponding to the green light emitting element DLG, thereby balancing the luminous efficiency of the red light emitting element DLR, the blue light emitting element DLB and the green light emitting element DLG, thereby improving the display brightness uniformity of the display panel and optimizing the display effect of the display panel.

[0048] The reference voltage connected to the auxiliary gate has a direct impact on the degree of reduction in the threshold voltage of the select transistor 210. The reference voltage corresponding to the red select transistor 210R is defined as the red reference voltage, and the reference voltage corresponding to the blue select transistor 210B is defined as the blue reference voltage. That is, the reference voltage connected to the auxiliary gate 310R is the red reference voltage, while the reference voltage connected to the auxiliary gate 310G is the green reference voltage. The red reference voltage and the blue reference voltage are different fixed voltages. Due to the different luminous efficiencies of the red light-emitting element DLR and the blue light-emitting element DLB, the red reference voltage and the blue reference voltage are optimized to be different fixed voltages. This specifically optimizes and reduces the threshold voltages of the red and blue select transistors 210R and 210B, thereby optimizing the charging effects of the pixel drive circuits 10 corresponding to the red light-emitting element DLR and the blue light-emitting element DLB, further balancing the luminous efficiencies of the red, blue, and green light-emitting elements DLR, DLB, and DLG, and further improving the display quality of the display panel. Alternatively, the reference voltage corresponding to the red light selection transistor 210R is defined as a red light reference voltage, and the reference voltage corresponding to the blue light selection transistor 210B is defined as a blue light reference voltage. That is, the reference voltage connected to the auxiliary gate 310R is the red light reference voltage, while the reference voltage connected to the auxiliary gate 310G is the green light reference voltage. The red and blue light reference voltages are the same fixed voltage. This allows for balanced regulation of the luminous efficiency of the red, blue, and green light-emitting elements DLR, DLB, and DLG while providing the same fixed voltage through a single reference voltage terminal. This reduces the number of reference voltage terminals and corresponding transmission lines, simplifying the wiring of the display panel.

[0049] like Figure 7 As shown in FIG. 1 , a structural diagram of another display panel provided by an embodiment of the present application, when the red reference voltage and the blue reference voltage are the same fixed voltage, the auxiliary gate 310R corresponding to the adjacent red light selection transistor 210R and the auxiliary gate 310B corresponding to the blue light selection transistor 210B can also extend and contact to form the same auxiliary gate 310R (310B), thereby expanding the electrostatic shielding area of ​​the auxiliary gate 310R (310B) and improving the electrostatic shielding effect of the auxiliary gate 310. Or continue as shown in FIG. Figure 7As shown, when the red reference voltage and the blue reference voltage are different fixed voltages, since the red light selection control signal MUXR and the blue light selection control signal MUXB are effective in time-sharing, the auxiliary gate 310R corresponding to the adjacent red light selection transistor 210R and the auxiliary gate 310B corresponding to the blue light selection transistor 210B can also be extended to contact the same auxiliary gate 310R (310B). At this time, the reference voltage terminal electrically connected to the auxiliary gate 310R (310B) is a port for outputting different reference voltages in time-sharing, that is, in the process of the red light selection control signal MUXR controlling the red light selection transistor 210R to be turned on, the reference voltage terminal outputs The corresponding reference voltage is output to the auxiliary gate 310R (310B) to specifically reduce the threshold voltage of the red light selection transistor 210R; and when the blue light selection control signal MUXB controls the blue light selection transistor 210B to be turned on, the reference voltage end outputs a reference voltage of other voltage values ​​to the auxiliary gate 310R (310B) to specifically reduce the threshold voltage of the blue light selection transistor 210B, thereby completing the adjustment of the charging effect of the data line 20 on the pixel driving circuit 10, expanding the electrostatic shielding area of ​​the auxiliary gate 310R (310B), and improving the electrostatic shielding effect of the auxiliary gate 310R (310B).

[0050] refer to Figure 8As shown, it is a structural schematic diagram of another display panel provided in an embodiment of the present application, wherein the display panel includes a plurality of pixel units, and the plurality of pixel units are arranged in an array along the row direction X and the column direction Y. The pixel unit includes a pixel driving circuit 10 electrically connected to the data line 20 and a light-emitting element DL electrically connected to the pixel driving circuit 10. The light-emitting element DL is a red light-emitting element DLR, a green light-emitting element DLG or a blue light-emitting element DLB, wherein the selection transistor 210 corresponding to the red light-emitting element DLR is defined as a red light selection transistor 210R, the selection transistor 210 corresponding to the green light-emitting element DLG is defined as a green light selection transistor 210G, and the selection transistor 210 corresponding to the blue light-emitting element DLB is defined as a blue light selection transistor 210B; the channel layer 211 of at least one of the red light selection transistors 210R is away from the gate dielectric layer 212 One side includes an auxiliary gate 310R, and the auxiliary gate 310R has an orthographic projection on the substrate 100 and an orthographic projection of the channel layer 211 on the substrate 100 that at least partially overlaps; and / or, the channel layer 211 of at least one of the blue light selection transistors 210B includes an auxiliary gate 310B on a side facing away from the gate dielectric layer 212, and the auxiliary gate 310B has an orthographic projection on the substrate 100 and an orthographic projection of the channel layer 211 on the substrate 100 that at least partially overlaps. Furthermore, the channel layer 211 of at least one of the green light selection transistors 210G also includes an auxiliary gate 310G on a side facing away from the gate dielectric layer 212, and the auxiliary gate 310G has an orthographic projection on the substrate 100 and an orthographic projection of the channel layer 211 on the substrate 100 that at least partially overlaps.

[0051] It can be understood that at least one red light selection transistor 210R in the display panel can be provided with an auxiliary gate 310R, and at least one green light selection transistor 210G can be provided with an auxiliary gate 310G; or, at least one blue light selection transistor 210B in the display panel can be provided with an auxiliary gate 310B, and at least one green light selection transistor 210G can be provided with an auxiliary gate 310G; or, at least one red light selection transistor 210R in the display panel can be provided with an auxiliary gate 310R, at least one blue light selection transistor 210B can be provided with an auxiliary gate 310B, and at least one green light selection transistor 210G can be provided with an auxiliary gate 310G. This application does not impose any specific restrictions on this. Preferably, at least one red light selection transistor 210R in the display panel can be provided with an auxiliary gate 310R, at least one blue light selection transistor 210B can be provided with an auxiliary gate 310B, and at least one green light selection transistor 210G can be provided with an auxiliary gate 310G. Thus, the charging effect of the pixel driving circuits 10 corresponding to all colors of light in the display panel is optimized and improved, thereby achieving the purpose of improving the overall display effect of the display panel.

[0052] Specific as Figure 8 In the display panel shown, during the process of the red light selection control signal MUXR controlling the red light selection transistor 210R to be turned on, the auxiliary gate 310R is connected to the corresponding reference voltage, thereby reducing the threshold voltage of the red light selection transistor 210R, increasing the current of the data signal passing through the red light selection transistor 210R, thereby improving the charging effect of the data line 20 on the corresponding pixel driving circuit 10 of the red light emitting element DLR, and improving the luminous efficiency of the red light emitting element DLR; and, during the process of the blue light selection control signal MUXB controlling the blue light selection transistor 210B to be turned on, the auxiliary gate 310B is connected to the corresponding reference voltage, thereby reducing the threshold voltage of the blue light selection transistor 210B, increasing the current of the data signal passing through the blue light selection transistor 210B, thereby improving the charging effect of the data line 20 on the corresponding pixel driving circuit 10 of the blue light emitting element DLB, and improving the luminous efficiency of the blue light emitting element DLB. In addition, during the process of the green light selection transistor 210G being turned on by the first green light selection control signal MUXG1 or the second green light selection control signal MUXG2, the auxiliary gate 310G is connected to the corresponding reference voltage, thereby reducing the threshold voltage of the green light selection transistor 210G, increasing the current of the data signal passing through the green light selection transistor 210G, and thereby improving the charging effect of the data line 20 on the pixel driving circuit 10 corresponding to the green light emitting element DLG, thereby improving the luminous efficiency of the green light emitting element DLG, thereby improving the luminous efficiency of the red light emitting element DLR, the blue light emitting element DLB and the green light emitting element DLG in the display panel, and optimizing the overall display effect of the display panel.

[0053] The reference voltage corresponding to the red light selection transistor 210R is defined as a red light reference voltage, the reference voltage corresponding to the blue light selection transistor 210B is defined as a blue light reference voltage, and the reference voltage corresponding to the green light selection transistor 210G is defined as a green light reference voltage; that is, the reference voltage connected to the auxiliary gate 310R is a red light reference voltage, and the reference voltage connected to the auxiliary gate 310G is a green light reference voltage, and the reference voltage connected to the auxiliary gate 310G is a green light reference voltage, wherein the red light reference voltage, the blue light reference voltage and the green light reference voltage are different fixed voltages. Since the luminous efficiencies of the red light emitting element DLR, the blue light emitting element DLB and the green light emitting element DLG are different, the red light reference voltage, the blue light reference voltage and the green light reference voltage are optimized to be different fixed voltages, and the threshold voltages of the red light selection transistor 210R, the blue light selection transistor 210B and the green light selection transistor 210G are optimized and reduced in a targeted manner, so as to optimize the charging effects of the pixel driving circuits 10 corresponding to the red light emitting element DLR, the blue light emitting element DLB and the green light emitting element DLG, respectively, so as to achieve the purpose of optimizing the overall display effect of the display panel. Alternatively, the reference voltage corresponding to the red light selection transistor 210R is defined as a red light reference voltage, the reference voltage corresponding to the blue light selection transistor 210B is defined as a blue light reference voltage, and the reference voltage corresponding to the green light selection transistor 210G is defined as a green light reference voltage; that is, the reference voltage connected to the auxiliary gate 310R is the red light reference voltage, and the reference voltage connected to the auxiliary gate 310G is the green light reference voltage, and the reference voltage connected to the auxiliary gate 310G is the green light reference voltage, wherein the red light reference voltage and the blue light reference voltage are the same fixed voltage, and the red light reference voltage and the blue light reference voltage are different fixed voltages from the green light reference voltage. Since the luminous efficiency of the red light emitting element DLR and the blue light emitting element DLB is much lower than that of the green light emitting element DLG, the red light reference voltage and the blue light reference voltage are optimized to be the same fixed voltage, and are set to a fixed voltage different from the green light reference voltage, so that the charging effect of the pixel driving circuit 10 corresponding to the red light emitting element DLR and the blue light emitting element DLB is different from the charging effect of the pixel driving circuit 10 corresponding to the green light emitting element DLG, thereby achieving the purpose of optimizing the overall display effect of the display panel; at the same time, the same fixed voltage can also be provided through the same reference voltage terminal, thereby reducing the number of reference voltage terminals and corresponding transmission lines, and simplifying the wiring of the display panel.

[0054] refer to Figure 9As shown, it is a structural diagram of another display panel provided by an embodiment of the present application. When the red light reference voltage and the blue light reference voltage are the same fixed voltage, the auxiliary gate 310R corresponding to the adjacent red light selection transistor 210R and the auxiliary gate 310B corresponding to the blue light selection transistor 210B can also be extended to contact the same auxiliary gate 310R (310B); similarly, the auxiliary gate 310G corresponding to the adjacent green light selection transistor 210B can also be extended to contact the same auxiliary gate 310G, thereby expanding the electrostatic shielding area of ​​the auxiliary gate and improving the electrostatic shielding effect of the auxiliary gate. Or continue as Figure 9 As shown, when the red reference voltage and the blue reference voltage are different fixed voltages, since the red light selection control signal MUXR and the blue light selection control signal MUXB are effective in time-sharing mode, the auxiliary gate 310R corresponding to the adjacent red light selection transistor 210R and the auxiliary gate 310B corresponding to the blue light selection transistor 210B can also be extended to contact the same auxiliary gate 310R (310B). At this time, the reference voltage terminal electrically connected to the auxiliary gate 310R (310B) is a port for outputting different reference voltages in time-sharing mode, that is, when the red light selection control signal MUXR controls the red light selection transistor 210R to be turned on, the auxiliary gate 310R (310B) is electrically connected to the blue light selection transistor 210B. During the process, the reference voltage terminal outputs a corresponding reference voltage to the auxiliary gate 310R (310B) to specifically reduce the threshold voltage of the red light selection transistor 210R; and during the process in which the blue light selection control signal MUXB controls the blue light selection transistor 210B to be turned on, the reference voltage terminal outputs a reference voltage of other voltage values ​​to the auxiliary gate 310R (310B) to specifically reduce the threshold voltage of the blue light selection transistor 210B, thereby completing the adjustment of the charging effect of the data line 20 on the pixel driving circuit 10, expanding the electrostatic shielding area of ​​the auxiliary gate, and improving the electrostatic shielding effect of the auxiliary gate.

[0055] Further references Figure 10As shown in FIG. 1 , a structural diagram of another display panel provided by an embodiment of the present application is shown. Regardless of whether the red light reference voltage and the blue light reference voltage are the same fixed voltage or different fixed voltages, since the red light selection control signal MUXR, the blue light selection control signal MUXB, the first green light selection control signal MUXG1, and the second green light selection control signal MUXG2 are effective in a time-sharing manner, the auxiliary gate 310R corresponding to the red light selection transistor 210R, the auxiliary gate 310B corresponding to the blue light selection transistor 210B, and the auxiliary gate 310G corresponding to the green light selection transistor 210B can be extended to contact the same auxiliary gate 310RBG. At this time, the reference voltage terminal electrically connected to the auxiliary gate 310RBG is a port that outputs different reference voltages in a time-sharing manner. That is, when the red light selection control signal MUXR controls the red light selection transistor 210R to be turned on, the reference voltage terminal outputs the corresponding reference voltage. to the auxiliary gate 310RBG, so as to specifically reduce the threshold voltage of the red light selection transistor 210R; and in the process of the blue light selection control signal MUXB controlling the blue light selection transistor 210B to be turned on, the reference voltage end outputs a reference voltage of another voltage value to the auxiliary gate 310RBG, so as to specifically reduce the threshold voltage of the blue light selection transistor 210B; and, in the process of the first green light selection control signal MUXG1 or the second green light selection control signal MUXG2 controlling the green light selection transistor 210G to be turned on, the reference voltage end outputs a reference voltage of another voltage value to the auxiliary gate 310RBG, so as to specifically reduce the threshold voltage of the green light selection transistor 210G, thereby completing the adjustment of the charging effect of the data line 20 on the pixel driving circuit 10, expanding the electrostatic shielding area of ​​the auxiliary gate 310RBG, and improving the electrostatic shielding effect of the auxiliary gate 310RBG.

[0056] It should be noted that the above embodiments are all described using the example of a 1:4 selector in which the multiplexer 200 includes four selection transistors 210 and one data signal terminal VD, and based on the arrangement of the pixel units, the red light selection transistor 210R and the blue light selection transistor 210B can be two independent selection transistors. In other embodiments of the present application, the multiplexer 200 provided in the present application can also include other numbers of selection transistors 210 and other pixel unit arrangements, and based on the arrangement of the pixel units, the red light selection transistor 210R and the blue light selection transistor 210B can also be the same selection transistor, and the present application does not impose any specific restrictions on this. For details, please refer to Figure 11FIG. 1 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application. The multiplexer 200 is a 1:2 selector including two selection transistors 210 and a data signal terminal. Specifically, the display panel includes a plurality of pixel units, which are arranged in an array along the row direction X and the column direction Y. The pixel units include a pixel driving circuit 10 electrically connected to the data line 20 and a light-emitting element DL electrically connected to the pixel driving circuit 10. The light-emitting element DL is a red light-emitting element DLR, a green light-emitting element DLG, or a blue light-emitting element DLB, wherein the select transistor 210 corresponding to the red light-emitting element DLR is defined as a red light select transistor, the select transistor 210 corresponding to the green light-emitting element DLG is defined as a green light select transistor 210G, and the select transistor 210 corresponding to the blue light-emitting element DLB is defined as a blue light select transistor; based on the arrangement of the pixel units, the corresponding drive circuits 10 of the red light-emitting elements DLR and the blue light-emitting elements DLB in the same column transmit data signals via the same data line 20, and therefore, the select transistor 210RB electrically connected to the data line 20 is a set of red and blue light select transistors. At least one select transistor 210RB includes an auxiliary gate 310RB on a side of the channel layer 211 facing away from the gate dielectric layer 212, and the auxiliary gate 310RB has an orthographic projection on the substrate 100 that at least partially overlaps with the orthographic projection of the channel layer 211 on the substrate 100. Furthermore, the channel layer 211 of at least one of the green light selection transistors 210G further includes an auxiliary gate 310G on the side facing away from the gate dielectric layer 212, and the auxiliary gate 310G and the orthographic projection of the channel layer 211 on the substrate 100 have at least a partially overlapping area.

[0057] Figure 11The following describes a display panel comprising two multiplexers and two data signal terminals, with the select transistor 210 being a P-type transistor. The two multiplexers 200 are the fifth multiplexer 205 and the sixth multiplexer 206, respectively, and the two data signal terminals are the fifth data signal terminal VD5 and the sixth data signal terminal VD6. Each of the fifth multiplexer 205 and the sixth multiplexer 206 includes two select transistors 210. All select transistors 210 in the fifth multiplexer 205 are electrically connected to the fifth data signal terminal VD5, and all select transistors 210 in the sixth multiplexer 206 are electrically connected to the sixth data signal terminal VD6. The main gate 213 of the select transistor 210RB in the fifth multiplexer 205 and the sixth multiplexer 206 is connected to the red and blue light select control signal MUXRB, while the main gate 213 of the green light select transistor 210G in the fifth multiplexer 205 and the sixth multiplexer 206 is connected to the green light select control signal MUXG.

[0058] The reference voltage corresponding to the red light selection transistor is defined as a red light reference voltage, the reference voltage corresponding to the blue light selection transistor is defined as a blue light reference voltage, and the reference voltage corresponding to the green light selection transistor 210G is defined as a green light reference voltage, wherein the red light reference voltage, the blue light reference voltage and the green light reference voltage can be different fixed voltages. Therefore, when the red and blue light selection control signal MUXRB controls the selection transistor 210RB to be turned on, and at this time, when the data line 20 charges the pixel driving circuit 10 connected to the red light emitting element DLR, the auxiliary gate 310RB is connected to the red light reference voltage, thereby reducing the threshold voltage of the selection transistor 210RB, increasing the current of the data signal passing through the selection transistor 210RB, and thereby improving the charging effect of the data line 20 on the pixel driving circuit 10 corresponding to the red light emitting element DLR, thereby improving the luminous efficiency of the red light emitting element DLR; and, when the red and blue light selection control signal MUXRB controls the selection transistor 210RB to be turned on, and at this time, when the data line 20 charges the pixel driving circuit 10 connected to the blue light emitting element DLB, the auxiliary gate 310RB is connected to the corresponding blue light reference voltage, thereby reducing the threshold voltage of the selection transistor 210RB, increasing the current of the data signal passing through the selection transistor 210RB, thereby improving the charging effect of the data line 20 on the pixel driving circuit 10 corresponding to the blue light emitting element DLB, thereby improving the luminous efficiency of the blue light emitting element DLB. In addition, when the green light selection control signal MUXG controls the green light selection transistor 210G to be turned on, the auxiliary gate 310G is connected to the corresponding green light reference voltage, which can reduce the threshold voltage of the green light selection transistor 210G, increase the current of the data signal passing through the green light selection transistor 210G, and thereby improve the charging effect of the data line 20 on the corresponding pixel driving circuit 10 of the green light emitting element DLG, thereby improving the luminous efficiency of the green light emitting element DLG, thereby improving the luminous efficiency of the red light emitting element DLR, the blue light emitting element DLB and the green light emitting element DLG in the display panel, and optimizing the overall display effect of the display panel.

[0059] Or continue as Figure 11As shown, the reference voltage corresponding to the red light selection transistor is defined as a red reference voltage, the reference voltage corresponding to the blue light selection transistor is defined as a blue reference voltage, and the reference voltage corresponding to the green light selection transistor 210G is defined as a green reference voltage. The red reference voltage and the blue reference voltage are the same fixed voltage, and the red reference voltage, the blue reference voltage, and the green reference voltage are different fixed voltages. Therefore, when the red and blue light selection control signal MUXRB controls the selection transistor 210RB to be turned on, regardless of whether the data line 20 is charging the pixel driving circuit 10 connected to the red light emitting element DLR or the pixel driving circuit 10 connected to the blue light emitting element DLB, the auxiliary gate 310RB is connected to the same fixed reference voltage, thereby lowering the threshold voltage of the selection transistor 210RB and increasing the current of the data signal passing through the selection transistor 210RB. This in turn improves the charging effect of the data line 20 on the pixel driving circuit 10 corresponding to the red light emitting element DLR or the blue light emitting element DLB, thereby improving the charging effect of the red light emitting element DLR or the blue light emitting element DLB. and, in the process of the green light selection transistor 210G being turned on under the control of the green light selection control signal MUXG, the auxiliary gate 310G is connected to the corresponding green light reference voltage, thereby reducing the threshold voltage of the green light selection transistor 210G, increasing the current of the data signal passing through the green light selection transistor 210G, and thereby improving the charging effect of the data line 20 on the pixel driving circuit 10 corresponding to the green light emitting element DLG, thereby improving the luminous efficiency of the green light emitting element DLG, thereby improving the luminous efficiency of the red light emitting element DLR, the blue light emitting element DLB and the green light emitting element DLG in the display panel, and optimizing the overall display effect of the display panel.

[0060] Further references Figure 12As shown in FIG. 1 , a structural diagram of another display panel provided by an embodiment of the present application is provided. Regardless of whether the red light reference voltage and the blue light reference voltage are the same fixed voltage or different fixed voltages, since the red and blue light selection control signal MUXRB and the green light selection control signal MUXG are effective in time-sharing, the auxiliary gate 310RB corresponding to the selection transistor 210RB and the auxiliary gate 310G corresponding to the green light selection transistor 210B can be extended to contact the same auxiliary gate 310RBG. At this time, the reference voltage end electrically connected to the auxiliary gate 310RBG is a port for outputting different reference voltages in time-sharing. That is, when the red and blue light selection control signal MUXRB controls the selection, the auxiliary gate 310RB corresponding to the green light selection transistor 210B can be extended to contact the auxiliary gate 310RBG. During the conduction process of the transistor 210RB, the reference voltage terminal outputs a corresponding reference voltage to the auxiliary gate 310RBG to specifically reduce the threshold voltage of the selection transistor 210RB; and during the conduction process of the green light selection transistor 210G controlled by the green light selection control signal MUXG, the reference voltage terminal outputs a reference voltage of other voltage values ​​to the auxiliary gate 310RBG to specifically reduce the threshold voltage of the green light selection transistor 210G, thereby completing the adjustment of the charging effect of the data line 20 on the pixel driving circuit 10, expanding the electrostatic shielding area of ​​the auxiliary gate 310RBG, and improving the electrostatic shielding effect of the auxiliary gate 310RBG.

[0061] refer to Figure 13As shown, it is a structural schematic diagram of another display panel provided in an embodiment of the present application, wherein the display panel includes a display area AA and a non-display area NA located outside the display area AA; the data line 20 is located in the non-display area NA and extends along the first direction Y, the multiple multiplexers 200 are located in the non-display area NA, and the multiple multiplexers 200 are located on the same side of the display area AA in the first direction Y; the display area is divided into multiple sub-display areas AA1 along the first direction Y of AA, wherein when the data line 20 transmits data signals to pixel units corresponding to light-emitting elements DL of the same light-emitting color in different sub-display areas AA1, the reference voltage is a different fixed voltage. Data line 20 transmits data signals with a delay. In the first direction Y, the delay when data line 20 transmits data signals to pixel units far from multiplexer 200 is greater than the delay when transmitting data signals to pixel units close to multiplexer 200. Therefore, when data line 20 transmits data signals to pixel units corresponding to light-emitting elements DL of the same luminous color in different sub-display areas AA1, setting the reference voltage to different fixed voltages will cause the threshold voltages of the select transistor to differ when the data line transmits signals to different sub-display areas. Furthermore, by optimizing the reference voltage, the threshold voltage of the select transistor when transmitting signals on the data line increases from display area AA to multiplexer 200. This allows for greater consistency in the delay of data line transmission signals to pixel units in different sub-display areas AA1, thereby improving the display quality of the display panel.

[0062] Specifically, the selection transistor 210 may be an N-type transistor. When the data line 20 sequentially transmits data signals to pixel units corresponding to light-emitting elements DL of the same luminous color in the sub-display area AA1 from the display area AA to the multiplexer 200, the reference voltage decreases. An N-type transistor is a transistor whose conduction is controlled by a high level. Therefore, a lower reference voltage is equivalent to increasing the threshold voltage of the selection transistor 210, while a higher reference voltage is equivalent to decreasing the threshold voltage of the selection transistor 210. Therefore, when the selection transistor 210 is an N-type transistor, the reference voltage when transmitting data signals to pixel units corresponding to light-emitting elements DL of the previous sub-display area AA1 from the display area AA to the multiplexer 200 is greater than the reference voltage when transmitting data signals to pixel units corresponding to light-emitting elements DL of the same luminous color in the next display area AA1. This increases the threshold voltage of the selection transistor 210, improves the delay difference when the data line 20 transmits data signals to different sub-display areas, and enhances the display quality of the display panel.

[0063] Alternatively, the select transistor 210 may be a P-type transistor. When the data line 20 sequentially transmits data signals to the pixel units of the sub-display area AA1 from the display area AA to the multiplexer 200, the reference voltage increases. Unlike N-type transistors, P-type transistors are transistors that conduct when a low level is applied. Therefore, a higher reference voltage is equivalent to increasing the threshold voltage of the select transistor 210, while a lower reference voltage is equivalent to decreasing the threshold voltage of the select transistor 210. Therefore, when the select transistor 210 is a P-type transistor, the reference voltage when transmitting data signals to the pixel units corresponding to the light-emitting elements DL of the previous sub-display area AA1 from the display area AA to the multiplexer 200 is lower than the reference voltage when transmitting data signals to the pixel units corresponding to the light-emitting elements DL of the same color in the next sub-display area AA1. This increases the threshold voltage of the select transistor 210, thereby improving the delay differences between the data lines 20 when transmitting data signals to different sub-display areas and enhancing the display quality of the display panel.

[0064] refer to Figure 14 As shown, it is a structural schematic diagram of another display panel provided in an embodiment of the present application, the selection transistor 210 can be a top-gate transistor, wherein the auxiliary gate 310 is located between the substrate 100 and the channel layer 211, and the selection transistor 210 includes: an interlayer insulating layer 214 located on the side of the main gate 213 away from the channel layer 211, and the source 215 and the drain 216 located on the side of the interlayer insulating layer 214 away from the channel layer 211, and the source 215 and the drain 216 are both in contact with the channel layer 211 through the interlayer insulating layer 214 and the gate dielectric layer 212. That is, the display panel includes a substrate 100; an auxiliary metal layer located on the substrate 100, the auxiliary metal layer including an auxiliary gate 310; an auxiliary insulating layer 320 located on the side of the auxiliary metal layer facing away from the substrate 100; a semiconductor layer located on the side of the auxiliary insulating layer 320 facing away from the substrate 100, the semiconductor layer including a channel layer 211; a gate dielectric layer 212 located on the side of the semiconductor layer facing away from the substrate 100; a gate metal layer located on the side of the gate dielectric layer 212 facing away from the substrate 100, the gate metal layer including a main gate 213; an interlayer insulating layer 214 located on the side of the gate metal layer facing away from the substrate 100; a source-drain metal layer located on the side of the interlayer insulating layer 214 facing away from the substrate 100, the source-drain metal layer including a source 215 and a drain 216.

[0065] In order to improve the electrostatic shielding effect of the auxiliary gate 310, the orthographic projection of the auxiliary gate 310 on the substrate 100 at least covers the orthographic projection of the channel layer 211 on the substrate 100. Figure 15As shown, the extension and connection between at least two adjacent auxiliary gates 310 not only expands the electrostatic shielding area of ​​the auxiliary gates 310 but also reduces the etching and segmentation process of the auxiliary gates 310, simplifying the manufacturing process. In addition, the reference voltage connected to the auxiliary gates 310 after the extension and connection can be the same fixed voltage or different fixed voltages. For this, please refer to the corresponding description of the light-emitting elements of different colors above and will not be repeated here.

[0066] The auxiliary gate 310 needs to be connected to a reference voltage, wherein the circuit connected to the reference voltage can be the same metal layer as the auxiliary gate 310. Alternatively, the reference voltage Figure 16 In the dotted structure shown, the circuit for accessing the reference voltage can be the same metal layer as the main gate 213, and the circuit for accessing the reference voltage is connected to the auxiliary gate 310 through the auxiliary insulating layer 320. Alternatively, continue to refer to Figure 16 In the solid line structure shown, the circuit connected to the reference voltage can be the same layer of metal as the source 215 and the drain 216, and the circuit connected to the reference voltage is connected to the auxiliary gate 310 through the interlayer insulating layer 214, the gate dielectric layer 212 and the auxiliary insulating layer 320. This application does not impose specific restrictions on this.

[0067] refer to Figure 17 As shown, it is a structural schematic diagram of another display panel provided in an embodiment of the present application, the selection transistor 210 can be a bottom-gate transistor, wherein the main gate 213 is located between the substrate 100 and the channel layer 211, and the selection transistor 210 includes: an interlayer insulating layer 214 located on the side of the auxiliary gate 310 away from the channel layer 211, and the source 215 and the drain 216 located on the side of the interlayer insulating layer 214 away from the channel layer 211, and the source 215 and the drain 216 are both in contact with the channel layer 211 through the interlayer insulating layer 214 and the auxiliary insulating layer 320. That is, the display panel includes a substrate 100; a gate metal layer located on the substrate 100, the gate metal layer including a main gate 213; a gate dielectric layer 212 located on the side of the gate metal layer facing away from the substrate 100; a semiconductor layer located on the side of the gate dielectric layer 212 facing away from the substrate 100, the semiconductor layer including a channel layer 211; an auxiliary insulating layer 320 located on the side of the semiconductor layer facing away from the substrate 100; an auxiliary metal layer located on the side of the auxiliary insulating layer 320 facing away from the substrate 100, the auxiliary metal layer including an auxiliary gate 310; an interlayer insulating layer 214 located on the side of the auxiliary metal layer facing away from the substrate 100; a source-drain metal layer located on the side of the interlayer insulating layer 214 facing away from the substrate 100, the source-drain metal layer including a source 215 and a drain 216.

[0068] The auxiliary gate 310 needs to be connected to a reference voltage, wherein the circuit connected to the reference voltage can be the same metal layer as the auxiliary gate 310. Alternatively, the reference voltage Figure 18 As shown, the circuit connected to the reference voltage can be the same metal layer as the source 215 and the drain 216, and the circuit connected to the reference voltage is connected to the auxiliary gate 310 through the interlayer insulating layer 214, the gate dielectric layer 212 and the auxiliary insulating layer 320. This application does not make specific restrictions on this. Figure 19 As shown, it is a structural schematic diagram of another display panel provided in an embodiment of the present application. The display panel may further include a buffer layer 300 located on the substrate 100. After the buffer layer 300 is formed on the substrate 100, subsequent structural layers are produced, thereby preventing impurities on the substrate 100 from entering the channel layer 211 and affecting device performance.

[0069] Based on the same inventive concept, an embodiment of the present application further provides an electronic device, the electronic device comprising the display panel provided by any of the above embodiments. Figure 20 1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application, wherein the electronic device 1000 may be a mobile terminal, and the electronic device 1000 includes a display panel provided in any one of the above embodiments.

[0070] It should be noted that the electronic device can also be a notebook, tablet computer, computer, wearable device, etc., and this application does not impose specific restrictions on this.

[0071] An embodiment of the present application provides a display panel and an electronic device, wherein the display panel includes a substrate and a plurality of multiplexers located on the substrate, the multiplexers including a plurality of selection transistors, the source electrodes and the drain electrodes of the selection transistors being electrically connected to a data signal terminal and a data line, respectively, the selection transistors including: a channel layer located on the substrate, a gate dielectric layer located on one side of the channel layer, and a main gate located on a side of the gate dielectric layer facing away from the channel layer, the main gate being connected to a selection control signal; at least one of the channel layers includes an auxiliary gate on a side facing away from the gate dielectric layer, an auxiliary insulating layer is included between the auxiliary gate and the channel layer, the auxiliary gate and an orthographic projection of the channel layer on the substrate have at least a partially overlapping area, and the auxiliary gate is connected to a reference voltage.

[0072] As can be seen from the foregoing, the technical solution provided by the embodiments of the present application, which provides an auxiliary gate on the side of the channel layer facing away from the gate dielectric layer, improves the multiplexer's ability to transmit data signals. The main gate and the auxiliary gate jointly control the flow of current in the channel, thereby improving the response speed of the select transistor and reducing the threshold voltage of the select transistor. This increases the current transmitted by the select transistor to the data line, improving the charging effect of the data line on the connected pixel unit, and ultimately achieving the purpose of optimizing the display effect of the display panel. Furthermore, the auxiliary gate can also act as an electrostatic shield, suppressing the problem of characteristic drift of the select transistor caused by static electricity.

[0073] In the description of the embodiments of the present application, it should be understood that the orientation or position relationship indicated by terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", and "circumferential" are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0074] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the embodiments of the present application, the meaning of "plurality" is at least two, for example, two, three, etc., unless otherwise clearly specified.

[0075] In the embodiments of this application, unless otherwise specified or limited, terms such as "installed," "connected," "connected," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections, electrical connections, or communication between them; direct connections, indirect connections through an intermediate medium, and internal connections between two components or interactions between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0076] In the embodiments of the present application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, a first feature being "above," "above," and "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0077] In the embodiments of the present application, if the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" appear, it means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction.

[0078] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A display panel comprising a substrate and a plurality of multiplexers located on the substrate, wherein the multiplexers include a plurality of selection transistors, wherein the source electrodes and the drain electrodes of the selection transistors are electrically connected to a data signal terminal and the data line, respectively, wherein: The selection transistor includes: a channel layer located on the substrate, a gate dielectric layer located on one side of the channel layer, and a main gate located on a side of the gate dielectric layer away from the channel layer, wherein the main gate receives a selection control signal; At least one of the channel layers includes an auxiliary gate on the side facing away from the gate dielectric layer, an auxiliary insulating layer is included between the auxiliary gate and the channel layer, the auxiliary gate and the orthographic projection of the channel layer on the substrate have at least a partially overlapping area, and the auxiliary gate is connected to a reference voltage.

2. The display panel according to claim 1, wherein: The display panel includes a plurality of pixel units, each pixel unit including a pixel driving circuit electrically connected to the data line and a light emitting element electrically connected to the pixel driving circuit; The light-emitting element is a red light-emitting element, a green light-emitting element or a blue light-emitting element, wherein the selection transistor corresponding to the red light-emitting element is defined as a red light selection transistor, the selection transistor corresponding to the green light-emitting element is defined as a green light selection transistor, and the selection transistor corresponding to the blue light-emitting element is defined as a blue light selection transistor; The channel layer of at least one of the red light selection transistors includes an auxiliary gate on a side facing away from the gate dielectric layer, and the auxiliary gate has an at least partially overlapping area with the orthographic projection of the channel layer on the substrate; and / or, the channel layer of at least one of the blue light selection transistors includes an auxiliary gate on a side facing away from the gate dielectric layer, and the auxiliary gate has an at least partially overlapping area with the orthographic projection of the channel layer on the substrate.

3. The display panel according to claim 2, wherein: defining the reference voltage corresponding to the red light selection transistor as a red light reference voltage, and defining the reference voltage corresponding to the blue light selection transistor as a blue light reference voltage; The red light reference voltage and the blue light reference voltage are the same fixed voltage.

4. The display panel according to claim 2, wherein: defining the reference voltage corresponding to the red light selection transistor as a red light reference voltage, and defining the reference voltage corresponding to the blue light selection transistor as a blue light reference voltage; The red light reference voltage and the blue light reference voltage are different fixed voltages.

5. The display panel according to claim 2, wherein: The channel layer of at least one of the green light selection transistors further includes an auxiliary gate on a side facing away from the gate dielectric layer, and an orthographic projection of the auxiliary gate on the substrate and an orthographic projection of the channel layer on the substrate have at least a partially overlapping area.

6. The display panel according to claim 5, wherein: The reference voltage corresponding to the red light selection transistor is defined as a red light reference voltage, the reference voltage corresponding to the blue light selection transistor is defined as a blue light reference voltage, and the reference voltage corresponding to the green light selection transistor is defined as a green light reference voltage; The red light reference voltage and the blue light reference voltage are the same fixed voltage, and the red light reference voltage, the blue light reference voltage and the green light reference voltage are different fixed voltages.

7. The display panel according to claim 5, wherein: The reference voltage corresponding to the red light selection transistor is defined as a red light reference voltage, the reference voltage corresponding to the blue light selection transistor is defined as a blue light reference voltage, and the reference voltage corresponding to the green light selection transistor is defined as a green light reference voltage; The red light reference voltage, the blue light reference voltage, and the green light reference voltage are different fixed voltages.

8. The display panel according to claim 1, wherein: The display panel includes a display area and a non-display area located outside the display area; the data lines are located in the non-display area and extend along a first direction; the multiplexers are located in the non-display area, and the multiplexers are located on the same side of the display area in the first direction; The display area is divided into a plurality of sub-display areas along the first direction, wherein when the data line transmits data signals to pixel units in different sub-display areas, the reference voltages are different fixed voltages.

9. The display panel according to claim 8, wherein: The selection transistor is an N-type transistor, wherein, in a direction from the display area to the multiplexer, when the data line sequentially transmits data signals to the pixel units of the sub-display area, the reference voltage tends to decrease.

10. The display panel according to claim 8, wherein The selection transistor is a P-type transistor, wherein, in a direction from the display area to the multiplexer, when the data line sequentially transmits data signals to the pixel units of the sub-display area, the reference voltage tends to increase.

11. The display panel according to claim 1, wherein The auxiliary gate is located between the substrate and the channel layer, and the selection transistor includes: an interlayer insulating layer located on the side of the main gate away from the channel layer, and the source and the drain located on the side of the interlayer insulating layer away from the channel layer, and the source and the drain are both in contact with the channel layer through the interlayer insulating layer.

12. The display panel according to claim 11, wherein: The orthographic projection of the auxiliary gate on the substrate at least covers the orthographic projection of the channel layer on the substrate.

13. The display panel according to claim 11, wherein: At least two adjacent auxiliary grids extend and connect with each other.

14. The display panel according to claim 1, wherein The main gate is located between the substrate and the channel layer, and the selection transistor includes: an interlayer insulating layer located on the side of the auxiliary gate away from the channel layer, and the source and the drain located on the side of the interlayer insulating layer away from the channel layer, and the source and the drain are both in contact with the channel layer through the interlayer insulating layer.

15. An electronic device, characterized in that: The electronic device comprises the display panel according to any one of claims 1 to 14.

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