Memory and electronic device

Abstract

The present disclosure provides a memory and an electronic device, wherein the memory includes a storage block area and a first transmission circuit; the storage block area includes a first storage area and a second storage area arranged along a first direction, and the first transmission circuit includes a first branch and a second branch; wherein the first branch transmits an amplified control signal sequentially from the top side to the bottom side of the first storage area, and the second branch transmits the amplified control signal sequentially from the bottom side to the top side of the second storage area.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a memory and an electronic device. Background Art

[0002] The array region in a semiconductor memory device consists of alternating sense amplifiers and memory blocks. Amplification control signals are sequentially input into the sense amplifiers from the peripheral region, causing the delay of the amplification control signal (RSANT) to gradually increase. Column select signals (CSL) are sequentially input into the memory blocks from both sides of the memory block region, causing the delay of the CSL signal to first increase and then decrease.

[0003] In the related art, since the delay growth patterns of the amplified control signal and the CSL signal are different, it is difficult to estimate the deviation of the delay time from row enable to column enable (Time RAS to CAS Delay, tRCD) based on the delay growth pattern, resulting in a large gap in tRCD between different storage blocks. It is impossible to adjust tRCD well to meet industry standard requirements, resulting in the memory not being able to work properly. Summary of the Invention

[0004] The present disclosure provides a memory and an electronic device.

[0005] The technical solution of the present disclosure is achieved as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a memory, the memory comprising a storage block area and a first transmission circuit;

[0007] The storage block area includes a first storage area and a second storage area arranged along a first direction, and the top side of the first storage area, the bottom side of the first storage area, the top side of the second storage area, and the bottom side of the second storage area are arranged in sequence along the first direction;

[0008] The first transmission circuit includes a first branch and a second branch; in the first direction, the first branch extends at least from the top side of the first storage area to the bottom side of the first storage area; the second branch extends at least from the bottom side of the second storage area to the top side of the second storage area;

[0009] The first transmission circuit is configured to output the amplified control signal to the first storage area through the first branch, and to output the amplified control signal to the second storage area through the second branch.

[0010] In some embodiments, the first storage area includes a plurality of storage blocks sequentially arranged along the first direction, the second storage area includes a plurality of storage blocks sequentially arranged along the first direction, and a sense amplifier is provided between every two storage blocks;

[0011] The first branch transmits the amplification control signal from the signal end to the top side of the first storage area; and sequentially outputs the amplification control signal to the plurality of sense amplifiers in the first storage area along the top side of the first storage area to the bottom side of the first storage area;

[0012] The second branch sequentially outputs the amplification control signal to the plurality of sense amplifiers in the second storage area along the bottom side of the second storage area to the top side of the second storage area.

[0013] In some embodiments, the input end of the first branch and the input end of the second branch are the same signal end, the signal end is located at the bottom side of the second storage area, and the signal end is used to receive the amplification control signal;

[0014] In a first direction, the first branch extends from the signal end to the top side of the first storage area, bends, and then continues to extend through the top side of the first storage area to the bottom side of the first storage area;

[0015] In the first direction, the second branch extends from the signal end to the top side of the second storage area, and a projection of the second branch along the second direction does not overlap with a projection of the first storage area along the second direction;

[0016] Correspondingly, the length of the first branch is greater than the length of the second branch, the first branch and the second branch do not overlap, and the first direction and the second direction are perpendicular.

[0017] In some embodiments, the number of delay units on the first branch is less than the number of delay units on the second branch.

[0018] In some embodiments, the load of the first branch is smaller than the load of the second branch.

[0019] In some embodiments, the first branch includes a first extension portion, a first bending portion, and a second extension portion connected in sequence; wherein,

[0020] The first extension portion extends upward from the signal end along a first direction to the top side of the first storage area;

[0021] The first bending portion extends a first preset distance from the end of the first extending portion toward the storage block area;

[0022] The second extending portion extends downward from an end of the first bent portion along the first direction to a bottom side of the first storage area.

[0023] In some embodiments, the first branch further includes a plurality of first sub-branches, the plurality of first sub-branches extend along the second direction, and the plurality of first sub-branches are arranged along the first direction;

[0024] The input ends of the plurality of first sub-branches are connected to the second extension portion, and the output ends of the plurality of first sub-branches are connected one-to-one with the plurality of sensitive amplifiers in the first storage area to output the amplification control signal to the plurality of sensitive amplifiers in the first storage area.

[0025] In some embodiments, the second branch includes a second bending portion and a third extending portion connected in sequence; wherein,

[0026] The second bent portion extends from the signal end toward the storage block area by a second preset distance;

[0027] The third extending portion extends upward from an end of the second bent portion along the first direction to a top side of the second storage area.

[0028] In some embodiments, the first extension portion, the second extension portion, and the third extension portion further include a plurality of signal drivers, each of the signal drivers being formed by an even number of inverters connected in series;

[0029] The signal driver is used to perform signal enhancement processing on the transmitted amplification control signal.

[0030] In some embodiments, the electrical path of the first extension portion is formed at least through the first metal layer, the electrical path of the second extension portion is formed at least through the second metal layer, and the electrical path of the third extension portion is formed at least through the second metal layer, and the resistance of the first metal layer is less than the resistance of the second metal layer;

[0031] Among the first extension portion, the second extension portion, and the third extension portion, the signal driver in the first extension portion provides the largest signal enhancement amplitude.

[0032] In some embodiments, among the first extending portion, the second extending portion, and the third extending portion, the signal driver in the first extending portion has the largest size.

[0033] In some embodiments, the second branch further includes a plurality of second sub-branches, the plurality of second sub-branches extend along the second direction, and the plurality of second sub-branches are arranged along the first direction;

[0034] The input ends of the plurality of second sub-branches are connected to the third extension portion, and the output ends of the plurality of second sub-branches are connected one-to-one with the plurality of sensitive amplifiers in the second storage area to output the amplification control signal to the plurality of sensitive amplifiers in the second storage area.

[0035] In some embodiments, the storage block area and the first transmission circuit are sequentially arranged along the second direction.

[0036] The projections of the first branch and the storage block area in the third direction do not overlap; the projections of the second branch and the storage block area in the third direction do not overlap;

[0037] The third direction is perpendicular to a plane where the first direction and the second direction lie.

[0038] In some embodiments, the memory further comprises: a first column decoding circuit, a second column decoding circuit, a second transmission circuit, and a third transmission circuit;

[0039] The first column decoding circuit is located at a side of the first storage area away from the second storage area and is configured to generate a first column selection signal;

[0040] The second column decoding circuit is located at a side of the second storage area away from the first storage area and is configured to generate a second column selection signal;

[0041] In the first direction, the second transmission circuit extends downward from the first column decoding circuit along the first direction to the bottom side of the first storage area to sequentially transmit the first column selection signal to the plurality of storage blocks in the first storage area;

[0042] In the first direction, the third transmission circuit extends upward from the second column decoding circuit along the first direction to the top side of the second storage area to sequentially transmit the second column selection signal to multiple storage blocks in the second storage area.

[0043] In a second aspect, an embodiment of the present disclosure provides an electronic device, characterized by the memory described in the above embodiment.

[0044] The embodiments of the present disclosure provide a memory and an electronic device. Since the amplification control signal is transmitted to the sensitive amplifier in sequence from both sides of the memory block area through a first branch and a second branch, the delay of the amplification control signal at both ends of the input memory block area is minimized, and the delay of the amplification control signal of the middle memory block is maximized. In other words, the delay of the CSL signal and the amplification control signal of the middle memory block is maximized. As long as the tRCD of the middle memory block meets the industry standard requirements, the tRCD of all memory blocks meets the industry standard requirements, thereby improving the working performance of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A schematic diagram of a memory structure provided in an embodiment of the present disclosure Figure 1 ;

[0046] Figure 2 A schematic diagram of a memory structure provided in an embodiment of the present disclosure Figure 2 ;

[0047] Figure 3 A schematic diagram of a memory structure provided in an embodiment of the present disclosure Figure 3 ;

[0048] Figure 4 A schematic diagram of a memory structure provided in an embodiment of the present disclosure Figure 4 ;

[0049] Figure 5 A schematic diagram of a memory structure provided in an embodiment of the present disclosure Figure 5 ;

[0050] Figure 6 A schematic diagram of a memory structure provided in an embodiment of the present disclosure Figure 6 ;

[0051] Figure 7 A schematic structural diagram of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0052] The following, in conjunction with the accompanying drawings, provides a clear and complete description of the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are intended solely to illustrate the related applications and are not intended to limit those applications. It should also be noted that, for ease of description, only portions of the drawings related to the related applications are shown. Unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by those skilled in the art to which the present disclosure relates. The terms used herein are for the purpose of describing the embodiments of the present disclosure only and are not intended to limit the present disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments. However, it should be understood that "some embodiments" may refer to the same or different subsets of all possible embodiments and may be combined with each other without conflict. It should be noted that the terms "first," "second," and "third" in the embodiments of the present disclosure are used solely to distinguish similar objects and do not represent a specific ordering of the objects. It should be understood that "first," "second," and "third" may be interchanged in a specific order or sequential order, where permitted, to enable the embodiments of the present disclosure described herein to be implemented in an order other than that illustrated or described.

[0053] The following are explanations of professional terms involved in the embodiments of this disclosure and the corresponding relationships between some terms:

[0054] Process, voltage, temperature (PVT);

[0055] Threshold voltage (VTH);

[0056] Slow process corner, low voltage, high temperature (SSLVHT).

[0057] Before introducing the embodiments of the present disclosure, the three directions for describing the three-dimensional structure that may be used in the following embodiments are defined. Taking the Cartesian coordinate system as an example, the three directions may include the X-axis, Y-axis and Z-axis directions. The memory may include a top surface on the front side and a bottom surface on the back side opposite to the front side; ignoring the flatness of the top surface and the bottom surface, the direction intersecting (for example, perpendicular) with the top surface and the bottom surface of the memory is defined as the third direction. In the directions of the top surface and the bottom surface of the memory (that is, the plane where the memory is located), two directions intersecting with each other are defined. For example, the direction in which the storage blocks are arranged may be defined as the first direction, and the direction in which the first sub-branch extends may be defined as the second direction. The plane direction of the memory may be determined based on the first direction and the second direction. In the embodiment of the present disclosure, the first direction and the second direction may be perpendicular to each other. In other embodiments, the first direction and the second direction may not be perpendicular. In the embodiment of the present disclosure, the first direction is defined as the X-axis direction, the second direction is defined as the Y-axis direction, and the third direction is the Z-axis direction.

[0058] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0059] In one embodiment, a memory 10 includes a memory bank and input circuits. The memory bank includes 65 memory blocks (BLKs) and a sense amplifier (SA) located between two adjacent memory blocks BLKs. The input circuits include a first input circuit 11, a second input circuit 12, and a third input circuit 13.

[0060] Please refer to Figure 1 The 65 memory blocks are BLK0 to BLK32L, and the sense amplifiers between two adjacent memory blocks BLK are SA0 to SA63. The amplification control signal RSANT_SKEW is transmitted unidirectionally to each sense amplifier SA in sequence through the MID terminal to the EDGE terminal of the first input circuit 11. For example, the amplification control signal RSANT_SKEW is sequentially input to SA63 to SA0 through the first input circuit 11. The amplification control signal RSANT_SKEW is output to the first input circuit 11 through the row decoder (X-Decoder). The amplification control signal RSANT_SKEW is provided as an input signal to the sense amplifier SA to provide an effect during the sensing phase.

[0061] Please continue to refer to Figure 1The memory 10 also includes two sets of column decoders (Y-Decoders, Y-DEC). The column decoders can output the column selection signal CSL corresponding to each memory block BLK according to the received control parameters to open the corresponding storage cells in the memory block BLK. In other words, the column decoders can obtain the column selection signal CSL corresponding to each memory block BLK through decoding. If the column selection signal CSL is low, the column is not opened, and if the column selection signal CSL is high, the column is opened. The column selection signal CSL includes the column selection signal CSL_EDGE and the column selection signal CSL_MID. The column selection signal CSL_EDGE is sequentially input to the memory blocks BLK0 to BLK0L / 32 through the second input circuit 12, and the column selection signal CSL_MID is sequentially input to the memory blocks BLK32L to BLK0L / 32 through the third input circuit 13.

[0062] Currently, under the condition @PVT = SSLVHT, the delay of the amplifier control signal RSANT_SKEW from the MID end to the EDGE end, as measured by modeling, is 393 picoseconds (ps), and the delay of the column select signal CSL from SA0 (63) to SA32 (33) is 359 ps. This results in a tRCD deviation of approximately 0.5 nanoseconds (ns) from BLK0 (BLK63) to BLK32 (33). Because it is difficult to predict the deviation between the amplifier control signal and the CSL signal based on the growth pattern of the delay, the tRCD between different memory blocks varies greatly, making it impossible to adjust tRCD to meet industry standards, resulting in the memory not functioning properly.

[0063] In another embodiment of the present disclosure, see Figure 2 , the memory 100 includes a storage block area 110 and a first transmission circuit 120;

[0064] The storage block area 110 includes a first storage area 111 and a second storage area 112 arranged along the X-axis direction, and the top side of the first storage area 111, the bottom side of the first storage area 111, the top side of the second storage area 112, and the bottom side of the second storage area 112 are arranged in sequence along the X-axis direction;

[0065] The first transmission circuit 120 includes a first branch 121 and a second branch 122. In the X-axis direction, the first branch 121 extends at least from the top side of the first storage area 111 to the bottom side of the first storage area 111; the second branch 122 extends at least from the bottom side of the second storage area 112 to the top side of the second storage area 112.

[0066] The first transmission circuit 120 is configured to output the amplified control signal to the first storage area 111 through the first branch 121 , and to output the amplified control signal to the second storage area 112 through the second branch 122 .

[0067] It should be noted that Figure 2 Only the memory block region 110 and the first transfer circuit 120 are shown, and the connection relationship between the memory block region 110 and the first transfer circuit 120 is not shown.

[0068] Here, the first storage area 111 and the second storage area 112 each include a plurality of sense amplifiers SA arranged along the X-axis. The larger the size of the storage area along the X-axis, the greater the number of sense amplifiers SA allocated to the storage area. In implementation, the sizes of the first storage area 111 and the second storage area 112 along the X-axis can be adjusted based on actual needs.

[0069] For example, the dimensions of the first storage area 111 and the second storage area 112 along the X-axis direction can be the same. In this way, the number of sensitive amplifiers SA in the first storage area 111 and the second storage area 112 is the same, so that the delay of the amplification control signal at the bottom of the first storage area 111 and the top of the second storage area 112 is the same. In this way, the tRCD of the signal transmitted to the bottom of the first storage area 111 or the top of the second storage area 112 can be estimated, that is, the maximum value of tRCD in the storage block area 110 can be estimated, so that the maximum value of tRCD can be adjusted so that the tRCD between all storage blocks can meet the industry standard requirements.

[0070] For another example, the sizes of the first storage area 111 and the second storage area 112 along the X-axis direction can be different. In this way, the delay of amplifying the control signal in the storage area with the smaller size can be reduced, which is conducive to reducing the response time of the storage area with the smaller size.

[0071] Similarly, the portion of the first branch 121 near the first storage area 111 can have the same size as the first storage area 111 along the X-axis, and the portion of the second branch 122 near the second storage area 112 can have the same size as the second storage area 112 along the X-axis. This ensures that the time intervals between transmissions to any two adjacent sense amplifiers SA are the same, facilitating the prediction of storage area delays.

[0072] In other embodiments, the portion of the first branch 121 near the first storage area 111 may have different dimensions along the X-axis than the first storage area 111, and / or the portion of the second branch 122 near the second storage area 112 may have different dimensions along the X-axis than the second storage area 112. For example, the portion of the first branch 121 near the first storage area 111 may be smaller than the dimension of the first storage area 111 along the X-axis. This reduces the distance over which the first branch 121 transmits the amplified control signal to the first storage area 111, thereby reducing the delay in transmitting the amplified control signal. For another example, the portion of the second branch 122 near the second storage area 112 may be smaller than the dimension of the second storage area 112 along the X-axis. This reduces the distance over which the second branch 122 transmits the amplified control signal to the second storage area 112, thereby reducing the delay in transmitting the amplified control signal.

[0073] Please continue to refer to Figure 2 The amplified control signal is output via a row decoder (not shown) and serves as the input signal to the sense amplifier SA, which functions during the sensing phase. The amplified control signal includes an amplified control signal RSANT_MID and an amplified control signal RSANT_EDGE. The amplified control signal RSANT_MID is output to the second storage area 112 via the second branch 122, while the amplified control signal RSANT_EDGE is output to the first storage area 111 via the first branch 121.

[0074] In the embodiment of the present disclosure, since the amplification control signal is transmitted to the sensitive amplifier in sequence from both sides of the storage block area through the first branch and the second branch, the delay of the amplification control signal at both ends of the input storage block area is minimized, and the delay of the amplification control signal of the intermediate storage block is maximized. In other words, the delay of the CSL signal and the amplification control signal of the intermediate storage block is maximized. As long as the tRCD of the intermediate storage block meets the industry standard requirements, the tRCD of all storage blocks meets the industry standard requirements, thereby improving the working performance of the memory.

[0075] In some embodiments, please refer to Figure 3 The first storage area 111 includes a plurality of storage blocks BLK sequentially arranged along the X-axis direction, and the second storage area 112 includes a plurality of storage blocks BLK sequentially arranged along the X-axis direction, and a sense amplifier SA is set between every two storage blocks BLK; Figure 3As shown by the middle arrow, the first branch 121 transmits the amplification control signal from the signal terminal 130 to the top side of the first storage area 111; and outputs the amplification control signal to the multiple sense amplifiers SA in the first storage area 111 in sequence along the top side of the first storage area 111 to the bottom side of the first storage area 111; the second branch 122 outputs the amplification control signal to the multiple sense amplifiers SA in the second storage area 112 in sequence along the bottom side of the second storage area 112 to the top side of the second storage area 112.

[0076] Here, the first storage area 111 includes 33 storage blocks BLK arranged in sequence along the X-axis direction, namely storage block BLK0 to storage block BLK0L / 32; the second storage area 112 includes 33 storage blocks BLK arranged in sequence along the X-axis direction, namely storage block BLK0L / 32 to storage block BLK32L; wherein, the first storage area 111 and the second storage area 112 share one storage block BLK0L / 32.

[0077] Also, please continue to refer to Figure 3 A sense amplifier SA0 is provided between memory blocks BLK0 and BLK1, a sense amplifier SA1 is provided between memory blocks BLK1 and BLK2, ..., and a sense amplifier SA31 is provided between memory blocks BLK31 and BLK0L / 32. A first branch 121 sequentially transmits the amplified control signal RSANT_EDGE to the sense amplifiers SA0, ..., and SA31. A sense amplifier SA32 is provided between memory blocks BLK0L / 32 and BLK33, a sense amplifier SA33 is provided between BLK33 and BLK34, ..., and a sense amplifier SA63 is provided between memory blocks BLK63 and BLK32L. A second branch 122 sequentially transmits the amplified control signal RSANT_MID to the sense amplifiers SA63, ..., and SA32.

[0078] In some embodiments, please refer to Figure 3The input end of the first branch 121 and the input end of the second branch 122 are the same signal end 130. The signal end 130 is located on the bottom side of the second storage area 112 and is used to receive the amplification control signal. In the X-axis direction, the first branch 121 extends from the signal end 130 to the top side of the first storage area 111, bends, and then continues to extend through the top side of the first storage area 111 to the bottom side of the first storage area 111. In the X-axis direction, the second branch 122 extends from the signal end 130 to the top side of the second storage area 112, and the projection of the second branch 122 along the Y-axis direction does not overlap with the projection of the first storage area 111 along the Y-axis direction. Accordingly, the length of the first branch 121 is greater than the length of the second branch 122, and the first branch 121 and the second branch 122 do not overlap.

[0079] Here, since the amplification control signal RSANT_MID and the amplification control signal RSANT_EDGE are outputted through the same row decoder, the amplification control signal RSANT_MID and the amplification control signal RSANT_EDGE have the same signal terminal 130 .

[0080] Please note that, please refer to Figure 3 In the embodiment of the present disclosure, the signal terminal 130 is located at the bottom side of the second storage area 112. In other embodiments, the signal terminal 130 can be located at any position on the side of the first storage area 111 and the second storage area 112; for example, please refer to Figure 4 , the signal terminal 130 may be located at the top side of the first storage area 111. Correspondingly, the first branch 121 outputs the amplification control signal RSANT_EDGE to the multiple sense amplifiers SA in the first storage area 111 in sequence along the top side of the first storage area 111 to the bottom side of the first storage area 111. The second branch 122 transmits the amplification control signal from the signal terminal 130 to the bottom side of the second storage area 112, and then outputs the amplification control signal RSANT_MID to the multiple sense amplifiers SA in the second storage area 112 in sequence along the bottom side of the second storage area 112 to the top side of the second storage area 112. For another example, please refer to Figure 5The signal terminal 130 may be located near the bottom side of the first storage area 111. Correspondingly, after the first branch 121 transmits the amplification control signal from the signal terminal 130 to the top side of the first storage area 111, it sequentially outputs the amplification control signal RSANT_EDGE to the multiple sense amplifiers SA in the first storage area 111 along the top side of the first storage area 111 to the bottom side of the first storage area 111; after the second branch 122 transmits the amplification control signal from the signal terminal 130 to the bottom side of the second storage area 112, it sequentially outputs the amplification control signal RSANT_MID to the multiple sense amplifiers SA in the second storage area 112 along the bottom side of the second storage area 112 to the top side of the second storage area 112.

[0081] Please continue to refer to Figure 3 The projection of the second branch 122 along the Y-axis direction does not overlap with the projection of the first storage area 111 along the Y-axis direction. In this way, the second branch 122 can be located on one side of the second storage area 112 along the Y-axis direction, and the first branch 121 can be located on one side of the first storage area 111 along the Y-axis direction, so that the space of the memory 10 can be effectively utilized and the space utilization rate can be improved.

[0082] Please refer to Figure 3 The length of the first branch 121 is greater than that of the second branch 122, and the first branch 121 and the second branch 122 do not overlap. In this way, by reasonably laying out the first branch 121 and the second branch 122, the transmission line can be effectively utilized.

[0083] In other embodiments, the projection of the first branch 121 along the Y-axis direction may not overlap with the projection of the second storage area 112 along the Y-axis direction. Figure 4 The length of the first branch 121 is less than the length of the second branch 122, and the first branch 121 and the second branch 122 do not overlap. In this way, by reasonably laying out the first branch 121 and the second branch 122, the transmission line can be effectively utilized. Alternatively, please refer to Figure 5 The length of the first branch 121 is approximately equal to the length of the second branch 122, and the first branch 121 and the second branch 122 do not overlap, so that the signal transmission distance between the first branch 121 and the second branch 122 is almost equal, which is beneficial to improving the delay of the amplified control signal transmitted to the sensitive amplifier SA.

[0084] Next, the signal terminal 130 is located at the bottom side of the second storage area 112 (eg Figure 3Taking the example of FIG. 1 and FIG. 2 as an example, other structures in the memory 100 are described. The case where the signal terminal 130 is located at any position on one side of the first storage area 111 and the second storage area 112 is similar to the case where the signal terminal 130 is located at the bottom side of the second storage area 112, and will not be described in detail here.

[0085] In some embodiments, the number of delay units on the first branch 121 is less than the number of delay units on the second branch 122 .

[0086] Here, since the length of the first branch 121 is greater than the length of the second branch 122, the signal transmission path on the first branch 121 is greater than the signal transmission path on the second branch 122. Accordingly, more delay units need to be added to the second branch 122 to ensure that the amplified control signals on the first branch 121 and the second branch 122 can be simultaneously input into the first storage area 111 and the second storage area 112.

[0087] In some embodiments, the load of the first branch 121 is smaller than the load of the second branch 122 .

[0088] Here, since the length of the first branch 121 is greater than the length of the second branch 122, the signal transmission path on the first branch 121 is greater than the signal transmission path on the second branch 122. Correspondingly, it is necessary to make the load of the first branch 121 smaller than the load of the second branch 122, so that the speed of signal transmission on the first branch 121 is greater than the speed of signal transmission on the second branch 122, thereby ensuring that the amplification control signals on the first branch 121 and the second branch 122 can be simultaneously input into the first storage area 111 and the second storage area 112.

[0089] It should be noted that Figure 3 The delay unit and the load are not shown.

[0090] In some embodiments, please refer to Figure 3 The first branch 121 includes a first extension portion 131, a first bend portion 132, and a second extension portion 133 connected in sequence; wherein the first extension portion 131 extends upward from the signal end 130 along the X-axis direction to the top side of the first storage area 111; the first bend portion 132 extends a first preset distance d1 from the end of the first extension portion 131 toward the direction close to the storage block area 110; the second extension portion 133 extends downward from the end of the first bend portion 132 along the X-axis direction to the bottom side of the first storage area 111.

[0091] It should be noted that the amplified control signal in the first extending portion 131 is the amplified control signal RSANT_SKEW, and after passing through the first extending portion 131 , the amplified control signal transmitted to the second extending portion 133 is the amplified control signal RSANT_EDGE.

[0092] Here, the first extension portion 131 and the first bending portion 132 transmit the amplified control signal RSANT_SKEW from the signal end 130 to the top side of the first storage area 111, so that the amplified control signal RSANT_SKEW can be sequentially transmitted from the top side of the first storage area 111 to the first storage area 111 from top to bottom.

[0093] In addition, the first extension portion 131 and the second extension portion 133 in the embodiment of the present disclosure can both extend along the X-axis direction, that is, the first extension portion 131 and the second extension portion 133 are parallel to each other. In this way, the length of the first branch 121 can be minimized, thereby reducing the delay of the signal on the first branch 121.

[0094] In some embodiments, please refer to Figure 3 The first branch 121 further includes a plurality of first sub-branches 134, which extend along the Y-axis direction and are arranged along the X-axis direction; the input ends of the plurality of first sub-branches 134 are connected to the second extension portion 133, and the output ends of the plurality of first sub-branches 134 are connected one-to-one with the plurality of sensitive amplifiers SA in the first storage area 111 to output amplification control signals to the plurality of sensitive amplifiers SA in the first storage area 111.

[0095] Here, the amplification control signal RSANT_EDGE is sequentially transmitted to the first sub-branches 134 arranged along multiple X-axis directions through the second extension portion 133 ; the first sub-branches 134 transmit the received signals to the corresponding sense amplifiers SA0 to SA31 .

[0096] In some embodiments, please refer to Figure 3 The second branch 122 includes a second bending portion 141 and a third extending portion 142 connected in sequence; wherein the second bending portion 141 extends a second preset distance d2 from the signal end 130 toward the direction close to the storage block area 110; the third extending portion 142 extends upward from the end of the second bending portion 141 along the X-axis direction to the top side of the second storage area 112.

[0097] Here, after passing through the second bending portion 141 , the amplified control signal RSANT_MID may be sequentially transmitted from the bottom side of the second storage area 112 to the top.

[0098] In addition, the first extension portion 131 and the third extension portion 142 in the embodiment of the present disclosure can both extend along the X-axis direction, that is, the first extension portion 131 and the third extension portion 142 are parallel to each other. In this way, the length of the first branch 121 can be minimized, thereby reducing the delay of the signal on the first branch 121.

[0099] In some embodiments, Figure 3 As shown in the memory 100, based on Figure 6 As shown, the first extension portion 131 , the second extension portion 133 and the third extension portion 142 further include a plurality of signal drivers 150 . Each signal driver 150 is formed by an even number of inverters connected in series. The signal driver 150 is used to perform signal enhancement processing on the transmitted amplified control signal.

[0100] Here, two inverters are connected in series to form a signal driver 150. Furthermore, the signal driver 150 located on the second extension portion 133 can be provided at the input end of the second extension portion 133, and the signal driver 150 located on the third extension portion 142 can be provided at the input end of the third extension portion 142. This allows the delay of the amplified control signal transmitted to the second extension portion 133 and the third extension portion 142 to increase uniformly, facilitating the estimation of tRCD.

[0101] In some embodiments, the electrical path of the first extension portion 131 is formed at least through the first metal layer, the electrical path of the second extension portion 133 is formed at least through the second metal layer, and the electrical path of the third extension portion 142 is formed at least through the second metal layer, and the resistance of the first metal layer is less than the resistance of the second metal layer; among the first extension portion 131, the second extension portion 133 and the third extension portion 142, the signal enhancement amplitude provided by the signal driver 150 in the first extension portion 131 is the largest.

[0102] It should be understood that the first metal layer is located on the surface of the second metal layer along the Z-axis direction. Since the higher the metal layer, the smaller the resistance on the metal layer, the resistance of the first metal layer is smaller than that of the second metal layer.

[0103] Please continue to refer to Figure 6 Since the lengths of the second extension portion 133 and the third extension portion 142 are equal, and the lengths of the first bend portion 132 and the second bend portion 141 are equal, the first branch 121 is longer than the second branch 122 by the length of the first extension portion 131. Therefore, it is necessary to reduce the delay of the signal on the first extension portion 131 as much as possible, so it is necessary to set the first extension portion 131 on a higher metal layer with lower resistance to reduce the delay on the first extension portion 131.

[0104] In some embodiments, among the first extending portion 131 , the second extending portion 133 , and the third extending portion 142 , the signal driver 150 in the first extending portion 131 has the largest size.

[0105] Here, since the larger the size of the signal driver 150, the better the performance of the signal driver 150, the greater the amplitude of the amplification control signal enhancement, and the smaller the delay of the amplification control signal, therefore, setting the size of the signal driver 150 in the first extension portion 131 to the maximum can effectively reduce the delay of the signal on the first extension portion 131.

[0106] Furthermore, since the amplified control signal is transmitted through the first extension portion 131 on the first branch 121 to the second extension portion 133 and directly transmitted to the third extension portion 142 on the second branch 122, although the delay in the first extension portion 131 is reduced as described above, the delay in the amplified control signal passing through the second extension portion 133 is still greater than the delay in the third extension portion 142. Therefore, in the disclosed embodiment, the signal driver 150 in the second extension portion 133 may be of the second largest size, while the signal driver 150 in the third extension portion 142 may be of the smallest size. By setting the signal amplification in the second extension portion 133 to be greater than that in the third extension portion 142, the delay in the first extension portion 131 is compensated, ensuring that the signal transmission time from the second extension portion 133 to the first storage area 111 and from the third extension portion 142 to the second storage area 112 is equal. This ensures more uniform transmission of the amplified control signal, thereby improving the stability of the memory 10.

[0107] In some embodiments, please refer to Figure 3 and Figure 6 The second branch 122 further includes a plurality of second sub-branches 143, which extend along the Y-axis direction and are arranged along the X-axis direction; the input ends of the plurality of second sub-branches 143 are connected to the third extension portion 142, and the output ends of the plurality of second sub-branches 143 are connected one-to-one with the plurality of sensitive amplifiers SA in the second storage area 112 to output amplification control signals to the plurality of sensitive amplifiers SA in the second storage area 112.

[0108] Here, the amplification control signal RSANT_MID is sequentially transmitted to the second sub-branches 143 arranged along multiple X-axis directions through the third extension portion 142 ; the second sub-branches 143 transmit the received signals to the corresponding sense amplifiers SA63 to SA32 .

[0109] In some embodiments, please refer to Figure 3 and Figure 6 The storage block area 110 and the first transmission circuit 120 (i.e., the first branch 121 and the second branch 122) are arranged in sequence along the Y-axis direction, and the projections of the first branch 121 and the storage block area 110 in the Z-axis direction do not overlap; the projections of the second branch 122 and the storage block area 110 in the Z-axis direction do not overlap.

[0110] Here, the first transmission circuit 120 is located on one side of the storage block area 110 along the Y-axis direction, that is, the storage block area 110 is located in the array area of ​​the memory 100, and the first transmission circuit 120 is located on the outside of the memory 100. In this way, by arranging the storage block area 110 and the first transmission circuit 120 in different areas, the accumulation of heat in the memory 100 can be reduced and the performance of the memory 100 can be improved.

[0111] In some embodiments, please refer to Figure 6 The memory 100 further includes: a first column decoding circuit 161, a second column decoding circuit 162, a second transmission circuit 171, and a third transmission circuit 172; the first column decoding circuit 161 is located on a side of the first storage area 111 away from the second storage area 112, and is configured to generate a first column selection signal CSL_EDGE; the second column decoding circuit 162 is located on a side of the second storage area 112 away from the first storage area 111, and is configured to generate a second column selection signal CSL_MID; in the X-axis direction, The second transmission circuit 171 extends downward from the first column decoding circuit 161 along the X-axis direction to the bottom side of the first storage area 111 to sequentially transmit the first column selection signal CSL_EDGE to the multiple storage blocks BLK in the first storage area 111; in the X-axis direction, the third transmission circuit 172 extends upward from the second column decoding circuit 162 along the X-axis direction to the top side of the second storage area 112 to sequentially transmit the second column selection signal CSL_MID to the multiple storage blocks BLK in the second storage area 112.

[0112] Please continue to refer to Figure 6 The memory 100 further includes: a fourth transmission circuit 180, configured to receive the amplification control signal generated by the row decoder and input the amplification control signal to the signal terminal 130, wherein the fourth transmission circuit 180 is provided with a signal driver 150 to perform signal enhancement processing on the transmitted amplification control signal.

[0113] In the embodiment of the present disclosure, since the amplified control signal RSANT_EDGE is sequentially transmitted from top to bottom to the first storage area 111 through the first branch 121, and at the same time, the first column selection signal CSL_EDGE is sequentially transmitted from top to bottom to the multiple storage blocks BLK in the first storage area 111 through the second transmission circuit 171; and the amplified control signal RSANT_MID is sequentially transmitted from bottom to top to the second storage area 112 through the second branch 122, and at the same time, the second column selection signal CSL_MID is sequentially transmitted from bottom to top to the multiple storage blocks BLK in the second storage area 112 through the third transmission circuit 172; so that the amplified control signal RSANT_EDGE transmitted to the first storage area 111 The directions of DGE and the first column selection signal CSL_EDGE are the same, and the directions of the amplifying control signal CSL_MID and the second column selection signal CSL_MID transmitted to the second storage area 112 are the same. In this way, since the growth rules of the delay of the amplifying control signal and the first column selection signal CSL_EDGE are the same, not only can tRCD be estimated by the delay of the amplifying control signal RSANT_EDGE (amplifying control signal RSANT_MID) and the first column selection signal CSL_EDGE (second column selection signal CSL_MID), but also the tRCD of the storage block located in the middle of the storage block area can be adjusted to ensure that the tRCD of all storage blocks meet the industry standard requirements.

[0114] In addition, please refer to Figure 7 The embodiment of the present disclosure further provides an electronic device 700, which includes the memory 100 in the above embodiment. The memory 100 includes: a storage block area 110 and a first transmission circuit 120; the storage block area 110 includes a first storage area 111 and a second storage area 112 arranged along the X-axis direction, and the top side of the first storage area 111, the bottom side of the first storage area 111, the top side of the second storage area 112, and the bottom side of the second storage area 112 are arranged in sequence along the X-axis direction; the first transmission circuit 120 includes a first branch 121 and a second branch 122; in the X-axis direction, the first branch 121 extends at least from the top side of the first storage area 111 to the bottom side of the first storage area 111; the second branch 122 extends at least from the bottom side of the second storage area 112 to the top side of the second storage area 112; wherein the first transmission circuit 120 is configured to output an amplified control signal to the first storage area 111 through the first branch 121, and output the amplified control signal to the second storage area 112 through the second branch 122.

[0115] It should be understood that the memory 100 can be, for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDRSDRAM), etc., and no specific limitation is given here.

[0116] Furthermore, in some embodiments, the memory 100 may include a DRAM chip. The DRAM chip may conform not only to memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, and DDR6, but also to memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, and LPDDR6, and this is not specifically limited here.

[0117] The above are only preferred embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure. It should be noted that in the present disclosure, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. The above serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments. The above are only specific implementation methods of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. A memory, characterized in that: The memory includes a storage block area and a first transmission circuit; The storage block area includes a first storage area and a second storage area arranged along a first direction, and the top side of the first storage area, the bottom side of the first storage area, the top side of the second storage area, and the bottom side of the second storage area are arranged in sequence along the first direction; The first transmission circuit includes a first branch and a second branch; in the first direction, the first branch extends at least from the top side of the first storage area to the bottom side of the first storage area; the second branch extends at least from the bottom side of the second storage area to the top side of the second storage area; The first transmission circuit is configured to output the amplified control signal to the first storage area through the first branch, and output the amplified control signal to the second storage area through the second branch; The first storage area includes a plurality of storage blocks sequentially arranged along the first direction, the second storage area includes a plurality of storage blocks sequentially arranged along the first direction, and a sense amplifier is provided between every two storage blocks; The first branch transmits the amplification control signal from the signal end to the top side of the first storage area; and sequentially outputs the amplification control signal to the plurality of sense amplifiers in the first storage area along the top side of the first storage area to the bottom side of the first storage area; The second branch sequentially outputs the amplification control signal to the plurality of sense amplifiers in the second storage area along the bottom side of the second storage area to the top side of the second storage area; The input end of the first branch and the input end of the second branch are the same signal end, the signal end is located at the bottom side of the second storage area, and the signal end is used to receive the amplification control signal; In a first direction, the first branch extends from the signal end to the top side of the first storage area, bends, and then continues to extend through the top side of the first storage area to the bottom side of the first storage area; In the first direction, the second branch extends from the signal end to the top side of the second storage area, and a projection of the second branch along the second direction does not overlap with a projection of the first storage area along the second direction; Correspondingly, the length of the first branch is greater than the length of the second branch, the first branch and the second branch do not overlap, and the first direction and the second direction are perpendicular.

2. The memory according to claim 1, wherein The number of delay units on the first branch is less than the number of delay units on the second branch.

3. The memory according to claim 1 or 2, characterized in that The load of the first branch is smaller than the load of the second branch.

4. The memory according to claim 1, wherein: The first branch includes a first extension portion, a first bending portion and a second extension portion connected in sequence; wherein, The first extension portion extends upward from the signal end along a first direction to the top side of the first storage area; The first bending portion extends a first preset distance from the end of the first extending portion toward the storage block area; The second extending portion extends downward from an end of the first bent portion along the first direction to a bottom side of the first storage area.

5. The memory according to claim 4, wherein: The first branch further includes a plurality of first sub-branches, the plurality of first sub-branches extend along the second direction, and the plurality of first sub-branches are arranged along the first direction; The input ends of the plurality of first sub-branches are connected to the second extension portion, and the output ends of the plurality of first sub-branches are connected one-to-one with the plurality of sensitive amplifiers in the first storage area to output the amplification control signal to the plurality of sensitive amplifiers in the first storage area.

6. The memory according to claim 4 or 5, characterized in that The second branch includes a second bending portion and a third extending portion connected in sequence; wherein, The second bent portion extends from the signal end toward the storage block area by a second preset distance; The third extending portion extends upward from an end of the second bent portion along the first direction to a top side of the second storage area.

7. The memory according to claim 6, wherein: The first extension portion, the second extension portion and the third extension portion further include a plurality of signal drivers, each of the signal drivers being formed by an even number of inverters connected in series; The signal driver is used to perform signal enhancement processing on the transmitted amplification control signal.

8. The memory according to claim 7, wherein: The electrical path of the first extension portion is formed at least through the first metal layer, the electrical path of the second extension portion is formed at least through the second metal layer, and the electrical path of the third extension portion is formed at least through the second metal layer, and the resistance of the first metal layer is smaller than the resistance of the second metal layer; Among the first extension portion, the second extension portion, and the third extension portion, the signal driver in the first extension portion provides the largest signal enhancement amplitude.

9. The memory according to claim 8, wherein: Among the first extending portion, the second extending portion, and the third extending portion, the signal driver in the first extending portion has the largest size.

10. The memory according to any one of claims 7 to 9, characterized in that: The second branch further includes a plurality of second sub-branches, the plurality of second sub-branches extend along the second direction, and the plurality of second sub-branches are arranged along the first direction; The input ends of the plurality of second sub-branches are connected to the third extension portion, and the output ends of the plurality of second sub-branches are connected one-to-one with the plurality of sensitive amplifiers in the second storage area to output the amplification control signal to the plurality of sensitive amplifiers in the second storage area.

11. The memory according to claim 10, wherein: The storage block area and the first transmission circuit are sequentially arranged along the second direction, The projections of the first branch and the storage block area in the third direction do not overlap; the projections of the second branch and the storage block area in the third direction do not overlap; The third direction is perpendicular to a plane where the first direction and the second direction lie.

12. The memory according to claim 11, wherein: The memory further comprises: a first column decoding circuit, a second column decoding circuit, a second transmission circuit and a third transmission circuit; The first column decoding circuit is located at a side of the first storage area away from the second storage area and is configured to generate a first column selection signal; The second column decoding circuit is located at a side of the second storage area away from the first storage area and is configured to generate a second column selection signal; In the first direction, the second transmission circuit extends downward from the first column decoding circuit along the first direction to the bottom side of the first storage area to sequentially transmit the first column selection signal to the plurality of storage blocks in the first storage area; In the first direction, the third transmission circuit extends upward from the second column decoding circuit along the first direction to the top side of the second storage area to sequentially transmit the second column selection signal to multiple storage blocks in the second storage area.

13. An electronic device, characterized in that: Comprising the memory according to any one of claims 1 to 12.

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