A chip stack structure, a multi-chip package structure, and a package structure

Abstract

The chip stacking structure disclosed in the embodiment of the present disclosure comprises: a plurality of core chips stacked, each of the core chips comprising a first core chip and a second core chip stacked vertically; wherein each of the core chips is interconnected through a micro metal bump, and the first core chip and the second core chip are interconnected through a hybrid bonding piece. By using the hybrid bonding process technology between the plurality of core chips, the hybrid bonding stacking is realized, the number of micro bumps of the packaging structure is reduced, the signal transmission speed of the packaging structure is improved, the thermal resistance of the packaging structure is reduced, and the integration of the packaging structure is improved.

Description

[0001] This application is a divisional application of the Chinese Patent Application with the title of “A packaging structure and a forming method thereof”, the application number of “202210066315.0”, and the filing date of January 20, 2022. TECHNICAL FIELD

[0002] The present disclosure relates to the field of semiconductor technology, and in particular to a chip stacking structure, a multi-chip packaging structure, and a packaging structure. BACKGROUND

[0003] With the development of people's requirements for electronic products towards miniaturization and multifunctionalization, packaging also develops towards high density and high integration, and integrated circuit products also develop from two dimensions to three dimensions. Three-dimensional packaging is a promising way to meet these requirements, which has the advantages of reducing the size of the package and increasing the reliability of the circuit, thereby realizing the integration of a system or a certain function in a three-dimensional structure. Therefore, it is very meaningful to develop new packaging processes to realize the overall packaging of chips with different functions to reduce the overall size of the chip packaging, and it is also a technical problem that needs to be solved urgently at present.

[0004] However, the performance of the current packaging structure still has deficiencies, and how to optimize the performance of the packaging structure is a technical problem that needs to be solved at the present stage. SUMMARY

[0005] The present disclosure provides a packaging structure, comprising: a logic chip; a plurality of core chips stacked in a vertical direction on the logic chip in sequence; wherein the plurality of core chips comprises a first sub-core chip and a second sub-core chip interconnected by a hybrid bonding member, the hybrid bonding member comprises: a first contact pad on the surface of the first sub-core chip; a second contact pad on the surface of the second sub-core chip; a first dielectric layer located at the periphery of the first contact pad and a second dielectric layer located at the periphery of the second contact pad; the first contact pad and the second contact pad are contact bonded, and the first dielectric layer and the second dielectric layer are contact bonded.

[0006] In some embodiments, the first contact pad is formed on the active surface of the first sub-core chip, the second contact pad is formed on the active surface of the second sub-core chip, and the active surface of the first sub-core chip is bonded to the active surface of the second sub-core chip; wherein the active surface is the side of the core chip on which the device layer is formed.

[0007] In some embodiments, the first contact pad is formed on an active side of the first sub-core chip, the second contact pad is formed on a non-active side of the second sub-core chip, and the active side of the first sub-core chip is bonded to the non-active side of the second sub-core chip; wherein the active side is one side of a device layer of the core chip, and the non-active side is an opposite side of the active side.

[0008] In some embodiments, the logic chip and the core chip adjacent to the logic chip are interconnected by a first bonding member, and the first bonding member includes: a third contact pad on a surface of the logic chip; a fourth contact pad on a surface of the core chip adjacent to the logic chip; wherein the third contact pad and the fourth contact pad are bonded to each other in contact.

[0009] In some embodiments, the package structure further includes: a first via and a second via in the first dielectric layer and the second dielectric layer, respectively; the first contact pad and the second contact pad are formed in the first via and the second via, respectively; wherein a gap region is between a sidewall of the first contact pad and a sidewall of the first via; and / or a gap region is between a sidewall of the second contact pad and a sidewall of the second via.

[0010] In some embodiments, the gap region is filled with an insulating material, and a Young's modulus of the insulating material is less than a Young's modulus of the first dielectric layer and the second dielectric layer.

[0011] In some embodiments, the package structure further includes: a packaging compound above the logic chip and covering the plurality of core chips.

[0012] In some embodiments, a Young's modulus of the first dielectric layer and the second dielectric layer is less than a Young's modulus of the packaging compound.

[0013] In some embodiments, the first contact pad and the second contact pad are made of different materials.

[0014] The embodiments of the present disclosure also provide a forming method of a packaging structure, comprising: providing a logic chip, a first sub-core chip and a second sub-core chip; disposing a first contact pad and a second contact pad on surfaces of the first sub-core chip and the second sub-core chip respectively, and a first dielectric layer surrounding the first contact pad and a second dielectric layer surrounding the second contact pad; stacking the first sub-core chip and the second sub-core chip on the logic chip in sequence, so that the first contact pad and the second contact pad are butted; and performing a bonding process, so that the first contact pad and the second contact pad, the first dielectric layer and the second dielectric layer are bonded to form a hybrid bonding member.

[0015] In some embodiments, the disposing of the first contact pad and the second contact pad on the surfaces of the first sub-core chip and the second sub-core chip respectively, and the first dielectric layer surrounding the first contact pad and the second dielectric layer surrounding the second contact pad comprises: forming the first dielectric layer and the second dielectric layer on the first sub-core chip and the second sub-core chip respectively; etching the first dielectric layer and the second dielectric layer to form a first via and a second via respectively; and forming the first contact pad and the second contact pad in the first via and the second via respectively.

[0016] In some embodiments, a top surface of the first contact pad is higher than a surface of the first dielectric layer, and a top surface of the second contact pad is lower than a surface of the second dielectric layer.

[0017] In some embodiments, after the forming of the first contact pad and the second contact pad in the first via and the second via respectively, the method further comprises: etching the first contact pad, so that a gap region is formed between a sidewall of the first contact pad and a sidewall of the first via; and / or etching the second contact pad, so that a gap region is formed between a sidewall of the second contact pad and a sidewall of the second via.

[0018] In some embodiments, after the forming of the gap region, the method further comprises: depositing an insulating material, the insulating material being filled in the gap region, and a Young's modulus of the insulating material being less than a Young's modulus of the first dielectric layer and the second dielectric layer.

[0019] In some embodiments, a bonding temperature of the bonding process is less than 200 degrees Celsius.

[0020] In some embodiments, the bonding process adopts an alternating annealing process.

[0021] The present disclosure realizes hybrid bonding stacking by adopting a hybrid bonding process technology between multiple core chips, reduces the number of micro bumps of the packaging structure, improves the signal transmission speed of the packaging structure, reduces the thermal resistance of the packaging structure, and improves the integration of the packaging structure.

[0022] Additional aspects and advantages of the present disclosure will be made apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0024] Figure 1a A cross-sectional schematic view of a packaging structure of an embodiment of the present disclosure;

[0025] Figure 1b A cross-sectional schematic view of a packaging structure of another embodiment of the present disclosure;

[0026] Figure 2a An enlarged schematic view of the hybrid bonding piece in the dashed box in Figure 1a

[0027] Figure 2b An enlarged schematic view of the hybrid bonding piece in the dashed box in Figure 1a

[0028] Figure 3a A cross-sectional schematic view of a packaging structure of another embodiment of the present disclosure;

[0029] Figure 3b A cross-sectional schematic view of a packaging structure of another embodiment of the present disclosure;

[0030] Figure 4a A cross-sectional schematic view of a packaging structure of another embodiment of the present disclosure;

[0031] Figure 4b A cross-sectional schematic view of a packaging structure of another embodiment of the present disclosure;

[0032] Figure 5 A flow chart of a forming method of a packaging structure of an embodiment of the present disclosure;

[0033] Figures 6a-6h A structural schematic view of a packaging structure in a forming process of another embodiment of the present disclosure.

[0034] REFERENCE SIGNS:​​

[0035] 110 - logic chip; 120 - core chip; 121 - first sub-core chip; 122 - second sub-core chip; 130 - hybrid bond; 131 - first contact pad; 131-1 - top surface of first contact pad; 132 - second contact pad; 132-1 - top surface of second contact pad; 133 - third contact pad; 134 - fourth contact pad; 135 - first dielectric layer; 135-1 - surface of first dielectric layer; 136 - second dielectric layer; 136-1 - surface of second dielectric layer; 137 - void region; 137-1 - first via; 137-2 - second via; 138 - insulating material; 140 - encapsulation compound; 150 - via; 160 - copper pillar bump. DETAILED DESCRIPTION

[0036] Example embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings. While example embodiments of the present disclosure are shown in the drawings, it is understood that the present disclosure can be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0037] In the drawings, the size of layers, regions, elements, and the like can be exaggerated for clarity. Like reference numerals refer to like elements throughout.

[0038] It will be understood that when an element or layer is referred to as being "on" or "adjacent" another element or layer, it can be directly on the other element or layer or intervening elements or layers can also be present. In contrast, when an element is referred to as being "directly on" or "directly adjacent" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. Similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present disclosure.

[0039] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is inverted, then a dependent element or feature described as "below" or "beneath" another element or feature would then be oriented "above" and "over" the other element or feature. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0041] Micro-bump technology is a process used in early 3D stacking, mainly applied to package stacking and low-density chip stacking. This technology uses TSV in the vertical direction, i.e. signal and power transmission between the active surface and the non-active surface of the chip, and the signal is transmitted to the next layer through the micro-bump, realizing 3D interconnection between layers. In this technology, a filling material needs to be filled in the gap between layers. If micro-bump is used to realize 3D stacking, the following problems can be caused: the parasitic capacitance and inductance of the micro-bump are large, which limits the signal propagation speed; since the thermal conductivity of the filling material is much lower than that of silicon, the heat inside the chip is limited to be transferred to the outside, causing a serious heat dissipation problem; the pitch of the micro-bump is usually greater than 30 microns, and after the density is improved, it is easy to cause bridging, false welding and other problems, which cannot meet the requirements of high-density 3D interconnection.

[0042] Based on this, the embodiment of the disclosure provides a packaging structure, as shown in FIG. 1. Figure 1a and FIG. 2 shows a packaging structure, as shown in FIG. 3. Figure 2a As shown in FIG. 4, FIG. 5 shows a packaging structure, as shown in FIG. 6. Figure 2a As shown in FIG. 7, FIG. 8 shows a packaging structure, as shown in FIG. 9. Figure 1aA mixed interconnect magnified schematic view within the dashed box, the package structure includes: a logic chip 110; a plurality of core chips 120, the plurality of core chips 120 are stacked in sequence along the vertical direction on the logic chip 110; wherein the plurality of core chips 120 includes a first sub-core chip 121 and a second sub-core chip 122 interconnected by a mixed interconnect 130, the mixed interconnect 130 includes: a first contact pad 131 located on the surface of the first sub-core chip; a second contact pad 132 located on the surface of the second sub-core chip; a first dielectric layer 135 located on the periphery of the first contact pad and a second dielectric layer 136 located on the periphery of the second contact pad; the first contact pad 131 and the second contact pad 132 are contact bonded, and the first dielectric layer 135 and the second dielectric layer 136 are contact bonded. The vertically stacked core chips 120 can be interconnected by a plurality of through holes 150, such as through silicon vias (TSVs). The logic chip 110 and the core chip 120 adjacent to the logic chip can be interconnected by copper pillar bumps 160 (Copper Pillar Bump). The material of the first contact pad 131 or the second contact pad 132 includes but is not limited to one or more alloys formed by copper, gold, silver, aluminum, nickel, tungsten, titanium, tin, conductive graphene or carbon nanotubes. The material of the first dielectric layer 135 or the second dielectric layer 136 includes but is not limited to silicon oxide, spin-on silicon glass, silicon nitride, silicon oxynitride, silicon carbonitride, aluminum oxide, amorphous silicon, silicon carbide or aluminum nitride. In a specific embodiment, the material of the first dielectric layer 135 or the second dielectric layer 136 is spin-on silicon glass, which has good filling capacity and good compatibility with core chips. In other embodiments, as shown in FIG. 10, the first sub-core chip 121 or the second sub-core chip 122 can be interconnected with other core chips 120 by copper pillar bumps 160 (Copper Pillar Bump). Figure 1b

[0043] The logic chip 110 can be a processor configured to communicate with the plurality of core chips 120 to access data from the core chips 120 and store data in one or more of the plurality of core chips 120. The logic chip 110 includes but is not limited to a graphics processing unit (GPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a central processing unit (CPU) or other known electronic circuits used as a processor. The core chips include dynamic random access memory (DRAM) memory chips.

[0044] Although Figures 1a-1b Only two and four core chips are shown respectively, in other embodiments any other number of core chips can be included, such as 8, 16, 32 and 64 core chips.​

[0045] Traditional multiple core chips are generally interconnected by micro-bump. The signal delay of micro-bump is high, and the parasitic capacitance is large. The micro-bump of interconnection is prone to false welding, leading to open circuit, and the adjacent micro-bump is prone to bridging. In addition, the adjacent micro-bump needs to be filled with insulating material, and the low thermal conductivity of the insulating material will limit the heat dissipation of the packaging structure. The present disclosure uses a hybrid bonding process technology between multiple core chips to realize hybrid bonding stacking, reduce the number of micro-bumps of the packaging structure, improve the signal transmission speed of the packaging structure, and reduce the thermal resistance of the packaging structure.

[0046] In some embodiments, the packaging structure further comprises: a packaging compound 140 located above the logic chip 110 and covering the plurality of core chips 120. The material of the packaging compound 140 can be, for example, epoxy, phenolic resin, polyimide, silica gel or spin-on silicon glass, etc. The packaging compound can protect the packaging structure from external dust, moisture and mechanical impact, and improve the reliability of the packaging structure.

[0047] In some embodiments, as shown in FIG. 1, the plurality of core chips 120 are arranged in a matrix form. Figure 2a As shown in FIG. 1, the plurality of core chips 120 are arranged in a matrix form. Figure 2a As shown in FIG. 1, the plurality of core chips 120 are arranged in a matrix form. Figure 1aThe mixed bonding member in the middle dashed box is enlarged and illustrated, and the packaging structure further comprises: a first via and a second via in the first dielectric layer 135 and the second dielectric layer 136 respectively; the first contact pad 131 and the second contact pad 132 are formed in the first via and the second via respectively; wherein, a gap region 137 is formed between the sidewall of the first contact pad and the sidewall of the first via; and / or, a gap region 137 is formed between the sidewall of the second contact pad and the sidewall of the second via. By designing the contact pads of the upper and lower core chips, a gap is reserved between the contact pad and the dielectric layer to reduce the strong binding of the dielectric layer to the contact pad, so that the first contact pad and the second contact pad have sufficient deformation space when bonded, reducing or avoiding bonding defects, preventing the generation of dielectric spacing delamination, and improving yield. At the same time, due to the sufficient deformation space reserved in the transverse direction, the metal reserved amount of the contact pad can be set in the longitudinal direction, for example, the top surface of the contact pad is designed to be higher than the surface of the dielectric layer, so that the first contact pad and the second contact pad are in full contact, avoiding bonding defects (metal gap or void), and realizing mixed bonding under low temperature conditions. In some embodiments, the width of the top of the gap region 137 is greater than the width of the bottom of the gap region 137 (not shown in the figure), wherein the top of the gap region 137 refers to the end of the gap region 137 away from the core chip, and the bottom refers to the end of the gap region 137 close to the core chip. Through the above different width setting, the bonding defects can be further reduced.

[0048] In some embodiments, the Young's modulus of the first dielectric layer 135 and the second dielectric layer 136 is less than the Young's modulus of the packaging compound 140. For example, the material of the first dielectric layer 135 or the second dielectric layer 136 can be spin-on glass (SOG), which has a relatively small Young's modulus and good ductility, so as to reduce packaging stress.

[0049] In some embodiments, as shown in FIG. 2, the packaging structure further comprises: a first dielectric layer 135 and a second dielectric layer 136, wherein the first dielectric layer 135 and the second dielectric layer 136 are respectively arranged on the first core chip 110 and the second core chip 120; a first contact pad 131 and a second contact pad 132 are respectively arranged on the first dielectric layer 135 and the second dielectric layer 136; and a packaging compound 140 is arranged on the first dielectric layer 135 and the second dielectric layer 136. Figure 2bAs shown, the void region 137 is filled with an insulating material 138, the Young's modulus of which is less than that of the first dielectric layer 135 and the second dielectric layer 136. In practice, the insulating material can be an organic polymer, such as synthetic rubber, synthetic fiber, polyethylene, polyvinyl chloride, etc., or spin-coated silicone glass. Since the void region has poor thermal conductivity and is prone to chip fatigue, by setting a highly malleable insulating material as a buffer layer in the void region, the contact pad metal deforms after bonding and adheres to the insulating dielectric layer, thus reducing voids and improving bonding quality. In some embodiments, the insulating material 138 may include two parts: a lower insulating material and an upper insulating material, wherein the Young's modulus of the lower insulating material is less than that of the upper insulating material, and the lower insulating material is closer to the first sub-core chip 121 or the second sub-core chip 122 than the upper insulating material. By setting the Young's modulus of the lower insulating material to be smaller than that of the upper insulating material, the deformation caused by metal bonding can be further buffered, the voids reduced, and the bonding quality improved.

[0050] In some embodiments, the first contact pad and the second contact pad are made of different materials. In conventional techniques, metal bonding often uses the same material. However, at lower bonding temperatures, or when there are depressions on the metal surface, insufficient metal expansion of the contact pad can lead to gaps between the metals, resulting in bonding defects. By using contact pads made of different materials and utilizing the differences in their coefficients of thermal expansion, the degree of expansion of the contact pads during bonding can be flexibly and precisely controlled, improving the controllability of the bonding process and reducing gap formation.

[0051] In some embodiments, as shown in the appendix Figure 1a and attached Figure 1bAs shown, the first contact pad 131 is formed on the active surface of the first sub-core chip 121, and the second contact pad 132 is formed on the active surface of the second sub-core chip 122. The active surfaces of the first sub-core chip 121 and the second sub-core chip 122 are bonded together. The active surface is the side of the core chip 120 where the device layer (not shown) is formed. For ease of understanding, the arrows in the figure point from the non-active surface of the core chip 120 to the active surface of the core chip 120, where the non-active surface is the opposite side of the active surface. By bonding the active surfaces of multiple core chips together, the device layers of the core chips are closer together, shortening the signal transmission path between core chips and improving transmission speed. In practical operation, the first sub-core chip 121 and the second sub-core chip 122 can be first hybrid-bonded, and then the hybrid-bonded core chip 120 can be bonded to the logic chip 110. In this process, the active surface of the first sub-core chip 121 is bonded to the active surface of the second sub-core chip 122. Due to the symmetrical structure, the stress distribution is more uniform, which improves the bonding quality.

[0052] In some embodiments, as shown in the appendix Figure 3a and attached Figure 3b As shown, the first contact pad 131 is formed on the active surface of the first sub-core chip 121, and the second contact pad 132 is formed on the non-active surface of the second sub-core chip 122. The active surface of the first sub-core chip 121 and the non-active surface of the second sub-core chip 122 are bonded together. The active surface is the side of the core chip 120 where the device layer (not shown) is formed, and the non-active surface is the opposite side of the active surface. In this packaging structure, all active surfaces of the core chip 120 face one side. Compared to bonding multiple active surfaces of the core chips together, this solution does not require additional flipping of the core chip, simplifying the core chip mounting process.

[0053] In some embodiments, as shown in the appendix Figure 4a and attached Figure 4b As shown, adjacent core chips 120 are interconnected via the hybrid bonding member 130. (See attached diagram.) Figure 1b and attached Figure 3b In the described scheme, the hybrid-bonded core chip is interconnected with adjacent core chips via copper pillar bumps. Compared to micro-metal bumps, copper pillar bumps offer advantages such as increased integration density and lower resistance, but their bonding performance still cannot meet the requirements of the application. In this embodiment, adjacent core chips 120 are interconnected via hybrid bonding, which further reduces the number of micro-metal bumps in the stacked structure and improves the signal transmission speed between core chips in the stacked structure.

[0054] In some embodiments, as shown in the appendix Figure 4a and attachedFigure 4b As shown, the logic chip 110 and the core chip 120 adjacent to the logic chip are interconnected by a first bonding member, the first bonding member comprising: a third contact pad 133 on the surface of the logic chip; a fourth contact pad 134 on the surface of the core chip adjacent to the logic chip; wherein the third contact pad 133 and the fourth contact pad 134 are in contact bonding with each other. In some other embodiments, the first bonding member further comprises: a third dielectric layer (not labeled in the figure) located at the periphery of the third contact pad and a fourth dielectric layer (not labeled in the figure) located at the periphery of the fourth contact pad; the third dielectric layer and the fourth dielectric layer are in contact bonding. The core chip and the logic chip are interconnected by hybrid bonding, further reducing the number of micro-bumps of the packaging structure, being able to improve the signal transmission speed between the core chip and the logic chip, and reducing the thermal resistance of the packaging structure.

[0055] The present disclosure also provides a method for forming a packaging structure, referring to the accompanying drawings Figure 5 , the method comprising:

[0056] Step 501: providing a logic chip, a first sub-core chip and a second sub-core chip;

[0057] Step 502: disposing a first contact pad and a second contact pad on the surface of the first sub-core chip and the second sub-core chip respectively, and a first dielectric layer at the periphery of the first contact pad and a second dielectric layer at the periphery of the second contact pad;

[0058] Step 503: sequentially stacking the first sub-core chip and the second sub-core chip on the logic chip, so that the first contact pad and the second contact pad are in butt joint;

[0059] Step 504: performing a bonding process, so that the first contact pad and the second contact pad, the first dielectric layer and the second dielectric layer are bonded with each other to form a hybrid bonding member.

[0060] The following will be described in detail with reference to the accompanying drawings Figures 6a-6h The forming method of the semiconductor structure provided by the embodiments of the present disclosure will be described in detail.

[0061] First, as shown in FIG. 1, a logic chip 110, a first sub-core chip 120 and a second sub-core chip 130 are provided. Figure 6aAs shown, step 501 is performed to provide a logic chip 110, a first sub-core chip 121 and a second sub-core chip 122. The logic chip 110 includes, but is not limited to, a graphics processing unit (GPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a central processing unit (CPU) or other known electronic circuitry used as a processor. The first sub-core chip 121 or the second sub-core chip 122 includes a dynamic random access memory (DRAM) memory chip.

[0062] Next, as shown in FIG. 1B, step 502 is performed to dispose a first contact pad 131 and a second contact pad 132 on a surface of the first sub-core chip 121 and the second sub-core chip 122, respectively, and a first dielectric layer 135 surrounding the first contact pad 131 and a second dielectric layer 136 surrounding the second contact pad 132. The material of the first contact pad 131 or the second contact pad 132 includes, but is not limited to, one or more of copper, gold, silver, aluminum, nickel, tungsten, titanium, tin, conductive graphene or carbon nanotube. Figures 6b-6d Specifically, first, as shown in FIG. 1C, a first dielectric layer 135 and a second dielectric layer 136 are formed on the first sub-core chip 121 and the second sub-core chip 122, respectively. Here, the formation process of the first dielectric layer 135 and the second dielectric layer 136 includes, but is not limited to, a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, an atomic layer deposition (ALD) process or a combination thereof. The material of the first dielectric layer 135 or the second dielectric layer 136 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, aluminum oxide, amorphous silicon, silicon carbide or aluminum nitride.

[0063] Figure 6b Next, as shown in FIG. 1D, the first dielectric layer 135 and the second dielectric layer 136 are etched to form a first via 137-1 and a second via 137-2, respectively. Here, the size and shape of the via can be determined as needed. The etching process includes wet etching or dry etching, such as high-density plasma (HDP) etching or reactive ion etching (RIE).

[0064] Then, as shown in FIG. 1E, step 503 is performed to dispose a first conductive layer 141 and a second conductive layer 142 on the first dielectric layer 135 and the second dielectric layer 136, respectively. The material of the first conductive layer 141 or the second conductive layer 142 includes, but is not limited to, one or more of copper, gold, silver, aluminum, nickel, tungsten, titanium, tin, conductive graphene or carbon nanotube. Figure 6c Finally, as shown in FIG. 1F, step 504 is performed to dispose a first conductive layer 141 and a second conductive layer 142 on the first dielectric layer 135 and the second dielectric layer 136, respectively. The material of the first conductive layer 141 or the second conductive layer 142 includes, but is not limited to, one or more of copper, gold, silver, aluminum, nickel, tungsten, titanium, tin, conductive graphene or carbon nanotube.

[0065] Figure 6d ​​As shown, the first contact pad 131 and the second contact pad 132 are formed in the first via 137-1 and the second via 137-2, respectively. The forming process of the first contact pad 131 and the second contact pad 132 can be physical vapor deposition (PVD) or chemical vapor deposition (CVD). In actual operation, a first contact pad material layer and a second contact pad material layer can be deposited above the first dielectric layer and the second dielectric layer, respectively, and a planarization process, such as chemical mechanical polishing (CMP), is performed to form the first contact pad and the second contact pad.

[0066] In an embodiment, the top surface 131-1 of the first contact pad is higher than the surface 135-1 of the first dielectric layer, and the top surface 132-1 of the second contact pad is lower than the surface 136-1 of the second dielectric layer. When performing the planarization process, the polishing rates of the dielectric layer and the contact pad are different, which often causes the metal surface to be concave, and even easily causes local over-polishing, resulting in serious dishing defects. At this time, when performing the bonding process, the dielectric layer contacts the dielectric layer first, and the metal contacts the metal due to the concave gap. If the bonding temperature is not high enough, the metal expansion is not enough to cause the gap between the metals, which further causes the bonding defects. The present solution designs the contact pad so that the top surface of one of the contact pads is higher than the surface of the dielectric layer, and the metal reserved amount of the contact pad can ensure that the contact pad is fully contacted during bonding, thereby improving the bonding quality. In actual operation, a first contact pad material layer can be deposited above the first dielectric layer, and the first contact pad material layer covering the surface of the first dielectric layer is etched by a mask to reserve the contact pad material layer in the first via, so that the top surface 131-1 of the first contact pad is higher than the surface 135-1 of the first dielectric layer. In other embodiments, the first dielectric layer can be etched after the planarization process to form the first contact pad, so that the top surface 131-1 of the first contact pad is higher than the surface 135-1 of the first dielectric layer. The top surface 132-1 of the second contact pad being lower than the surface 136-1 of the second dielectric layer can be caused by the dishing defect caused by the planarization process, or can be designed and formed by etching the second contact pad.

[0067] In an embodiment, as shown in FIG. 1C, the first dielectric layer 135 and the second dielectric layer 136 are formed on the substrate 110, and the first contact pad 131 and the second contact pad 132 are formed in the first via 137-1 and the second via 137-2, respectively. The first contact pad 131 and the second contact pad 132 can be formed by physical vapor deposition (PVD) or chemical vapor deposition (CVD). Figure 6eAs shown, after forming a first contact pad 131 and a second contact pad 132 in the first through-hole 137-1 and the second through-hole 137-2 respectively, the method further includes: etching the first contact pad to form a gap region 137 between the sidewall of the first contact pad and the sidewall of the first through-hole; and / or etching the second contact pad to form a gap region 137 between the sidewall of the second contact pad and the sidewall of the second through-hole. By leaving a gap between the contact pad and the dielectric layer, the strong binding of the dielectric layer on the contact pad is reduced, allowing sufficient deformation space for the first and second contact pads to bond, reducing or avoiding bonding defects, preventing dielectric delamination, and improving yield. In other embodiments, a gap region can be formed between the first contact pad and the first dielectric layer by etching a portion of the first dielectric layer, and / or a gap region can be formed between the second contact pad and the second dielectric layer by etching a portion of the second dielectric layer.

[0068] In one embodiment, as shown in the appendix Figure 6f As shown, after forming the void region 137, the method further includes: depositing an insulating material 138, which fills the void region 137. The Young's modulus of the insulating material is less than that of the first dielectric layer 135 and the second dielectric layer 136. In practice, the insulating material can be an organic polymer, such as synthetic rubber, synthetic fiber, polyethylene, polyvinyl chloride, etc. Because the void region has poor thermal conductivity and is prone to chip fatigue, by setting a highly malleable insulating material as a buffer layer in the void region, the contact pad metal deforms after bonding and adheres to the insulating dielectric layer, thus reducing voids and improving bonding quality.

[0069] Next, as attached Figure 6g As shown, in step 503, the first sub-core chip 121 and the second sub-core chip 122 are sequentially stacked on the logic chip 110, such that the first contact pad 131 and the second contact pad 132 are mated. It should be noted that the logic chip and the core chip adjacent to it can be interconnected via copper pillar bumps (not shown in the figure). In other embodiments, the logic chip and the core chip adjacent to it can be interconnected via hybrid bonding elements. Optionally, before mating the first contact pad 131 and the second contact pad 132, the first sub-core chip 121 or the second sub-core chip 122 can be surface activated. The activation methods include plasma surface treatment, ion powder or atomic surface treatment, etc., to remove surface particles and oxide layers, ensuring the bonding interface performance.

[0070] Finally, as attachedFigure 6h As shown, step 504 is performed to carry out a bonding process to bond the first contact pad 131 and the second contact pad 132, and the first dielectric layer 135 and the second dielectric layer 136 to form a hybrid bonding member 130. The bonding temperature and pressure are determined according to the materials of the dielectric layers and the contact pads, and the corresponding pressure has a corresponding relationship with the required temperature, which is consistent with the conventional bonding temperature and pressure, and will not be described in detail here.

[0071] In some embodiments, the bonding temperature of the bonding process is less than 200 degrees Celsius. By designing the contact pads of the upper and lower core chips, the contact pads of one layer are higher than the dielectric layer, and the metal allowance of the contact pads can ensure that the contact pads are in sufficient contact during bonding, without the need to apply high temperature to make the contact pad metal expand, so that low-temperature bonding can be achieved, the thermal damage of the packaging structure is small, and the thermal budget is reduced.

[0072] In some embodiments, the bonding process adopts an alternating annealing process. The alternating annealing process refers to an annealing method that alternately changes the annealing temperature, for example, alternating annealing at two temperatures of 150 degrees Celsius and 180 degrees Celsius. By alternating multiple times, the multiple times of melting bonding can reduce internal voids (gaps or cavities between metals) and improve the internal uniformity of the hybrid bonding member. In another embodiment, the alternating annealing process includes a first temperature and a second temperature, wherein the first temperature is less than 200 degrees Celsius, and the second temperature is greater than 200 degrees Celsius. For example, alternating annealing at a first temperature of 100 degrees Celsius, 125 degrees Celsius, 150 degrees Celsius, or 175 degrees Celsius, and a second temperature of 225 degrees Celsius, 250 degrees Celsius, 275 degrees Celsius, 300 degrees Celsius, 400 degrees Celsius, 500 degrees Celsius, or 600 degrees Celsius. Low temperature can make the thermal damage of the packaging structure small, and reduce the thermal budget, but there may be insufficient expansion of the contact pad metal during bonding, resulting in bonding defects. High temperature can make the contact pads fully contact during bonding, but it may cause thermal damage. By adopting the alternating annealing process of high and low temperatures, the bonding quality can be effectively improved while reducing thermal damage.

[0073] In summary, the present disclosure achieves hybrid bonding stacking by adopting a hybrid bonding process technology between multiple core chips, reduces the number of micro-bumps of the packaging structure, improves the signal transmission speed of the packaging structure, reduces the thermal resistance of the packaging structure, and improves the integration of the packaging structure.

[0074] It is noted that the packaging structure and the forming method thereof provided by the embodiments of the present disclosure can be applied to any integrated circuit including the structure, including but not limited to vertical integration of processed integrated circuits, and is used for 3D SOC, micro-pad packaging, low-cost and high-performance replacement flip-chip, wafer-level packaging, thermal management, unique device structure (such as metal base device). Applications further include but are not limited to integrated circuits (such as back-illuminated image sensors), RF front ends, micro-electrical mechanical structures (MEMS) (including but not limited to pico-projectors and gyroscopes), 3D stacked memories (including but not limited to hybrid memory cubes), high-bandwidth memories, DIRAM, 2.5D (including but not limited to FPGAs tilted on interposers), and products using these circuits (including but not limited to mobile phones and other mobile devices, laptops, servers).

[0075] The technical features in the technical solutions described in the embodiments can be combined in any manner without conflict. Those skilled in the art can change the order of the steps of the forming method described above without departing from the protection scope of the present disclosure. The steps in the embodiments of the present disclosure can be executed simultaneously or in sequence without conflict.

[0076] The above is only a preferred embodiment of the present disclosure, and is not intended to limit the protection scope of the present disclosure. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A chip stack structure, characterized by, The application comprises: a plurality of core chips stacked, each of the core chips comprising a first sub-core chip and a second sub-core chip stacked vertically; wherein each of the core chips is only interconnected by micro metal bumps, and the first sub-core chip and the second sub-core chip are only interconnected by hybrid bonding.

2. The chip stack structure of claim 1, wherein, The hybrid bonding comprises a first contact pad and a second contact pad arranged on a surface of the first sub-core chip and a surface of the second sub-core chip respectively, and the first sub-core chip and the second sub-core chip are directly bonded and interconnected through the first contact pad and the second contact pad.

3. The chip stack structure of claim 2, wherein, The first contact pad is located on an active surface of the first sub-core chip, and the second contact pad is located on an active surface or a non-active surface of the second sub-core chip.

4. The chip stack structure of claim 1, wherein, Each of the core chips is interconnected by copper pillar bumps.

5. The chip stack structure of claim 3, wherein, The hybrid bonding further comprises a first dielectric layer arranged on the active surface of the first sub-core chip, and a second dielectric layer arranged on the active surface or the non-active surface of the second sub-core chip, and the first dielectric layer and the second dielectric layer are directly bonded and interconnected.

6. The chip stack structure of claim 5, wherein, The first dielectric layer and the first contact pad have a gap region therebetween; and / or, the second dielectric layer and the second contact pad have a gap region therebetween, and a width of a top of the gap region is greater than a width of a bottom of the gap region.

7. The chip stack structure of claim 6, wherein, The gap region between the first dielectric layer and the first contact pad has an insulating material thereinside; and / or, the gap region between the second dielectric layer and the second contact pad has the insulating material thereinside, wherein a Young's modulus of the insulating material is less than a Young's modulus of the first dielectric layer and / or the second dielectric layer.

8. The chip stack structure of claim 5, wherein, A packaging compound is further included, which is located between and covers each of the core chips, and a Young's modulus of the packaging compound is greater than a Young's modulus of the first dielectric layer and the second dielectric layer.

9. A multi-chip package structure, comprising: The application comprises: a logic chip and a core chip located on the logic chip, the logic chip is electrically connected with the core chip; a plurality of the core chips are only interconnected by micro metal bumps, the core chip comprises a first sub-core chip and a second sub-core chip located on the first sub-core chip, and the first sub-core chip and the second sub-core chip are only interconnected by hybrid bonding.

10. The multi-chip package structure of claim 9, wherein, The logic chip and the core chip are interconnected by micro metal bumps.

11. The multi-chip package structure of claim 9, wherein, The logic chip and the core chip are hybrid bonded by a first bonding, the first bonding comprises a third contact pad located on a surface of the logic chip and a fourth contact pad located on a surface of the core chip adjacent to the logic chip, and the third contact pad and the fourth contact pad are bonded and contacted with each other.

12. A package structure, characterized by, The application comprises: a plurality of core chips, a plurality of the core chips are only interconnected by micro metal bumps, each of the core chips comprises a first sub-core chip and a second sub-core chip, and the first sub-core chip and the second sub-core chip are only interconnected by hybrid bonding. A logic chip, the logic chip being interconnected with at least one core chip of the plurality of core chips through micro metal bump interconnects.

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