Array substrate and display panel

Abstract

The present application discloses an array substrate and a display panel. The array substrate includes a substrate, a first electrode, a first insulating layer, an auxiliary conductive layer, a second electrode, a semiconductor layer, a second insulating layer, and a gate electrode. The substrate, first insulating layer, auxiliary conductive layer, and second electrode are stacked, the auxiliary conductive layer is electrically connected to the second electrode, a first portion of the semiconductor layer is disposed on a side of the first electrode away from the substrate, a second portion of the semiconductor layer is disposed on a side of the first insulating layer, and a third portion of the semiconductor layer is disposed on the surface of the second electrode and the auxiliary conductive layer. The distance from the side of the auxiliary conductive layer facing the semiconductor layer to the side of the first insulating layer facing the semiconductor layer is less than or equal to 0.7 microns, and the distance from the side of the second electrode facing the semiconductor layer to the side of the auxiliary conductive layer facing the semiconductor layer is greater than 0. The present application aims to reduce fluctuations in the channel length of the semiconductor layer to improve the electrical stability of thin-film transistor devices.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] In thin film transistor (TFT) devices, as the channel length decreases, the precision required for the process of manufacturing the TFT devices becomes higher and higher.

[0003] However, in traditional short-channel thin-film transistor devices, due to the limited precision of the process, the channel length fluctuates greatly during the actual process, resulting in reduced electrical stability of the thin-film transistor device.

[0004] Therefore, it is necessary to propose a new technical solution to solve the above technical problems. Summary of the Invention

[0005] The purpose of the present application is to provide an array substrate and a display panel, aiming to reduce the fluctuation of the channel length of the semiconductor layer to improve the electrical stability of the thin film transistor device.

[0006] To solve the above problems, the technical solutions of this application are as follows:

[0007] In a first aspect, the present application proposes an array substrate, comprising:

[0008] substrate;

[0009] A first electrode is provided on the substrate;

[0010] a first insulating layer, provided on a side of the first electrode away from the substrate;

[0011] an auxiliary conductive layer, provided on a side of the first insulating layer away from the substrate;

[0012] a second electrode, disposed on a side of the auxiliary conductive layer away from the substrate and electrically connected to the first electrode;

[0013] a semiconductor layer comprising a first portion provided on a side of the first electrode away from the substrate, a second portion provided on a side of the first insulating layer, and a third portion provided on a surface of the second electrode and the auxiliary conductive layer;

[0014] a second insulating layer, disposed on a side of the semiconductor layer away from the substrate; and

[0015] a gate, disposed on a side of the second insulating layer away from the substrate;

[0016] The distance from the side of the auxiliary conductive layer facing the semiconductor layer to the side of the first insulating layer facing the semiconductor layer is less than or equal to 0.7 microns, and the distance from the side of the second electrode facing the semiconductor layer to the side of the auxiliary conductive layer facing the semiconductor layer is greater than 0.

[0017] In one embodiment of the present application, the thickness of the auxiliary conductive layer is smaller than the thickness of the second electrode, and the thickness of the auxiliary conductive layer is smaller than the thickness of the first insulating layer.

[0018] In one embodiment of the present application, the thickness of the auxiliary conductive layer is in a range of 100 angstroms to 1000 angstroms.

[0019] In one embodiment of the present application, the resistivity of the material of the auxiliary conductive layer is lower than the resistivity of the material of the second electrode.

[0020] In one embodiment of the present application, the resistivity of the material of the auxiliary conductive layer is less than 0.00001 ohm·meter.

[0021] In one embodiment of the present application, a side surface of the auxiliary conductive layer facing the semiconductor layer is flush with a side surface of the first insulating layer facing the semiconductor layer;

[0022] The channel of the semiconductor layer is provided on a side of the first insulating layer facing the semiconductor layer.

[0023] In one embodiment of the present application, the semiconductor layer includes:

[0024] a first conductor portion, provided on a side of the first electrode away from the substrate and electrically connected to the first electrode;

[0025] a first channel portion, provided on a side surface of the first insulating layer;

[0026] A second conductor portion is provided on a side surface of the auxiliary conductive layer;

[0027] a third conductor portion, provided on a side of the auxiliary conductive layer away from the first insulating layer and located on a side of the second electrode;

[0028] a fourth conductor portion, disposed on a side surface of the second electrode; and

[0029] a fifth conductor portion, provided on a side of the second electrode away from the auxiliary conductive layer;

[0030] wherein the first conductor portion, the first channel portion, the second conductor portion, the third conductor portion, the fourth conductor portion, and the fifth conductor portion are connected in sequence;

[0031] The length of the first channel portion is in a range of 1000 angstroms to 10000 angstroms.

[0032] In one embodiment of the present application, an orthographic projection of a side surface of the auxiliary conductive layer facing the semiconductor layer on the substrate is located within a range of an orthographic projection of the first insulating layer on the substrate.

[0033] In one embodiment of the present application, the absolute value of the difference between the angle A1 formed by the side of the first insulating layer facing the semiconductor layer and the plane where the substrate is located and the angle A2 formed by the side of the auxiliary conductive layer facing the semiconductor layer and the plane where the substrate is located is less than or equal to 10 degrees.

[0034] In one embodiment of the present application, the semiconductor layer includes:

[0035] a first conductor portion, provided on a side of the first electrode away from the substrate;

[0036] a first channel portion, provided on a side surface of the first insulating layer;

[0037] A second channel portion is provided on a side of the first insulating layer away from the first electrode and located on a side of the auxiliary conductive layer;

[0038] A second conductor portion is provided on a side surface of the auxiliary conductive layer;

[0039] a third conductor portion, provided on a side of the auxiliary conductive layer away from the first insulating layer and located on one side of the second electrode;

[0040] a fourth conductor portion, disposed on a side surface of the second electrode; and

[0041] a fifth conductor portion, provided on a side of the second electrode away from the auxiliary conductive layer;

[0042] The first conductor portion, the first channel portion, the second channel portion, the second conductor portion, the third conductor portion, the fourth conductor portion, and the fifth conductor portion are connected in sequence;

[0043] The length of the first channel portion is in a range of 1000 angstroms to 10000 angstroms;

[0044] The length of the second channel portion is less than or equal to 7000 angstroms.

[0045] In one embodiment of the present application, a first via hole is formed in the first insulating layer, and the first via hole exposes a surface of the first electrode away from the substrate;

[0046] The auxiliary conductive layer is extended around the circumference of the first via hole to form a second via hole, and the hole wall of the second via hole is flush with the hole wall of the first via hole;

[0047] The second electrode is extended around the circumference of the second via hole and forms a third via hole;

[0048] The first portion of the semiconductor layer is provided on a side of the first electrode exposed to the first via hole, the second portion of the semiconductor layer is provided on a hole wall of the first via hole, and the third portion of the semiconductor layer is provided on a hole wall of the second via hole and a hole wall of the third via hole;

[0049] The orthographic projection of the hole wall of the third via hole on the substrate is located outside the orthographic projection of the hole wall of the second via hole on the substrate.

[0050] In the second aspect, the present application proposes a display panel, comprising an array substrate, the array substrate comprising a substrate, a first electrode, a first insulating layer, an auxiliary conductive layer, a second electrode, a semiconductor layer, a second insulating layer and a gate, the first electrode being arranged on the substrate; the first insulating layer being arranged on a side of the first electrode away from the substrate; the auxiliary conductive layer being arranged on a side of the first insulating layer away from the substrate; the second electrode being arranged on a side of the auxiliary conductive layer away from the substrate and electrically connected to the first electrode; the semiconductor layer comprising a first part being arranged on a side of the first electrode away from the substrate, a second part being arranged on a side of the first insulating layer, and a third part being arranged on the surface of the second electrode and the auxiliary conductive layer; the second insulating layer being arranged on a side of the semiconductor layer away from the substrate; the gate being arranged on a side of the second insulating layer away from the substrate; the distance from the side of the auxiliary conductive layer facing the semiconductor layer to the side of the first insulating layer facing the semiconductor layer is less than or equal to 0.7 microns, and the distance from the side of the second electrode facing the semiconductor layer to the side of the auxiliary conductive layer facing the semiconductor layer is greater than 0.

[0051] In the present application, an auxiliary conductive layer is disposed between the second electrode and the first insulating layer. After the semiconductor layer is formed, the channel length of the semiconductor layer is the sum of the lengths of the portion of the semiconductor layer disposed on the side of the first insulating layer and the portion of the semiconductor layer disposed on the side of the auxiliary conductive layer. The fluctuation range of the channel length of the semiconductor layer depends on the distance from the side of the auxiliary conductive layer facing the semiconductor layer to the side of the first insulating layer facing the semiconductor layer, which is less than or equal to 0.7 microns. The design of the auxiliary conductive layer can reduce fluctuations in the channel length of the semiconductor layer, thereby improving the electrical stability of the thin-film transistor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 is a schematic diagram of a conventional array substrate;

[0053] Figure 2 is a schematic diagram of a first embodiment of an array substrate of the present application;

[0054] Figure 3 is a schematic diagram of a first embodiment of an array substrate of the present application;

[0055] Figure 4 is a schematic diagram of a second embodiment of an array substrate of the present application;

[0056] Figure 5 is a schematic diagram of a second embodiment of an array substrate of the present application;

[0057] Figure 6 is a schematic diagram of a third embodiment of an array substrate of the present application;

[0058] Figure 7 is a schematic diagram of the display panel of the present application. DETAILED DESCRIPTION

[0059] The meanings of the terms used in this specification and claims correspond to those commonly understood by persons of ordinary skill in the art to which this application belongs. The terms used in this specification and claims are intended solely to facilitate the description and understanding of this application and are not intended to limit this application to the narrow interpretations of the specific terms used in the specification and claims.

[0060] See also Figure 1A conventional array substrate 100a includes a substrate 10a, a buffer layer 20a, a first electrode 30a, a first insulating layer 40a, an auxiliary conductive layer 50a, a second electrode 60a, a semiconductor layer 70a, a second insulating layer 80a, and a gate electrode 90a. The first electrode 30a serves as the source electrode of the thin-film transistor device, and the second electrode 60a serves as the drain electrode of the thin-film transistor device. Since the second electrode 60a serves as the drain electrode, it is located in the same film layer as the data lines of the conventional array substrate 100a. Through a patterning process, the second electrode 60a and the data lines are formed in one step. To reduce impedance, the second electrode 60a and the data lines typically comprise at least two metal layers made of different materials. Therefore, the second electrode 60a and the data lines are relatively thick, typically exceeding 8000 angstroms. Because the etching rate of the material of the second electrode 60a differs from that of the material of the first insulating layer 40a, and the thickness and number of layers of the second electrode 60a also affect the etching rate, the etching rate is also affected. During the one-step etching process of the second electrode 60a and the first insulating layer 40a, due to the different etching rates of the side of the second electrode 60a and the side of the first insulating layer 40a, the channel lengths (L1+L2) of different thin film transistors in the same array substrate 100a may be different. For example, when the distance (L1) between the side of the second electrode 60a and the side of the first insulating layer 40a is relatively small, the channel length (L1+L2) of the thin film transistor is relatively small. When the distance (L1) between the side of the second electrode 60a and the side of the first insulating layer 40a is relatively large, the channel length of the thin film transistor is relatively large. That is, in traditional thin film transistors, the channel length of the semiconductor layer 70a fluctuates greatly and is uncontrollable, resulting in uneven electrical performance of different thin film transistors in the same array substrate 100a, resulting in poor electrical stability of the thin film transistors.

[0061] The present application proposes a display panel 1000 , which may be a liquid crystal display (LCD) panel 1000 or an organic light emitting diode (OLED) display panel 1000 . The display panel 1000 includes an array substrate 100 .

[0062] Optionally, taking the liquid crystal display panel 1000 as an example, the display panel 1000 further includes liquid crystal 200 and an opposing substrate 300. The liquid crystal 200 is disposed between the array substrate 100 and the opposing substrate 300. The opposing substrate 300 is a color filter substrate, i.e., the color filter layer is integrated into the opposing substrate 300. In some embodiments, the color filter layer can also be integrated into the array substrate 100.

[0063] See also Figure 2The present application proposes an array substrate 100, comprising a substrate 10, a first electrode 30, a first insulating layer 40, an auxiliary conductive layer 50, a second electrode 60, a semiconductor layer 70, a second insulating layer 80, and a gate 90. The first electrode 30 is disposed on the substrate 10. The first insulating layer 40 is disposed on a side of the first electrode 30 away from the substrate 10. The auxiliary conductive layer 50 is disposed on a side of the first insulating layer 40 away from the substrate 10. The second electrode 60 is disposed on a side of the auxiliary conductive layer 50 away from the substrate 10 and is electrically connected to the first electrode 30. A first portion of the semiconductor layer 70 is disposed on a side of the first electrode 30 away from the substrate 10, a second portion of the semiconductor layer 70 is disposed on a side of the first insulating layer 40, and a third portion of the semiconductor layer 70 is disposed on the surface of the second electrode 60 and the auxiliary conductive layer 50. The second insulating layer 80 is disposed on a side of the semiconductor layer 70 away from the substrate 10. The gate 90 is disposed on a side of the second insulating layer 80 away from the substrate 10. The distance (L4) between the side of the auxiliary conductive layer 50 facing the semiconductor layer 70 and the side of the first insulating layer 40 facing the semiconductor layer 70 is less than or equal to 0.7 micrometers. The distance between the side of the second electrode 60 facing the semiconductor layer 70 and the side of the auxiliary conductive layer 50 facing the semiconductor layer 70 is greater than 0.

[0064] In the present application, an auxiliary conductive layer 50 is disposed between the second electrode 60 and the first insulating layer 40. After the semiconductor layer 70 is formed, the channel length of the semiconductor layer 70 is the sum of the lengths of the portion of the semiconductor layer 70 disposed on the side of the first insulating layer 40 and the portion of the semiconductor layer 70 disposed on the side of the auxiliary conductive layer 50. The fluctuation range of the channel length of the semiconductor layer 70 depends on the distance (L4) from the side of the auxiliary conductive layer 50 facing the semiconductor layer 70 to the side of the first insulating layer 40 facing the semiconductor layer 70. This distance (L4) is less than or equal to 0.7 microns. The design of the auxiliary conductive layer 50 can reduce the fluctuation of the channel length of the semiconductor layer 70, thereby improving the electrical stability of the thin film transistor device.

[0065] In this embodiment, the distance from the side of the second electrode 60 facing the semiconductor layer 70 to the side of the auxiliary conductive layer 50 facing the semiconductor layer 70 is greater than 0, which can increase the contact area between the conductor part of the semiconductor layer 70 and the second electrode 60 and the auxiliary conductive layer 50, thereby reducing the internal impedance of the thin film transistor, increasing the on-state current of the thin film transistor, and thus enhancing the electrical stability of the thin film transistor.

[0066] Optionally, the distance (L4) from the side of the auxiliary conductive layer 50 facing the semiconductor layer 70 to the side of the first insulating layer 40 facing the semiconductor layer 70 is 0, 0.01 micron, 0.02 micron, 0.03 micron, 0.04 micron, 0.05 micron, 0.06 micron, 0.07 micron, 0.08 micron, 0.09 micron, 0.10 micron, 0.11 micron, 0.12 micron, 0.13 micron, 0.14 micron, 0.15 micron, 0.16 micron, 0.17 micron, 0.18 micron, 0.19 micron, 0.20 micron, 0.21 micron, 0.22 micron, 0.23 micron, 0.24 micron, 0.25 micron, 0.26 micron, 0.27 micron, 0.28 micron, 0.29 micron, 0.30 micron, 0.31 micron, 0.32 One of the following values: micrometer, 0.33 micrometer, 0.34 micrometer, 0.35 micrometer, 0.36 micrometer, 0.37 micrometer, 0.38 micrometer, 0.39 micrometer, 0.40 micrometer, 0.41 micrometer, 0.42 micrometer, 0.43 micrometer, 0.44 micrometer, 0.45 micrometer, 0.46 micrometer, 0.47 micrometer, 0.48 micrometer, 0.49 micrometer, 0.50 micrometer, 0.51 micrometer, 0.52 micrometer, 0.53 micrometer, 0.54 micrometer, 0.55 micrometer, 0.56 micrometer, 0.57 micrometer, 0.58 micrometer, 0.59 micrometer, 0.60 micrometer, 0.61 micrometer, 0.62 micrometer, 0.63 micrometer, 0.64 micrometer, 0.65 micrometer, 0.66 micrometer, 0.67 micrometer, 0.68 micrometer, 0.69 micrometer, or 0.70 micrometer.

[0067] Optional, see Figure 2 In the first embodiment of the present application, a distance (L4) from the side of the auxiliary conductive layer 50 facing the semiconductor layer 70 to the side of the first insulating layer 40 facing the semiconductor layer 70 is in the range of 0.01 microns to 0.70 microns.

[0068] Optional, see Figure 4 In the second embodiment of the present application, the distance (L4) between the side of the auxiliary conductive layer 50 facing the semiconductor layer 70 and the side of the first insulating layer 40 facing the semiconductor layer 70 is 0. In the second embodiment, the side of the auxiliary conductive layer 50 facing the semiconductor layer 70 is flush with the side of the first insulating layer 40 facing the semiconductor layer 70.

[0069] Optionally, the array substrate 100 further includes a buffer layer 20. The buffer layer 20 is located between the substrate 10 and the first electrode 30. The material of the buffer layer 20 includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0070] Optionally, the first electrode 30 is a source electrode of a thin film transistor device, and the second electrode 60 is a drain electrode of the thin film transistor device.

[0071] Optionally, the array substrate 100 further includes a data line. The data line and the second electrode 60 are located in the same film layer and are electrically connected to the second electrode 60.

[0072] Optionally, the material of the semiconductor layer 70 is one of amorphous silicon, a mixture of polycrystalline silicon and amorphous silicon, and indium gallium zinc oxide (IGZO). This application uses the material of the semiconductor layer 70 as an example to illustrate, and does not elaborate on the materials of other semiconductor layers 70 one by one.

[0073] Optionally, the thickness of the semiconductor layer 70 is in a range of 250 angstroms to 700 angstroms.

[0074] Optionally, the thickness of the second insulating layer 80 is in the range of 1000 angstroms to 3000 angstroms.

[0075] Optionally, the material of the first insulating layer 40 includes at least one of silicon nitride, silicon oxide and silicon oxynitride.

[0076] Optionally, the material of the second insulating layer 80 includes at least one of silicon nitride, silicon oxide and silicon oxynitride.

[0077] Optionally, the resistivity of the material of the second electrode is less than 0.0001 ohm·m.

[0078] Optionally, the resistivity of the material of the auxiliary conductive layer 50 is lower than the resistivity of the material of the second electrode 60 .

[0079] In this embodiment, the auxiliary conductive layer 50 is located between the second electrode 60 and the channel of the semiconductor layer 70, and the resistivity of the material of the auxiliary conductive layer 50 is less than the resistivity of the material of the second electrode 60, which can reduce the internal impedance of the thin film transistor and increase the on-state current of the thin film transistor.

[0080] Optionally, the resistivity of the material of the auxiliary conductive layer 50 is less than 0.00001 ohm·meter.

[0081] In this embodiment, the auxiliary conductive layer 50 is made of a low-resistance material, which can reduce the internal impedance of the thin film transistor and increase the on-state current of the thin film transistor device, thereby improving the electrical stability of the thin film transistor device.

[0082] Optionally, the material of the auxiliary conductive layer 50 includes one of a metal material and a conductive non-metallic material.

[0083] Optionally, the auxiliary conductive layer 50 is made of a metal material, which is selected from one of molybdenum, titanium, and tungsten, wherein molybdenum, titanium, and tungsten can be etched together with silicon oxide.

[0084] Optionally, the auxiliary conductive layer 50 is made of metal oxide, and the metal oxide includes indium tin oxide (ITO).

[0085] Optionally, the auxiliary conductive layer 50 is made of a conductive non-metallic material, and the conductive non-metallic material is selected from one of a conductive compound, graphite, and a conductive polymer material.

[0086] Optionally, the conductive compound includes titanium nitride.

[0087] Optionally, the auxiliary conductive layer 50 is one of a conductive graphite film and a graphitized film.

[0088] Optionally, the conductive polymer material includes polyacetylene.

[0089] Optionally, the thickness of the auxiliary conductive layer 50 is smaller than the thickness of the second electrode 60 .

[0090] Optionally, the thickness of the auxiliary conductive layer 50 is in a range of 100 angstroms to 1000 angstroms.

[0091] Optionally, the thickness of the auxiliary conductive layer 50 is one of 100 angstroms, 150 angstroms, 200 angstroms, 250 angstroms, 300 angstroms, 350 angstroms, 400 angstroms, 450 angstroms, 500 angstroms, 550 angstroms, 600 angstroms, 650 angstroms, 700 angstroms, 750 angstroms, 800 angstroms, 850 angstroms, 900 angstroms, 950 angstroms, and 1000 angstroms.

[0092] Optionally, the auxiliary conductive layer 50 is a single-layer film.

[0093] Optionally, the second electrode 60 includes at least two metal film layers.

[0094] Optionally, the second electrode 60 includes two metal film layers, which are one of aluminum (Al) / molybdenum (Mo) stacked layers, aluminum (Al) / titanium (Ti) stacked layers, and aluminum (Al) / tungsten (W) stacked layers.

[0095] Optionally, the second electrode 60 includes three metal film layers, which are one of a molybdenum (Mo) / aluminum (Al) / molybdenum (Mo) stack, a titanium (Ti) / aluminum (Al) / titanium (Ti) stack, and a tungsten (W) / aluminum (Al) / tungsten (W) stack.

[0096] Optionally, the thickness of the second electrode 60 is in the range of 2000 angstroms to 7000 angstroms.

[0097] Optionally, the value of the second electrode 60 is 2000 angstroms, 2100 angstroms, 2200 angstroms, 2300 angstroms, 2400 angstroms, 2500 angstroms, 2600 angstroms, 2700 angstroms, 2800 angstroms, 2900 angstroms, 3000 angstroms, 3100 angstroms, 3200 angstroms, 3300 angstroms, 3400 angstroms, 3500 angstroms, 3600 angstroms, 3700 angstroms, 3800 angstroms, 3900 angstroms, 4000 angstroms, 4100 angstroms, 4200 angstroms, 4300 angstroms, 4400 angstroms, , one of the following values: 4500 angstroms, 4600 angstroms, 4700 angstroms, 4800 angstroms, 4900 angstroms, 5000 angstroms, 5100 angstroms, 5200 angstroms, 5300 angstroms, 5400 angstroms, 5500 angstroms, 5600 angstroms, 5700 angstroms, 5800 angstroms, 5900 angstroms, 6000 angstroms, 6100 angstroms, 6200 angstroms, 6300 angstroms, 6400 angstroms, 6500 angstroms, 6600 angstroms, 6700 angstroms, 6800 angstroms, 6900 angstroms, and 7000 angstroms.

[0098] Optionally, the thickness of the auxiliary conductive layer 50 is smaller than the thickness of the first insulating layer 40 .

[0099] Optionally, the thickness of the first insulating layer 40 is in a range from 1000 angstroms to 10000 angstroms.

[0100] Optionally, the thickness of the first insulating layer 40 is one of 1000 angstroms, 1500 angstroms, 2000 angstroms, 2500 angstroms, 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, 5000 angstroms, 5500 angstroms, 6000 angstroms, 6500 angstroms, 7000 angstroms, 7500 angstroms, 8000 angstroms, 8500 angstroms, 9000 angstroms, 9500 angstroms, and 10000 angstroms.

[0101] Optional, see Figure 2 In the first embodiment of the present application, the orthographic projection of the side of the auxiliary conductive layer 50 facing the semiconductor layer 70 on the substrate 10 is located within the range of the orthographic projection of the first insulating layer 40 on the substrate 10 .

[0102] In the first embodiment, the side surface of the auxiliary conductive layer 50 facing the semiconductor layer 70 is retracted from the side surface of the first insulating layer 40 facing the semiconductor layer 70. The distance (L4) between the side surface of the auxiliary conductive layer 50 facing the semiconductor layer 70 and the side surface of the first insulating layer 40 facing the semiconductor layer 70 is less than 0.7 micrometers.

[0103] In this embodiment, the channel length (L3+L4) of the semiconductor layer 70 depends on the thickness of the first insulating layer 40 and the distance from the side of the auxiliary conductive layer 50 facing the semiconductor layer 70 to the side of the first insulating layer 40 facing the semiconductor layer 70. The first insulating layer 40 is an inorganic insulating layer formed on the first electrode 30 by chemical vapor deposition, and the thickness of the first insulating layer 40 can be controlled by the process rate and time, so the thickness of the first insulating layer 40 is controllable.

[0104] The first manufacturing method of the array substrate 100 of the present application includes at least the following steps:

[0105] Step 101 : forming a buffer layer 20 , a first electrode 30 , a first insulating layer 40 and an auxiliary conductive layer 50 in sequence on a substrate 10 .

[0106] Step 102: The auxiliary conductive layer 50 and the first insulating layer 40 are etched in one step through a mask. After etching, the distance from the side of the auxiliary conductive layer 50 facing the semiconductor layer 70 to the side of the first insulating layer 40 facing the semiconductor layer 70 is less than 0.7 microns.

[0107] Among them, the method of etching the auxiliary conductive layer 50 and the first insulating layer 40 in one step can reduce the number of masks and reduce production costs.

[0108] In the first embodiment, the auxiliary conductive layer 50 is a single metal layer, and the material of the auxiliary conductive layer 50 is one of molybdenum, titanium, and tungsten. The thickness of the auxiliary conductive layer 50 is in the range of 100 angstroms to 1000 angstroms, which is much smaller than the thickness of the first insulating layer 40. Therefore, the etching rate of the auxiliary conductive layer 50 is similar to that of the first insulating layer 40.

[0109] Therefore, in the first embodiment, after the auxiliary conductive layer 50 and the first insulating layer 40 are etched by a one-step etching, since the etching rate of the auxiliary conductive layer 50 is similar to the etching rate of the first insulating layer 40, the distance (L4) from the side of the auxiliary conductive layer 50 facing the semiconductor layer 70 to the side of the first insulating layer 40 facing the semiconductor layer 70 can be controlled within a range of less than 0.7 microns, thereby reducing the fluctuation range of the channel length of the semiconductor layer 70 and improving the electrical stability of the thin film transistor device.

[0110] Optionally, according to the size of the distance (L4) from the side of the auxiliary conductive layer 50 facing the semiconductor layer 70 to the side of the first insulating layer 40 facing the semiconductor layer 70 in actual production, the thickness of the auxiliary conductive layer 50 and the first insulating layer 40 can be further adjusted so that the distance (L4) from the side of the auxiliary conductive layer 50 facing the semiconductor layer 70 to the side of the first insulating layer 40 facing the semiconductor layer 70 tends to 0, so that the side of the auxiliary conductive layer 50 facing the semiconductor layer 70 is flush with the side of the first insulating layer 40 facing the semiconductor layer 70.

[0111] Optionally, the thickness of the first insulating layer 40 can be relatively reduced while increasing the thickness of the auxiliary conductive layer 50. This achieves the effect of relatively slowing down the etching speed of the auxiliary conductive layer 50 while relatively accelerating the etching speed of the first insulating layer 40. The distance (L4) between the side of the auxiliary conductive layer 50 facing the semiconductor layer 70 and the side of the first insulating layer 40 facing the semiconductor layer 70 approaches zero, thereby reducing the channel length of the semiconductor layer 70 and increasing the on-state current of the thin film transistor.

[0112] Optional, see Figure 3 In the first embodiment of the present application, the absolute value of the difference between the angle A1 formed by the side of the first insulating layer 40 facing the semiconductor layer 70 and the plane where the substrate 10 is located and the angle A2 formed by the side of the auxiliary conductive layer 50 facing the semiconductor layer 70 and the plane where the substrate 10 is located is less than or equal to 10 degrees.

[0113] In the first manufacturing method of the array substrate 100 of the present application, since the etching rates of the auxiliary conductive layer 50 and the first insulating layer 40 are similar, the absolute value of the difference between the angle A1 formed by the side of the first insulating layer 40 facing the semiconductor layer 70 and the plane where the substrate 10 is located and the angle A2 formed by the side of the auxiliary conductive layer 50 facing the semiconductor layer 70 and the plane where the substrate 10 is located is less than or equal to 10 degrees.

[0114] Optionally, the absolute value of the difference between the angle A1 formed by the side of the first insulating layer 40 facing the semiconductor layer 70 and the plane where the substrate 10 is located and the angle A2 formed by the side of the auxiliary conductive layer 50 facing the semiconductor layer 70 and the plane where the substrate 10 is located is 0, 0.1 degree, 0.2 degree, 0.3 degree, 0.4 degree, 0.5 degree, 0.6 degree, 0.7 degree, 0.8 degree, 0.9 degree, 1.0 degree, 1.1 degree, 1.2 degree, 1.3 degree, 1.6 degree, 1.7 degree, 1.8 degree, 1.9 degree, 2.0 degree, 2.1 degree, 2.2 degree, 2.3 degree, 2.4 degree, 2.5 degree, 2.6 degree, 2.7 degree, 2.8 degree, 2.9 degree, 3.0 degree, 3.1 degree, 3.2 degree, 3.3 degree, 3.4 degree, 3.5 degree, 3.6 degree, 3.7 degree, 3.8 degree, 3.9 degree, 4. .3 degrees, 1.4 degrees, 1.5 degrees, 1.6 degrees, 1.7 degrees, 1.8 degrees, 1.9 degrees, 2.0 degrees, 2.1 degrees, 2.2 degrees, 2.3 degrees, 2.4 degrees, 2.5 degrees, 2.6 degrees, 2.7 degrees, 2.8 degrees, 2.9 degrees, 3.0 degrees, 3.1 degrees, 3.2 degrees, 3.3 degrees, 3.4 degrees, 3.5 degrees, 3.6 degrees, 3.7 degrees, 3.8 degrees, 3.9 degrees, 4.0 degrees, 4.1 degrees, 4.2 degrees, 4.3 degrees, 4.4 degrees, 4.5 degrees, 4.6 degrees, 4.7 degrees, 4.8 degrees, 4.9 degrees, 5.0 degrees, 5.1 degrees, 5.2 degrees, 5.3 degrees, 5.4 degrees, 5.5 degrees, 5.6 degrees, 5.7 degrees, 5.8 degrees, 5.9 degrees, 6.0 degrees, 6.1 degrees, 6.2 degrees, 6.3 degrees, 6.4 degrees, 6.5 degrees, 6.6 degrees, 6.7 degrees, 6.8 degrees, 6.9 degrees, 7.0 degrees, 7.1 degrees, 7.2 One of the following values: 7.3 degrees, 7.4 degrees, 7.5 degrees, 7.6 degrees, 7.7 degrees, 7.8 degrees, 7.9 degrees, 8.0 degrees, 8.1 degrees, 8.2 degrees, 8.3 degrees, 8.4 degrees, 8.5 degrees, 8.6 degrees, 8.7 degrees, 8.8 degrees, 8.9 degrees, 9.0 degrees, 9.1 degrees, 9.2 degrees, 9.3 degrees, 9.4 degrees, 9.5 degrees, 9.6 degrees, 9.7 degrees, 9.8 degrees, 9.9 degrees, and 10.0 degrees.

[0115] Optionally, an angle A1 formed between the side surface of the first insulating layer 40 facing the semiconductor layer 70 and the plane where the substrate 10 is located is in a range of 30 degrees to 70 degrees.

[0116] Optionally, an angle A2 formed between the side surface of the auxiliary conductive layer 50 facing the semiconductor layer 70 and the plane where the substrate 10 is located is in a range of 30 degrees to 70 degrees.

[0117] In this embodiment, when the absolute value of the difference between the angle A1 formed by the side of the first insulating layer 40 facing the semiconductor layer 70 and the plane where the substrate 10 is located and the angle A2 formed by the side of the auxiliary conductive layer 50 facing the semiconductor layer 70 and the plane where the substrate 10 is located tends to 0, the climbing portion of the semiconductor layer 70 covering the side of the first insulating layer 40 facing the semiconductor layer 70 and the side of the auxiliary conductive layer 50 facing the semiconductor layer 70 becomes smoother, so that the film quality of this portion of the semiconductor layer 70 is relatively better, thereby reducing the impedance of the semiconductor layer 70 and improving the electrical stability of the thin film transistor device.

[0118] Optional, see Figure 3 In the first embodiment of the present application, the semiconductor layer 70 includes a first conductor portion 71, a first channel portion 72, a second channel portion 73, a second conductor portion 74, a third conductor portion 75, a fourth conductor portion 76, and a fifth conductor portion 77, which are connected in sequence. The first conductor portion 71 is provided on a side of the first electrode 30 away from the substrate 10. The first channel portion 72 is provided on a side of the first insulating layer 40. The second channel portion 73 is provided on a side of the first insulating layer 40 away from the first electrode 30 and is located on a side of the auxiliary conductive layer 50. The second conductor portion 74 is provided on a side of the auxiliary conductive layer 50. The third conductor portion 75 is provided on a side of the auxiliary conductive layer 50 away from the first insulating layer 40 and is located on a side of the second electrode 60. The fourth conductor portion 76 is provided on a side of the second electrode 60. The fifth conductor portion 77 is provided on a side of the second electrode 60 away from the auxiliary conductive layer 50.

[0119] In this embodiment, the channel of the semiconductor layer 70 includes a first channel portion 72 and a second channel portion 73. The channel length of the semiconductor layer 70 is the sum of the length of the first channel portion 72 and the length of the second channel portion 73.

[0120] Optionally, the length of the first channel portion 72 is in a range of 1000 angstroms to 10000 angstroms.

[0121] Optionally, the length of the first channel portion 72 is one of 1000 angstroms, 1500 angstroms, 2000 angstroms, 2500 angstroms, 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, 5000 angstroms, 5500 angstroms, 6000 angstroms, 6500 angstroms, 7000 angstroms, 7500 angstroms, 8000 angstroms, 8500 angstroms, 9000 angstroms, 9500 angstroms, and 10000 angstroms.

[0122] Optionally, the length of the second channel portion 73 is less than or equal to 7000 angstroms.

[0123] Optionally, the length of the second channel portion 73 is one of 0, 500 angstroms, 1000 angstroms, 1500 angstroms, 2000 angstroms, 2500 angstroms, 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, 5000 angstroms, 5500 angstroms, 6000 angstroms, 6500 angstroms, and 7000 angstroms.

[0124] Optionally, the channel length of the semiconductor layer 70 is less than or equal to 17,000 angstroms.

[0125] Among them, under the premise that the thickness of the first insulating layer 40 remains unchanged, the channel length of the semiconductor layer 70 depends only on the length of the second channel portion 73. The length of the second channel portion 73 depends on the distance (L4) from the side of the auxiliary conductive layer 50 facing the semiconductor layer 70 to the side of the first insulating layer 40 facing the semiconductor layer 70. Because the distance (L4) from the side of the auxiliary conductive layer 50 facing the semiconductor layer 70 to the side of the first insulating layer 40 facing the semiconductor layer 70 is less than 0.7 microns, the fluctuation range of the channel length of the semiconductor layer 70 is within the range of 0 to 0.7 microns, which is much smaller than the fluctuation range of the channel length of traditional thin film transistors. The present application can reduce the fluctuation of the channel length of the semiconductor layer 70 and improve the electrical stability of the thin film transistor device.

[0126] See also Figure 3 In the first embodiment of the present application, the second conductor portion 74 and the third conductor portion 75 of the semiconductor layer 70 cover the surface of the auxiliary conductive layer 50, and the fourth conductor portion 76 and the fifth conductor portion 77 of the semiconductor layer 70 cover the surface of the second electrode 60. The second electrode 60 is electrically connected to the auxiliary conductive layer 50. Compared to conventional thin-film transistor devices, the semiconductor layer 70 in this embodiment is electrically connected to the second electrode 60 and the auxiliary conductive layer 50. Because the auxiliary conductive layer 50 is made of a low-resistance material with a resistivity of less than 0.00001 ohm·m, it can reduce the internal impedance of the thin-film transistor, increase the on-state current of the thin-film transistor, and thus enhance the electrical stability of the thin-film transistor.

[0127] Optional, see Figure 4 In the second embodiment of the present application, the side of the auxiliary conductive layer 50 facing the semiconductor layer 70 is flush with the side of the first insulating layer 40 facing the semiconductor layer 70. The channel of the semiconductor layer 70 is provided on the side of the first insulating layer 40 facing the semiconductor layer 70.

[0128] It is understandable that Figure 4 and Figure 5 The second embodiment shown is Figure 2 and Figure 3 The difference of the first embodiment shown is that the side of the auxiliary conductive layer 50 facing the semiconductor layer 70 is flush with the side of the first insulating layer 40 facing the semiconductor layer 70, so the channel of the semiconductor layer is only located on the side of the first insulating layer 40. Figure 4 and Figure 5 Redundant description of the second embodiment shown.

[0129] In this embodiment, the material of the semiconductor layer 70 is indium gallium zinc oxide. Since the second electrode 60 is electrically connected to the auxiliary conductive layer 50, the top and bottom portions of the semiconductor layer 70 located on the side of the first insulating layer 40 are electrically connected to the auxiliary conductive layer 50 and the first electrode 30, respectively. Therefore, the portion of the semiconductor layer 70 located on the side of the first insulating layer 40 forms a channel of the semiconductor layer 70. When a threshold voltage is applied to the gate 90, the portion of the semiconductor layer 70 located on the side of the first insulating layer 40 forms a conductive channel, enabling carrier transfer between the auxiliary conductive layer 50 and the first electrode 30.

[0130] In this embodiment, the channel length (L5) of the semiconductor layer 70 depends solely on the thickness of the first insulating layer 40. The first insulating layer 40 is an inorganic insulating layer formed on the first electrode 30 by chemical vapor deposition, and the thickness of the first insulating layer 40 can be controlled by the process rate and time. Therefore, the thickness of the first insulating layer 40 is controllable. Compared to the first embodiment, the channel length of the semiconductor layer 70 in the second embodiment has less fluctuation, and the thin-film transistor has greater electrical stability.

[0131] The second manufacturing method of the array substrate 100 of the present application includes at least the following steps:

[0132] Step 201 : forming a buffer layer 20 , a first electrode 30 , a first insulating layer 40 and an auxiliary conductive layer 50 in sequence on a substrate 10 .

[0133] Step 202: wet-etching the auxiliary conductive layer 50 through a mask, wherein the auxiliary conductive layer 50 is a single layer of metal material, and the metal material is selected from one of molybdenum, titanium, and tungsten.

[0134] Step 203: After the auxiliary conductive layer 50 is etched, the first insulating layer 40 is etched along the side of the auxiliary conductive layer 50 by a dry etching process using the auxiliary conductive layer 50 as a mask, so that the side of the first insulating layer 40 and the side of the auxiliary conductive layer 50 are self-aligned and flush.

[0135] Compared to the first method for manufacturing the array substrate 100 of the present application, the channel length of the semiconductor layer 70 formed by the second method for manufacturing the array substrate 100 of the present application depends solely on the thickness of the first insulating layer 40. Therefore, the fluctuation range of the channel length of the semiconductor layer 70 in the second embodiment is extremely small and can be ignored. The thin-film transistor device of the second embodiment has greater electrical stability.

[0136] Optionally, an angle A1 formed between the side surface of the first insulating layer 40 facing the semiconductor layer 70 and the plane where the substrate 10 is located is in a range of 30 degrees to 70 degrees.

[0137] Optionally, an angle A2 formed between the side surface of the auxiliary conductive layer 50 facing the semiconductor layer 70 and the plane where the substrate 10 is located is in a range of 30 degrees to 70 degrees.

[0138] Optionally, since the side of the first insulating layer 40 facing the semiconductor layer 70 is flush with the side of the auxiliary conductive layer 50 facing the semiconductor layer 70, the angle A1 formed by the side of the first insulating layer 40 facing the semiconductor layer 70 and the plane where the substrate 10 is located is equal to the angle A2 formed by the side of the auxiliary conductive layer 50 facing the semiconductor layer 70 and the plane where the substrate 10 is located.

[0139] In this embodiment, since the side surface of the first insulating layer 40 facing the semiconductor layer 70 is flush with the side surface of the auxiliary conductive layer 50 facing the semiconductor layer 70, the film quality of the semiconductor layer 70 in the climbing section of the side surface of the first insulating layer 40 facing the semiconductor layer 70 and the side surface of the auxiliary conductive layer 50 facing the semiconductor layer 70 can be enhanced, thereby reducing the impedance of the semiconductor layer 70 and improving the electrical stability of the thin film transistor.

[0140] Optional, see Figure 5 In the second embodiment of the present application, the semiconductor layer 70 includes a first conductor portion 71, a first channel portion 72, a second conductor portion 74, a third conductor portion 75, a fourth conductor portion 76, and a fifth conductor portion 77, which are connected in sequence. The first conductor portion 71 is provided on a side of the first electrode 30 away from the substrate 10, and is electrically connected to the first electrode 30. The first channel portion 72 is provided on a side of the first insulating layer 40. The second conductor portion 74 is provided on a side of the auxiliary conductive layer 50. The third conductor portion 75 is provided on a side of the auxiliary conductive layer 50 away from the first insulating layer 40, and is located on a side of the second electrode 60. The fourth conductor portion 76 is provided on a side of the second electrode 60. The fifth conductor portion 77 is provided on a side of the second electrode 60 away from the auxiliary conductive layer 50.

[0141] In the second embodiment of the present application, the channel of the semiconductor layer 70 includes only the first channel portion 72 , and the channel length of the semiconductor layer 70 is the length of the first channel portion 72 .

[0142] Optionally, the length of the first channel portion 72 is in a range of 1000 angstroms to 10000 angstroms.

[0143] Optionally, the length of the first channel portion 72 is one of 1000 angstroms, 1500 angstroms, 2000 angstroms, 2500 angstroms, 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, 5000 angstroms, 5500 angstroms, 6000 angstroms, 6500 angstroms, 7000 angstroms, 7500 angstroms, 8000 angstroms, 8500 angstroms, 9000 angstroms, 9500 angstroms, and 10000 angstroms.

[0144] Optionally, the channel of the semiconductor layer 70 is in the range of 1000 to 10000 angstroms.

[0145] Compared to the first embodiment of the present application, the channel length in the second embodiment is only related to the thickness of the first insulating layer 40. The thickness of the first insulating layer 40 is easily controlled. Therefore, compared to the first embodiment, the channel length of the semiconductor layer 70 in the second embodiment hardly fluctuates, thereby ensuring improved electrical stability of the multiple thin film transistors in the array substrate 100.

[0146] Optional, see Figure 6 In the third embodiment of the present application, a first via hole H1 is formed in the first insulating layer 40. The first via hole H1 exposes a surface of the first electrode 30 away from the substrate 10. The auxiliary conductive layer 50 extends around the circumference of the first via hole H1 and forms a second via hole H2. The hole wall of the second via hole H2 is flush with the hole wall of the first via hole H1. The second electrode 60 extends around the circumference of the second via hole H2 and forms a third via hole H3. The first portion of the semiconductor layer 70 is provided on the side of the first electrode 30 exposed to the first via hole H1, the second portion of the semiconductor layer 70 is provided on the hole wall of the first via hole H1, and the third portion of the semiconductor layer 70 is provided on the hole wall of the second via hole H2 and the hole wall of the third via hole H3. The orthographic projection of the hole wall of the third via hole H3 on the substrate 10 is located outside the orthographic projection of the hole wall of the second via hole H2 on the substrate 10.

[0147] It is understandable that Figure 6 The third embodiment shown is Figure 4 and Figure 5 The difference between the second embodiment shown is that the semiconductor layer of the third embodiment is a ring-shaped vertical channel, while the semiconductor layer of the second embodiment is a side vertical channel. Figure 6 Redundant description of the third embodiment shown.

[0148] In the third embodiment, the channel length of the semiconductor layer 70 is the portion of the semiconductor layer 70 located on the wall of the first via hole H1. The width of the semiconductor layer 70 formed in the third embodiment is related to the aperture of the first via hole H1, and its length is related to the depth of the first via hole H1. Compared to the second embodiment, the annular vertical channel thin-film transistor device formed in the third embodiment increases the width-to-length ratio (W / L) of the semiconductor layer 70, thereby improving the on-state current of the thin-film transistor and enhancing the electrical stability of the thin-film transistor.

[0149] The above describes in detail the specific embodiments of the present application. The above embodiments disclosed in this application are merely preferred embodiments of the present application. Those skilled in the art will appreciate that many variations and improvements can be made without departing from the spirit of the present application. These variations and improvements fall within the scope of protection defined by the claims of this application.

Claims

1. An array substrate, characterized in that: include: substrate; A first electrode is provided on the substrate; a first insulating layer, provided on a side of the first electrode away from the substrate; an auxiliary conductive layer, provided on a side of the first insulating layer away from the substrate; a second electrode, disposed on a side of the auxiliary conductive layer away from the substrate and electrically connected to the first electrode; a semiconductor layer comprising a first portion provided on a side of the first electrode away from the substrate, a second portion provided on a side of the first insulating layer, and a third portion provided on a surface of the second electrode and the auxiliary conductive layer; a second insulating layer, provided on a side of the semiconductor layer away from the substrate; as well as a gate, disposed on a side of the second insulating layer away from the substrate; The distance from the side of the auxiliary conductive layer facing the semiconductor layer to the side of the first insulating layer facing the semiconductor layer is less than or equal to 0.7 microns, and the distance from the side of the second electrode facing the semiconductor layer to the side of the auxiliary conductive layer facing the semiconductor layer is greater than 0.

2. The array substrate according to claim 1, wherein: The thickness of the auxiliary conductive layer is smaller than the thickness of the second electrode, and the thickness of the auxiliary conductive layer is smaller than the thickness of the first insulating layer.

3. The array substrate according to claim 1, wherein: The resistivity of the material of the auxiliary conductive layer is lower than the resistivity of the material of the second electrode.

4. The array substrate according to claim 1, wherein: The resistivity of the material of the auxiliary conductive layer is less than 0.00001 ohm·m.

5. The array substrate according to claim 1, wherein: A side surface of the auxiliary conductive layer facing the semiconductor layer is flush with a side surface of the first insulating layer facing the semiconductor layer.

6. The array substrate according to claim 5, wherein: The semiconductor layer includes: a first conductor portion, provided on a side of the first electrode away from the substrate and electrically connected to the first electrode; a first channel portion, provided on a side surface of the first insulating layer; A second conductor portion is provided on a side surface of the auxiliary conductive layer; a third conductor portion, provided on a side of the auxiliary conductive layer away from the first insulating layer and located on a side of the second electrode; a fourth conductor portion, disposed on a side surface of the second electrode; and a fifth conductor portion, provided on a side of the second electrode away from the auxiliary conductive layer; wherein the first conductor portion, the first channel portion, the second conductor portion, the third conductor portion, the fourth conductor portion, and the fifth conductor portion are connected in sequence; The length of the first channel portion is in a range of 1000 angstroms to 10000 angstroms.

7. The array substrate according to claim 1, wherein: The orthographic projection of the side surface of the auxiliary conductive layer facing the semiconductor layer on the substrate is located within the range of the orthographic projection of the first insulating layer on the substrate.

8. The array substrate according to claim 7, wherein: The semiconductor layer includes: a first conductor portion, provided on a side of the first electrode away from the substrate; a first channel portion, provided on a side surface of the first insulating layer; A second channel portion is provided on a side of the first insulating layer away from the first electrode and located on a side of the auxiliary conductive layer; A second conductor portion is provided on a side surface of the auxiliary conductive layer; a third conductor portion, provided on a side of the auxiliary conductive layer away from the first insulating layer and located on one side of the second electrode; a fourth conductor portion, disposed on a side surface of the second electrode; and a fifth conductor portion, provided on a side of the second electrode away from the auxiliary conductive layer; The first conductor portion, the first channel portion, the second channel portion, the second conductor portion, the third conductor portion, the fourth conductor portion, and the fifth conductor portion are connected in sequence; The length of the first channel portion is in a range of 1000 angstroms to 10000 angstroms; The length of the second channel portion is less than or equal to 7000 angstroms.

9. The array substrate according to claim 1, wherein: A first via hole is formed in the first insulating layer, wherein the first via hole exposes a surface of the first electrode away from the substrate; The auxiliary conductive layer is extended around the circumference of the first via hole to form a second via hole, and the hole wall of the second via hole is flush with the hole wall of the first via hole; The second electrode is extended around the circumference of the second via hole and forms a third via hole; The first portion of the semiconductor layer is provided on a side of the first electrode exposed to the first via hole, the second portion of the semiconductor layer is provided on a hole wall of the first via hole, and the third portion of the semiconductor layer is provided on a hole wall of the second via hole and a hole wall of the third via hole; The orthographic projection of the hole wall of the third via hole on the substrate is located outside the orthographic projection of the hole wall of the second via hole on the substrate.

10. A display panel, characterized in that: The display panel includes the array substrate according to any one of claims 1 to 9.

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