Solar cells and photovoltaic modules
By designing a hybrid structure of multiple pyramid structures and ridge-like structures on the side of the solar cell, combining alumina and silicon nitride layers, the problem of reducing light absorption under thinning of silicon wafers is solved, and the photoelectric conversion efficiency of solar cells is improved. Coating quality.
Patent Information
- Application Number
- CN202411357965.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-27
- Publication Date
- 2025-01-14
- Estimated Expiration
- 2044-09-27
AI Technical Summary
In the case of thinning of silicon wafers, how to further increase the light absorption rate of solar cells to avoid the problem of decreasing the coating quality of the passivation layer.
By designing a plurality of first texture areas and a second texture areas on the side of the solar cell, the first texture area includes a smaller first pyramid structure, the second texture area includes a larger second pyramid structure, and at the passivation layer An alumina layer and a silicon nitride layer are provided in it to enhance the coating quality and photoelectric conversion efficiency.
It achieves the improvement of the photoelectric conversion efficiency of solar cells under thinning silicon wafers, takes into account the side light trapping effect and passivation performance, and improves the coating quality.
Smart Images

Figure CN119069554B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of photovoltaic technology, and in particular to a solar cell and a photovoltaic module. Background Art
[0002] Solar cells can convert light energy into electrical energy, which is of great significance to energy development and environmental protection. Cells made of monocrystalline silicon have advantages such as high conversion efficiency and mature technology, and have occupied a large share of the photovoltaic industry. In order to reduce production costs, thinning of silicon wafers will be an inevitable trend. However, thinner silicon wafers will lead to lower light absorption by the substrate and a decrease in the number of photogenerated carriers. With the trend of thinning silicon wafers, how to further increase the light absorption of the cell will be an urgent problem to be solved. In the prior art, a pyramid velvet structure is set on the side of the solar cell to improve the light trapping effect on the side and increase the light absorption of the solar cell. However, such a structure will affect the coating quality of the passivation layer on the side of the solar cell, reduce the passivation performance of the solar cell, and thus affect the efficiency of the solar cell. Summary of the invention
[0003] The purpose of the present application is to provide a solar cell and a photovoltaic module, which improves the photoelectric conversion efficiency of the solar cell by controlling the morphology of the side surface of the solar cell and balancing the light trapping effect and passivation performance of the side surface.
[0004] In order to achieve the above-mentioned object, in the first aspect, the present application provides a solar cell. The solar cell comprises a silicon substrate and a passivation layer, wherein the silicon substrate comprises a first surface and a second surface opposite to each other and a plurality of side surfaces connecting the first surface and the second surface. At least one side surface comprises a plurality of first texture areas and a second texture area, wherein each first texture area comprises a plurality of first pyramid structures, and the second texture area comprises a plurality of second pyramid structures. The structural size of the second pyramid structure is greater than the structural size of the first pyramid structure. There is a second texture area between adjacent first texture areas. The passivation layer covers the first texture area and the second texture area of at least one of the side surfaces.
[0005] In some embodiments, the second textured region extends between the first textured regions in any one or more of a straight line, a broken line, or a curved line.
[0006] In some embodiments, the extension direction of the second texture region is not parallel to the thickness direction of the solar cell, and / or the extension directions of at least two second texture regions are arranged in parallel.
[0007] In some embodiments, the second textured region includes prismatic structures, and the length of the prismatic structures ranges from 200 nm to 6 μm.
[0008] In some embodiments, the first pyramid structure has a structural size ranging from 0.05 μm to 2 μm.
[0009] In some embodiments, the second pyramid structure has a structural size ranging from 2 μm to 6 μm.
[0010] In some embodiments, the side surface includes a first area connected to the first surface, the first texture area and the second texture are both arranged on the first area, and the width of the first area accounts for 20% to 100% of the width of the side surface.
[0011] In some embodiments, the side surface includes a first area and a second area, the first texture area and the second texture area are both arranged on the first area, the second area is connected to one side of the second surface, and the second area includes a plurality of tower base structures.
[0012] In some embodiments, a boundary line between the first region and the second region is a curve, and a pit is provided in the second region near the boundary line.
[0013] In some embodiments, along the thickness direction of the silicon substrate, the width of the region where the pit is provided is 0 to 60% of the width of the second region.
[0014] In some embodiments, the shape of the pit includes one or more of an inverted pyramid, an inverted hemisphere, and a terrace, and / or the cross-sectional area of the pit gradually increases along a direction vertically and away from the side.
[0015] In some embodiments, the diameter of the cross section of the pit on the side is 0.1 μm to 5 μm, and / or the depth of the pit is 0.05 μm to 2 μm.
[0016] In some embodiments, along a direction away from the silicon substrate, the passivation layer includes an aluminum oxide layer and a silicon nitride layer disposed in sequence.
[0017] In the above-mentioned solar cell, the first pyramid structure in the first texture area can enhance the light trapping effect on the side of the solar cell and improve the utilization rate of light by the solar cell. Although the first pyramid structure with a smaller structural size increases the surface roughness of the side, it is not conducive to the coating quality of the subsequent passivation layer on the side of the solar cell. However, in the embodiment of the present application, a second pyramid structure is also designed to be formed in the second texture area. The larger structural size of the second pyramid structure can provide a larger surface area than the first pyramid structure, providing a larger coating area for subsequent coating and improving the coating quality. Therefore, the mixed structure of multiple first pyramid structures and multiple second pyramid structures can better take into account the side passivation and light trapping effects of the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell.
[0018] The second aspect of the present application provides a photovoltaic module, which includes a plurality of solar cells electrically connected to each other, and the solar cells are the solar cells provided in the first aspect of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 FIG. 1 is a schematic diagram of the texture structure distribution on the side of a solar cell according to an embodiment of the present application.
[0020] Figure 2 FIG. 1 is a schematic structural diagram of a solar cell according to an embodiment of the present application.
[0021] Figure 3 for Figure 2 Schematic diagram of the structure of the silicon substrate of the solar cell.
[0022] Figure 4 for Figure 2 Schematic diagram of the texture structure distribution of the silicon substrate of the solar cell.
[0023] Figure 5 This is a scanning electron microscope image of the side surface of a solar cell according to an embodiment of the present application.
[0024] Figure 6 Another scanning electron microscope image of the side surface of a solar cell according to an embodiment of the present application.
[0025] Figure 7 This is a scanning electron microscope image of the first surface of a solar cell according to an embodiment of the present application.
[0026] Figure 8 It is a schematic diagram of the structural dimensions of the pyramid structure and the structural dimensions of the tower base structure in a solar cell according to an embodiment of the present application.
[0027] Description of main component symbols:
[0028] 100-solar cell, 10-silicon substrate, 11-first surface, 12-second surface, 13-side, 131-first side, 132-second side, 133-third side, 134-fourth side, 20-first dielectric layer, 30-first doped conductive layer, 40-second dielectric layer, 50-second doped conductive layer, A1-first region, A11-first texture region, A12-second texture region, A2-second region, T11-pyramid structure, T12-prismatic structure, T13-tower base structure, T21-third pyramid structure, R-pit, D1-thickness direction of silicon substrate. DETAILED DESCRIPTION
[0029] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit this application.
[0030] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the embodiments of the present application, and cannot be understood as limiting the present application.
[0031] In the description of the embodiments of the present application, terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the implementation methods of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.
[0032] In the description of the embodiments of the present application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features.
[0033] In the description of the embodiments of the present application, unless otherwise specified, “plurality” means two or more than two.
[0034] In the description of the embodiments of the present application, unless otherwise specified, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal connection of two elements or the interaction relationship between two elements.
[0035] For those skilled in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0036] Please refer to Figure 1 and Figure 2 The solar cell 100 includes a silicon substrate 10 , and the silicon substrate 10 may be an N-type silicon substrate or a P-type silicon substrate.
[0037] Specifically, the silicon substrate 10 includes a first surface 11 and a second surface 12 opposite to each other and a side surface 13 connecting the first surface 11 and the second surface 12 .
[0038] The cell type of the solar cell 100 is not limited to Figure 2As shown. Specifically, the cell type of the solar cell 100 can be a tunnel oxide passivated contact back contact (Tunnel oxide passivated contact Back Contact, TBC) cell, a tunnel oxide passivated contact (Tunnel Oxide Passivated Contact, TOPCon) cell and a hybrid back contact cell. Among them, the hybrid back contact cell refers to a back contact cell in which the N region and the P region correspond to a tunnel passivated contact structure and a heterogeneous contact structure respectively, or a back contact cell in which the N region and the P region correspond to a tunnel passivated contact structure and a passivated emitter structure respectively. The solar cell 100 can be an N-type solar cell or a P-type solar cell.
[0039] The structure of the silicon substrate 10 is described in detail below. Figure 3 for Figure 2 Schematic diagram of the structure of the silicon substrate 10 of the solar cell 100. Figure 3 As shown, the silicon substrate 10 is substantially in the shape of a cuboid. The side surface 13 includes a first side surface 131, a second side surface 132, a third side surface 133 and a fourth side surface 134 connected in sequence. The first side surface 131 is disposed opposite to the third side surface 133. The second side surface 132 is disposed opposite to the fourth side surface 134.
[0040] Figure 4 for Figure 2 Schematic diagram of the texture structure distribution of the silicon substrate 10 of the solar cell 100. Figure 5 FIG. 1 is a scanning electron microscope image of the side surface 13 of the solar cell 100 according to an embodiment of the present application.
[0041] Please refer to Figures 1 to 5 , at least one side 13 of the silicon substrate 10 is provided with a plurality of pyramid structures T11. Specifically, the plurality of pyramid structures T11 include a plurality of first pyramid structures and a plurality of second pyramid structures. More specifically, the distribution of the plurality of pyramid structures T11 makes at least one side 13 of the silicon substrate 10 include a plurality of first texture areas A11 and a second texture area A12. Each first texture area A11 includes a plurality of first pyramid structures. The second texture area A12 includes a second pyramid structure. The structural size of the second pyramid structure is greater than the structural size of the first pyramid structure. There is a second texture area A12 between adjacent first texture areas A11. The solar cell 100 includes a passivation layer (not shown), and the passivation layer covers the first texture area A11 and the second texture area A12 of at least one side 13.
[0042] It should be noted that, in the embodiments of the present application, the structural dimension of the first pyramid structure refers to any one of the length, width or diagonal length of the base of the first pyramid structure, and / or the tower height of the first pyramid structure. The structural dimension of the second pyramid structure refers to any one of the length, width or diagonal length of the base of the second pyramid structure, and / or the tower height of the second pyramid structure.
[0043] In the related art, a pyramid texture structure is formed on the side of the silicon substrate of the solar cell. Although the pyramid texture structure can improve the coating quality of the passivation layer on the side, it will increase the reflectivity of light and reduce the light absorption performance of the solar cell. Alternatively, a pyramid velvet structure of a single size range is formed on the side of the silicon substrate of the solar cell. The velvet structure can increase the light trapping effect of the side of the silicon substrate of the solar cell, but the velvet structure will increase the roughness of the side of the silicon substrate, which is not conducive to improving the passivation performance of the side of the silicon substrate.
[0044] In the embodiment of the present application, the side 13 of the solar cell 100 includes a plurality of pyramid structures T11. The first pyramid structure of the first texture area A11 can enhance the light trapping effect of the side of the solar cell 100, and improve the light utilization rate of the solar cell 100. In addition, a second pyramid structure in the second texture area A12 is also designed and formed in the embodiment of the present application. The larger structural size of the second pyramid structure can provide a larger surface area than the first pyramid structure, and provide a larger coating area for the subsequent passivation layer, thereby improving the coating quality of the passivation layer and the passivation performance of the side 13. Therefore, compared with the tower base texture structure or the pyramid structure of a single structural size in the related art, the mixed structure of multiple first pyramid structures and multiple second pyramid structures can better take into account the side passivation and light trapping effects of the solar cell, and improve the photoelectric conversion efficiency of the solar cell.
[0045] In some embodiments, the passivation layer further covers the side surface 13 except the first texture area A11 and the second texture area A12 .
[0046] In some embodiments, reference Figure 2 The solar cell 100 further includes a first dielectric layer 20 , a first doped conductive layer 30 , a second dielectric layer 40 , and a second doped conductive layer 50 .
[0047] The first dielectric layer 20 and the second dielectric layer 40 are alternately arranged on the second surface 12. The first doped conductive layer 30 is located on the side of the first dielectric layer 20 away from the silicon substrate 10. The second doped conductive layer 50 is located on the side of the second dielectric layer 40 away from the silicon substrate 10.
[0048] The first doped conductive layer 30 and the second doped conductive layer 50 have opposite conductivity types. The conductivity type of the first doped conductive layer 30 may be N-type, and the conductivity type of the second doped conductive layer 50 may be P-type; or, the conductivity type of the first doped conductive layer 30 may be P-type, and the conductivity type of the second doped conductive layer 50 may be N-type.
[0049] A spacing region is formed between the first dielectric layer 20 and the second dielectric layer 40 and between the first doped conductive layer 30 and the second doped conductive layer 50 to form electrical isolation between the first doped conductive layer 30 and the second doped conductive layer 50. It should be noted that in actual situations, a spacing region may be provided for electrical isolation, or other methods may be adopted without providing a spacing region, as long as electrical isolation between film layers or regions of different doping types can be achieved.
[0050] The materials of the first dielectric layer 20 and the second dielectric layer 40 can be, but are not limited to, silicon oxide, aluminum oxide, titanium oxide or intrinsic amorphous silicon. The materials of the first doped conductive layer 30 and the second doped conductive layer 50 can be, but are not limited to, doped polysilicon or doped amorphous silicon.
[0051] The passivation layer covers the first face 11 and / or the second face 12 in addition to at least one side face 13. Specifically, the passivation layer covers at least one side face 13 and the first face 11 of the solar cell 100, or the passivation layer covers at least one side face 13 and the second face 12 of the solar cell 100, or the passivation layer covers at least one side face 13, the first face 11 and the second face 12 of the solar cell 100. When the passivation layer covers the second face 12, the passivation layer covers the side of the first doped conductive layer 30 facing away from the silicon substrate 10 and the side of the second doped conductive layer 50 facing away from the silicon substrate 10.
[0052] The material of the passivation layer can be but is not limited to one or more of aluminum oxide, silicon nitride, silicon oxynitride and the like, which is used to passivate the surface of the silicon substrate 10 or the functional layer, and reduce or eliminate the reflected light on the surface of the solar cell 100, thereby increasing the utilization rate of sunlight by the solar cell 100 and improving the photoelectric conversion efficiency.
[0053] In some embodiments, the passivation layer includes an aluminum oxide layer and a silicon nitride layer arranged in sequence. The thickness of the aluminum oxide layer ranges from 4nm to 10nm (such as 4nm to 6nm, 6nm to 8nm, 8nm to 10nm, etc.). The silicon nitride layer may be a single layer or a stacked structure with different refractive indices, and the thickness of the silicon nitride layer ranges from 50nm to 100nm (such as 50nm to 60nm, 60nm to 70nm, 70nm to 80nm, 80nm to 90nm, 90nm to 100nm, etc.).
[0054] The passivation layer can use field passivation or chemical passivation to reduce the recombination centers on the surface of the silicon substrate or other film layers, reduce the recombination of carriers on the surface of the battery, and thus improve the efficiency of the battery. In addition, the outermost passivation layer can also reduce the reflection of sunlight and enhance the battery's ability to absorb light. For example, the aluminum oxide layer saturates the dangling bonds on the surface of the side 13, reduces the interface state density, and passivates the side. The silicon nitride layer can protect the aluminum oxide layer and realize internal reflection, thereby improving the utilization rate of light by the solar cell.
[0055] In some embodiments, the thickness of the silicon nitride layer on the side surface 13 is greater than the thickness of the silicon nitride layer on the first surface 11 or the second surface 12. In comparison, since the area of the side surface 13 is much smaller than that of the first surface 11 or the second surface 12, the quality of the passivation layer coating is not as good as that of the first surface 11 or the second surface 12. Therefore, a thicker silicon nitride layer can maximize the continuity of the silicon nitride layer coating covering the side surface, and achieve the protection and passivation of the aluminum oxide layer and the side surface 13, as well as the reflection of light.
[0056] In some embodiments, the second texture area A12 extends between the first texture areas A11 in any one or more of a straight line, a folded line, or a curve. Further, the extension direction of the second texture area A12 is not parallel to the thickness direction of the solar cell 100, and / or the extension directions of at least two second texture areas A12 are arranged in parallel.
[0057] This is beneficial to enhance the regularity of the side morphology changes of the solar cell 100 , thereby further improving the uniformity of the film layer formed based on the side of the solar cell 100 , thereby improving its passivation effect on the side of the solar cell 100 .
[0058] Specifically, the side surface 13 has a first area A1 connected to the first surface 11. The first texture area A11 and the second texture area A12 are both arranged on the first area A1. The structural size of the first pyramid structure in the pyramid structure T11 ranges from 0.05 μm to 2 μm. The structural size of the second pyramid structure in the pyramid structure T11 ranges from 2 μm to 6 μm.
[0059] For example, the size range of the base of the first pyramid structure in the pyramid structure T11 and / or the size range of the tower height of the first pyramid structure is 0.05μm to 2μm (such as 0.05μm to 0.1μm, 0.1μm to 0.5μm, 0.5μm to 1.1μm, 1.1μm to 1.3μm, 1.3μm to 1.5μm, 1.5μm to 1.8μm, 1.8μm to 2μm, etc.). The size range of the base of the second pyramid structure in the pyramid structure T11 and / or the size range of the tower height of the second pyramid structure is 2μm to 6μm (2μm to 2.3μm to 2.8μm, 2.8μm to 3.3μm, 3.3μm to 4μm, 4μm to 5μm, 5μm to 6μm, etc.).
[0060] The following combination Figure 5 The embodiments of the present application are described in more detail.
[0061] like Figure 5 As shown, the second texture area A12 extends between the first texture areas A11 in a folded line manner. Further, the extension direction of the second texture area A12 is not parallel to the thickness direction of the solar cell 100 .
[0062] It should be noted that Figure 5 In FIG. 1 , two second texture areas A12 are indicated by solid line frames, and Figure 5 Only part of the second texture area A12 is illustrated. In actual applications, the number of second texture areas A12 in the side 13 includes but is not limited to the second texture areas A12 illustrated by the black frame, and the size and extension direction of the second texture area A12 are not limited to the second texture areas A12 illustrated by the solid line frame.
[0063] The angle calculation rule between the extension direction of the second texture area A12 and the thickness direction D1 of the solar cell 100 is the same, which means: the angle between the extension direction of the second texture area A12 and the thickness direction D1 of the solar cell 100 along the counterclockwise direction (or clockwise direction).
[0064] In some embodiments, the orthographic projections of the second pyramid structures on the side surface 13 overlap.
[0065] In addition, the second texture area A12 also includes a plurality of prismatic structures T12 (such as Figure 5In the dotted ellipse area, the prismatic structure T12 can provide a flatter surface than the first pyramid structure, and the prismatic structure T12 has a larger surface area, which provides a larger deposition area for the subsequent deposition of the passivation layer. Therefore, the prismatic structure T12 can be beneficial to further improve the quality of the subsequent coating. Therefore, compared with the single suede structure or tower base structure in the related art, the mixed structure of multiple first pyramid structures, multiple second pyramid structures and multiple prismatic structures T12 can better take into account the passivation and light trapping of the side 13 of the solar cell 100.
[0066] In some embodiments, the length of the prismatic structure T12 ranges from 200 nm to 6 μm (eg, 200 nm to 500 nm, 500 nm to 1 μm, 1 μm to 3 μm, 3 μm to 5 μm, 5 μm to 6 μm, etc.).
[0067] It should be noted that the length of the prismatic structure T12 refers to the distance from the lowest end to the highest end of the prismatic structure T12 along the inclined direction of the prismatic structure T12.
[0068] In some embodiments, the partial prismatic structure T12 includes a prism-shaped bottom and a substantially pyramid-shaped top connected to the bottom. The partial prismatic structure T12 is substantially prism-shaped as a whole.
[0069] The side surface 13 further includes a second area A2 . The second area A2 is connected to a side of the first area A1 close to the second surface 12 .
[0070] Figure 6 FIG. 1 is another SEM image of the side surface 13 of the solar cell 100 according to an embodiment of the present application. Figure 6 As shown, the second area A2 includes a plurality of tower foundation structures T13.
[0071] The second region A2 having a plurality of tower base structures T13 is conducive to increasing the specific surface area of the side of the solar cell 100, so as to increase the specific surface area of the subsequent coating film layer, thereby improving the passivation effect of the passivation layer on the side of the solar cell 100. In addition, the passivation performance of the tower base structure T13 of the second region A2 after the passivation layer is plated is better, and the better passivation performance of the part close to the second surface 12 can reduce the probability of carrier recombination at the edge of the solar cell 100, which is conducive to improving the performance of the solar cell 100.
[0072] The combined process can improve the problem of over-etching of the second surface 12. In the solar cell 100 of the embodiment of the present application, setting the second area A2 on the side can improve the passivation performance of the solar cell 100 while reducing the over-etching of the second surface functional layer by the etching solution.
[0073] In some embodiments, the shape of the tower base structure T13 includes a square or an approximately square shape.
[0074] For example, the transverse dimension of the tower base structure T13 ranges from 10 μm to 30 μm (e.g., 10 μm to 12 μm, 12 μm to 13 μm, 13 μm to 14.5 μm, 14.5 μm to 15 μm, 15 μm to 20 μm, 20 μm to 25 μm, 25 μm to 28 μm, 28 μm to 30 μm, etc.). Specifically, the transverse dimension of the tower base structure T13 is the farthest distance from the tower base surface of the tower base structure T13.
[0075] For example, the longitudinal height range of the base of the base structure T13 is 0.01μm to 8μm (such as 0.01μm to 0.05μm, 0.05μm to 0.1μm, 0.1μm to 0.4μm, 0.4μm to 0.5μm, 0.5μm to 0.7μm, 0.7μm to 1μm, 1μm to 1.3μm, 1.3μm to 1.5μm, 1.5μm to 1.8μm, 1.8μm to 2.3μm, 2.3μm to 2.8μm, 2.8μm to 3.3μm, 3.3μm to 4μm, 4μm to 5μm, 5μm to 6μm, 6μm to 7μm, 7μm to 8μm, etc.).
[0076] In some embodiments, the tower base structure T13 is not fully displayed in the second area A2.
[0077] In some embodiments, a boundary line between the first area A1 and the second area A2 is a curve, a pit R is provided in the second area A2 near the boundary line, and along the thickness direction of the silicon substrate 10, a width of the area where the pit R is provided is 0 to 60% (e.g., 0 to 10%, 10 to 20%, 20 to 30%, 30 to 40%, 40 to 50%, 50 to 60%, etc.) of the width of the second area A2.
[0078] In some embodiments, the shape of the pit R includes one or more of an inverted pyramid, an inverted hemisphere, and a terrace.
[0079] In some embodiments, the cross-sectional area of the recess R gradually increases along a direction perpendicular to and away from the side surface 13 .
[0080] In some embodiments, the diameter of the cross section of the pit R on the side 13 is 0.1 μm to 5 μm (eg, 0.1 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 3.5 μm, 3.5 μm to 5 μm, etc.).
[0081] Specifically, the diameter of the pit R in the cross section on the side 13 is the diameter of the cross section farthest from the bottom surface of the pit R. In other words, it is the diameter of the cross section of the opening of the pit R.
[0082] The diameter of the pit R can be obtained by a three-dimensional microscope or a scanning electron microscope, and the depth of the pit R can be obtained by scanning with a three-dimensional microscope.
[0083] The pit R is arranged at the junction of the first area A1 and the second area A2, so that the morphology of the first area A1 and the second area A2 presents a transitional change trend, reducing the obvious ups and downs of the side surface 13, which is conducive to improving the coating quality at the subsequent junction. In addition, the pit R located in the second area A2 can also partially improve the light trapping effect of the incident light.
[0084] In some embodiments, the depth of the pit R is 0.05 μm to 2 μm (eg, 0.05 μm to 0.1, 0.1 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, etc.).
[0085] In some embodiments, the distribution ratio of the first area A1 on the side surface 13 along the direction extending from the first surface 11 to the second surface 12 is 20%-100%. Specifically, the distribution ratio of the first area A1 on the side surface 13 along the direction extending from the first surface 11 to the second surface 12 refers to: the percentage of the length of the first area A1 in the thickness direction of the solar cell 100 to the thickness of the solar cell 100. More specifically, the length of the first area A1 in the thickness direction of the solar cell 100 refers to: the vertical distance from the intersection of the first surface 11 and the side surface 13 to the lowest point of the boundary line between the first area A1 and the second area A2 along the thickness direction of the solar cell 100.
[0086] In some embodiments, along the direction extending from the first surface 11 to the second surface 12, the first area A1 has a width X (shown in FIG. Figure 4 The width X of the first area A1 and the thickness L of the silicon substrate 10 (shown in Figure 4 The ratio range is 20%-100% (e.g., 20% to 35%, 35% to 40%, 40% to 55%, 55% to 70%, 70% to 80%, 80% to 85%, 85% to 90%, 90% to 95%, 95% to 100%, etc.).
[0087] Therefore, the minimum value of the proportion range of the first area A1 can ensure that the pyramid structure T11 is distributed on the side 13, which can increase the light trapping effect of the side 13, and the maximum value of the proportion range can ensure that the pyramid structure T11 satisfies the light trapping effect while having sufficient area to allow the second texture area A12 to extend between the first texture areas A11, thereby increasing the surface area of the side with the first texture area and improving the coating quality of the passivation layer.
[0088] In some embodiments, combined with the process, the proportion of the first area A1 can ensure that the film layer to be cleaned on the first surface 11 is completely removed during the chain etching process, providing a good surface foundation for subsequent texturing, coating and other processes. At the same time, the proportion of the first area A1 can improve the problem of excessive etching of the film layer on the back side (second surface 12) during the chain etching process.
[0089] In some embodiments, the first area A1 accounts for 80%-100% of the side 13, so that the distribution of the multiple pyramid structures T11 and the multiple prismatic structures T12 occupies most or even all of the side 13, and thus the multiple pyramid structures T11 and the multiple prismatic structures T12 on the side 13 are beneficial to improving the light trapping effect and passivation performance of the solar cell 100 while balancing the relationship between the two, ultimately improving the cell efficiency of the solar cell 100.
[0090] In some embodiments, along the direction extending from the second surface 12 to the first surface 11, the distribution ratio of the second area A2 on the side surface 13 is greater than 0 and less than or equal to 80%. Specifically, along the direction extending from the second surface 12 to the first surface 11, the ratio of the width (LX) of the second area A2 to the thickness L of the silicon substrate 10 is greater than or equal to 0 and less than or equal to 80% (e.g., 0 to 5%, 5% to 10%, 10% to 15%, 15% to 18%, 18% to 20%, 20% to 35%, 35% to 40%, 40% to 55%, 55% to 70%, 70% to 80%, etc.).
[0091] When the ratio of the width (LX) of the second area A2 to the thickness L of the silicon substrate 10 is too small, the risk of over-etching the functional layer of the second surface 12 increases; when the ratio is too large, it is difficult to ensure the de-plating effect of the first surface 11. In this way, the probability of generating micro defects between layers due to the different lateral etching efficiencies of the functional layer and the silicon substrate 10 can be reduced, so as to reduce the problem of compounding of the final battery, improve the passivation effect of the battery, and thus improve the battery efficiency of the battery.
[0092] In some embodiments, the side surface 13 is composed of the first area A1 and the second area A2. That is, in any side surface 13, along the direction extending from the second surface 12 to the first surface 11, the sum of the distribution ratio of the first area A1 on the side surface 13 and the distribution ratio of the second area A2 on the side surface 13 is 100%.
[0093] In some embodiments, the second area A2 is formed on at least one of the first side surface 131, the second side surface 132, the third side surface 133, and the fourth side surface 134. That is, the second area A2 (or the coexistence structure of the polishing surface and the tower base structure T13) can be formed on any one, any two, any three, or any four of the first side surface 131, the second side surface 132, the third side surface 133, and the fourth side surface 134.
[0094] In some embodiments, the second area A2 may not exist on the first side surface 131 , the second side surface 132 , the third side surface 133 , and the fourth side surface 134 .
[0095] Figure 7 FIG. 1 is a scanning electron microscope image of the first surface 11 of the solar cell 100 according to an embodiment of the present application. Figure 7 As shown, the first surface 11 has a plurality of third pyramid structures T21 to increase the light trapping effect on the side where the first surface 11 of the solar cell 100 is located.
[0096] It should be noted that the sizes of the third pyramid structure T21 on the first surface 11 and the pyramid structure T11 on the side surface 13 are not completely consistent, and there is a size difference between them.
[0097] Illustratively, the bottom surface size of the third pyramid structure T21 ranges from 0.05 μm to 2 μm (eg, 0.05 μm to 0.1 μm, 0.1 μm to 0.5 μm, 0.5 μm to 1.1 μm, 1.1 μm to 1.3 μm, 1.3 μm to 1.5 μm, 1.5 μm to 1.8 μm, 1.8 μm to 2 μm, etc.).
[0098] For example, the height of the third pyramid structure T21 ranges from 0.1 μm to 2 μm (e.g., 0.1 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.3 μm, 1.3 μm to 1.5 μm, 1.5 μm to 1.8 μm, 1.8 μm to 2 μm, etc.). When the lateral dimension of the bottom surface of the third pyramid structure T21 and the longitudinal height are not appropriate, the secondary reflection of the light by the third pyramid structure T21 is insufficient, resulting in an increase in the suede reflectivity, which deteriorates the light absorption performance of the battery.
[0099] Specifically, the orthographic projection shape of the bottom surface of the pyramid structure T11 on the side surface 13 and the orthographic projection shape of the third pyramid structure T21 on the first surface 11 can be a regular quadrilateral or an irregular polygon. Figure 8In Figure (a), the structural dimensions of the base of the pyramid structure T11 and the third pyramid structure T21 are: the length d1 of the longest diagonal line of the base of the pyramid structure or the longest side length d2. When it is an irregular quadrilateral, the side length and diagonal length of the base of the pyramid structure T11 and the third pyramid structure T21 are not absolute, but are artificially defined to characterize the size of the bottom surface. For example, the side length of the base of the pyramid structure T11 and the third pyramid structure T21 can be defined as the side length of the longest side of the irregular quadrilateral, and the diagonal length of the base of the pyramid structure T11 and the third pyramid structure T21 can be defined as the length of the longest diagonal line of the irregular quadrilateral. The tower height of the pyramid structure T11 and the third pyramid structure T21 is: the height from the top of the pyramid structure to the bottom surface. It can be understood that the above is only an exemplary description, and it can be flexibly defined according to actual needs in practice.
[0100] It should be noted that the pyramid structures T11 and the third pyramid structures T21 are both distributed in different sizes, and the above sizes are the structural sizes of the pyramid structures T11 and / or the structural sizes of the third pyramid structures T21 that are more evenly distributed in the interface when the velvet surface on the first surface 11 or the side surface 13 is magnified and observed. Figure 8 Figure (a) is a schematic diagram of the testing method, and has no direct correlation with the actual bottom surface morphology of the pyramid structure T11 and the actual bottom surface morphology of the third pyramid structure T21.
[0101] Specifically, Figure 8 As shown in Figure (b), the method for testing the base surface size of the tower base structure T13 is: parallel to the bottom surface direction of the tower base structure T13, the larger value of the diagonal length d3 and the diagonal length d4 of the tower base, and the method for testing the longitudinal height of the tower base structure T13 is: the height difference between the bottom surface of the tower base structure T13 and the plane of the side surface 13.
[0102] It should be noted that the tower base structures T13 are distributed in different sizes, and the above size is the size of the tower base structure T13 that is relatively evenly distributed in the interface when the velvet surface on the side surface 13 is magnified. Figure 8 Figure (b) is a schematic diagram of the test method and has no direct correlation with the actual morphology of the tower base structure T13.
[0103] The embodiment of the present application also provides a photovoltaic assembly. The photovoltaic assembly includes a plurality of solar cells electrically connected to each other. The solar cell is a solar cell according to any of the above embodiments.
[0104] In some embodiments, the method for preparing a solar cell of the above embodiment includes the following steps S10 to S60.
[0105] According to different requirements, the order of some steps or sub-steps of the method for preparing the solar cell can be changed, and some steps or sub-steps can be omitted or combined.
[0106] Step S10: providing a silicon substrate, the silicon substrate comprising a first surface and a second surface opposite to each other and a side surface connecting the first surface and the second surface, and forming a tower base structure on the first surface, the second surface and the side surface.
[0107] Specifically, the silicon substrate can be a P-type original silicon wafer or an N-type original silicon wafer. The silicon substrate is subjected to alkali polishing in a slot machine to form a tower base morphology on the surface of the silicon substrate. The tower base morphology includes a coexistence structure of a polished surface and a tower base structure, or the tower base morphology is a polished tower base structure.
[0108] Illustratively, the lateral dimension range of the base of the base structure formed in step S10 is 10μm to 30μm (such as 10μm to 12μm, 12μm to 13μm, 13μm to 14.5μm, 14.5μm to 15μm, 15μm to 20μm, 20μm to 25μm, 25μm to 28μm, 28μm to 30μm, etc.).
[0109] Illustratively, the longitudinal height range of the tower base structure formed in step S10 is 0.01μm to 8μm (such as 0.01μm to 0.05μm, 0.05μm to 0.1μm, 0.1μm to 0.4μm, 0.4μm to 0.5μm, 0.5μm to 0.7μm, 0.7μm to 1μm, 1μm to 1.3μm, 1.3μm to 1.5μm, 1.5μm to 1.8μm, 1.8μm to 2.3μm, 2.3μm to 2.8μm, 2.8μm to 3.3μm, 3.3μm to 4μm, 4μm to 5μm, 5μm to 6μm, 6μm to 7μm, 7μm to 8μm, etc.).
[0110] For example, the tower base of the tower base structure formed in step S10 is rectangular, the size of the rectangle is 15 μm×14.5 μm, and the longitudinal size of the tower base of the tower base structure is 0.5 μm.
[0111] Step S20: sequentially forming a dielectric layer and a doped conductive layer on the second surface, the side surface and at least a portion of the first surface of the silicon substrate, wherein the doped conductive layer is located on the side of the dielectric layer away from the silicon substrate. The doped conductive layer may be a doped polysilicon layer.
[0112] Specifically, a passivation layer (such as silicon oxide or aluminum oxide) is prepared by low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD), and doping atoms are diffused to form a boron-doped polysilicon structure or / and a phosphorus-doped polysilicon structure. The dielectric layer and the doped polysilicon layer cover the second surface, multiple side surfaces, and a portion of the first surface.
[0113] The dielectric layer formed in step S20 is the first dielectric layer and the second dielectric layer mentioned above.
[0114] The step of doping atom diffusion in step S20 is performed at least once. In some embodiments, the step of doping atom diffusion may be performed twice or more.
[0115] Step S30: removing the dielectric layer and the doped polysilicon layer on the first surface and at least removing a portion of the dielectric layer and the doped polysilicon layer on the first region of the side surface close to the first surface.
[0116] In step S30, a chain etching device is used to etch away the dielectric layer and the doped polysilicon layer on the entire first surface and all or part of the side surfaces.
[0117] Specifically, a silicon substrate formed with a dielectric layer and a doped polysilicon layer is placed in a chain etching device, so that one side of the first surface of the silicon substrate is in contact with the etching solution used by the chain etching device, and the etching solution at least covers part of the dielectric layer and the doped polysilicon layer located on the side.
[0118] In some embodiments, along the direction extending from the first surface to the second surface, the distribution ratio of the first area on the side surface is 20%-100%.
[0119] For example, 85% of the side surface is in full contact with the etching liquid (the side close to the first surface), and 15% of the side surface is not in contact with the etching liquid (the side close to the second surface).
[0120] Step S40: forming a first region and / or a second region on the side surface.
[0121] Alkali texturing is performed to form a pyramid structure. The size of the pyramid structure can be controlled by controlling the type of additives and the reaction time to form a first pyramid structure and a second pyramid structure, or the first pyramid structure and the second pyramid structure can be formed separately by step-by-step texturing.
[0122] During the alkali texturing process, the exposed silicon substrate surface is corroded by the alkali solution to form a velvet pyramid structure. However, the unexposed silicon substrate surface does not form a velvet surface during texturing, because the dielectric layer (such as silicon oxide) and the alkali solution basically do not react under the process conditions, and the velvet surface of this part of the silicon substrate surface does not appear to be a tower base structure.
[0123] For example, during the alkali texturing process, the first surface of the exposed silicon substrate and 85% of the side surface near the front surface will be alkali-etched to form a combined structure of the first texture area and the second texture area. The 15% side surface near the back surface is protected by the dielectric layer and the doped polysilicon layer, and no pyramid structure is formed, and the pyramid base structure can be observed.
[0124] Step S50: forming a passivation layer and an anti-reflection layer.
[0125] Specifically, an atomic layer deposition (ALD) can be used to deposit a passivation layer on the side where the first surface of the silicon substrate is located, the side where the second surface is located, and multiple side surfaces to provide a passivation effect. Plasma-enhanced chemical vapor deposition can be used to deposit an anti-reflection layer on the side where the first surface of the silicon substrate is located, the side where the second surface is located, and multiple side surfaces. The velvet pyramid structure on the front side and the velvet pyramid and tower base combined morphology on the side surface can be observed after the passivation layer and the anti-reflection layer are formed.
[0126] Step S60: forming electrodes.
[0127] Specifically, the electrode can be formed by screen printing. The morphology of the front velvet pyramid structure combined with the side velvet pyramid structure and the tower base structure can be observed after printing the electrode.
[0128] In summary, the side of the solar cell of the embodiment of the present application includes multiple first pyramid structures, multiple second pyramid structures and multiple prismatic structures. The first pyramid structure in the first texture area can enhance the light trapping effect on the side of the solar cell and improve the light utilization rate of the solar cell. In addition, the second pyramid structure in the second texture area is designed, and the larger structural size of the second pyramid structure can provide a larger surface area than the first pyramid structure, providing a larger coating area for subsequent coating and improving the coating quality. Therefore, the mixed structure of multiple first pyramid structures and multiple second pyramid structures can better take into account the side passivation and light trapping effects of the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell.
[0129] In addition, compared to the velvet structure of the pyramid, the prismatic structure of the second texture area has a larger surface area, providing a larger deposition area for the subsequent deposition of the passivation layer. Therefore, compared to the single velvet structure in the related art, the hybrid structure of the first pyramid structure, the second pyramid structure and the prismatic structure can better take into account the passivation and light trapping functions of the side of the solar cell.
[0130] The above implementation modes are only used to illustrate the technical solutions of the present application and are not intended to limit the present application. Although the present application has been described in detail with reference to the above preferred implementation modes, a person skilled in the art should understand that the technical solutions of the present application may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present application.
Claims
1. A solar cell, characterized in that: The invention comprises a silicon substrate and a passivation layer, wherein the silicon substrate comprises a first surface and a second surface opposite to each other and a plurality of side surfaces connecting the first surface and the second surface; At least one of the side surfaces comprises a plurality of first textured regions and a second textured region, each of the first textured regions comprises a plurality of first pyramid structures, and each of the second textured regions comprises a plurality of second pyramid structures; The structural size of the second pyramid structure is greater than the structural size of the first pyramid; The second texture area is provided between adjacent first texture areas; The passivation layer covers the first texture region and the second texture region of at least one of the side surfaces.
2. The solar cell according to claim 1, wherein: The second texture area extends between the first texture areas in any one or more of a straight line, a broken line or a curved line.
3. The solar cell according to claim 2, characterized in that An extension direction of the second texture region is not parallel to a thickness direction of the solar cell, and / or extension directions of at least two of the second texture regions are arranged in parallel.
4. The solar cell according to claim 1, wherein: The second textured region includes prismatic structures, and the length of the prismatic structures ranges from 200 nm to 6 μm.
5. The solar cell according to claim 1, wherein: The structural size of the first pyramid structure ranges from 0.05 μm to 2 μm.
6. The solar cell according to claim 1, wherein: The second pyramid structure has a structural size ranging from 2 μm to 6 μm.
7. The solar cell according to claim 1, wherein: The side surface includes a first area, the first area is connected to the first surface, the first texture area and the second texture area are both arranged on the first area, and the width of the first area accounts for 20% to 100% of the width of the side surface.
8. The solar cell according to claim 1, wherein: The side surface includes a first area and a second area, the first texture area and the second texture area are both arranged on the first area, the second area is connected to one side of the second surface, and the second area includes a plurality of tower base structures.
9. The solar cell according to claim 8, characterized in that A boundary line between the first region and the second region is a curve, and a pit is arranged in the second region near the boundary line.
10. The solar cell according to claim 9, characterized in that Along the thickness direction of the silicon substrate, the width of the region where the pit is provided is 0 to 60% of the width of the second region.
11. The solar cell according to claim 9, wherein: The shape of the pit includes one or more of an inverted pyramid, an inverted hemisphere, and a terrace, and / or the cross-sectional area of the pit gradually increases along a direction vertically and away from the side surface.
12. The solar cell according to claim 9, wherein: The diameter of the cross section of the pit on the side surface is 0.1 μm to 5 μm, and / or the depth of the pit is 0.05 μm to 2 μm.
13. The solar cell according to claim 1, wherein: Along a direction away from the silicon substrate, the passivation layer includes an aluminum oxide layer and a silicon nitride layer which are sequentially arranged.
14. A photovoltaic module, characterized in that: The invention comprises a plurality of solar cells electrically connected to each other, wherein the solar cells are the solar cells according to any one of claims 1 to 13.
Citation Information
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