A Method and Circuit for Suppressing Charge Pump Electromagnetic Interference

Abstract

The present invention discloses a method and a circuit for suppressing electromagnetic interference of a charge pump, which relates to the technical field of charge pump oscillation, and aims to solve the problem of excessive electromagnetic interference during the operation of the charge pump in the prior art. The method includes: performing clock frequency division on the system clock of the charge pump according to the Gaussian distribution curve to obtain a first clock frequency division; determining a target oscillation unit based on the first clock frequency division and in combination with the performance parameters of multiple oscillation units in the oscillation circuit; determining a target oscillator based on the target oscillation unit; turning on the target oscillator, and obtaining a target clock source square wave for driving the charge pump to operate by using a buffer circuit; the target clock source square wave is used to reduce the electromagnetic interference during the operation of the charge pump; driving the charge pump based on the target clock source square wave; realizing that the electromagnetic interference of the charge pump takes the main radiation frequency as the core oscillation frequency and is distributed according to the Gaussian curve, and improving the suppression effect on the electromagnetic interference.

Description

Technical Field

[0001] The present invention relates to the technical field of electromagnetic spectrum, and in particular to a method and circuit for suppressing charge pump electromagnetic interference. Background Art

[0002] Electromagnetic Interference (EMI) refers to the impact of an electronic device or system on the surrounding electromagnetic environment during operation, which may interfere with the normal operation of other devices or systems. This interference may originate from the radiation emissions of various electronic devices or the influence of external electromagnetic fields on the device.

[0003] A charge pump, also known as a switched-capacitor DC / DC converter, is a DC / DC converter that uses so-called "flying" or "pumping" capacitors (instead of inductors or transformers) to store energy. It can increase or decrease the input voltage and can also be used to generate negative voltages. The internal FET switch array controls the charging and discharging of the pump capacitors in a certain way, so that the input voltage is multiplied or decreased by a certain factor (0.5 times voltage, 2 times voltage or 3 times voltage) to obtain the required output voltage. This special modulation process can ensure an efficiency of up to 80%, and only requires an external ceramic capacitor to complete. However, since the circuit operates in a switching state, the charge pump will also generate certain output ripple and EMI (electromagnetic interference).

[0004] In the prior art, a motor drive chip with a built-in charge pump usually uses a fixed oscillator as the clock source. When the charge pump operates, a very high charge pump current will be generated at some specific frequencies, resulting in too high EMI of the entire chip. For the problem of too high EMI, the commonly used method is to configure a board-level filter with a very high suppression ability for a single frequency to suppress the high-oscillation EMI, but this only treats the symptoms and does not solve the problem fundamentally, hindering the rapid application of the motor drive chip with a built-in charge pump. Therefore, there is an urgent need to design a design scheme that can reduce the excessive electromagnetic interference when the charge pump in the motor drive chip operates, so as to solve the problem of excessive electromagnetic interference when the charge pump operates in the prior art. Summary of the Invention

[0005] The purpose of the present invention is to disclose a method and circuit for suppressing charge pump electromagnetic interference, which is used to solve the problem of excessive electromagnetic interference when the charge pump operates in the prior art.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] In a first aspect, the present invention provides a method for suppressing charge pump electromagnetic interference, which may include:

[0008] According to the Gaussian distribution curve, the system clock of the charge pump is frequency-divided to obtain the first clock frequency division.

[0009] Based on the first clock frequency division and in combination with the performance parameters of multiple oscillation units in the oscillation circuit, a target oscillation unit is determined; wherein, the current sources of the multiple oscillation units are proportionally set according to the Gaussian distribution.

[0010] Based on the target oscillation unit, a target oscillator is determined; the target oscillator is used to control the MOS transistor connected to the target oscillator in the target oscillation unit.

[0011] The target oscillator is turned on, and a target clock source square wave for driving the charge pump to work is obtained by using a buffer circuit; the target clock source square wave is used to reduce the electromagnetic interference during the operation of the charge pump.

[0012] Based on the target clock source square wave, the charge pump is driven.

[0013] Preferably, the step of turning on the target oscillator and obtaining a target clock source square wave for driving the charge pump to work by using a buffer circuit may include:

[0014] During the charging process, when it is detected that the voltage of the charge and discharge node of the oscillation circuit is at a low level, the high-side current source of the target oscillation unit is turned on, and the low-side current source of the target oscillation unit is turned off to charge a target capacitor; the target capacitor is a capacitor connected to the charge and discharge node.

[0015] During the discharging process, when it is detected that the voltage of the charge and discharge node of the oscillation circuit is at a high level, the high-side current source of the target oscillation unit is turned off, and the low-side current source of the target oscillation unit is turned on to discharge the target capacitor.

[0016] Based on the buffer circuit connected to the charge and discharge node, the target clock source square wave for driving the charge pump to work is obtained.

[0017] Preferably, the step of driving the charge pump based on the target clock source square wave may include: driving the charge pump based on the target clock source square wave and in combination with the current levels in the charge pump according to a preset working stage.

[0018] Preferably, the current levels may include a first current level, a second current level, a third current level, a fourth current level, and a fifth current level.

[0019] The step of driving the charge pump according to a preset working stage may include: in the startup stage of the charge pump, only the second current level and the first current level are turned on; the second current level is used to increase the startup speed of the charge pump; the first current level is a normally open current source.

[0020] During the stage when the charge pump provides a large current to the load, only the third current stage and the first current stage are turned on; the third current stage is used to increase the charge pump speed; the driving ability of the third current stage is greater than that of the second current stage;

[0021] During the stage when the load current is stable, only the first current stage is turned on;

[0022] During the stage when the load current changes instantaneously, the fourth current stage is turned on; the fourth current stage is used to increase the charge pump response speed;

[0023] During the stage when the current of the charge pump output stage remains high, the fifth current stage is turned on; the fifth current stage is used to accelerate the decrease of the current of the charge pump output stage.

[0024] In a second aspect, the present invention provides a circuit for suppressing electromagnetic interference of a charge pump. The suppression circuit is used to implement the method for suppressing electromagnetic interference of a charge pump described in the first aspect. The circuit may at least include:

[0025] An oscillation circuit, an enable control circuit, a buffer circuit, and a charge pump;

[0026] The oscillation circuit is connected to the enable control circuit; the oscillation circuit may include a plurality of oscillation units, and the current sources of the plurality of oscillation units are set in proportion according to a Gaussian distribution; the enable control circuit includes a plurality of oscillators, and the oscillators are used to control the MOS transistors in the oscillation units connected to the oscillators;

[0027] The oscillation circuit is connected to the buffer circuit, and the buffer circuit is connected to the charge pump; the buffer circuit is used to determine the target clock source square wave for driving the charge pump to work, and based on the target clock source square wave, drive the charge pump; wherein, the target clock source square wave is used to reduce the electromagnetic interference during the operation of the charge pump.

[0028] Preferably, the plurality of oscillation units may at least include a first oscillation unit, a second oscillation unit, a third oscillation unit, a fourth oscillation unit, and a fifth oscillation unit;

[0029] The current sources of the first oscillation unit, the second oscillation unit, the third oscillation unit, the fourth oscillation unit, and the fifth oscillation unit are set in proportion according to a Gaussian distribution;

[0030] The enabling control circuit may at least include a first oscillator, a second oscillator, a third oscillator, a fourth oscillator, and a fifth oscillator; the first oscillator is connected to the first oscillation unit, the second oscillator is connected to the second oscillation unit, the third oscillator is connected to the third oscillation unit, the fourth oscillator is connected to the fourth oscillation unit, and the fifth oscillator is connected to the fifth oscillation unit.

[0031] Preferably, the first oscillation unit may include a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor; the first oscillator may include a first logic OR gate, a first logic AND gate, and a first logic NOT gate;

[0032] The source of the first PMOS transistor is connected to the power supply terminal, the gate is connected to the P reference terminal, and the drain is connected to the source of the second PMOS transistor; the gate of the second PMOS transistor is connected to the output terminal of the first logic OR gate, and the drain is connected to the charge and discharge node;

[0033] The source of the first NMOS transistor is grounded, the gate is connected to the N reference terminal, and the drain is connected to the source of the second NMOS transistor; the gate of the second NMOS transistor is connected to the output terminal of the first logic AND gate, and the drain is connected to the charge and discharge node;

[0034] The first input terminal of the first logic OR gate is connected to the charge and discharge node, and the second input terminal is connected to the first oscillator enable terminal; the first input terminal of the first logic AND gate is connected to the output terminal of the first logic NOT gate, the input terminal of the first logic NOT gate is connected to the first oscillator enable terminal, and the second input terminal of the first logic AND gate is connected to the charge and discharge node.

[0035] Preferably, the buffer circuit may at least include a thirteenth PMOS transistor, a fourteenth PMOS transistor, a thirteenth NMOS transistor, and a fourteenth NMOS transistor;

[0036] The source of the thirteenth PMOS transistor is connected to the power supply terminal, the gate is connected to the charge and discharge node, and the drain is connected to the first output terminal of the buffer circuit; the source of the thirteenth NMOS transistor is grounded, the gate is connected to the charge and discharge node, and the drain is connected to the first output terminal of the buffer circuit;

[0037] The source of the fourteenth PMOS transistor is connected to the power supply terminal, the gate is connected to the first output terminal of the buffer circuit, and the drain is connected to the second output terminal of the buffer circuit; the source of the fourteenth NMOS transistor is grounded, the gate is connected to the first output terminal of the buffer circuit, and the drain is connected to the second output terminal of the buffer circuit.

[0038] Preferably, the charge pump may at least include an input stage, a current stage, an output stage, and a boost stage;

[0039] The input stage is connected to the buffer circuit, the current stage, and the output stage; the current stage is connected to the output stage; the output stage is connected to the boost stage; the boost stage is connected to an external load.

[0040] Preferably, the current stage may include a first current stage, a second current stage, a third current stage, a fourth current stage, and a fifth current stage; an oscillation circuit, an enable control circuit, a buffer circuit, and a charge pump.

[0041] The oscillation circuit is connected to the enable control circuit; the oscillation circuit includes a plurality of oscillation units, and the current sources of the plurality of oscillation units are proportionally set according to a Gaussian distribution; the enable control circuit includes a plurality of oscillators, and the oscillators are used to control the MOS transistors in the oscillation units connected to the oscillators; the oscillation circuit is connected to the buffer circuit, and the buffer circuit is connected to the charge pump; the buffer circuit is used to determine a target clock source square wave for driving the charge pump to work, and based on the target clock source square wave, drive the charge pump; wherein, the target clock source square wave is used to reduce electromagnetic interference during the operation of the charge pump.

[0042] Preferably, the plurality of oscillation units at least include a first oscillation unit, a second oscillation unit, a third oscillation unit, a fourth oscillation unit, and a fifth oscillation unit; the current sources of the first oscillation unit, the second oscillation unit, the third oscillation unit, the fourth oscillation unit, and the fifth oscillation unit are proportionally set according to a Gaussian distribution; the enable control circuit at least includes a first oscillator, a second oscillator, a third oscillator, a fourth oscillator, and a fifth oscillator; the first oscillator is connected to the first oscillation unit, the second oscillator is connected to the second oscillation unit, the third oscillator is connected to the third oscillation unit, the fourth oscillator is connected to the fourth oscillation unit, and the fifth oscillator is connected to the fifth oscillation unit.

[0043] Preferably, the first oscillation unit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor; the first oscillator includes a first logic OR gate, a first logic AND gate, and a first logic NOT gate; the source of the first PMOS transistor is connected to the power supply terminal, the gate is connected to the P reference terminal, and the drain is connected to the source of the second PMOS transistor. The gate of the second PMOS transistor is connected to the output terminal of the first logic OR gate, and the drain is connected to the charge and discharge node; the source of the first NMOS transistor is grounded, the gate is connected to the N reference terminal, and the drain is connected to the source of the second NMOS transistor. The gate of the second NMOS transistor is connected to the output terminal of the first logic AND gate, and the drain is connected to the charge and discharge node; the first input terminal of the first logic OR gate is connected to the charge and discharge node, and the second input terminal is connected to the first oscillator enable terminal; the first input terminal of the first logic AND gate is connected to the output terminal of the first logic NOT gate, the input terminal of the first logic NOT gate is connected to the first oscillator enable terminal, and the second input terminal of the first logic AND gate is connected to the charge and discharge node.

[0044] Preferably, the buffer circuit includes at least an eleventh PMOS transistor, a twelfth PMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor; the source of the eleventh PMOS transistor is connected to the power supply terminal, the gate is connected to the charge and discharge node, and the drain is connected to the first output terminal of the buffer circuit; the source of the eleventh NMOS transistor is grounded, the gate is connected to the charge and discharge node, and the drain is connected to the first output terminal of the buffer circuit; the source of the twelfth PMOS transistor is connected to the power supply terminal, the gate is connected to the first output terminal of the buffer circuit, and the drain is connected to the second output terminal of the buffer circuit; the source of the twelfth NMOS transistor is grounded, the gate is connected to the first output terminal of the buffer circuit, and the drain is connected to the second output terminal of the buffer circuit.

[0045] Preferably, the charge pump includes at least an input stage, a current stage, an output stage, and a boosting stage; the input stage is connected to the buffer circuit, the current stage, and the output stage; the current stage is connected to the output stage; the output stage is connected to the boosting stage; the boosting stage is connected to an external load.

[0046] Preferably, the current levels include a first current level, a second current level, a third current level, a fourth current level, and a fifth current level; the first current level includes a fifteenth NMOS transistor; the second current level includes a sixteenth NMOS transistor and a seventeenth NMOS transistor; the third current level includes an eighteenth NMOS transistor and a nineteenth NMOS transistor; the fourth current level includes a twentieth NMOS transistor and a twenty-first NMOS transistor; the fifth current level includes a twenty-second NMOS transistor; the drain of the fifteenth NMOS transistor is connected to the input stage of the charge pump, the gate is connected to the N reference terminal, and the source is grounded; the drain of the sixteenth NMOS transistor is connected to the drain of the fifteenth NMOS transistor, the gate is connected to the first charge pump enable signal terminal, and the source is connected to the drain of the seventeenth NMOS transistor; the gate of the seventeenth NMOS transistor is connected to the N reference terminal and the source is grounded; the drain of the eighteenth NMOS transistor is connected to the drain of the fifteenth NMOS transistor, the gate is connected to the second charge pump enable signal terminal, and the source is connected to the drain of the nineteenth NMOS transistor; the gate of the nineteenth NMOS transistor is connected to the N reference terminal and the source is grounded; the drain of the twentieth NMOS transistor is connected to the drain of the fifteenth NMOS transistor, the gate is connected to the third charge pump enable signal terminal, and the source is connected to the drain of the twenty-first NMOS transistor; the gate of the twenty-first NMOS transistor is connected to the N reference terminal and the source is grounded; the drain of the twenty-second NMOS transistor is connected to the drain of the fifteenth NMOS transistor, the gate is connected to the output stage, and the source is connected to the drain of the twenty-first NMOS transistor.

[0047] Compared with the prior art, a method for suppressing electromagnetic interference of a charge pump provided by the present invention performs clock division on the system clock of the charge pump according to the Gaussian distribution curve to obtain a first clock division; based on the first clock division, in combination with the performance parameters of multiple oscillation units in the oscillation circuit, a target oscillation unit is determined; wherein, the current sources of the multiple oscillation units are set proportionally according to the Gaussian distribution; based on the target oscillation unit, a target oscillator is determined; the target oscillator is used to control the MOS transistors connected to the target oscillator in the target oscillation unit; the target oscillator is turned on, and a target clock source square wave for driving the charge pump to work is obtained by using a buffer circuit; the target clock source square wave is used to reduce the electromagnetic interference during the operation of the charge pump; based on the target clock source square wave, the charge pump is driven; based on this, based on the Gaussian distribution curve, the charge pump can work at different clock frequencies at different times, distribute the pulsed current to different frequencies, and achieve that the electromagnetic interference of the charge pump takes the main radiation frequency as the core oscillation frequency and is distributed according to the Gaussian curve, improving the suppression effect on the electromagnetic interference generated during the operation of the charge pump. Description of the Drawings

[0048] The accompanying drawings described herein are used to provide a further understanding of the present invention, and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0049] Figure 1 is a schematic structural diagram of a motor drive chip with a built-in charge pump in the prior art;

[0050] Figure 2 is an improved schematic structural diagram of a motor drive chip with a built-in charge pump in the prior art;

[0051] Figure 3 is a schematic flowchart of a method for suppressing charge pump electromagnetic interference provided by the present invention;

[0052] Figure 4 is a charge pump output EMI frequency distribution diagram of a method for suppressing charge pump electromagnetic interference provided by the present invention;

[0053] Figure 5 is a filter frequency response distribution diagram of a method for suppressing charge pump electromagnetic interference provided by the present invention;

[0054] Figure 6 is a first schematic structural diagram of a circuit for suppressing charge pump electromagnetic interference provided by the present invention;

[0055] Figure 7 is a second schematic structural diagram of a circuit for suppressing charge pump electromagnetic interference provided by the present invention;

[0056] Figure 8 is a first schematic structural diagram of a suppression circuit for suppressing charge pump electromagnetic interference provided by the present invention;

[0057] Figure 9 is a second schematic structural diagram of a suppression circuit for suppressing charge pump electromagnetic interference provided by the present invention.

[0058] Reference numerals: 500 - Oscillation circuit, 600 - Enable control circuit, 700 - Buffer circuit, 800 - Charge pump, 510 - First oscillation unit, 520 - Second oscillation unit, 530 - Third oscillation unit, 540 - Fourth oscillation unit, 550 - Fifth oscillation unit, 610 - First oscillator, 620 - Second oscillator, 630 - Third oscillator, 640 - Fourth oscillator, 650 - Fifth oscillator, 810 - Input stage, 820 - Current stage, 830 - Output stage, 840 - Boost stage, 821 - First current stage, 822 - Second current stage, 823 - Third current stage, 824 - Fourth current stage, 825 - Fifth current stage, 841 - First capacitor, 842 - Second capacitor, 843 - First diode, 844 - Second diode. DETAILED DESCRIPTION

[0059] In order to facilitate the clear description of the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, the words "first", "second" and the like are used to distinguish the same items or similar items with substantially the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and do not limit their order of precedence. Those skilled in the art can understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like do not necessarily limit them to be different.

[0060] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0061] In the present invention, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects in the previous time are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.

[0062] The charge pump uses an external fast-charging capacitor (Flying Capacitor) to switch internally at a certain frequency to charge the capacitor, and together with the input voltage, it performs a step-up (or step-down) conversion and finally outputs a constant voltage.

[0063] In recent years, charge pumps have been widely used, from unregulated single-output ICs to regulated ICs with multiple output voltages. Output power and efficiency have also been developed, so that today's charge pumps can output currents up to 250mA with efficiencies of 75% (average). Charge pumps are mostly used in systems that require batteries, such as cellular phones, pagers, Bluetooth systems, and portable electronic devices.

[0064] Currently, for motor driver chips with built-in charge pumps, please refer to Figure 1 ,Figure 1 It is a schematic structural diagram of a motor drive chip with a built-in charge pump in the prior art. In Figure 1 , a single-oscillation-frequency oscillator is used as the clock source for driving the charge pump inside; when the charge pump is working, since the clock source is of a single frequency, the charge pump will generate a very high charge pump current at certain frequencies, resulting in excessive EMI (Electromagnetic Interference) of the entire chip. To address this problem, a board-level filter with a very high suppression ability for a single frequency is required to filter out the electromagnetic interference, increasing the design difficulty of the board-level filter.

[0065] In view of the above problems, there is an improved solution in the prior art. Please refer to Figure 2 , Figure 2 It is a schematic structural diagram of an improved motor drive chip with a built-in charge pump in the prior art. In Figure 2 , an EMI improvement circuit is adopted to randomize the output frequency of the oscillator circuit or randomize the frequency of the charge pump, so that the operating frequency of the charge pump is randomly distributed or distributed according to Gaussian white noise; although this solution can avoid the large current caused by a single clock frequency, after the driving frequency of the charge pump is randomly distributed, the current generated by the charge pump will be randomized within a certain frequency range; therefore, a board-level filter with a very wide suppression band is required to filter out the electromagnetic interference generated by the charge pump; this technical solution does not completely solve the problem of electromagnetic interference of the motor drive chip with a built-in charge pump in the prior art, and also puts forward higher requirements for the filtering performance of the board-level filter, resulting in difficult filter design and even inability to meet the design of a wide suppression band; it hinders the commercial application of the chip with a built-in charge pump.

[0066] In view of this, the present invention provides a method and circuit for suppressing charge pump electromagnetic interference, which can solve the problem of excessive electromagnetic interference when the charge pump works in the prior art. After suppressing the charge pump electromagnetic interference through the technical solution provided by the present invention, the electromagnetic interference generated by the charge pump can be filtered out by a currently conventional board-level filter, meeting the noise design requirements of the motor drive chip with a built-in charge pump.

[0067] Next, the technical solution of the present invention will be described in detail with reference to the accompanying drawings:

[0068] Please refer to Figure 3 , Figure 3 It is a schematic flow diagram of a method for suppressing charge pump electromagnetic interference provided by the present invention. Its execution subject is a server or a terminal device equipped with the technical solution disclosed in the embodiment of the present invention, such as a test service platform or a motor drive chip with a built-in charge pump, etc.

[0069] In Figure 3Among them, the method may include:

[0070] Step 310: According to the Gaussian distribution curve, perform clock division on the system clock of the charge pump to obtain the first clock division.

[0071] Step 320: Based on the first clock division, combined with the performance parameters of multiple oscillation units in the oscillation circuit, determine the target oscillation unit; wherein, the current sources of the multiple oscillation units are proportionally set according to the Gaussian distribution.

[0072] In steps 310 to 320, first, the system clock of the charge pump is divided according to the Gaussian distribution curve to obtain the first clock division that follows the Gaussian distribution; and the current sources of the oscillation units are proportionally set according to the Gaussian distribution; further, based on the first clock division, combined with the performance parameters of multiple oscillation units in the oscillation circuit, determine the target oscillation unit to be turned on when the clock is input, and generate a clock current that conforms to the Gaussian distribution based on this target oscillation unit.

[0073] Step 330: Based on the target oscillation unit, determine the target oscillator; the target oscillator is used to control the MOS transistor connected to the target oscillator in the target oscillation unit.

[0074] Step 340: Turn on the target oscillator, and use the buffer circuit to obtain the target clock source square wave for driving the charge pump to work; the target clock source square wave is used to reduce the electromagnetic interference during the operation of the charge pump.

[0075] Step 350: Drive the charge pump based on the target clock source square wave.

[0076] In steps 330 to 350, after determining the target oscillation unit, it is necessary to determine the target oscillator to drive the target oscillation unit to work; that is, the working state of the MOS transistor connected to the target oscillator in the target oscillation unit can be controlled through the state of the target oscillator to turn on or off the target oscillation unit, so as to achieve the purpose of generating current sources of different sizes; further, the buffer circuit connected to the oscillation unit can be used to generate the target clock square wave, that is, buffer the current source that conforms to the Gaussian distribution curve generated by the oscillation circuit, so as to obtain the target clock square wave for driving the charge pump, and this square wave also conforms to the Gaussian distribution. Finally, use this target clock source square wave to drive the charge pump, thereby reducing the EMI of the charge pump.

[0077] It should be noted that the Gaussian distribution curve is also called the "normal distribution curve", and its graph has the following characteristics:

[0078] Central tendency: The peak of the normal curve is located in the center, that is, at the position of the mean.

[0079] Symmetry: The normal curve is centered around the mean, symmetric on both the left and right sides, and the two ends of the curve never intersect the horizontal axis.

[0080] Uniform variability: The normal curve starts from the mean and gradually and uniformly descends to both the left and right sides.

[0081] Since the area between the Gaussian distribution curve and the horizontal axis is always equal to 1, which is equivalent to the probability that the function of the probability density function integrates from positive infinity to negative infinity being 1, that is, the total frequency is 100%. Therefore, the clock frequency division varies with time, and the frequency distribution of the divided clock conforms to the Gaussian distribution. The clock square wave that conforms to the Gaussian distribution is input into the charge pump, so that the charge pump works at different clock frequencies at different times, and the pulse current is distributed to different frequencies, thereby reducing the electromagnetic interference generated by the charge pump, and the intensity of the electromagnetic interference also conforms to the Gaussian distribution.

[0082] Further, based on experimental tests, the test results are shown in Figures 4 to 5 , Figure 4 which is the EMI frequency distribution diagram of the charge pump output for a method for suppressing electromagnetic interference of a charge pump provided by the present invention; Figure 5 which is the filter frequency response distribution diagram of a method for suppressing electromagnetic interference of a charge pump provided by the present invention.

[0083] In Figure 4 , the horizontal axis represents the deviation from the center frequency, with the unit of Hz; the vertical axis is the intensity of the electromagnetic interference generated by the charge pump, with the unit of dB; it can be undoubtedly obtained from the curve shown in Figure 4 that the distribution curve of the electromagnetic interference generated during the operation of the charge pump also conforms to the Gaussian distribution.

[0084] In Figure 5 , the horizontal axis represents the deviation from the center frequency, with the unit of Hz; the vertical axis is the intensity of the electromagnetic interference generated by the charge pump, with the unit of dB; it can be undoubtedly obtained from the curve shown in Figure 5 that since the distribution curve of the electromagnetic interference generated during the operation of the charge pump also conforms to the Gaussian distribution; when the operating frequency distribution is like the Gaussian distribution, the operating frequency is very similar to the frequency response curve of the filter, and the filter has a high noise filtering efficiency; therefore, the frequency response of the filter only needs to be designed according to the Gaussian distribution, and there will not be too high a design difficulty, and the conventional design method can meet the frequency response requirements of the filter.

[0085] Based on this, a method for suppressing electromagnetic interference of a charge pump provided by the present invention divides the system clock of the charge pump according to a Gaussian distribution curve to obtain a first clock division; based on the first clock division, in combination with the performance parameters of multiple oscillation units in the oscillation circuit, a target oscillation unit is determined; wherein, the current sources of the multiple oscillation units are set proportionally according to a Gaussian distribution; and based on the target oscillation unit, a target oscillator is determined; the target oscillator is used to control the MOS transistor connected to the target oscillator in the target oscillation unit; further, the target oscillator is turned on, and a target clock source square wave for driving the charge pump to work is obtained by using a buffer circuit; the target clock source square wave is used to reduce the electromagnetic interference during the operation of the charge pump; finally, based on the target clock source square wave, the charge pump is driven; thereby solving the problem of excessive electromagnetic interference during the operation of the charge pump in the prior art, and the electromagnetic interference generated during the operation of the charge pump also conforms to a Gaussian distribution. Therefore, a currently conventional board-level filter can be used for filtering, meeting the noise design requirements of the built-in charge pump motor drive chip, without increasing the design difficulty of the board-level filter, and promoting the commercial application of the built-in charge pump motor drive chip.

[0086] Preferably, in step 340, the turning on the target oscillator and obtaining a target clock source square wave for driving the charge pump to work by using a buffer circuit may include:

[0087] During the charging process, when it is detected that the voltage of the charge-discharge node of the oscillation circuit is at a low level, the high-side current source of the target oscillation unit is turned on, and the low-side current source of the target oscillation unit is turned off, and a target capacitor is charged; the target capacitor is a capacitor connected to the charge-discharge node.

[0088] During the discharging process, when it is detected that the voltage of the charge-discharge node of the oscillation circuit is at a high level, the high-side current source of the target oscillation unit is turned off, and the low-side current source of the target oscillation unit is turned on, and the target capacitor is discharged.

[0089] Based on the buffer circuit connected to the charge-discharge node, the target clock source square wave for driving the charge pump to work is obtained.

[0090] Based on this, the working states of the high-side current source and the low-side current source of the target oscillation unit in the oscillation circuit can be controlled by detecting the level of the voltage at the charge-discharge node, generating a current clock division that conforms to a Gaussian distribution, and using a buffer circuit to obtain a target clock source square wave for driving the charge pump to drive the charge pump and perform the first-stage noise reduction on the charge pump, so that a lower electromagnetic interference signal that conforms to a Gaussian distribution is generated during the operation of the charge pump.

[0091] Preferably, in step 350, driving the charge pump based on the target clock source square wave may include: driving the charge pump based on the target clock source square wave, in combination with the current levels in the charge pump, according to a preset working stage.

[0092] Preferably, the current levels may include a first current level, a second current level, a third current level, a fourth current level, and a fifth current level.

[0093] Driving the charge pump according to a preset working stage may specifically include:

[0094] In the charge pump startup stage, only the second current level and the first current level are turned on; the second current level is used to increase the startup speed of the charge pump; the first current level is a normally-on current source.

[0095] In the stage where the charge pump provides a large current to the load, only the third current level and the first current level are turned on; the third current level is used to increase the charge pump speed; the driving ability of the third current level is greater than that of the second current level.

[0096] In the stage where the load current is stable, only the first current level is turned on.

[0097] In the stage where the load current changes instantaneously, the fourth current level is turned on; the fourth current level is used to increase the response speed of the charge pump.

[0098] In the stage where the output stage current of the charge pump remains high, the fifth current level is turned on; the fifth current level is used to accelerate the decrease of the output stage current of the charge pump.

[0099] Based on this, different current levels with different driving abilities can be used to drive the charge pump at different stages of the charge pump's operation through the current levels set in the charge pump, to perform the second-level noise reduction on the electromagnetic interference generated by the charge pump; thus effectively suppressing the electromagnetic interference generated by the charge pump.

[0100] In a second aspect, based on the same design concept as the first aspect, an electromagnetic interference suppression circuit for a charge pump according to the present invention is provided, and this suppression circuit is used to implement an electromagnetic interference suppression method for a charge pump disclosed in the first aspect; please refer to Figures 6 to 7 , Figure 6 is a first structural schematic diagram of an electromagnetic interference suppression circuit for a charge pump provided by the present invention; Figure 7 is a second structural schematic diagram of an electromagnetic interference suppression circuit for a charge pump provided by the present invention.

[0101] In Figure 6In this invention, an electrode driving chip for improving EMI is proposed. An oscillator is designed according to an algorithm in which the EMI improvement circuit conforms to the Gaussian distribution to obtain clock frequency division conforming to the Gaussian distribution, and the charge pump is driven to effectively suppress the electromagnetic interference generated during the operation of the charge pump.

[0102] Specifically, please refer to Figure 7 . In Figure 7 , the circuit may at least include:

[0103] An oscillation circuit 500, an enable control circuit 600, a buffer circuit 700, and a charge pump 800.

[0104] The oscillation circuit 500 is connected to the enable control circuit 600; the oscillation circuit 500 includes a plurality of oscillation units, and the current sources of the plurality of oscillation units are set proportionally according to the Gaussian distribution; the enable control circuit 600 includes a plurality of oscillators, and the oscillators are used to control the MOS transistors in the oscillation units connected to the oscillators.

[0105] The oscillation circuit 500 is connected to the buffer circuit 700, and the buffer circuit 700 is connected to the charge pump 800; the buffer circuit 700 is used to determine the target clock source square wave for driving the charge pump 800 to work, and based on the target clock source square wave, drive the charge pump 800; wherein, the target clock source square wave is used to reduce the electromagnetic interference during the operation of the charge pump 800.

[0106] Based on this, a suppression circuit for the electromagnetic interference of a charge pump according to this invention can implement a method for suppressing the electromagnetic interference of a charge pump disclosed in the first aspect; thus solving the problem of excessive electromagnetic interference during the operation of the charge pump in the prior art, and the electromagnetic interference generated during the operation of the charge pump also conforms to the Gaussian distribution. Therefore, a currently conventional board-level filter can be used for filtering, meeting the noise design requirements of the built-in charge pump motor drive chip.

[0107] Preferably, please refer to Figure 8 , Figure 8 which is the first schematic diagram of the suppression circuit structure of a suppression circuit for the electromagnetic interference of a charge pump provided by this invention.

[0108] In Figure 8 , the plurality of oscillation units at least include a first oscillation unit 510, a second oscillation unit 520, a third oscillation unit 530, a fourth oscillation unit 540, and a fifth oscillation unit 550.

[0109] The current sources of the first oscillation unit 510, the second oscillation unit 520, the third oscillation unit 530, the fourth oscillation unit 540, and the fifth oscillation unit 550 are set proportionally according to the Gaussian distribution.

[0110] The enabling control circuit at least includes a first oscillator 610, a second oscillator 620, a third oscillator 630, a fourth oscillator 640, and a fifth oscillator 650; the first oscillator 610 is connected to the first oscillation unit 510, the second oscillator 620 is connected to the second oscillation unit 520, the third oscillator 630 is connected to the third oscillation unit 530, the fourth oscillator 640 is connected to the fourth oscillation unit 540, and the fifth oscillator 650 is connected to the fifth oscillation unit 550.

[0111] Based on this, different enabling control signals can be used to control the operation of different oscillation units. For example: when the enabling signal of the first oscillator 610 is at a low level, the second oscillator 620, the third oscillator 630, the fourth oscillator 640, and the fifth oscillator 650 are at a high level; that is, the first oscillator 610 is turned on, and the second oscillator 620, the third oscillator 630, the fourth oscillator 640, and the fifth oscillator 650 are turned off.

[0112] When the charging node is at a high level, the gate of MP2 is at a high level, the high-side current source is turned off, the gate of MN2 is at a high level, the low-side current source is turned on, and the capacitor is discharged. The discharge speed is determined by the first oscillation unit 510.

[0113] When the charging node is at a low level, the gate of MP2 is at a low level, the high-side current source is turned on, the gate of MN2 is at a low level, the low-side current source is turned off, and the capacitor is charged. The charging speed is determined by the first oscillation unit 510.

[0114] OSC_P and OSC_N follow the charge and discharge nodes to output complementary square waves for the charge pump at the back end of the circuit. At this time, the oscillation period of the square wave is proportional to the oscillation period of the first oscillation unit 510.

[0115] It should be noted that only one oscillation unit is turned on once during the operation of the enabling control circuit, and the other four oscillation units are turned off; when any one oscillation unit is turned on, the oscillation period of the square wave generated by the buffer circuit is proportional to the oscillation period of the currently turned-on oscillation unit, maintaining that both the input and output frequencies satisfy the Gaussian distribution.

[0116] Preferably, the first oscillation unit 510 includes a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, and a second NMOS transistor MN2; the first oscillator 610 includes a first logic OR gate, a first logic AND gate, and a first logic NOT gate.

[0117] The second oscillation unit 520 includes a third PMOS transistor MP3, a fourth PMOS transistor MP4, a third NMOS transistor MN3, and a fourth NMOS transistor MN4; the second oscillator 620 includes a second logic OR gate, a second logic AND gate, and a second logic NOT gate.

[0118] The third oscillation unit 530 includes a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a fifth NMOS transistor MN5, and a sixth NMOS transistor MN6; the third oscillator 630 includes a third logic OR gate, a third logic AND gate, and a third logic NOT gate.

[0119] The fourth oscillation unit 540 includes a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a seventh NMOS transistor MN7, and an eighth NMOS transistor MN8; the fourth oscillator 640 includes a fourth logic OR gate, a fourth logic AND gate, and a fourth logic NOT gate.

[0120] The fifth oscillation unit 550 includes a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, a ninth NMOS transistor MN9, and a tenth NMOS transistor MN10; the fifth oscillator 650 includes a fifth logic OR gate, a fifth logic AND gate, and a fifth logic NOT gate.

[0121] Based on this, the current sources of the first oscillation unit 510, the second oscillation unit 520, the third oscillation unit 530, the fourth oscillation unit 540, and the fifth oscillation unit 550 are proportionally set according to a Gaussian distribution. Specifically, the aspect ratios of the MOS transistors in each oscillation unit can be set in the following manner to meet the design requirements that the current sources of the first oscillation unit 510, the second oscillation unit 520, the third oscillation unit 530, the fourth oscillation unit 540, and the fifth oscillation unit 550 are proportionally set according to a Gaussian distribution.

[0122] As an example:

[0123] Set the lengths of the PMOS transistors MP1, MP3, MP5, MP7, and MP9 in the following ratio:

[0124] MP1 length: MP3 length: MP5 length: MP7 length: MP9 length is: 1:1:1:1:1.

[0125] Set the widths of the PMOS transistors MP1, MP3, MP5, MP7, and MP9 in the following ratio:

[0126] MP1 width: MP3 width: MP5 width: MP7 width: MP9 width is: 74:65:45:1. Set the lengths of the NMOS transistors MN1, MN3, MN5, MN7, and MN9 in the following ratio:

[0127] The lengths of MN1, MN3, MN5, MN7, and MN9 are in the ratio of 1:1:1:1:1.

[0128] The widths of NMOS transistors MN1, MN3, MN5, MN7, and MN9 are set in the following ratio:

[0129] Width of MN1: Width of MN3: Width of MN5: Width of MN7: Width of MN9 is 74:65:45:1.

[0130] Furthermore, MP2, MP4, MP6, MP8, MP10, MN2, MN4, MN6, MN8, and MN10 are gating switches controlled by an enable control circuit.

[0131] Based on this, different-sized P current sources can be generated by MP1, MP3, MP5, MP7, and MP9; different-sized N current sources can be generated by MN1, MN3, MN5, MN7, and MN9; since the current magnitude is proportional to its corresponding width, the current sources of the first oscillation unit 510, the second oscillation unit 520, the third oscillation unit 530, the fourth oscillation unit 540, and the fifth oscillation unit 550 are set in proportion according to the Gaussian distribution.

[0132] It should be noted that the connection manners among the internal components of the first oscillation unit 510, the second oscillation unit 520, the third oscillation unit 530, the fourth oscillation unit 540, and the fifth oscillation unit 550 are the same; the connection manners among the internal components of the first oscillator 610, the second oscillator 620, the third oscillator 630, the fourth oscillator 640, and the fifth oscillator 650 are the same; and the connection manner between the first oscillator 610 and the first oscillation unit 510, between the second oscillator 620 and the second oscillation unit 520, between the third oscillator 630 and the third oscillation unit 530, between the fourth oscillator 640 and the fourth oscillation unit 540, and between the fifth oscillator 650 and the fifth oscillation unit 550 are also the same; only the connection manners inside and between the first oscillation unit 510 and the first oscillator 610 are taken as an example for illustration below, and the connection manners of other oscillation units and oscillators are not elaborated.

[0133] As an example, in the first oscillation unit 510, the source of the first PMOS transistor MP1 is connected to the power supply terminal, the gate is connected to the P reference terminal, and the drain is connected to the source of the second PMOS transistor MP2. The gate of the second PMOS transistor MP2 is connected to the output terminal of the first logic OR gate, and the drain is connected to the charge and discharge node.

[0134] The source of the first NMOS transistor MN1 is grounded, the gate is connected to the N reference terminal, and the drain is connected to the source of the second NMOS transistor MN2. The gate of the second NMOS transistor MN2 is connected to the output terminal of the first logic AND gate, and the drain is connected to the charge and discharge node. Herein, P reference and N reference represent that the current source provides a reference voltage to enable the current source to provide current.

[0135] One end of the charge and discharge capacitor is connected to the charge and discharge node, and the other end is grounded; the charge and discharge node is connected to the buffer circuit.

[0136] Further, in the first oscillator 610, the first input terminal of the first logic OR gate is connected to the charge and discharge node, and the second input terminal is connected to the first oscillator enable terminal; that is, the second input terminal of the first logic OR gate is connected to enable 1. The first input terminal of the first logic AND gate is connected to the output terminal of the first logic NOT gate, the input terminal of the first logic NOT gate is connected to the first oscillator enable terminal, and the second input terminal of the first logic AND gate is connected to the charge and discharge node.

[0137] Based on this, the digital controller can control the on or off of the MOS transistors in the first oscillation unit 510 through the first oscillator 610 in the enable control circuit to generate a driving current source. Similarly, the digital controller can also control the on or off of the MOS transistors in the first oscillation unit 510 through the first oscillator 610, control the on or off of the MOS transistors in the second oscillation unit 520 through the second oscillator 620, control the on or off of the MOS transistors in the third oscillation unit 530 through the third oscillator 630, control the on or off of the MOS transistors in the fourth oscillation unit 540 through the fourth oscillator 640, and control the on or off of the MOS transistors in the fifth oscillation unit 550 through the fifth oscillator 650 to generate driving current sources of different magnitudes. Since the circuit design between the oscillation units in the oscillation circuit conforms to the Gaussian distribution, the clock source square wave generated based on this oscillation circuit also conforms to the Gaussian distribution.

[0138] Further, the buffer circuit can at least include an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, an eleventh NMOS transistor MN11, and a twelfth NMOS transistor MN12. Among them, the eleventh PMOS transistor MP11 and the eleventh NMOS transistor MN11 are the first-stage buffer, and the twelfth PMOS transistor MP12 and the twelfth NMOS transistor MN12 are the second-stage buffer. The buffer circuit is used to provide a frequency source for the subsequent charge pump to generate a target clock source square wave.

[0139] Preferably, the source of the eleventh PMOS transistor MP11 is connected to the power supply terminal, the gate is connected to the charge and discharge node, and the drain is connected to the first output terminal of the buffer circuit; the source of the eleventh NMOS transistor MN11 is grounded, the gate is connected to the charge and discharge node, and the drain is connected to the first output terminal of the buffer circuit; the source of the twelfth PMOS transistor MP12 is connected to the power supply terminal, the gate is connected to the first output terminal of the buffer circuit, and the drain is connected to the second output terminal of the buffer circuit; the source of the twelfth NMOS transistor MN12 is grounded, the gate is connected to the first output terminal of the buffer circuit, and the drain is connected to the second output terminal of the buffer circuit.

[0140] Based on this, a target clock source square wave for driving the charge pump to work can be obtained by using the buffer circuit; the target clock source square wave is input to the charge pump to drive the charge pump to work.

[0141] Further, please refer to Figure 9 , Figure 9 which is a schematic diagram of the second suppression circuit structure of a charge pump electromagnetic interference suppression circuit provided by the present invention. Figure 9 The second electromagnetic interference suppression circuit structure shown is the circuit structure inside the charge pump.

[0142] In Figure 9 , the charge pump 800 at least includes an input stage 810, a current stage 820, an output stage 830, and a boost stage 840.

[0143] The input stage 810 is connected to the buffer circuit 700, the current stage 820, and the output stage 830; the current stage 820 is connected to the output stage 830; the output stage 830 is connected to the boost stage 840; the boost stage 840 is connected to an external load. The input stage shapes the input differential oscillation waveform and connects it to the output stage.

[0144] Preferably, the input stage 810 includes a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a fifteenth PMOS transistor MP15, a thirteenth NMOS transistor MN13, and a fourteenth NMOS transistor MN14; among them, the thirteenth PMOS transistor MP13 is a normally open power supply.

[0145] Specifically, the source of the thirteenth PMOS transistor MP13 is connected to the power supply terminal, the drain is connected to the source of the fifteenth PMOS transistor MP15, and the gate is connected to the gate of the fourteenth PMOS transistor MP14; the source of the fourteenth PMOS transistor MP14 is connected to the power supply terminal, the drain is connected to the drain of the fourteenth NMOS transistor MN14; the drain of the fourteenth PMOS transistor MP14 is connected to the drain of the thirteenth NMOS transistor MN13, and the gate is connected to the gate of the fourteenth PMOS transistor MP14; the gate of the thirteenth NMOS transistor MN13 is connected to the OSC_N terminal in the buffer circuit; the gate of the fourteenth NMOS transistor MN14 is connected to the OSC_P terminal in the buffer circuit, and the source is connected to the source of the thirteenth NMOS transistor MN13.

[0146] Preferably, the current stage 820 includes a first current stage 821, a second current stage 822, a third current stage 823, a fourth current stage 824, and a fifth current stage 825.

[0147] Specifically, the first current stage 821 includes a fifteenth NMOS transistor MN15; the second current stage 822 includes a sixteenth NMOS transistor MN16 and a seventeenth NMOS transistor MN17; the third current stage 823 includes an eighteenth NMOS transistor MN18 and a nineteenth NMOS transistor MN19; the fourth current stage 824 includes a twentieth NMOS transistor MN20 and a twenty-first NMOS transistor MN21; the fifth current stage 825 includes a twenty-second NMOS transistor MN22.

[0148] Among them, the drain of the fifteenth NMOS transistor MN15 is connected to the input stage 810 of the charge pump, the gate is connected to the N reference terminal, and the source is grounded; that is, the drain of the fifteenth NMOS transistor MN15 is connected to the source of the thirteenth NMOS transistor MN13.

[0149] The drain of the sixteenth NMOS transistor MN16 is connected to the drain of the fifteenth NMOS transistor MN15, the gate is connected to the first charge pump enable signal terminal, and the source is connected to the drain of the seventeenth NMOS transistor MN17; the gate of the seventeenth NMOS transistor MN17 is connected to the N reference terminal and the source is grounded.

[0150] The drain of the eighteenth NMOS transistor MN18 is connected to the drain of the fifteenth NMOS transistor MN15, the gate is connected to the second charge pump enable signal terminal, and the source is connected to the drain of the nineteenth NMOS transistor MN19; the gate of the nineteenth NMOS transistor MN19 is connected to the N reference terminal and the source is grounded.

[0151] The drain of the twentieth NMOS transistor MN20 is connected to the drain of the fifteenth NMOS transistor MN15, the gate is connected to the third charge pump enable signal terminal, and the source is connected to the drain of the twenty-first NMOS transistor MN21; the gate of the twenty-first NMOS transistor MN21 is connected to the N reference terminal and the source is grounded.

[0152] The drain of the twenty-second NMOS transistor MN22 is connected to the drain of the fifteenth NMOS transistor MN15, the gate is connected to the output stage, and the source is connected to the drain of the twenty-first NMOS transistor MN21.

[0153] Preferably, the output stage 830 may include a sixteenth PMOS transistor MP16, a seventeenth PMOS transistor MP17, an eighteenth PMOS transistor MP18, a twenty-third NMOS transistor MN23, a twenty-fourth NMOS transistor MN24, a twenty-fifth NMOS transistor MN25, a twenty-sixth NMOS transistor MN26, a twenty-seventh NMOS transistor MN27, and a twenty-eighth NMOS transistor MN28.

[0154] Specifically, the source of the sixteenth PMOS transistor MP16 is connected to the power supply terminal, the gate is connected to the gate of the fourteenth PMOS transistor MP14, and the drain is connected to the drain of the twenty-third NMOS transistor MN23; the source of the seventeenth is connected to the power supply terminal, the gate is connected to the drain of the sixteenth PMOS transistor MP16, and the drain is connected to the drain of the twenty-fifth NMOS transistor MN25; the source of the eighteenth PMOS transistor MP18 is connected to the power supply terminal, the gate is connected to the drain of the fourteenth PMOS transistor MP14, and the drain is connected to the drain of the twenty-eighth NMOS transistor MN28.

[0155] The gate of the twenty-third NMOS transistor MN23 is connected to the gate of the fourteenth NMOS transistor MN14, the source is connected to the drain of the twenty-fourth NMOS transistor MN24; the gate of the twenty-fourth NMOS transistor MN24 is connected to the N reference connection and the source is grounded; the gate of the twenty-fifth NMOS transistor MN25 is connected to the N reference connection and the source is grounded; the gate of the twenty-sixth NMOS transistor MN26 is connected to the N reference connection and the source is grounded;

[0156] The drain of the twenty-seventh NMOS transistor MN27 is connected to the power supply terminal, the gate is connected to the drain of the seventeenth PMOS transistor MP17, and the source is connected to the drain of the twenty-eighth NMOS transistor MN28; the gate of the twenty-eighth NMOS transistor MN28 is connected to the gate of the thirteenth NMOS transistor MN13, the source is connected to the drain of the twenty-sixth NMOS transistor MN26, and the source of the twenty-eighth NMOS transistor MN28 is connected to the gate of the twenty-second NMOS transistor MN22.

[0157] Based on this, the output stage 830 can be used to drive the final boost capacitor, that is, to drive the first capacitor 841; in the output stage, the eighteenth-stage PMOS transistor MP18 and the twenty-eighth NMOS transistor MN28 are the core buck-boost transistors; MP16, MP17 and MN27 form a delay follower to further improve the driving ability for the first capacitor 841; the current sources MN24, MN25 and MN26 are used to supply current to the driving stage; thereby further improving the output driving ability.

[0158] Preferably, the boost stage 840 may include a first capacitor 841, a second capacitor 842, a first diode 843, and a second diode 844.

[0159] Specifically, one end of the first capacitor 841 is connected to the drain of the twenty-eighth NMOS transistor MN28, and the other end is connected to the negative terminal of the first diode 843; the positive terminal of the first diode 843 is connected to the power supply terminal; the positive terminal of the second diode 844 is connected to the negative terminal of the first diode 843, and the negative terminal is connected to the charge pump output terminal; one end of the second capacitor 842 is connected to the charge pump output terminal, and the other end is grounded.

[0160] Based on this, the first capacitor 841 and the first diode 843 of the boost stage are used to boost the voltage; the second diode 844 and the second capacitor 842 are used for rectification, and the output charge pump voltage provides gate drive for the load.

[0161] In summary, a charge pump electromagnetic interference suppression circuit provided by the present invention, the suppression circuit is used to implement a charge pump electromagnetic interference suppression method described in the first aspect; based on the Gaussian distribution curve, the charge pump works at different clock frequencies at different times, distributes the pulsed current to different frequencies, realizes that the electromagnetic interference of the charge pump takes the main radiation frequency as the core oscillation frequency and is distributed according to the Gaussian curve, improves the suppression effect on the electromagnetic interference generated during the operation of the charge pump; the electromagnetic interference generated by the charge pump can be filtered by a currently conventional board-level filter, meeting the noise design requirements of the motor drive chip with a built-in charge pump, and is more conducive to promoting the commercial application of the built-in charge pump chip.

[0162] Although the present invention has been described in conjunction with various embodiments herein, however, in the process of implementing the claimed invention, those skilled in the art can understand and achieve other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "one" does not exclude a plurality of cases. A single processor or other unit can implement several functions recited in the claims. Certain measures are recited in mutually different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0163] Although the present invention has been described in connection with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made thereto without departing from the spirit and scope of the invention. Accordingly, the specification and drawings are merely exemplary illustrations of the invention as defined by the appended claims and are considered to cover any and all modifications, variations, combinations or equivalents within the scope of the invention. Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these changes and modifications.

Claims

1. A method for suppressing charge pump electromagnetic interference, characterized in that Including: According to the Gaussian distribution curve, clock-divide the system clock of the charge pump to obtain the first clock division; Based on the first clock division, combined with the performance parameters of multiple oscillation units in the oscillation circuit, determine the target oscillation unit; wherein, the current sources of the multiple oscillation units are set proportionally according to the Gaussian distribution; Based on the target oscillation unit, determine the target oscillator; the target oscillator is used to control the MOS transistor in the target oscillation unit connected to the target oscillator; Turn on the target oscillator, and use the buffer circuit to obtain the target clock source square wave for driving the charge pump to work; the target clock source square wave is used to reduce the electromagnetic interference during the operation of the charge pump; Based on the target clock source square wave, drive the charge pump; The driving the charge pump based on the target clock source square wave includes: based on the target clock source square wave, combined with the current levels in the charge pump, drive the charge pump according to the preset working stages; The current levels include: the first current level, the second current level, the third current level, the fourth current level, and the fifth current level; The driving the charge pump according to the preset working stages includes: in the charge pump startup stage, only turn on the second current level and the first current level; the second current level is used to increase the startup speed of the charge pump; the first current level is a normally-on current source; in the stage where the charge pump provides a large current to the load, only turn on the third current level and the first current level; the third current level is used to increase the charge pump speed; the driving ability of the third current level is greater than that of the second current level; in the stage where the load current is stable, only turn on the first current level; in the stage where the load current changes instantaneously, turn on the fourth current level; the fourth current level is used to increase the response speed of the charge pump; in the stage where the output stage current of the charge pump remains high, turn on the fifth current level; the fifth current level is used to accelerate the decrease of the output stage current of the charge pump.

2. The method according to claim 1, wherein The turning on the target oscillator and using the buffer circuit to obtain the target clock source square wave for driving the charge pump to work includes: During the charging process, when it is detected that the voltage of the charge and discharge node of the oscillation circuit is at a low level, turn on the high-side current source of the target oscillation unit and turn off the low-side current source of the target oscillation unit to charge the target capacitor; the target capacitor is the capacitor connected to the charge and discharge node; During the discharging process, when it is detected that the voltage of the charge and discharge node of the oscillation circuit is at a high level, turn off the high-side current source of the target oscillation unit and turn on the low-side current source of the target oscillation unit to discharge the target capacitor; Based on the buffer circuit connected to the charge and discharge node, obtain the target clock source square wave for driving the charge pump to work.

3. A suppression circuit for charge pump electromagnetic interference, characterized in that The suppression circuit is used to implement the method for suppressing electromagnetic interference of a charge pump described in any one of claims 1 to 2. The circuit at least includes: An oscillation circuit, an enable control circuit, a buffer circuit, and a charge pump; The oscillation circuit is connected to the enable control circuit; the oscillation circuit includes a plurality of oscillation units, and the current sources of the plurality of oscillation units are proportionally arranged according to a Gaussian distribution; the enable control circuit includes a plurality of oscillators, and the oscillators are used to control the MOS transistors in the oscillation units connected to the oscillators. The oscillation circuit is connected to the buffer circuit, and the buffer circuit is connected to the charge pump; the buffer circuit is used to determine a target clock source square wave for driving the charge pump to operate, and based on the target clock source square wave, drive the charge pump; wherein, the target clock source square wave is used to reduce electromagnetic interference during the operation of the charge pump.

4. The circuit according to claim 3, wherein The plurality of oscillation units at least include a first oscillation unit, a second oscillation unit, a third oscillation unit, a fourth oscillation unit, and a fifth oscillation unit. The current sources of the first oscillation unit, the second oscillation unit, the third oscillation unit, the fourth oscillation unit, and the fifth oscillation unit are proportionally arranged according to a Gaussian distribution. The enable control circuit at least includes a first oscillator, a second oscillator, a third oscillator, a fourth oscillator, and a fifth oscillator; the first oscillator is connected to the first oscillation unit, the second oscillator is connected to the second oscillation unit, the third oscillator is connected to the third oscillation unit, the fourth oscillator is connected to the fourth oscillation unit, and the fifth oscillator is connected to the fifth oscillation unit.

5. The circuit according to claim 4, wherein The first oscillation unit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor; the first oscillator includes a first logical OR gate, a first logical AND gate, and a first logical NOT gate. The source of the first PMOS transistor is connected to the power supply terminal, the gate is connected to the P reference terminal, and the drain is connected to the source of the second PMOS transistor; the gate of the second PMOS transistor is connected to the output terminal of the first logical OR gate, and the drain is connected to the charge and discharge node. The source of the first NMOS transistor is grounded, the gate is connected to the N reference terminal, and the drain is connected to the source of the second NMOS transistor; the gate of the second NMOS transistor is connected to the output terminal of the first logical AND gate, and the drain is connected to the charge and discharge node. The first input terminal of the first logical OR gate is connected to the charge and discharge node, and the second input terminal is connected to the first oscillator enable terminal; the first input terminal of the first logical AND gate is connected to the output terminal of the first logical NOT gate, the input terminal of the first logical NOT gate is connected to the first oscillator enable terminal, and the second input terminal of the first logical AND gate is connected to the charge and discharge node.

6. The circuit according to claim 5, wherein The buffer circuit at least includes an eleventh PMOS transistor, a twelfth PMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor. The source of the eleventh PMOS transistor is connected to the power supply terminal, the gate is connected to the charge and discharge node, and the drain is connected to the first output terminal of the buffer circuit; the source of the eleventh NMOS transistor is grounded, the gate is connected to the charge and discharge node, and the drain is connected to the first output terminal of the buffer circuit. The source of the twelfth PMOS transistor is connected to the power supply terminal, the gate is connected to the first output terminal of the buffer circuit, and the drain is connected to the second output terminal of the buffer circuit; the source of the twelfth NMOS transistor is grounded, the gate is connected to the first output terminal of the buffer circuit, and the drain is connected to the second output terminal of the buffer circuit.

7. The circuit according to claim 6, wherein The charge pump at least includes an input stage, a current stage, an output stage, and a boosting stage; The input stage is connected to the buffer circuit, the current stage, and the output stage; The current stage is connected to the output stage; The output stage is connected to the boosting stage; The boosting stage is connected to an external load.

8. The circuit according to claim 7, characterized in that, The current stage includes a first current stage, a second current stage, a third current stage, a fourth current stage, and a fifth current stage; The first current stage includes a fifteenth NMOS transistor; the second current stage includes a sixteenth NMOS transistor and a seventeenth NMOS transistor; the third current stage includes an eighteenth NMOS transistor and a nineteenth NMOS transistor; the fourth current stage includes a twentieth NMOS transistor and a twenty-first NMOS transistor; the fifth current stage includes a twenty-second NMOS transistor; The drain of the fifteenth NMOS transistor is connected to the input stage of the charge pump, the gate is connected to the N reference terminal, and the source is grounded; The drain of the sixteenth NMOS transistor is connected to the drain of the fifteenth NMOS transistor, the gate is connected to the first charge pump enable signal terminal, and the source is connected to the drain of the seventeenth NMOS transistor; the gate of the seventeenth NMOS transistor is connected to the N reference terminal and the source is grounded; The drain of the eighteenth NMOS transistor is connected to the drain of the fifteenth NMOS transistor, the gate is connected to the second charge pump enable signal terminal, and the source is connected to the drain of the nineteenth NMOS transistor; the gate of the nineteenth NMOS transistor is connected to the N reference terminal and the source is grounded; The drain of the twentieth NMOS transistor is connected to the drain of the fifteenth NMOS transistor, the gate is connected to the third charge pump enable signal terminal, and the source is connected to the drain of the twenty-first NMOS transistor; the gate of the twenty-first NMOS transistor is connected to the N reference terminal and the source is grounded; The drain of the twenty-second NMOS transistor is connected to the drain of the fifteenth NMOS transistor, the gate is connected to the output stage, and the source is connected to the drain of the twenty-first NMOS transistor.

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