Voltage level converter

Abstract

The present application discloses a voltage level converter, characterized by comprising: a second-stage circuit operating between a high voltage AVDD and a medium voltage VMID, configured to receive a pair of control signals to output a pair of inverted output signals; and a first-stage circuit, further comprising a P-type transistor P1, a P-type transistor P2, an N-type transistor N2, and an N-type transistor N1 connected in series in sequence, and a P-type transistor P3, a P-type transistor P4, an N-type transistor N4, and an N-type transistor N3 connected in series in sequence.

Description

Technical Field

[0001] This application belongs to the field of voltage level converters or level shifters (hereinafter referred to as LVSH, level shifter), and relates to a voltage level converter including fewer transistors. Background Art

[0002] Please refer to Figure 1 As shown, it is a block diagram of an existing liquid crystal display screen 100. In order to control the liquid crystal display 110, the liquid crystal display screen 100 includes a gate control circuit 120 and an output stage circuit 122 of the corresponding gate driving circuit. The liquid crystal display screen 100 also includes a source control circuit 130 and an output stage circuit 132 of the corresponding source driving circuit. Among the output stage circuits 132 of the existing source driving circuits, multiple LVSHs are usually included.

[0003] Please refer to Figure 2 As shown, it is a block diagram of an existing LVSH 200. The existing LVSH 200 usually includes a pair of inverted input ports 210 and a pair of inverted output ports 220. Please refer to Figure 3 As shown, it is a diagram of the voltage values of the signals of the input port 210 and the output port 220 of the LVSH 200. In Figure 3 it, the inverted signals of the input port 210 are usually a lower logic circuit level and the ground voltage GND, which can represent the logic signal 1 and the logic signal 0 respectively. The above-mentioned logic circuit levels are usually 1.5V and 0V, but those of ordinary skill in the art to which this application pertains can understand that the logic circuit levels referred to in this application are not limited to 1.5V. For example, they can be 0.9V, 1.2V, 1.8V, etc. After the level shift of the LVSH 200, the voltage value range of the signal of the output port 220 is raised to the middle voltage VMID and the high voltage VADD.

[0004] Under the application of a small and medium-sized liquid crystal display screen 100, the liquid crystal switching voltage is within 6V. Therefore, for a liquid crystal panel architecture with all-positive half-voltage, the high voltage VADD will be within 12V. Thus, different from the source driver circuit of a large-sized liquid crystal screen, high-voltage components such as 32V are required. The source driver circuit applied to the small and medium-sized liquid crystal display screen 100 often uses medium-voltage components. That is, the voltage of the signal at the output port 220 of the existing LVSH 200 is 6V to 12V. Those of ordinary skill in the art to which this application pertains can understand that the use of a medium voltage VMID of 6V and a high voltage VADD of 12V hereinafter in this application is only exemplary. The voltage of the medium voltage VMID is usually half of the voltage of the high voltage VADD. For example, 6V is 12V / 2. The medium voltage VMID and the high voltage VADD involved in this application can be other voltage values.

[0005] Please refer to Figure 4 as shown, which is a block diagram of the existing LVSH 400. In Figure 4 the LVSH 400 shown, it includes an LVSH core circuit 410, which requires the supply of a relay high voltage VQH and a relay low voltage VQL. Therefore, the LVSH 400 also includes a VQH rectifier circuit 420 and a VQL rectifier circuit 430, which are respectively used to supply the relay high voltage VQH and the relay low voltage VQL to the above-mentioned LVSH core circuit 410.

[0006] The aforementioned relay high voltage VQH is usually three-quarters of the high voltage VADD. The aforementioned relay low voltage VQL is usually one-quarter of the high voltage VADD. When the high voltage VADD is 12V, the relay high voltage VQH is 9V, and the relay low voltage VQL is 3V.

[0007] Please refer to Figure 5 as shown, which is Figure 4 the circuit diagram of the LVSH core circuit 410 shown. In Figure 5 the circuit diagram shown, it can be seen that the LVSH core circuit 410 includes five-stage circuits 510 to 550. Each stage of the circuit includes a circuit combination of four transistors. The first-stage circuit 510 includes a pair of inverted input ports IN and INB. The last fifth-stage circuit 550 includes a pair of inverted output ports OUT and OUTB.

[0008] A pair of output signals O1 and O1B of the first-stage circuit 510 respectively control the gates of two transistors of the second-stage circuit 520. Similarly, a pair of output signals O2 and O2B of the second-stage circuit 520 respectively control the gates of two transistors of the third-stage circuit 530. A pair of output signals O3 and O3B of the third-stage circuit 530 respectively control the gates of two transistors of the fourth-stage circuit 540. A pair of output signals O4 and O4B of the fourth-stage circuit 540 respectively control the gates of two transistors of the fifth-stage circuit 550.

[0009] Please refer to Figure 6 As shown, it is a schematic diagram of the operating voltages of the stages of the LVSH core circuit 410. The LVSH core circuit 410 converts the VDD and GND voltages of the input signals IN and INB into the high voltage AVDD and the medium voltage VMID through 20 transistors of these five stages. The voltage across the first-stage circuit 510 is between VMID and GND, which is 6V. The voltage across the second-stage circuit 520 is between the relay low voltage VQL and the medium voltage VMID, which is 3V. The voltage across the third-stage circuit 530 is between the relay low voltage VQL and the relay high voltage VQH, which is 6V. The voltage across the fourth-stage circuit 540 is between the medium voltage VMID and the relay high voltage VQH, which is 3V. The voltage across the last fifth-stage circuit 550 is between the medium voltage VMID and the high voltage AVDD, which is 6V. Since all the voltage drops across these five stages 510 to 550 are within 6V, general medium-voltage components can be used for implementation.

[0010] In other words, Figure 4 the LVSH core circuit 410 shown needs to use 20 medium-voltage metal-oxide-semiconductor field-effect transistors (MOSFETs). In addition, Figure 4 the LVSH 400 shown also requires a VQH rectifier circuit 420 and a VQL rectifier circuit 430 to supply the relay low voltage VQL and the relay high voltage VQH to the LVSH core circuit 410. Since the existing LVSH 400 is connected to more voltages, additional cuts need to be made to the transistor wells in the layout, occupying a larger area, resulting in higher costs and more power consumption.

[0011] Accordingly, a LVSH design that occupies a smaller area is required to reduce costs and save energy. In particular, small and medium-sized liquid crystal display screens 100 are usually used in mobile electronic devices, such as mobile phones, tablet computers, etc. These mobile electronic devices usually use batteries to supply power to the liquid crystal display screen 100. If a LVSH design with a smaller area and higher energy efficiency can be used, it will be able to reduce the size and energy consumption of the mobile electronic device, and further improve the performance of the mobile electronic device. Summary of the Invention

[0012] This application proposes a voltage level converter to solve the deficiencies in the prior art. The purpose is to use a smaller area and have higher energy efficiency to reduce costs and increase the usage time of mobile devices.

[0013] To achieve the above object, this application adopts the following technical solutions:

[0014] According to an embodiment of the present application, there is provided a voltage level converter, characterized in that it includes: a second-stage circuit operating between a high voltage AVDD and a medium voltage VMID, for receiving a pair of control signals to output a pair of inverted output signals; and a first-stage circuit, further including a P-type transistor P1, a P-type transistor P2, an N-type transistor N2, and an N-type transistor N1 connected in series in sequence, and a P-type transistor P3, a P-type transistor P4, an N-type transistor N4, and an N-type transistor N3 connected in series in sequence, wherein the sources of the P-type transistor P1 and the P-type transistor P3 are respectively connected to the high voltage AVDD, the gate of the P-type transistor P3 is connected to the drain of the P-type transistor P1 to serve as the first signal O1 of the pair of control signals, the gate of the P-type transistor P1 is connected to the drain of the P-type transistor P3 to serve as the second signal O1B of the pair of control signals, the drains of the N-type transistor N1 and the N-type transistor N3 are respectively connected to the ground voltage GND, and the gates of the N-type transistor N1 and the N-type transistor N3 are respectively connected to a pair of inverted input signals.

[0015] To reduce the occupied area, the above voltage level converter is characterized in that the above P-type transistor P2, P-type transistor P4, N-type transistor N2, and N-type transistor N4 are medium voltage components.

[0016] To reduce the types of supply voltages, the above voltage level converter is characterized in that the gates of the above P-type transistor P2, P-type transistor P4, N-type transistor N2, and N-type transistor N4 are respectively connected to the medium voltage VMID.

[0017] To reduce the occupied area, the above voltage level converter is characterized in that the breakdown voltages of the above P-type transistor P2 and P-type transistor P4 are greater than the sum of the medium voltage VMID and the corresponding threshold voltage VTH.

[0018] To reduce the occupied area, the above-mentioned voltage level converter is characterized in that the breakdown voltages of the above-mentioned N-type transistor N2 and N-type transistor N4 are greater than a difference value, which is the sum of the high voltage VADD and the corresponding threshold voltage VTH minus the middle voltage VMID.

[0019] To provide an output signal with a voltage swing from VMID to AVDD, the above-mentioned voltage level converter is characterized in that the second-stage circuit further includes a P-type transistor P5 and an N-type transistor N5 connected in series between the high voltage VADD and the middle voltage VMID in sequence, and a P-type transistor P6 and an N-type transistor N6 connected in series between the high voltage VADD and the middle voltage VMID in sequence, wherein the gate of the P-type transistor P5 receives the above-mentioned first signal O1, the gate of the P-type transistor P6 receives the above-mentioned second signal O1B, the drain of the P-type transistor P5 is connected to the gate of the N-type transistor N6 as one of the pair of inverted output signals, and the drain of the P-type transistor P6 is connected to the gate of the N-type transistor N5 as the other of the pair of inverted output signals.

[0020] The above-mentioned voltage level converter is characterized in that the middle voltage VMID is approximately half of the high voltage AVDD.

[0021] According to an embodiment of the present application, an output stage circuit is provided, which is characterized by including: a voltage supply module for supplying AVGP voltage and AVGN voltage respectively; and more than one voltage level converter for outputting a pair of inverted output signals, and the pair of inverted output signals operate between the high voltage AVDD and the middle voltage VMID. The voltage level converter includes: a P-type transistor P1, a P-type transistor P2, an N-type transistor N2 and an N-type transistor N1 connected in series in sequence; and a P-type transistor P3, a P-type transistor P4, an N-type transistor N4 and an N-type transistor N3 connected in series in sequence, wherein the sources of the P-type transistor P1 and the P-type transistor P3 are respectively connected to the high voltage AVDD, the gate of the P-type transistor P3 is connected to the drain of the P-type transistor P1 to serve as the first signal OUT of the pair of inverted output signals, the gate of the P-type transistor P1 is connected to the drain of the P-type transistor P3 to serve as the second signal OUTB of the pair of inverted output signals, the drains of the N-type transistor N1 and the N-type transistor N3 are respectively connected to the ground voltage GND, the gates of the N-type transistor N1 and the N-type transistor N3 are respectively connected to a pair of inverted input signals, the gates of the above-mentioned P-type transistor P2 and P-type transistor P4 are respectively connected to the AVGP voltage, and the gates of the above-mentioned N-type transistor N2 and N-type transistor N4 are respectively connected to the AVGN voltage.

[0022] To reduce the occupied area, the above-mentioned output stage circuit is characterized in that the breakdown voltages of the above-mentioned P-type transistor P2 and P-type transistor P4 are greater than the medium voltage VMID.

[0023] To reduce the occupied area, the above-mentioned output stage circuit is characterized in that the breakdown voltages of the above-mentioned N-type transistor N2 and N-type transistor N4 are greater than the difference between the high voltage VADD and the medium voltage VMID.

[0024] To provide the AVGP voltage and the AVGN voltage, the above-mentioned output stage circuit is characterized in that the voltage supply module includes a P-type transistor PS and an N-type transistor NS, wherein the source of the P-type transistor PS is connected to the medium voltage VMID, and the gate and drain of the P-type transistor PS are connected to the ground voltage through a first current source to provide the above-mentioned AVGP voltage, wherein the drain of the N-type transistor NS is connected to the medium voltage VMID, and the gate and source of the N-type transistor NS are connected to the high voltage AVDD through a second current source to provide the above-mentioned AVGN voltage.

[0025] To reduce the occupied area, the above-mentioned output stage circuit is characterized in that the above-mentioned P-type transistor P2, P-type transistor P4, N-type transistor N2 and N-type transistor N4 are medium voltage components.

[0026] According to an embodiment of the present application, a liquid crystal display screen is provided, including a source output circuit for controlling the display of the liquid crystal display screen, wherein the source output circuit includes the voltage level converter or output stage circuit as described above.

[0027] Due to the adoption of the above solution, the beneficial effects of the present application are as follows: The voltage level converter, output stage circuit and liquid crystal display screen provided by the present application have fewer components than the voltage level converter in the prior art, can reduce the chip area and have high energy efficiency, can not only reduce the cost, increase the reliability, but also reduce the size and energy consumption of the mobile electronic device, and further improve the performance of the mobile electronic device. Description of the Drawings

[0028] Figure 1 It is a block diagram of an existing liquid crystal display screen 100.

[0029] Figure 2 It is a block diagram of an existing LVSH 200.

[0030] Figure 3 It is a schematic diagram of the voltage values of the input port 210 signal and the output port 220 signal of the LVSH 200.

[0031] Figure 4 It is a block diagram of an existing LVSH 400.

[0032] Figure 5 For Figure 4 the circuit diagram of the LVSH core circuit 410 shown in the figure.

[0033] Figure 6 It is a schematic diagram of the operating voltage of each stage of the LVSH core circuit 410.

[0034] Figure 7 It is a schematic circuit diagram of the LVSH 700 according to the first embodiment of the present application.

[0035] Figure 8 It is a schematic diagram of the operating voltage of each stage of the LVSH 700.

[0036] Figure 9 It is a schematic circuit diagram of the output stage circuit 900 according to the second embodiment of the present application.

[0037] Figure 10 It is a schematic diagram of the operating voltage of the output stage circuit 900.

[0038] Figure 11 It is a block diagram of the output stage circuit 1100 according to the embodiment of the present application. Detailed implementation manners

[0039] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other implementation manners obtained by those of ordinary skill in the art without creative efforts belong to the scope protected by the present application.

[0040] The terms "first", "second", "third", etc. (if any) in the specification, claims and drawings of the present application are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that these described objects can be interchanged under appropriate circumstances. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise clearly and specifically defined. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. Some of the block diagrams shown in the drawings are functional entities, and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or in one or more hardware circuits or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0041] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present application.

[0042] In the description of the present application, it should be noted that unless otherwise clearly specified and limited, the terms "mounted", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a connection that can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, and can be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the foregoing terms in the present application can be understood according to specific circumstances.

[0043] To make the objectives, features, and advantages of the present application more obvious and understandable, the present application will be further described in detail below in conjunction with the drawings and specific embodiments.

[0044] Please refer to Figure 7 as shown, which is a circuit schematic diagram of LVSH 700 according to the first embodiment of the present application. Figure 7 The LVSH 700 shown includes two levels of circuits. The first-level circuit 710 includes eight transistors. The upper half of the first-level circuit 710 includes four P-type transistors, P1 to P4. The lower half of the first-level circuit 710 includes four N-type transistors, N1 to N4. The second-level circuit 720 includes four transistors, namely the P-type transistors P5 and P6 and the N-type transistors N5 and N6.

[0045] and Figure 4 compared with the existing LVSH 400 shown, Figure 7 the LVSH 700 shown omits the VQH rectifier circuit 420 and the VQL rectifier circuit 430. The LVSH 700 uses 12 transistors. Compared with the 20 transistors used in the LVSH core circuit 410 shown in Figure 5 , the number of components is also significantly reduced, from 20 transistors to 12 transistors.

[0046] The four transistors P2, P4, N2, and N4 of the first-stage circuit 710 can use medium-voltage components to distribute the high-voltage AVDD to each transistor. When the voltage of the input signal IN is 1.5V, the voltage of the inverted input signal INB is the ground voltage GND or 0V. At this time, the potential at point D will be the ground voltage GND or 0V, and the potential at point C will also be the ground voltage GND or 0V. The potential at point O1B is pulled to VMID + VTH, where VTH is the threshold voltage or critical voltage of the transistor. The potential at point O1 is the high-voltage AVDD. The potential at point A will also be the high-voltage AVDD, and the potential at point B is VMID - VTH.

[0047] In the above case, the drain-to-source voltage (VDS) of the P-type transistor P4 is equal to the potential difference between point C and point O1B, that is, 0V to VMID + VTH. The VDS of the P-type transistor P4 is VMID + VTH. The VDS of the N-type transistor N2 is equal to the potential difference between point B and point A, that is, VMID - VTH to VADD, which is VADD - (VMID - VTH) or VADD - VMID + VTH. Since the VDS of the P-type transistor P4 and the N-type transistor N2 do not exceed their respective breakdown voltages, medium-voltage components can be used to implement the P-type transistor P4 and the N-type transistor N2.

[0048] Conversely, when the voltage of the input signal IN is the ground voltage GND or 0V, the voltage of the inverted input signal INB is 1.5V. At this time, the potential at point B will be the ground voltage GND or 0V, and the potential at point A will also be the ground voltage GND or 0V. The potential at point O1 is pulled to VMID + VTH. The potential at point O1B is the high-voltage AVDD. The potential at point C will also be the high-voltage AVDD, and the potential at point D is VMID - VTH.

[0049] In the above case, the drain-to-source voltage (VDS) of the P-type transistor P2 is equal to the potential difference between point A and point O1, that is, 0V to VMID + VTH. The VDS of the P-type transistor P2 is VMID + VTH. The VDS of the N-type transistor N4 is equal to the potential difference between point D and point C, that is, VMID - VTH to VADD, which is VADD - (VMID - VTH) or VADD - VMID + VTH. Since the VDS of the P-type transistor P2 and the N-type transistor N4 do not exceed their respective breakdown voltages, medium-voltage components can be used to implement the P-type transistor P2 and the N-type transistor N4.

[0050] A pair of output signals O1 and O1B of the first-stage circuit 710 respectively control the gates of two P-type transistors P5 and P6 of the second-stage circuit 720. The function of the second-stage circuit 720 is to convert the voltage from the original VMID + VTH to AVDD to VMID to AVDD, because the voltage from VMID to AVDD is the voltage required for the LVSH output. Compared with the existing LVSH 400, the LVSH700 only uses two-stage circuits and only requires a pair of output signals O1 and O1B of the first-stage circuit 710 to control the second-stage circuit 720. In addition, the LVSH 700 omits the VQH rectifier circuit 420 and the VQL rectifier circuit 430. Therefore, the LVSH 700 can reduce the occupied area and power consumption.

[0051] Please refer to Figure 8 as shown, which is a schematic diagram of the operating voltages of each stage of the LVSH 700. The voltage values at the output points O1 and O1B of the first-stage circuit 710 are between the high voltage AVDD and VMID + VTH. The voltage values at the output points OUT and OUTB of the second-stage circuit 720 are between the high voltage AVDD and the medium voltage VMID.

[0052] Since the LVSH 700 only has two-stage circuits 710 and 720, the signal passes through fewer stages during transmission, so the signal propagation delay is shorter, and the energy consumed during signal transmission is less. Compared with Figure 5 the five-stage circuit of the existing LVSH 400 shown, it can output signals faster and be more power-saving.

[0053] Please refer to Figure 9 as shown, which is a schematic circuit diagram of the output stage circuit 900 according to the second embodiment of the present application. Compared with Figure 7 the LVSH 700 shown, the output stage circuit 900 removes the second-stage circuit 720 and has a voltage supply module 930 including two bias circuits.

[0054] The LVSH910 has the same structure with eight transistors as Figure 7 the first-stage circuit 710 shown. It also has four P-type transistors P1 to P4 and four N-type transistors N1 to N4. The sources of the P-type transistors P1 and P3 are also connected to the high voltage AVDD. The drains of the N-type transistors N1 and N3 are also connected to the ground voltage GND or 0V. Except that the gates of the P-type transistors P2 and P4 are connected to the AVGP voltage, and the gates of the N-type transistors N2 and N4 are connected to the AVGN voltage, the remaining connection methods are the same as Figure 7 the first-stage circuit 710 shown. Its output is still the original O1 and O1 B, but is renamed OUT and OUTB.

[0055] Figure 9 The second embodiment shown adds a voltage supply module 930. The voltage supply module 930 includes two bias circuits to supply AVGP voltage and AVGN voltage to the gates of P-type transistors P2 and P4 and the gates of N-type transistors N2 and N4, respectively. The P-type transistors P2 and P4 and the N-type transistors N2 and N4 can use medium-voltage components.

[0056] The AVGP bias circuit operates between the medium voltage VMID and the ground voltage GND or 0V. The AVGP bias circuit includes a P-type transistor PS and a first current source 931. The source of the P-type transistor PS is connected to the medium voltage VMID. The drain of the P-type transistor PS is connected to the gate and the positive pole of the first current source 931 to supply the AVGP voltage to the gates of the P-type transistors P2 and P4. The AVGP voltage is equal to VMID minus a VGS, and when there is current flowing through P2 and P4, the source voltage is equal to AVGP plus a VGS. Therefore, after appropriate design, the source voltage when there is current flowing through P2 and P4 can be made equal to VMID.

[0057] The AVGN bias circuit operates between the high voltage AVDD and the medium voltage VMID. The AVGN bias circuit includes an N-type transistor NS and a second current source 932. The drain of the N-type transistor PN is connected to the medium voltage VMID. The source of the N-type transistor PN is connected to the gate and the negative pole of the second current source 932 to supply the AVGN voltage to the gates of the N-type transistors N2 and N4. The AVGN voltage is equal to VMID plus a VGS, and when there is current flowing through N2 and N4, the source voltage is equal to AVGN minus a VGS. Therefore, after appropriate design, the source voltage when there is current flowing through N2 and N4 can be made equal to VMID.

[0058] In this way, the maximum VDS voltage across the N-type transistors N2 and N4 will be reduced from AVDD - VMID + VTH to AVDD - VMID, and the maximum VDS voltage across the P-type transistors P2 and P4 will be reduced from VMID + VTH to VMID. The low voltage levels of OUT and OUTB will change from VMID + VTH in the first embodiment to VMID in the second embodiment. Therefore, the second-stage circuit 720 in the first embodiment can be removed.

[0059] Figure 9 The voltage supply module 930 shown supplies the AVGP and AVGN voltages to the gates of the P-type transistors P2 and P4 and the gates of the N-type transistors N2 and N4, respectively. And Figure 7Compared with the LVSH 700 shown, by reducing the VDS voltage of the P-type transistors P2 and P4 and the N-type transistors N2 and N4 in the first-stage circuit 910, the reliability of the P-type transistors P2 and P4 and the N-type transistors N2 and N4 can be increased.

[0060] Please refer to Figure 10 shown, which is Figure 9 a schematic diagram of the operating voltage of the output-stage circuit 900 shown. The voltage values of the output points OUT and OUTB are between the high voltage AVDD and the medium voltage VMID. Whether it is Figure 7 the LVSH 700 or Figure 9 the LVSH 910, its output level must be between the high voltage AVDD and the medium voltage VMID. The output of the first-stage circuit 710 of the LVSH 700 is between the high voltage AVDD and (VMID + VTH), so the second-stage circuit 720 is required to convert the output to between the high voltage AVDD and the medium voltage VMID. Since the output of the LVSH 910 is directly between the high voltage AVDD and the medium voltage VMID, the second-stage circuit 720 can be omitted.

[0061] Please refer to Figure 11 shown, which is a block schematic diagram of the output-stage circuit 1000 according to an embodiment of the present application. In Figure 11 the output-stage circuit 1100 shown, it may only include a single Figure 9 shown voltage supply module 930, and the AVGP voltage and AVGN voltage supplied by it can be connected to multiple voltage level converters 910. As shown in the embodiment of Figure 10 shown, it may include multiple voltage level converters 910-1, 910-2,..., 910-N, where N is a positive integer greater than 1.

[0062] When the output-stage circuit 1100 is applied to Figure 1 the source driver circuit of the liquid crystal display screen 100 shown, the above-mentioned N can be a positive integer greater than 1000. Since thousands of voltage level converters 910 only require one voltage supply module 930, the proportion of the increased area is quite limited, but it can reduce the VDS of thousands of components in thousands of voltage level converters 910 and remove the second stage of the first embodiment. Therefore, each voltage level converter 910 can have 4 fewer components than the voltage level converter 700 of the first embodiment. Therefore, whether it is the LVSH 700 or 910, when applied in the source driver circuit, it can have significantly fewer components than the traditional source driver circuit. This not only reduces the cost but also improves the reliability of the source driver circuit.

[0063] According to an embodiment of the present application, a voltage level converter is provided, which is characterized by including: a second-stage circuit operating between a high voltage AVDD and a medium voltage VMID, for receiving a pair of control signals to output a pair of inverted output signals; and a first-stage circuit, further including a P-type transistor P1, a P-type transistor P2, an N-type transistor N2, and an N-type transistor N1 connected in series in sequence, and a P-type transistor P3, a P-type transistor P4, an N-type transistor N4, and an N-type transistor N3 connected in series in sequence, wherein the sources of the P-type transistor P1 and the P-type transistor P3 are respectively connected to the high voltage AVDD, the gate of the P-type transistor P3 is connected to the drain of the P-type transistor P1 to serve as the first signal O1 of the pair of control signals, the gate of the P-type transistor P1 is connected to the drain of the P-type transistor P3 to serve as the second signal O1B of the pair of control signals, the drains of the N-type transistor N1 and the N-type transistor N3 are respectively connected to the ground voltage GND, and the gates of the N-type transistor N1 and the N-type transistor N3 are respectively connected to a pair of inverted input signals.

[0064] In order to reduce the occupied area, the above voltage level converter is characterized in that the above P-type transistor P2, P-type transistor P4, N-type transistor N2, and N-type transistor N4 are medium voltage components.

[0065] In order to reduce the types of supply voltages, the above voltage level converter is characterized in that the gates of the above P-type transistor P2, P-type transistor P4, N-type transistor N2, and N-type transistor N4 are respectively connected to the medium voltage VMID.

[0066] In order to reduce the occupied area, the above voltage level converter is characterized in that the breakdown voltages of the above P-type transistor P2 and P-type transistor P4 are greater than the sum of the medium voltage VMID and the corresponding threshold voltage VTH.

[0067] In order to reduce the occupied area, the above voltage level converter is characterized in that the breakdown voltages of the above N-type transistor N2 and N-type transistor N4 are greater than a difference value, which is the sum of the high voltage VADD and the corresponding threshold voltage VTH minus the medium voltage VMID.

[0068] To provide an output signal with a voltage swing from VMID to AVDD, the above voltage level converter is characterized in that the second-stage circuit further includes a P-type transistor P5 and an N-type transistor N5 connected in series between the high voltage VADD and the middle voltage VMID in sequence, and a P-type transistor P6 and an N-type transistor N6 connected in series between the high voltage VADD and the middle voltage VMID in sequence. The gate of the P-type transistor P5 receives the above first signal O1, the gate of the P-type transistor P6 receives the above second signal O1B, the drain of the P-type transistor P5 is connected to the gate of the N-type transistor N6 as one of the pair of inverted output signals, and the drain of the P-type transistor P6 is connected to the gate of the N-type transistor N5 as the other of the pair of inverted output signals.

[0069] The above voltage level converter is characterized in that the middle voltage VMID is approximately half of the high voltage AVDD.

[0070] According to an embodiment of the present application, an output stage circuit is provided, which is characterized in that it includes: a voltage supply module for supplying AVGP voltage and AVGN voltage respectively; and more than one voltage level converter for outputting a pair of inverted output signals, the pair of inverted output signals operating between the high voltage AVDD and the middle voltage VMID. The voltage level converter includes: a P-type transistor P1, a P-type transistor P2, an N-type transistor N2 and an N-type transistor N1 connected in series in sequence; and a P-type transistor P3, a P-type transistor P4, an N-type transistor N4 and an N-type transistor N3 connected in series in sequence. The sources of the P-type transistor P1 and the P-type transistor P3 are respectively connected to the high voltage AVDD, the gate of the P-type transistor P3 is connected to the drain of the P-type transistor P1 to be used as the first signal OUT of the pair of inverted output signals, the gate of the P-type transistor P1 is connected to the drain of the P-type transistor P3 to be used as the second signal OUTB of the pair of inverted output signals, the drains of the N-type transistor N1 and the N-type transistor N3 are respectively connected to the ground voltage GND, the gates of the N-type transistor N1 and the N-type transistor N3 are respectively connected to a pair of inverted input signals, the gates of the above P-type transistor P2 and P-type transistor P4 are respectively connected to the AVGP voltage, and the gates of the above N-type transistor N2 and N-type transistor N4 are respectively connected to the AVGN voltage.

[0071] To reduce the occupied area, the above output stage circuit is characterized in that the breakdown voltages of the above P-type transistor P2 and P-type transistor P4 are greater than the middle voltage VMID.

[0072] To reduce the occupied area, the above output stage circuit is characterized in that the breakdown voltages of the above N-type transistor N2 and N-type transistor N4 are greater than the difference between the high voltage VADD and the middle voltage VMID.

[0073] To provide the AVGP voltage and the AVGN voltage, the above output stage circuit is characterized in that the voltage supply module includes a P-type transistor PS and an N-type transistor NS. The source of the P-type transistor PS is connected to the medium voltage VMID. The gate and drain of the P-type transistor PS are connected to the ground voltage through a first current source to provide the above AVGP voltage. The drain of the N-type transistor NS is connected to the medium voltage VMID. The gate and source of the N-type transistor NS are connected to the high voltage AVDD through a second current source to provide the above AVGN voltage.

[0074] To reduce the occupied area, the above output stage circuit is characterized in that the above P-type transistor P2, P-type transistor P4, N-type transistor N2, and N-type transistor N4 are medium voltage components.

[0075] According to an embodiment of the present application, a liquid crystal display screen is provided, including a source output circuit for controlling the display of the liquid crystal display screen, wherein the source output circuit includes the voltage level converter or the output stage circuit as described above.

[0076] Due to the adoption of the above solution, the beneficial effects of the present application are as follows: The voltage level converter, output stage circuit, and liquid crystal display screen provided by the present application have fewer components than the voltage level converter of the prior art, can reduce the chip area and have high energy efficiency. It can not only reduce costs and increase reliability, but also reduce the size and power consumption of mobile electronic devices, and further improve the performance of mobile electronic devices.

[0077] As described above, only the preferred specific embodiments of the present application are given, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application, according to the technical solution and application concept of the present application, makes equivalent replacements or changes, and should be covered by the protection scope of the present application.

Claims

1. A voltage level converter, characterized in that, Comprising: A second-stage circuit operating between a high-voltage AVDD and a medium-voltage VMID, for receiving a pair of control signals from a first-stage circuit to output a pair of inverted output signals, wherein the voltages of the pair of inverted output signals operate between the high-voltage AVDD and the medium-voltage VMID; and The first-stage circuit, further comprising: A P-type transistor P1, a P-type transistor P2, an N-type transistor N2, and an N-type transistor N1 connected in series in sequence; and A P-type transistor P3, a P-type transistor P4, an N-type transistor N4, and an N-type transistor N3 connected in series in sequence, wherein the sources of the P-type transistor P1 and the P-type transistor P3 are respectively connected to the high-voltage AVDD, the gate of the P-type transistor P3 is connected to the drain of the P-type transistor P1 to serve as the first signal O1 of the pair of control signals, the gate of the P-type transistor P1 is connected to the drain of the P-type transistor P3 to serve as the second signal O1B of the pair of control signals, the drains of the N-type transistor N1 and the N-type transistor N3 are respectively connected to the ground voltage GND, and the gates of the N-type transistor N1 and the N-type transistor N3 are respectively connected to a pair of inverted input signals.

2. The voltage level converter according to claim 1, wherein The above-mentioned P-type transistor P2, P-type transistor P4, N-type transistor N2, and N-type transistor N4 are medium-voltage components.

3. The voltage level converter according to claim 1, characterized in that, The gates of the above-mentioned P-type transistor P2, P-type transistor P4, N-type transistor N2, and N-type transistor N4 are respectively connected to the medium-voltage VMID.

4. The voltage level converter according to claim 3, wherein The breakdown voltages of the above-mentioned P-type transistor P2 and P-type transistor P4 are greater than the sum of the medium-voltage VMID and the corresponding threshold voltage VTH.

5. The voltage level converter according to claim 3, wherein The breakdown voltages of the above-mentioned N-type transistor N2 and N-type transistor N4 are greater than a difference value, which is the sum of the high-voltage VADD and the corresponding threshold voltage VTH minus the medium-voltage VMID.

6. The voltage level converter according to any one of claims 1 to 5, characterized in that, The second-stage circuit further comprises: A P-type transistor P5 and an N-type transistor N5 connected in series in sequence between the high-voltage VADD and the medium-voltage VMID, and A P-type transistor P6 and an N-type transistor N6 connected in series in sequence between the high-voltage VADD and the medium-voltage VMID, wherein the gate of the P-type transistor P5 receives the above-mentioned first signal O1, the gate of the P-type transistor P6 receives the above-mentioned second signal O1B, the drain of the P-type transistor P5 is connected to the gate of the N-type transistor N6 to serve as one of the pair of inverted output signals, and the drain of the P-type transistor P6 is connected to the gate of the N-type transistor N5 to serve as the other of the pair of inverted output signals.

7. The voltage level converter according to any one of claims 1 to 5, characterized in that, The medium-voltage VMID is half of the high-voltage AVDD.

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