Method of screening non-volatile memory cells

Abstract

A method for screening memory cells, the method comprising: erasing a memory cell; weakly programming the memory cell to a modified erased state; performing a first read operation on the memory cell after the erasing and the weak programming; screening any memory cell that exhibits a read current below a margin read current threshold M1 during the first read operation; baking the memory cell after the first read operation; performing a second read operation on the memory cell after the baking; and screening any memory cell that exhibits a read current below the margin read current threshold M1 during the second read operation.

Description

[0001] Related Applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 330,650, filed April 13, 2022, and U.S. Patent Application No. 17 / 858,185, filed July 6, 2022. TECHNICAL FIELD

[0003] The present disclosure relates to a method of screening non-volatile memory cells for data retention. BACKGROUND

[0004] Non-volatile memory cells having a floating gate for storing charge thereon are well known in the art. Referring to FIG. 1, a cross-sectional view of a conventional non-volatile memory cell 10 is shown. The memory cell 10 includes a semiconductor substrate 12 of a first conductivity type, such as P-type. At or near a surface of the substrate 12 is a first region 14 (also referred to herein as a drain or drain region) of a second conductivity type, such as N-type. Spaced apart from the first region 14 is a second region 16 (also referred to herein as a source or source region) also of the second conductivity type. A portion of the substrate 10 between the first region 14 and the second region 16 is a channel region 18. A word line gate (also referred to herein as a select gate) 20, which can be made of polysilicon, is positioned over a first portion of the channel region 18. The word line gate 20 is spaced apart from the channel region 18 by an insulating layer 22 (e.g., silicon dioxide). Immediately adjacent to and spaced apart from the word line gate 20 is a floating gate 24, which can also be made of polysilicon, and is positioned over another portion of the channel region 18. The floating gate 24 is separated from the channel region 18 by another insulating layer 30 (e.g., silicon dioxide). A control gate (also referred to as a coupling gate) 26, which can also be made of polysilicon, is positioned over the floating gate 24 and is insulated therefrom by another insulating layer 32 (such that any voltage applied to the control gate 26 is capacitively coupled to the floating gate 24). On the other side of the floating gate 24 and spaced apart therefrom is an erase gate 28, which can also be made of polysilicon. The erase gate 28 is positioned over and insulated from the second region 16. The erase gate 28 is also immediately adjacent to and spaced apart from the control gate 26. In operation of the memory cell 10, the charge stored on the floating gate 24 (or the lack of charge on the floating gate 24) controls the flow of current between the first region 14 and the second region 16 through the channel region 18. In the case where there is charge (i.e., electrons) on the floating gate 24 (i.e., the floating gate is negatively charged), the floating gate 24 is considered to be programmed. In the case where there is little to no electron charge on the floating gate 24 (i.e., the floating gate is considered to be positively charged), the floating gate 24 is considered to be erased. The charge state of the floating gate 24 controls the conductivity of that portion of the channel region 18 underneath the floating gate 24, and the voltage applied to the word line gate 20 controls the conductivity of that portion of the channel region 18 underneath the word line gate 20.

[0005] Memory cell 10 operates as follows. During a program operation to store (electronic) charge on floating gate 24, a first positive voltage is applied to word line gate 20, thereby making the portion of channel region 18 under word line gate 20 conductive. A second positive voltage is applied to control gate 26. A third positive voltage is applied to second region 16. A current is applied to first region 14. Electrons are attracted to the positive voltage at second region 16. As they approach floating gate 24, they experience a sudden increase in the electric field caused by the voltage applied to control gate 26, which is capacitively coupled to floating gate 24, thereby causing charge to be injected onto floating gate 24. Thus, programming occurs through the mechanism of hot electron injection.

[0006] During an erase operation to remove (electronic) charge from floating gate 24, a high positive voltage is applied to erase gate 28. A negative voltage or a ground voltage can be applied to control gate 26, word line gate 20, or both. Charge is transferred from floating gate 24 to erase gate 28 by tunneling through the insulating layer between floating gate 24 and erase gate 28. In particular, floating gate 24 can be formed with a sharp tip facing erase gate 28, thereby facilitating Fowler-Nordheim tunneling of electrons from the tip on floating gate 24 through the insulating layer between floating gate 24 and erase gate 28 and onto erase gate 28.

[0007] During a read operation, a first positive voltage is applied to word line gate 20, thereby turning on the portion of channel region 18 under word line gate 20. A second positive voltage is applied to control gate 26. A voltage difference is applied to first region 14 and second region 16. If floating gate 24 is programmed, i.e., floating gate 24 stores electrons, the second positive voltage applied to control gate 26 is unable to overcome the negative potential caused by the electrons stored on floating gate 24, and thus the portion of channel region 18 under floating gate 24 remains non-conductive. Accordingly, no or minimal current flows between first region 14 and second region 16. This is sensed as a programmed, i.e., 0, state. However, if floating gate 24 is erased, i.e., floating gate 24 is considered to be positively charged, the second positive voltage applied to control gate 26, which is capacitively coupled to floating gate 24, is able to make the portion of channel region 18 under floating gate 24 conductive. Accordingly, current flows between first region 14 and second region 16. This is sensed as an erased, i.e., 1, state.

[0008] Memory cells 10 are typically formed in an array on a semiconductor wafer, the array having a plurality of rows and columns of memory cells 10. After the memory cells 10 are fabricated on the wafer, the memory cells 10 on the wafer are subjected to testing to determine the ability of each memory cell 10 to retain its programmed or erased state, particularly the ability of the floating gate 24 in each memory cell 10 to retain its charge state in electronic form or primarily the lack of electrons. During testing, the memory cells 10 are first programmed to place charge (electrons) on the floating gate 24 or erased to remove charge (electrons) from the floating gate 24 to a substantial degree. The memory cells 10 are then baked, which involves subjecting the memory cells 10 to high temperatures for a period of time (as a non-limiting example, three days at 250 degrees Celsius). Finally, each memory cell 10 in the device is subjected to a read operation in which the read current from the memory cell 10 under test is compared to a read reference current.

[0009] Referring to FIG. 2, a plot of the standard deviation of the read current Ir distribution of various memory cells 10 set in different programmed states (i.e., different amounts of charge on the respective floating gates 24) is shown. Memory cells 10 in the erased state typically have a higher read current 40 compared to the read current 42 of memory cells in the neutral charge state (i.e., having some charge on the floating gate), which in turn typically have a higher read current compared to the read current 44 of memory cells in the programmed state (i.e., fully programmed with electrons on the floating gate). During normal use operations of the memory cells, determination of the programmed state of the memory cells is made by performing a read operation and comparing the read current Ir of the memory cell (i.e., the current through the channel region 18 when a normal use operation read voltage is applied) to a read reference current. A non-limiting example of a read reference current is about 30% of the typical read current of an erased memory cell. If the read current is higher than the read reference current, the memory cell is deemed to be erased. If the read current is lower than the read reference current, the memory cell is deemed to be programmed. Due to the dispersion of parameters of the cells integrated in the memory array, the read current 42 of some cells in the neutral charge state can be higher than the read reference current, and the read current 42 of some cells can be lower than the read reference current.

[0010] In the case where memory cell 10 has a leakage path for charge to pass through the dielectric surrounding the floating gate 24, the read current from such a defective memory cell 10 in the erased state will decrease (as electrons leak onto the floating gate) and tend to have the characteristics of current 42. If the read current from the defective memory cell 10 under test remains above the read reference current, this condition cannot be detected after high temperature baking. Similarly, the read current from a defective memory cell 10 in the programmed state will increase (as electrons leak from the floating gate) and tend to have the characteristics of current 42. If the read current from the defective memory cell 10 under test remains below the read reference current, this condition cannot be detected after high temperature baking.

[0011] Because of these characteristics of non-volatile memory cell 10, testing of a memory device having memory cells 10 of the prior art involves two operations. In a first operation, a first data pattern is stored in the memory cells, followed by a first baking operation, followed by a test operation to determine the read current of memory cell 10 and compare it to the read reference current. In a second operation, a second data pattern, which is the inverse of the first data pattern, is stored in the memory cells, followed by a second baking operation, followed by a test operation to determine the read current of memory cell 10 and compare it to the read reference current. Because the time to store the data pattern in the memory cells and the time to bake the device is quite long, this increases the cost of testing the memory device. However, even with the prior art double bake process, some defective memory cells 10 can not be found defective after data retention screening (i.e., testing to identify defective memory cells that cannot adequately maintain their programmed state for storing data). For example, a defective memory cell 10 can have a read current 42 that is higher than the read reference current. In the first test, when the defective memory cell 10 is in the erased state (in addition to the electrons that have leaked onto the floating gate), the read current from such a memory cell will decrease due to the leakage and still tend to have the characteristics of current 42, such that its read current remains above the read reference current, and the defective cell 10 will not be detected as defective. In the second test, when the defective cell 10 is in the programmed state (in addition to the electrons that have leaked from the floating gate), the read current from such a cell will increase due to the leakage and still tend to have the characteristics of read current 42. However, if the leakage is too slow during the baking process, the read current from the defective cell 10 will not have time to increase above the read reference current during the baking process. Thus, because the read reference current is typically close to the read current 42, the leakage of electrons during the baking process is typically slow, and some defective cells 10 can remain undetected defective after data retention screening.

[0012] There is a need to improve the efficiency of data retention screening processes for defective memory cells. SUMMARY

[0013] The above problems and needs are addressed by a method for screening memory cells, the method comprising: erasing a memory cell; weakly programming the memory cell to a modified erased state; performing a first read operation on the memory cell after the erasing and the weakly programming; screening any memory cell that exhibits a read current below a margin read current threshold Ml during the first read operation; baking the memory cell after the first read operation; performing a second read operation on the memory cell after the baking; and screening any memory cell that exhibits a read current below a margin read current threshold M2 during the second read operation.

[0014] A method for screening memory cells comprises: erasing a memory cell; weakly programming the memory cell to a modified erased state; performing a first read operation on the memory cell after the erasing and the weakly programming; screening any memory cell that exhibits a read current below a margin read current threshold Ml during the first read operation; baking the memory cell after the first read operation; performing a second read operation on the memory cell after the baking; and screening any memory cell that exhibits a read current below a margin read current threshold M2 during the second read operation. The margin read current thresholds Ml and M2 are greater than a read reference current used to determine an erased state of the memory cell during a nominal read operation, and the margin read current threshold M2 is less than the margin read current threshold Ml.

[0015] A method for screening memory cells includes strongly erasing memory cells, where each memory cell includes a control gate; after the strong erase, performing a first read operation on the memory cells, the first read operation including applying a first read voltage to the control gate, the first read voltage being lower than a nominal read voltage for the control gate; screening any memory cells that exhibit a read current lower than a margin read current threshold Ml during the first read operation; weakly programming the memory cells to a modified erased state; after the weak programming, performing a second read operation on the memory cells, the second read operation including applying a second read voltage to the control gate, the second read voltage being lower than the nominal read voltage for the control gate and greater than the first read voltage; screening any memory cells that exhibit a read current lower than the margin read current threshold Ml during the second read operation; baking the memory cells after the second read operation; after the baking, performing a third read operation on the memory cells, the third read operation including applying a third read voltage to the control gate, the third read voltage being lower than the nominal read voltage for the control gate and greater than the second read voltage; and screening any memory cells that exhibit a read current lower than the margin read current threshold Ml during the third read operation.

[0016] A method for screening memory cells includes strongly erasing memory cells, where each memory cell includes a control gate; after the strong erase, performing a first read operation on the memory cells, the first read operation including applying a first read voltage to the control gate, the first read voltage being lower than a nominal read voltage for the control gate; screening any memory cells that exhibit a read current lower than a margin read current threshold Ml during the first read operation; weakly programming the memory cells to a modified erased state; after the weak programming, performing a second read operation on the memory cells, the second read operation including applying a second read voltage to the control gate, the second read voltage being lower than the nominal read voltage for the control gate and greater than the first read voltage; screening any memory cells that exhibit a read current lower than a margin read current threshold M2 during the second read operation; baking the memory cells after the second read operation; after the baking, performing a third read operation on the memory cells, the third read operation including applying a third read voltage to the control gate, the third read voltage being lower than the nominal read voltage for the control gate and greater than the second read voltage; and screening any memory cells that exhibit a read current lower than a margin read current threshold M3 during the third read operation. The margin read current thresholds Ml, M2, and M3 are greater than a read reference current used to determine an erased state of the memory cells during a nominal read operation, the margin read current threshold M3 is less than the margin read current threshold M2, and the margin read current threshold M2 is less than the margin read current threshold Ml.

[0017] Other objects and features of this disclosure will become apparent from a review of the specification, claims and drawings. Attached Figure Description

[0018] Figure 1 is a side cross-sectional view of a conventional non-volatile memory cell.

[0019] Figure 2 is a graph showing the distribution of read current in erased memory cells, memory cells in a neutral charge state, and programmed memory cells.

[0020] Figure 3 It is a graph showing the distribution of read current as a function of the control gate voltage of a memory cell in different programming states.

[0021] Figure 4 It is a graph showing the distribution of read current as a function of the control gate voltage of a memory cell in different programming states.

[0022] Figure 5 It is a graph showing the standard deviation distribution of the threshold voltage of memory cells in different programming states.

[0023] Figure 6 This is a flowchart illustrating the operational steps of a first example of memory cell screening.

[0024] Figure 7 It shows the basis Figure 6 The first example is a graph showing the standard deviation distribution of the threshold voltage of memory cells in different programming states.

[0025] Figure 8 It is a graph showing the standard deviation distribution of the threshold voltage of a memory cell in a modified erase state.

[0026] Figure 9 This is a flowchart illustrating the operational steps of a second example of memory cell screening.

[0027] Figure 10 It shows the basis Figure 9 The second example is a graph showing the standard deviation distribution of the threshold voltage of memory cells in different programming states.

[0028] Figure 11 This is another flowchart illustrating the operational steps of a second example of memory cell screening.

[0029] Figure 12 This is a flowchart illustrating the operational steps of a third example of memory cell screening.

[0030] Figure 13 It shows the basis Figure 12The third example is a graph showing the standard deviation distribution of the threshold voltage of memory cells in different programming states.

[0031] Figure 14 This is another flowchart illustrating the operational steps of a third example of memory cell filtering. Detailed Implementation

[0032] The inventors have determined that, after a high-temperature baking operation, 0-to-1 faults (where electrons leak from the floating gate) are more common in the memory cells of Figure 1 than 1-to-0 faults (where electrons leak onto the floating gate). This means that baking memory cells in a programmed "0" state is more effective for data retention screening (i.e., detection of leaky defective memory cells that fail to maintain their programmed state sufficiently over time) than baking memory cells in an erased "1" state. It was found that memory cells in a neutral charge state (the end of the leak bit) generally have a higher cell current than the read reference current, and are therefore closer to an erased state than a programmed state. Therefore, compared to read operations using a tolerance read current threshold set closer to the erase "1" state (referred to herein as "tolerance 1" and tolerance read current threshold M1) for data retention screening from the erase "1" state, read operations using a tolerance read current threshold set closer to the programming "0" state (referred to herein as "tolerance 0") for data retention screening from the programming "0" state are more effective in detecting excessive leakage and thus defective memory cells. Another reason for the greater effectiveness of data retention screening from the programming "0" state is that the erase distribution (i.e., the distribution of read current and threshold voltage across erased memory cells) is substantially wider than the programming distribution (i.e., the distribution of read current and threshold voltage across programmed memory cells). This is due to the less controllable Fowler Nordheim tunneling mechanism used for erasure, while programming is based on a more controllable hot electron injection mechanism. Defective memory cells that would otherwise leak are often normal, meaning they may originate from the central portion of the erase or programming read current distribution. Therefore, a wider erase or program read current distribution necessitates setting the tolerance read current threshold used for data retention screening to detect leaky memory cells further away from this distribution. This results in longer detection times for leaky memory cells because leakage occurs over time. In other words, in rare cases, due to the strong asymmetric nature of leakage, leaky memory cells may show a change in charge state from the erase "1" state much faster than a programmed "0" state. Improvements in data retention screening efficiency are needed.

[0033] Figure 3 The figure shows the dependence of the memory cell read current Ir on the read voltage Vcg applied to the control gate 26 (CG) of the memory cell in FIG1 under various normal use read operation conditions in different cell states.Figure 3 The curves in the figure illustrate the read current characteristics of a leaky memory cell as a function of the read voltage Vcg applied to the control gate. Specifically, curve (a) corresponds to a memory cell immediately following an erase operation (i.e., the erased memory cell has a positive floating gate charge (positive Qfg)). Curve (b) corresponds to a memory cell immediately following a programming operation (i.e., the programmed memory cell has a negative floating gate charge (negative Qfg)). Curve (c) corresponds to the neutral charge state of the floating gate (zero floating gate charge (Qfg = 0)). Curves (d) and (e) correspond to the fault detection thresholds for the read current used for data retention screening in erase state "1" and programming state "0", respectively. For example, if the read current characteristic curve of an erased memory cell shifts to the right from curve (a) beyond curve (d) (i.e., due to the floating gate charge leaking towards the neutral charge state), it will be considered defective. Similarly, if the read current characteristic curve of a programmable memory cell shifts to the left from curve (b) beyond curve (e) (i.e., due to floating gate charge loss), it will be considered defective.

[0034] Any change in the programming state of the floating gate (i.e., its charge state) causes a corresponding shift in the characteristic curve along the Vcg axis, without changing the shape of the curve. Typically, the floating gate charge (Qfg) of a leaky memory cell shifts to its neutral charge state under unbiased conditions. Therefore, as... Figure 3 As shown, if the memory cell begins in the programming "0" state (indicated by the "electron charge loss" arrow), the read current Ir of the memory cell increases over time during the baking process, and if the memory cell begins in the erase "1" state (indicated by the "electron charge gain" arrow), the read current Ir of the memory cell decreases during the baking process, both approaching a neutral charge state (Qfg = 0). Using tolerance 1 and tolerance 0 reference currents, respectively set higher and lower than the normal read reference current, data retention faults can be detected more effectively. Specifically, Figure 3In this context, "normal read" refers to the read reference current during a nominal read operation (including the application of the nominal read voltage Vcg_read on the control gate) that distinguishes between erasing and programming a memory cell. As used herein, nominal read, nominal program, and nominal erase operations (including the nominal voltage applied during these nominal operations) refer to read, program, and erase operations performed on memory cells under the control of a controller that manages read, program, and erase operations to read, program, and erase data into / from memory cells during normal use conditions of a memory device containing memory cells. Tolerance 1 represents a tolerance read current threshold (which is higher than a predetermined read reference current) and is a read current threshold below which erased memory cells are considered defective. Similarly, tolerance 0 represents a tolerance read current threshold (which is lower than a predetermined read reference current) and is a read current threshold above which programmed memory cells are considered defective. By setting tolerance 0 below the read reference current (used for nominal read operations) and tolerance 1 above the read reference current, data retention efficiency can be improved by reducing the failure time of leaky memory cells. Another way to reduce the failure time of leaky memory cells is to apply a voltage higher than the nominal read voltage Vcg_read used for data retention filtering of memory cells in the programming "0" state to the control gate during read operations, and a voltage lower than the nominal read voltage Vcg_read used for data retention filtering of memory cells in the erasure "1" state.

[0035] One criterion for selecting the tolerance level could be to provide a protection band to account for cell-to-cell variations in read current of normal (defect-free) programmed and erased memory cells in the array, which in Figure 4 As shown in the diagram. During a read operation, a nominal read voltage Vcg_read is applied to the control gate. The lowest read current Ir after an erase operation in the memory array is significantly larger than tolerance 1 (A1), and the highest read current Ir after a programming operation is significantly smaller than tolerance 0 (A0), as shown by... Figure 4 As indicated by arrows A1 and A0. The protective band prevents good memory cells from being filtered out from the inherently variable tail. For example... Figure 4 As shown, the cell-to-cell transition after an erase operation is wider than the cell-to-cell transition after a programming operation.

[0036] Figure 5The diagram schematically illustrates the distribution of the memory cell array threshold voltage (Vtcg) after erase and program operations. The cell threshold voltage Vtcg is the minimum read voltage applied to the control gate required to generate a certain level of read current (e.g., tolerance 0, normal read, tolerance 1) through the memory cell during a read operation. Figure 5 The Vtcg distribution after erasure corresponds to the control gate read voltage required to match the cell current to the read current threshold of tolerance 1. Figure 5 The Vtcg distribution after programming corresponds to the control gate read voltage required to match the cell current to the zero read current threshold. Figure 5 The Vtcg, which is equal to Vcg_read, corresponds to the read reference current used to distinguish erased memory cells from programmed memory cells during a nominal read operation. Tolerance 1 and Tolerance 0 read current thresholds are set for data retention screening of defective memory cells to be outside the inherent distributions of the erase and programmed states, respectively. Because the Vtcg distribution after erasure is wider than that after programming, data retention screening of leaky memory cells in the erase state is less efficient (i.e., longer failure time) compared to the programmed state, due to electronic leakage over time.

[0037] The inventors have recognized that data retention screening from erase state "1" can be enhanced by compressing the erase distribution of erased memory cells (i.e., the distribution of the threshold voltage of tolerance 1). This is achieved by applying a weak programming operation after the erase operation to place the memory cells in a modified (i.e., compressed) erase state. Once the modified (compressed) erase state is achieved, the tolerance read current threshold (tolerance 1) can be set closer to the center of the erase state "1" distribution, thus improving data retention screening efficiency (i.e., reducing the failure time of leaky memory cells that may originate from the center of the distribution). The Vtcg distribution can be compressed by applying several weak programming operations with gradually increasing programming voltages and performing read verification operations between the weak programming operations. As explained in further detail below, additional techniques can be used in conjunction with the weak programming operations to identify defective leaky memory cells, which will be explained in more detail below. For example, to reduce yield loss caused by finite inherent negative Ir shift (or positive Vtcg shift) during high-temperature baking (which is independent of defective leakage from the floating gate), a lower Vcg_read operation can be performed before the baking operation compared to a higher Vcg_read after baking. Another technique for compensating for inherent Ir shift during baking is to use a higher tolerance 1 level before the baking operation compared to a lower tolerance 1 level after baking. As another technique, to further enhance data retention screening for leaky memory cell detection, a stronger erase operation (compared to the nominal erase operation) can be applied first to further push the finally compressed erase distribution away from the neutral charge state. As another technique, the Vcg_read used to verify the strong erase operation can be set to be lower than the Vcg_read after the erase distribution is compressed by a weak programming operation. As another technique, a higher tolerance 1 level for read operations after an erase operation can be used compared to a tolerance 1 level for read operations after a weak programming operation.

[0038] Figures 6 to 8 A first method is illustrated, wherein data retention filtering includes compressing the distribution of the threshold voltage Vtcg of the erased memory cells by performing weak programming operations on the erased memory cells. (As shown) Figure 6 As shown, for step 1A of this example, a nominal erase operation is used to erase the memory cell. In step 2A, a weak programming operation is used to weakly program the memory cell to compress the distribution of the threshold voltage Vcg of the memory cell. After the weak programming operation, the memory cell is in a modified erase state. Figure 7The diagram shows the threshold voltage distribution after an erase operation (the line labeled "Erase State") and a more compact threshold voltage distribution after a weak programming operation (the line labeled "Modified Erase State"). To compress the erase distribution, weak programming can be applied, with conditions selected to keep the shift of the higher standard deviation portion of the erase distribution low, while causing larger shifts in the middle and lower portions of the standard deviation erase distribution. This ensures that the memory cell in the modified erase state remains below the threshold voltage Vcg associated with the nominal operation and exhibits a sufficiently high read current during the nominal read operation, so that the memory cell in the modified erase state is still considered erased (i.e., the goal is to avoid overprogramming the memory cell, keeping the cell current above the tolerance level 1). Figure 7 As shown, a single-operation weak programming operation can significantly tighten the erase distribution. In step 3A, a first screening read is performed, wherein the memory cell is read using the nominal read operation voltage Vcg_read on the control gate (also referred to herein as the nominal read voltage Vcg_read, the nominal read voltage Vcg_read of the control gate, and in this example as the first read voltage) to screen any memory cell having a read current below the tolerance read current threshold M1 as defective. As mentioned above, the tolerance read current threshold M1 is greater than the read reference current exhibited by the memory cell in the nominal read operation that would be considered to be erased. As used herein, screening refers to identifying any memory cell having a read current below the tolerance read current threshold M1 as defective, and a screening read refers to a combination of a read operation and the identification of any memory cell as defective using the result of the read operation. In step 4A, a high-temperature baking operation is then performed (e.g., at 250 degrees Celsius for three days). In step 5A, a second screening read is performed, wherein the memory cell is read using the nominal Vcg_read on the control gate in the second read operation, thereby screening any memory cell with a read current below the tolerance read current threshold M1 as defective.

[0039] like Figure 8As shown, the erase distribution of the threshold voltage Vtcg can be further tightened by applying a weak programming algorithm. This algorithm uses pulses of programming voltage separated by read verification operations, where one or more programming voltages are gradually increased pulse by pulse, with read verification operations occurring between pulses, until the modified erase state is achieved. The programming voltage increment can be selected based on the sorting time budget and the duration of the programming time for each increment. The advantage of applying a programming algorithm with smaller voltage increments is that a more compact distribution can be achieved. However, programming may take longer, and therefore, an optimization or trade-off between distribution compactness and increased test time is envisioned when determining whether to use single-pulse or multi-pulse weak programming operations to achieve the desired modified erase state of the memory cell.

[0040] Figures 9 to 10 A second method is illustrated, in which data retention screening uses different read operation conditions before and after the baking operation, relative to the nominal read operation. Following the erase operation in step 1B and the weak programming operation in step 2B to place the memory cells in a modified erase state (where incremental programming with read verification provides a more concentrated standard deviation distribution compared to a single weak programming step), a first screening read is performed in step 3B, where the first read operation is performed using a read voltage Vcg_read1 (also referred to as the first read voltage relative to this example) on the control gate that is less than the nominal Vcg_read, thereby screening any memory cells with read currents below the tolerance read current threshold M1 as defective. In step 4B, a high-temperature baking operation is then performed (e.g., for three days at 250 degrees Celsius). In step 5B, a second screening read is performed, wherein a memory cell is read using a read voltage Vcg_read2 (also referred to as the second read voltage relative to this example) on the control gate that is greater than Vcg_read1 and less than the nominal Vcg_read voltage, thereby screening any memory cell with a read current below the tolerance read current threshold M1 as defective. This example is advantageous because weak programming conditions can be selected so that the shift of the center of the erase distribution is increased more than the upper edge of the distribution with the highest standard deviation Vtcg (which should be shifted minimally). The guard band provided between Vcg_read1 and Vcg_read2 explains the inherent read current shift mechanism, which is independent of charge leakage from the floating gate through defects during the baking operation. Instead of, or in addition to increasing the voltage of the control gate applied to the second screening read relative to the first screening read as described above, the second tolerance read current threshold M2 for the second screening read may be less than the first tolerance read current threshold M1 for the first screening read, but still greater than the read reference current. If otherwise, in Figure 9In step 5B, the second tolerance reading current threshold M2 replaces the first tolerance reading current threshold M1 for filtering the reading, such as... Figure 11 As shown.

[0041] Figures 12 to 13 A third method is illustrated, in which data retention filtering comprises three read operations. In step 1C, a strong erase operation is used to erase the memory cell, meaning that the erase voltage applied to the erase gate is higher than the voltage applied during the nominal erase operation, the application time is longer than the nominal erase operation, or both, such that the memory cell is erased more deeply than during the nominal erase operation. In step 2C, a first filter read is performed, wherein a first read operation is performed using a read voltage Vcg_read1 (also referred to as the first read voltage relative to this example) on the control gate that is less than the nominal Vcg_read voltage, and any memory cell having a read current below the tolerance read current threshold M1 is filtered as defective. In step 3C, a weak programming operation is performed to place the memory cell in a modified erase state. In step 4C, a second screening read is performed, wherein the memory cells are read using a read voltage Vcg_read2 (also referred to as the second read voltage in this example) on the control gate that is greater than Vcg_read1 and less than the nominal Vcg_read voltage, and any memory cells with a read current below the tolerance read current threshold M1 are screened as defective. In step 5C, a high-temperature baking operation is then performed (e.g., at 250 degrees Celsius for three days). In step 6C, a third screening read is performed, wherein the memory cells are read using a read voltage Vcg_read3 (also referred to as the third read voltage in this example) on the control gate that is greater than Vcg_read2 and less than the nominal Vcg_read voltage, and any memory cells with a read current below the tolerance read current threshold M1 are screened as defective. In this example, deep erasure and the application of the first screening read before weak programming help to account for any possible overshoot during weak programming. Instead of, or in addition to, increasing the voltage applied to the control gate in successive first, second, and third filter reads as described above, the tolerance read current threshold M1 for successive first, second, and third filter reads can be continuously decreased. For example, the second tolerance read current threshold M2 for the second filter read can be less than the first tolerance read current threshold M1 for the first filter read, and the third tolerance read current threshold M3 for the third filter read can be less than the second tolerance read current threshold M2 for the second filter read, wherein all three tolerance read current thresholds M1, M2, and M3 are still greater than the read reference current. If otherwise, then in Figure 12In step 4C, the second tolerance read current threshold M2 replaces the first tolerance read current threshold M1 for filtering reads, and... Figure 12 In step 6C, the third tolerance read current threshold M3 replaces the first tolerance read current threshold M1 for filtering reads, such as... Figure 14 As shown.

[0042] It should be understood that this disclosure is not limited to the examples above and illustrated herein, but covers any and all variations within the scope of any claim. For example, references to this disclosure or the invention or examples herein are not intended to limit the scope of any claim or claim terminology, but only to one or more features that may be covered by one or more claims. The examples of materials, processes, and values ​​described above are merely illustrative and should not be construed as limiting the claims.

Claims

1. A method for screening memory cells, the method comprising: Erase the memory cell; The memory cell is weakly programmed to a modified erase state; A first read operation is performed on the memory cell after the erasure and the weak programming. Filter any memory cell that exhibits a read current below the tolerance read current threshold M1 during the first read operation; The memory cell is baked after the first read operation; After the baking process, a second read operation is performed on the memory cell; as well as Filter any memory cell that exhibits a read current below the tolerance read current threshold M1 during the second read operation.

2. The method of claim 1, wherein the tolerance read current threshold M1 is greater than the read reference current used to determine the erase state of the memory cell during a nominal read operation.

3. The method according to claim 1, wherein: Each of the memory cells includes a control gate; The execution of the first read operation includes applying a first read voltage to the control gate, the first read voltage being equal to the nominal read voltage of the control gate; and The execution of the second read operation includes applying the first read voltage to the control gate.

4. The method according to claim 1, wherein: Each of the memory cells includes a control gate; The execution of the first read operation includes applying a first read voltage to the control gate, the first read voltage being less than the nominal read voltage of the control gate; and The execution of the second read operation includes applying a second read voltage to the control gate, the second read voltage being less than the nominal read voltage of the control gate and greater than the first read voltage.

5. A method for screening memory cells, the method comprising: Erase the memory cell; The memory cell is weakly programmed to a modified erase state; A first read operation is performed on the memory cell after the erasure and the weak programming. Filter any memory cell that exhibits a read current below the tolerance read current threshold M1 during the first read operation; The memory cell is baked after the first read operation; After the baking process, a second read operation is performed on the memory cell; as well as Filter any memory cell that exhibits a read current below the tolerance read current threshold M2 during the second read operation; The tolerance read current thresholds M1 and M2 are greater than the read reference current used to determine the erase state of the memory cell during a nominal read operation, and the tolerance read current threshold M2 is less than the tolerance read current threshold M1.

6. The method according to claim 5, wherein: Each of the memory cells includes a control gate; The execution of the first read operation includes applying a first read voltage to the control gate, the first read voltage being less than the nominal read voltage of the control gate; and The execution of the second read operation includes applying a second read voltage to the control gate, the second read voltage being less than the nominal read voltage of the control gate and greater than the first read voltage.

7. A method for screening memory cells, the method comprising: The memory cells are forcefully erased, wherein each memory cell includes a control gate; After the strong erase, a first read operation is performed on the memory cell, the first read operation including applying a first read voltage to the control gate, the first read voltage being lower than the nominal read voltage of the control gate; Filter any memory cell that exhibits a read current below the tolerance read current threshold M1 during the first read operation; The memory cell is weakly programmed to a modified erase state; After the weak programming, a second read operation is performed on the memory cell, the second read operation including applying a second read voltage to the control gate, the second read voltage being lower than the nominal read voltage of the control gate and greater than the first read voltage; Filter any memory cell that exhibits a read current below the tolerance read current threshold M1 during the second read operation; The memory cell is baked after the second read operation; After the baking process, a third read operation is performed on the memory cell, the third read operation including applying a third read voltage to the control gate, the third read voltage being lower than the nominal read voltage of the control gate and greater than the second read voltage; as well as Filter any memory cell that exhibits a read current below the tolerance read current threshold M1 during the third read operation.

8. The method of claim 7, wherein the tolerance read current threshold M1 is greater than the read reference current used to determine the erase state of the memory cell during a nominal read operation.

9. A method for screening memory cells, the method comprising: The memory cells are forcefully erased, wherein each memory cell includes a control gate; After the strong erase, a first read operation is performed on the memory cell, the first read operation including applying a first read voltage to the control gate, the first read voltage being lower than the nominal read voltage of the control gate; Filter any memory cell that exhibits a read current below the tolerance read current threshold M1 during the first read operation; The memory cell is weakly programmed to a modified erase state; After the weak programming, a second read operation is performed on the memory cell, the second read operation including applying a second read voltage to the control gate, the second read voltage being lower than the nominal read voltage of the control gate and greater than the first read voltage; Filter any memory cell that exhibits a read current below the tolerance read current threshold M2 during the second read operation; The memory cell is baked after the second read operation; After the baking process, a third read operation is performed on the memory cell, the third read operation including applying a third read voltage to the control gate, the third read voltage being lower than the nominal read voltage of the control gate and greater than the second read voltage; as well as Filter any memory cell that exhibits a read current below the tolerance read current threshold M3 during the third read operation; The tolerance read current thresholds M1, M2, and M3 are greater than the read reference current used to determine the erase state of the memory cell during a nominal read operation, wherein the tolerance read current threshold M3 is less than the tolerance read current threshold M2, and the tolerance read current threshold M2 is less than the tolerance read current threshold M1.

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