Broadband digital triggering system, method and related electronic equipment

Abstract

An embodiment of the present disclosure provides a broadband digital trigger system, method, and related electronic equipment, which includes: an analog front end for receiving a signal under test; an interleaved analog-to-digital conversion module, including multiple analog-to-digital converters, wherein the multiple analog-to-digital converters are used to perform interleaved sampling on the output signal of the analog front end to obtain multiple first signals; an extraction and de-embedding module, which is used to filter and extract at least part of the first signal to obtain a filtered and extracted signal, and de-embed the filtered and extracted signal to obtain a second signal; a filtering and interpolation module, which is used to filter and interpolate the second signal to obtain a third signal; and a trigger judgment module, which is used to determine whether a trigger condition is met based on the third signal, and issue a trigger instruction in response to the trigger condition being met, thereby reducing the size and power consumption of the broadband digital trigger system.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of signal processing technology, and in particular to a broadband digital triggering system, method, and related electronic equipment. Background Art

[0002] Signal measurement equipment, such as oscilloscopes, typically includes a trigger function that allows users to capture specific waveforms and quickly assess signal quality. As communication signal transmission rates increase, the measurement and analysis of high-speed signals place higher demands on signal measurement equipment. The accuracy of the trigger function in signal measurement equipment is particularly important. Due to signal distortion in the trigger chain, the trigger signal generated after the measured signal passes through the trigger chain differs from the signal displayed on the signal measurement device, resulting in a decrease in trigger accuracy.

[0003] To improve trigger accuracy, the trigger signal can be compensated before triggering. Currently, analog triggers are commonly used for wide-bandwidth triggering. However, analog trigger compensation requires equalization circuits, which are inaccurate and expensive. To improve accuracy and reduce costs, digital architectures are used in some applications to achieve high-precision digital trigger compensation. However, current high-precision digital trigger compensation implemented using digital architectures suffers from the large size of the compensation circuits, which results in larger broadband digital systems and higher power consumption. Summary of the Invention

[0004] Embodiments of the present disclosure provide a broadband digital triggering system, method, and related electronic equipment.

[0005] In a first aspect, an embodiment of the present disclosure provides a broadband digital trigger system, comprising: an analog front end for receiving a signal under test; an interleaved analog-to-digital conversion module, comprising a plurality of analog-to-digital converters, wherein the plurality of analog-to-digital converters are used to perform interleaved sampling on the output signal of the analog front end to obtain a plurality of first signals; an extraction and de-embedding module, for filtering and extracting at least a portion of the first signal to obtain a filtered and extracted signal, and de-embedding the filtered and extracted signal to obtain a second signal; a filtering and interpolation module, for filtering and interpolating the second signal to obtain a third signal; and a trigger judgment module, for determining whether a trigger condition is met based on the third signal, and issuing a trigger instruction in response to the trigger condition being met.

[0006] According to the above scheme, since the output signal of the analog front end is sampled in an interleaved manner by the multi-channel analog-to-digital converter, a high sampling rate of the output signal of the analog front end can be guaranteed. In addition, at least part of the first signal output by the multi-channel analog-to-digital converter is filtered and extracted, and the filtered and extracted signal is compensated, which reduces the amount of data for compensation processing. At the same time, it can also reduce the volume of the broadband digital trigger system and reduce the power consumption of the broadband digital trigger system.

[0007] In combination with the first aspect, in certain embodiments of the first aspect, the extraction and de-embedding module includes a filtering extraction module and a de-embedding module, wherein the signal input end of the filtering extraction module is connected to the output end of at least one analog-to-digital converter among the multiple analog-to-digital converters, and the filtering extraction module is used to receive at least part of the first signal output by the at least one analog-to-digital converter through the signal input end, and filter and extract at least part of the first signal to obtain the filtered and extracted signal; the de-embedding module is used to receive the filtered and extracted signal, and use a preset de-embedding filter to de-embed the filtered and extracted signal to obtain the second signal.

[0008] According to the above solution, filtering and extracting at least a portion of the first signal and processing the filtered and extracted signal using a de-embedding sub-module are beneficial to reducing the circuit scale of the de-embedding module.

[0009] Furthermore, the signal input end of the filtering and extraction module is connected to the output ends of the two analog-to-digital converters, and the filtering and extraction module is used to receive the first signals respectively output by the two analog-to-digital converters and filter and extract the first signals respectively output by the two analog-to-digital converters according to their respective timings.

[0010] According to the above scheme, using the first signals output by two analog-to-digital converters among multiple analog-to-digital converters for trigger judgment can reduce the data processing amount of trigger judgment, reduce the volume of the broadband digital trigger system, and facilitate the specific implementation of the broadband digital trigger system.

[0011] Furthermore, the signal input end of the filtering and extraction module is connected to the output end of each of the analog-to-digital converters, and the filtering and extraction module is used to sequentially receive the first signals output by each of the analog-to-digital converters after sampling according to their respective clock phases; and filter and extract each received first signal.

[0012] According to the above solution, the volume of the broadband digital system can be reduced and the accuracy of trigger judgment can be ensured.

[0013] Furthermore, the preset de-embedding filter has a plurality of compensation coefficients corresponding to a plurality of frequencies respectively.

[0014] According to the above solution, multiple frequencies can be effectively de-embedded using compensation coefficients corresponding to the multiple frequencies.

[0015] Furthermore, the filtering and extraction module is used to perform M-fold filtering and extraction on at least part of the first signal; wherein M is an integer greater than or equal to 2.

[0016] According to the above solution, the volume and power consumption of the broadband digital trigger system can be further reduced.

[0017] Furthermore, the filtering and extraction module is used to perform M-fold filtering and extraction on at least part of the first signal through a low-pass filter, and the cutoff frequency of the low-pass filter is related to the first sampling rate corresponding to the filtered and extracted signal.

[0018] According to the above solution, a low-pass filter is used to implement M-fold filtering and decimation, which can simplify the implementation of filtering and decimation.

[0019] In combination with the first aspect, in certain embodiments of the first aspect, it further includes a sampling module, a storage module and a display module; wherein the sampling module is used to collect each first signal; and in response to the trigger judgment module outputting a trigger instruction, the first signals collected in this cycle are stored in the storage module; wherein each first signal has its own corresponding phase; the display module is used to extract each first signal from the storage module according to the phase, integrate each first signal, and calibrate and output it as a display signal.

[0020] According to the above solution, the detected signal that meets the trigger condition can be displayed.

[0021] In combination with the first aspect, in some embodiments of the first aspect, the extraction and de-embedding module is implemented based on a digital processing device.

[0022] According to the above solution, the extraction and de-embedding modules are implemented by digital processing devices, which can realize high-precision detection of high-speed signals.

[0023] In a second aspect, an embodiment of the present disclosure provides a broadband digital triggering method for use in the broadband digital triggering system of the first aspect, the method comprising: performing time-interleaved sampling on a measured signal to obtain multiple first signals; filtering and extracting at least a portion of the first signals to obtain a filtered and extracted signal, and de-embedding the filtered and extracted signal to obtain a second signal; filtering and interpolating the second signal to obtain a third signal; determining whether a trigger condition is met based on the third signal, and issuing a trigger instruction in response to the trigger condition being met.

[0024] According to the above scheme, at least part of the first signal output by the multi-channel analog-to-digital converter is filtered and extracted, and the filtered and extracted signal is compensated, which reduces the amount of data for compensation processing, can reduce the scale of the digital circuit for compensating the signal, and further reduce the volume and power consumption of the broadband digital trigger system.

[0025] In conjunction with the second aspect, in some embodiments of the second aspect, filtering and extracting at least a portion of the first signal to obtain a filtered and extracted signal includes:

[0026] filtering at least a portion of the first signal;

[0027] Extract at least a portion of the first signal after filtering to obtain the filtered and extracted signal.

[0028] According to the above solution, filtering is performed before decimation to avoid aliasing during the decimation process.

[0029] In conjunction with the second aspect, in certain implementations of the second aspect, de-embedding the filtered and extracted signal to obtain the second signal includes:

[0030] De-embedding the filtered and decimated signal using a preset de-embedding filter.

[0031] According to the above scheme, de-embedding can be used to compensate for the influence of the frequency response of the broadband digital trigger system on the measured signal, and the influence of the external environment on the measured signal can also be compensated, thereby obtaining an accurate second signal, which helps to improve the accuracy of trigger judgment.

[0032] In conjunction with the second aspect, in certain embodiments of the second aspect, the method further includes:

[0033] Collecting each first signal; and storing each first signal collected in this cycle in a storage module in response to a trigger instruction; wherein each first signal has its own corresponding phase;

[0034] The first signals of various channels are extracted from the storage module according to the phase, and the first signals of various channels are integrated, calibrated and output as display signals.

[0035] According to the above solution, a measured signal that meets the trigger condition can be presented.

[0036] In a third aspect, an embodiment of the present disclosure provides an electronic device comprising the broadband digital trigger system of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0038] Figure 1 A schematic diagram of trigger signal and display signal;

[0039] Figure 2 A schematic diagram of the digital trigger system provided as an example;

[0040] Figure 3 A schematic diagram of the structure of the broadband digital trigger system provided in the embodiment of the present disclosure Figure 1 ;

[0041] Figure 4 A schematic diagram of the structure of the broadband digital trigger system provided in the embodiment of the present disclosure Figure 2 ;

[0042] Figure 5 A schematic diagram of the structure of the broadband digital trigger system provided in the embodiment of the present disclosure Figure 3 ;

[0043] Figure 6 A schematic flow chart of a broadband digital triggering method provided in an embodiment of the present disclosure.

[0044] Description of reference numerals:

[0045] 201-analog front end; 202-analog-to-digital conversion module; 203-de-embedding module; 204-trigger judgment module; 205-sampling module; 206-storage module;

[0046] 301-analog front end; 302-interleaved analog-to-digital conversion module; 303-extraction and de-embedding module; 304-filtering and interpolation module; 305-trigger judgment module; 306-sampling module; 307-storage module; 308-display module; 3031-filtering and extraction module; 3032-de-embedding module. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present disclosure will be described below with reference to the accompanying drawings in the embodiments of the present disclosure.

[0048] In signal measurement equipment (such as an oscilloscope), when the sweep signal is synchronized with the voltage changes of the measured signal, the trigger function of the signal measurement device can capture and display the waveform of the measured signal changing over time. The trigger function is implemented by the trigger link.

[0049] However, after the measured signal is input into the signal measurement device, the trigger chain of the signal measurement device will affect the measured signal, so there will usually be a difference between the trigger signal and the measured signal. The trigger signal here refers to the measured signal that has not been compensated in the trigger chain.

[0050] Please refer to Figure 1 , Figure 1 A schematic diagram of a trigger signal and a display signal. Figure 1 Let's take the pulse width trigger mode as an example. The pulse width trigger mode refers to triggering on a positive pulse or negative pulse of a specified width. In the pulse width trigger mode, a pulse width with certain conditions is set. When the pulse width of the input signal meets the conditions, the signal measurement device will trigger. In the signal measurement device, the time difference between the two points where the trigger level intersects the positive pulse is defined as the positive pulse width, and the time difference between the two points where the trigger level intersects the negative pulse is defined as the negative pulse width. Due to the distortion of the trigger signal generated by the trigger link, there is a difference between the trigger signal and the signal being measured by the oscilloscope. For example Figure 1 As shown in the figure, the solid line is the waveform of the measured signal, and the dotted line is the waveform of the trigger signal after the measured signal passes through the trigger link. The trigger pulse width in the trigger signal is different from the actual pulse width of the measured signal, and there is a difference between the pulse width of the trigger signal and the pulse width of the measured signal. As the trigger level deviates from the center of the signal, the difference between the pulse width of the pulse signal and the measured signal increases, as shown in the figure. Figure 1 The difference between trigger pulse width 2 and actual pulse width 2 is greater than the difference between trigger pulse width 1 and actual pulse width 1. Due to the difference between the pulse width of the measured signal and the pulse width of the trigger signal, the accuracy of the trigger function is reduced.

[0051] Therefore, the trigger signal needs to be compensated before trigger judgment. In order to improve the accuracy of trigger compensation and reduce the cost of trigger compensation, a digital architecture can be used to implement the compensation of the trigger signal.

[0052] In one example, the digital trigger system includes an analog front end, an analog-to-digital conversion module, a de-embedding module, an acquisition module, a trigger judgment module, a sampling module, and a storage module. Figure 2 , Figure 2 This is a structural diagram of a digital trigger system. Figure 2As shown, in this digital trigger system, an analog front end 201 inputs a test signal. This signal is then transmitted to an analog-to-digital conversion module 202, which samples and quantizes the output signal from the analog front end 201 to generate a digital sequence. This digital sequence is then input to a de-embedding module 203, which (implemented by digital circuitry) compensates the digital sequence. Compensation includes amplitude and phase compensation, echo compensation, and equalization. The output signal of the de-embedding module 203 is input to a trigger determination module 204. Simultaneously, a sampling module 205 collects the output signal of the de-embedding module 203. The trigger determination module 204 determines the trigger condition of the output signal of the de-embedding module 203. If the signal meets the trigger condition, the sampling module collects the output signal of the de-embedding module 203 and stores it in a storage module 206. The signal in storage module 206 can be displayed.

[0053] In this example, the digital circuit scale of the de-embedding module 203 increases with the increase of the sampling rate. If the sampling rate doubles, the digital circuit scale of the de-embedding module 203 will increase to 4 times the original scale. In ultra-high-speed signal measurement equipment that needs to capture and display the waveform of high-frequency signals, since the sampling rate of ultra-high-speed signal measurement equipment is very high (billions of samples per second), according to Figure 2 In the illustrated solution, the circuitry in de-embedding module 203 is large and consumes high power. Furthermore, this solution requires that full-sampling-rate data be aggregated to the de-embedding module in a very short time. However, ultra-high-speed signal measurement equipment typically uses multiple analog-to-digital converters to interleave the measured signal, making it difficult to aggregate full-sampling-rate data in a short time.

[0054] Therefore, the above-mentioned digital trigger system has the problems of large circuit scale and high power consumption.

[0055] In the solution provided by the present disclosure, an analog front end receives a measured signal, an interleaved analog-to-digital conversion module performs interleaved sampling on the output signal of the analog front end to obtain multiple first signals, an extraction and de-embedding module filters and extracts at least a portion of the first signals to obtain a filtered and extracted signal, the filtered and extracted signal is de-embedded to obtain a second signal, and a filter interpolation module filters and interpolates the second signal to obtain three signals. A trigger determination module determines whether a trigger condition is satisfied based on the third signal and issues a trigger instruction in response to the satisfaction of the trigger condition. Therefore, in the trigger chain, some of the multiple first signals can be used for filtering, extraction, and de-embedding (i.e., compensation), which can reduce the amount of data requiring de-embedding and, accordingly, the scale of the digital circuitry in the de-embedding module. This can further reduce the scale of the broadband digital trigger system, reduce the space used by the broadband digital trigger system, help reduce the size of the signal measurement device, and reduce the power consumption of the signal measurement device.

[0056] Please refer to Figure 3 , Figure 3 The structure of the broadband digital trigger system provided by this disclosure is shown as follows: Figure 1 ,like Figure 3 As shown, the broadband digital trigger system includes:

[0057] The analog front end 301 is used to receive the signal under test;

[0058] An interleaved analog-to-digital conversion module 302 includes a plurality of analog-to-digital converters, wherein the plurality of analog-to-digital converters are configured to perform interleaved sampling on the output signal of the analog front end to obtain a plurality of first signals;

[0059] an extraction and de-embedding module 303 configured to filter and extract at least a portion of the first signal to obtain a filtered and extracted signal, and de-embed the filtered and extracted signal to obtain a second signal;

[0060] The filtering and interpolation module 304 is configured to perform filtering and interpolation on the second signal to obtain a third signal.

[0061] The trigger judgment module 305 is configured to determine whether a trigger condition is satisfied according to the third signal, and issue a trigger instruction in response to the trigger condition being satisfied.

[0062] In this embodiment, the analog front end 301 can be connected to the component under test and receive the test signal generated by the component under test. The component under test here can be a component in various devices, such as a component in a communication device. The above-mentioned test signal can be a high-speed signal.

[0063] Measuring high-speed signals requires both a high sampling rate and high sampling accuracy. A high sampling rate generally requires a wider bandwidth for the signal measurement device. The bandwidth of a signal measurement device (measured in Hertz (Hz)) is the range of signal frequencies that the device can accurately display. For example, a bandwidth of 500 MHz means the device can accurately display signals with frequencies up to 500 MHz.

[0064] The signal input of interleaved analog-to-digital conversion module 302 is connected to the analog front end. Interleaved analog-to-digital conversion module 302 may include multiple analog-to-digital converters, such as analog-to-digital converter 1, analog-to-digital converter 2, ..., and analog-to-digital converter N. Each analog-to-digital converter forms a channel. These multiple analog-to-digital converters may actually be multiple independent analog-to-digital converters. Alternatively, they may be a multi-channel analog-to-digital converter comprising multiple channels, each of which has an analog-to-digital conversion circuit to perform analog-to-digital conversion.

[0065] The multiple analog-to-digital converters in the interleaved analog-to-digital conversion module 302 respectively sample and quantize the output signal of the analog front end 301 to obtain multiple first signals. Interleaved sampling of the signal by multiple analog-to-digital converters refers to a sampling format in which the multiple analog-to-digital converters use the same sampling rate for sampling, but the sampling times of two adjacent analog-to-digital converters are staggered in the time domain. The multiple analog-to-digital converters in the interleaved analog-to-digital conversion module 302 each have a fixed clock phase. The multiple analog-to-digital converters synchronously sample the measured signal according to their respective clock phases, and each analog-to-digital converter can output one first signal, thereby obtaining multiple first signals. There is a fixed clock phase difference between the multiple first signals.

[0066] The clock phase of the nth ADC can be determined by the following formula:

[0067]

[0068] Wherein, N is the total number of analog-to-digital converters in the interleaved analog-to-digital conversion module 302 .

[0069] For example, if the interleaved analog-to-digital conversion module 302 includes four analog-to-digital converters, the interleaved analog-to-digital conversion module samples the measured signal, and the clock phase difference between the first signals of each adjacent analog-to-digital converter is fixed at π / 2. The clock phase corresponding to the first analog-to-digital converter is 0, the clock phase corresponding to the second analog-to-digital converter is π / 2, the clock phase corresponding to the third analog-to-digital converter is π, and the clock phase corresponding to the fourth analog-to-digital converter is 3π / 2.

[0070] By using multiple ADCs to perform interleaved sampling of the measured signal, the sampling rate of each ADC can be reduced, provided the total sampling rate requirement is fixed. By using multiple ADCs and performing interleaved sampling, the bandwidth requirements of each ADC can be reduced while maintaining a high sampling rate (also known as sampling frequency) for the output signal of the analog front end 301.

[0071] For a bandwidth of f s For a broadband digital trigger system, if the interleaved analog-to-digital conversion module 302 has N analog-to-digital converters, the sampling rate of the first signal obtained by each analog converter sampling the measured signal is f s / N. Since multiple analog-to-digital converters have their own clock phases, the bandwidth of the broadband digital trigger system f s It is divided into N parts. The bandwidth of each part is f s / N. The first signals outputted by the multiple analog-to-digital converters can be combined into a pair of measured signals according to the sampling rate of f according to their respective corresponding clock phases. s The signal sequence obtained by sampling.

[0072] For multiple first signals obtained by interleaving the measured signal through multiple analog-to-digital converters, the spectrum of each first signal will be aliased. For example, if the number of analog-to-digital converters is N, assuming that the maximum sampling rate of the broadband digital trigger system is f s , then the sampling rate of each analog-to-digital converter is f s / N. The Nyquist bandwidth of each analog-to-digital converter is The spectrum of the first signal is mixed with the mirror frequency point, and the mirror frequency point of the first signal can be .

[0073] The extraction and de-embedding module 303 may perform filtering and extraction on at least a portion of the first signal to obtain a filtered and extracted signal, and de-embed the filtered and extracted signal to obtain a second signal.

[0074] The at least part of the first signal here may be one first signal, two first signals, or multiple first signals; it may also be a part of any one or multiple first signals, etc.

[0075] The extraction and de-embedding module 303 can filter at least a portion of the first signal. The filtering can be performed using a low-pass filter with a preset cutoff frequency to filter and extract at least a portion of the first signal. For example, at least a portion of the first signal can be filtered and extracted M times. Illustratively, at least a portion of the first signal can be filtered and extracted M times using a low-pass filter to obtain a filtered and extracted signal at the first sampling rate. The cutoff frequency of the low-pass filter is related to the first sampling rate.

[0076] For example, the cutoff frequency is half of the first sampling rate. The cutoff frequency of the low-pass filter can be set according to specific application scenarios.

[0077] If the sampling rate of the first signal is f p , the sampling rate of the signal after M-fold filtering is f p / M. The cutoff frequency of the low-pass filter is .

[0078] Performing M-fold filtering and decimation on at least a portion of the first signal can be considered downsampling the filtered first signal. The amount of signal data obtained after the M-fold filtering and decimation is 1 / M of the amount of data obtained from the first signal without the M-fold filtering and decimation. M is an integer greater than or equal to 2.

[0079] In some embodiments, M may be related to the sampling rate of the first signal and the sampling rate of the filtered and decimated signal, for example, to the ratio of the sampling rate of the filtered and decimated signal to the sampling rate of the first signal.

[0080] The filtered and extracted signal can be de-embedded (i.e., compensated) to obtain a second signal. The frequency response (FRE) of the broadband digital trigger system and other external signals can affect the filtered and extracted signal, causing distortion and affecting the accuracy of the analog front-end output signal sampling results. To improve the accuracy of the output signal sampling results, a preset de-embedding filter can be used to de-embed the filtered and extracted signal.

[0081] As an implementation manner, the preset de-embedding filter has multiple compensation coefficients corresponding to multiple frequencies.

[0082] Schematically, each frequency may correspond to a compensation coefficient.

[0083] Specifically, distortion information caused by the broadband digital trigger system and external signals can be pre-measured, and compensation coefficients at different frequencies can be determined based on this distortion information. De-embedding filters can be created based on the compensation coefficients at different frequencies. In this pre-set de-embedding filter, for each of the multiple frequencies, the filtered and extracted signal is de-embedded based on the compensation coefficient corresponding to that frequency.

[0084] In some implementations, the decimation and de-embedding module 303 may be implemented based on digital processing devices.

[0085] Specifically, the extraction and de-embedding module 303 may be implemented by one or more of the following digital processing devices: a Field Programmable Gate Array (FPGA), an Application-Specific Integrated Circuit (ASIC), or a Digital Signal Processor (DSP).

[0086] Because at least a portion of the first signal is filtered and extracted before de-embedding, the amount of data that needs to be de-embedded (compensated) in the trigger chain is reduced, and the digital circuit scale of the de-embedding module in the trigger chain can be reduced. This helps reduce the size and power consumption of the wideband digital trigger system.

[0087] The filtering and interpolation module 304 is connected to the extraction and de-embedding module 303 and receives the second signal output by the extraction and de-embedding module 303. The filtering and interpolation module 304 can perform filtering and interpolation on the second signal input thereto and output a third signal.

[0088] The filtering and interpolation module 304 performs K-fold filtering and interpolation on the second signal output by the extraction and de-embedding module 303 , where K is any value greater than 0. The K-fold filtering and interpolation inserts a 0 every (K-1) values in the time domain.

[0089] Specifically, a filter can be set to perform K-fold filtering and interpolation. This filter inserts a zero every (K-1) values. Directly inserting zeros will create a mirror image in the spectrum. For example, a signal with a bandwidth of f / 2 will become a signal with a bandwidth of f.

[0090] Let's use 2x interpolation as an example. We perform 2x interpolation on the second signal, adding a zero to every other data point in the time domain. Assume that the sampling rate of the second signal before interpolation is f0, and f0 / 2 is the Nyquist frequency of the second signal. After 2x interpolation, the sampling rate is increased to 2f0. The signal at f0 / 4 remains essentially unchanged. Interpolation generates a signal 3f0 / 4 symmetrical about f0 / 2 at f0 / 4. Signals outside f0 / 2 are then filtered out, but the signal at f0 / 2 remains. This results in a sampling rate of 2f0, but the signal remains at f0 / 4, increasing resolution without affecting the signal itself.

[0091] By performing K-fold filtering and interpolation, the sampling rate of the third signal can be increased. For example, the sampling rate of the third signal can be greater than the sampling rate of the interleaved analog-to-digital conversion module. Therefore, using the high-sampling-rate third signal for triggering can improve the time precision of the triggering judgment, thereby improving the accuracy of the triggering judgment.

[0092] The trigger determination module 305 may compare the third signal with one or more preset levels, and determine whether a trigger condition is met based on the comparison result. If the trigger condition is met, scanning is started.

[0093] In this embodiment, filtering, extracting, and de-embedding at least a portion of the first signals output by the multi-channel analog-to-digital converter to obtain a second signal, and performing triggering judgment based on the de-embedded signal can reduce the amount of data requiring de-embedding processing, reduce the scale of the digital circuitry for signal compensation, and thereby reduce the size of the broadband digital trigger system. The power consumption of the broadband digital trigger system can also be reduced.

[0094] In some embodiments, the decimation compensation module includes a filtering decimation module 3031 and a de-embedding module 3032.

[0095] The signal input terminal of the filtering and extraction module 3031 is connected to the output terminal of at least one analog-to-digital converter among the multiple analog-to-digital converters. The filtering and extraction module is configured to receive at least a portion of the first signal output by the at least one analog-to-digital converter through the signal input terminal, and filter and extract at least a portion of the first signal to obtain a filtered and extracted signal.

[0096] The de-embedding module 3032 is configured to receive the filtered and extracted signal and de-embed the filtered and extracted signal using a preset de-embedding filter to obtain a second signal. In one example, the de-embedding module 3032 de-embeds the filtered and extracted signal using a filter having compensation coefficients corresponding to multiple frequencies to obtain the second signal.

[0097] It is understandable that the compensation coefficients corresponding to different frequencies can be set according to specific application scenarios.

[0098] In this example, a preset de-embedding filter having compensation coefficients corresponding to multiple frequencies is used to filter the second signal (to perform de-embedding), which can complete compensation of signals of different frequencies at one time, thus simplifying the complexity of the de-embedding module.

[0099] In this embodiment, a filtering extraction module is used to filter and extract at least part of the first signal, and a de-embedding module is used to de-embed the filtered and extracted signal. The filtering extraction and de-embedding are modularized, and the circuit of each module can be designed separately, which is conducive to simplifying the overall circuit design complexity.

[0100] In some embodiments, the filtering and decimation module is configured to perform M-fold filtering and decimation on at least a portion of the first signal, where M is an integer greater than or equal to 2.

[0101] In these embodiments, at least a portion of the first signal may be filtered and then decimated, for example, by an M-fold decimation. Decimating at least a portion of the first signal by an M-fold means extracting and retaining one data point every (M-1) data points in the digital sequence corresponding to at least a portion of the first signal. The above decimation process can produce a signal that has been filtered and decimated by an M-fold decimation.

[0102] As an implementation, the filtering and decimation module is configured to perform M-fold filtering and decimation on at least a portion of the first signal using a low-pass filter. The low-pass filter can be implemented using a software algorithm or dedicated digital hardware. Software algorithms such as finite impulse response (FIR) or infinite impulse response (IIR) filters can calculate the output value of each sampling point to remove high-frequency noise. Digital hardware, on the other hand, may utilize a lookup table or application-specific integrated circuits (ASICs) to achieve fast signal processing.

[0103] The low-pass filter may include one or more low-pass filters.

[0104] By filtering and decimating at least a portion of the first signal, the amount of data in the resulting signal after decimation is 1 / M of the amount of data in the at least portion of the first signal before decimation. In other words, the amount of data entering the de-embedding module is 1 / M of the amount of data in the at least portion of the first signal before decimation. This reduces the size of the digital circuitry required for de-embedding.

[0105] In some embodiments, the signal input end of the filtering and extraction module is connected to the output end of the two channel analog-to-digital converters, and the filtering and extraction module is used to receive the first signals respectively output by the two channel analog-to-digital converters and filter and extract the first signals respectively output by the two channel analog-to-digital converters according to their respective timings.

[0106] In these embodiments, the first signals output by two analog-to-digital converters can be selected from the multiple analog-to-digital converters of the interleaved analog-to-digital conversion module to perform triggering judgment. s In a multi-channel analog-to-digital converter with a capacity of 1 / N, the first signals outputted by two analog-to-digital converters are selected and inputted into the filter extraction module in sequence. After the first signals outputted by the two analog-to-digital converters are inputted into the filter in sequence, the sampling rate of the signal inputted into the filter is equivalent to 2f s / N.

[0107] The following description assumes that N is 4 and M is 2. Figure 4 , Figure 4 A schematic diagram of the structure of the broadband digital trigger system provided in the embodiment of the present disclosure Figure 2 .like Figure 4 As shown, the interleaved analog-to-digital conversion module includes four analog-to-digital converters. The first signal output by analog-to-digital converter 1 and the third signal output by analog-to-digital converter 3 are input into the extraction and de-embedding module 303. The extraction and de-embedding module 303 may include a filtering extraction module 3031 and a de-embedding module 3032. The filtering extraction module 3031 can implement 2x filtering extraction. The de-embedding module can de-embed the 2 filtered and extracted signals to obtain a second signal. The extraction and de-embedding module 303 outputs the second signal, and the filtering interpolation module 304 performs K-fold filtering and interpolation on the second signal to obtain a third signal, which is then output to the trigger determination module 305.

[0108] The measured signal passes through 4 analog-to-digital converters (such as Figure 4 After time-sharing sampling by analog-to-digital converter 1, analog-to-digital converter 2, analog-to-digital converter 3 and analog-to-digital converter 4, four first signals with inconsistent phases are obtained.

[0109] The sampling rate of each first signal is f s / 4, here f s is the sampling rate of the broadband digital trigger system. The Nyquist bandwidth of each first signal is f s / 8, that is, the mirror frequency points of each first signal are f s Because each first signal corresponds to its own phase, the four first signals divide the bandwidth of the broadband digital trigger system into four equal parts.

[0110] In this embodiment, the hardware frequency response of the broadband digital trigger system is from a specific frequency point to the Nyquist bandwidth (f s / 2,f s The attenuation of the hardware frequency response is large (over 60%) within the attenuation range (maximum sampling rate of the broadband digital trigger system). The number of analog-to-digital converters and the characteristics of the analog-to-digital converters in the broadband digital trigger system can be designed so that one or more repetitive cycles in the frequency response of each analog-to-digital converter fall within this attenuation range. Since the analog-to-digital converter undersamples the measured signal, signal spectrum aliasing will occur. It may be a mirror-symmetrical point, and the frequency spectrum of the first signal may be aliased about the mirror-symmetrical point.

[0111] The spectrum of the first signal in the above attenuation range is aliased to 0~ Since the hardware frequency response of the broadband digital trigger system is greatly attenuated in this attenuation range, the spectrum in the above attenuation range is different from 0~ When the spectra within the interval are mixed together, the effect of the hardware frequency response of this attenuation interval on the signal can be ignored.

[0112] To reduce the amount of data aggregated within a short period of time in the trigger judgment link, in this embodiment, two first signals can be extracted from all first signals for trigger judgment. For example, if the interleaved analog-to-digital conversion module includes four analog-to-digital converters, the first signals output by two of the four analog-to-digital converters can be extracted for trigger judgment.

[0113] In this embodiment, the first signals outputted by the two analog-to-digital converters are sequentially inputted into the filtering and extraction module 3031 according to the order of their respective clock phases. The filtering and extraction module 3031 performs filtering and extraction on the signals inputted thereto. Assuming that the sampling rate of the first signal before being inputted into the filtering and extraction module 3031 is f s / N, the two first signals are input to the filter extraction module in their respective orders, and the sampling rate of the signal input to the filter extraction module 3031 is equivalent to .

[0114] The spectrum of the first signal output by each of the two analog-to-digital converters can overlap with its own mirror-symmetric point, where the mirror-symmetric point can be, for example, the Nyquist frequency point of the first signal. Similarly, the sampling rate of the signal input to the filter extraction module is The signal received by the filter extraction module 3031 is also about its own mirror symmetric point f s / N are symmetrical and overlapping.

[0115] The filtering and extraction module 3031 may include a low-pass filter. In the filtering and extraction module 3031, at least a portion of the first signal input thereto is filtered and extracted M times by the low-pass filter. The cutoff frequency of the low-pass filter may be related to the first sampling rate corresponding to the filtered and extracted signal. For example, the cutoff frequency is half the first sampling rate corresponding to the filtered and extracted signal.

[0116] For example, you can choose the first signal of the first channel (sampling rate is f s / 4) and the third channel first signal (sampling rate is f s / 4) are sequentially sent to the 2x filter extraction module 3031 according to their respective clock phases. The sampling rate of the signal received by the filter extraction module 3031 is regarded as f s / 2.

[0117] If the interleaved analog-to-digital conversion module 302 includes four analog-to-digital converters, and the system sampling rate of the interleaved analog-to-digital conversion module is f s , the first signals corresponding to two of the four analog-to-digital converters are input into the filtering and extraction module, and a 2x filtering and extraction is performed. The first sampling rate of the signal after filtering and extraction is f s / 4. The spectrum of the second first signal and the fourth first signal without filtering extraction is between 0 and f s / 4 and f s / 4~f s / 2 corresponds to aliasing. After the above 2 times filtering, f s / 8~3f s / 8 signal. Then use 3f s / 8~f s The frequency response of the system hardware with a frequency response of / 2 is greatly attenuated due to the characteristics of the signal itself. The signal after 2 times filtering and extraction can be regarded as non-aliasing, that is, only the 0~f s / 8 this frequency range.

[0118] In this way, the amount of data entering the de-embedding module 3032 is reduced to half of the amount of data entering the de-embedding module 3032 at the full sampling rate; at the same time, the double decimation filter is used to implement anti-aliasing filtering, which reduces the number of filtering decimations and can reduce the circuit scale, thereby helping to reduce the size of the broadband digital trigger system and reduce the power consumption of the broadband digital system. Since the sampling rate of the signal to be de-embedded is f s / 2, the circuit scale corresponding to the real-time de-embedding module can also be reduced to 1 / 16 of the circuit scale for de-embedding full sampling rate data, thereby reducing the circuit scale of the broadband digital trigger system, reducing the volume of the digital broadband digital trigger system, and also helping to reduce power consumption.

[0119] In some embodiments, the signal input end of the filtering and extraction module is connected to the output end of each analog-to-digital converter, and the filtering and extraction module is used to sequentially receive the first signals output by each analog-to-digital converter after sampling according to its own clock phase; and filter and extract each received first signal.

[0120] If the interleaved analog-to-digital conversion module includes N analog-to-digital converters, the N analog-to-digital converters sample the output signal of the analog front end according to their respective clock phases, and each outputs a first signal. That is, each first signal has its own corresponding clock phase. Each first signal is input to the filtering and extraction module 3031 according to its own clock phase. The filtering and extraction module 3031 can receive each first signal. Since the filtering and extraction module 3031 receives each first signal, each first signal has its own clock phase. The sampling rate of the first signal received by the filtering and extraction module 3031 can be the same as the sampling rate f corresponding to the interleaved analog-to-digital conversion module. s same.

[0121] The sampling rate of each first signal is f s / N, the Nyquist frequency corresponding to each first signal is The N first signals are input to the filter extraction module 3031 according to their respective clock phases. The corresponding sampling rate of the signal input to the filter extraction module 3031 is f s . In order to prevent aliasing, the input signal can be filtered and extracted in the filter extraction module first, for example, M-fold filtering and extraction can be performed to obtain the filtered and extracted signal. The above-mentioned M-fold filtering and extraction of the signal input to the filter module can be implemented by one or more low-pass filters. For example, a 3-fold filtering and extraction low-pass filter and a 2-fold filtering and extraction low-pass filter can be used to implement 6-fold filtering and extraction of the above-mentioned signal. After the above-mentioned filtering and extraction, the signal between.

[0122] The amount of data of the signal after M-fold filtering and extraction is 1 / M of the amount of the signal input to the filtering and extraction module. Therefore, the amount of data that needs to be processed by the de-embedding module 3032 is the amount of data of the measured signal with a sampling rate of f. s The sampling rate of the signal after filtering and extraction can be regarded as f s / M. The scale of the compensation circuit in the de-embedding module 3032 is the original The de-embedding module 3032 may de-embed the signal after the M-fold filtering and decimation to obtain a second signal.

[0123] The following description assumes that N is 4 and M is 4. Please refer to Figure 5 , Figure 5 A schematic diagram of the structure of the broadband digital trigger system provided in the embodiment of the present disclosure Figure 3 Compared to Figure 3 Interleaved analog-to-digital conversion module 302 includes four analog-to-digital converters (ADC 1, ADC 2, ADC 3, and ADC 4). ADC 1 outputs a first first signal, ADC 2 outputs a second first signal, ADC 3 outputs a third first signal, and ADC 4 outputs a fourth first signal. These four first signals are all input into decimation and de-embedding module 303. Decimation and de-embedding module 303 includes a filtering and decimation module 3031 and a de-embedding module 3032. Filtering and decimation module 3031 can be a 4x filtering and decimation module.

[0124] The output signal of the analog front end 301 is sampled by the four analog-to-digital converters to obtain the first signal with four clock phase inconsistencies. s , the sampling rate of each first signal is f s / 4. The 4-way first signal is input to the filter extraction module. For the 4-fold filter extraction module, the received signal is equivalent to sampling the measured signal at a rate of f s To avoid aliasing during 4x decimation, the signal input to the filter extraction module can be filtered with a cutoff frequency of f. s / 8 low-pass filter, filter out f s / 8~f s / 2 frequency band signal. Then the filtered signal is decimated by 4 times. The first sampling rate of the signal after decimation by 4 can be regarded as f s / 4.

[0125] After decimation by 4, the amount of data entering the de-embedding module is equivalent to that using the sampling rate f sThe signal under test is sampled to obtain 1 / 4 of the data volume. The signal obtained after decimation by 4 is then de-embedded.

[0126] Since the amount of data processed by the de-embedding module is equivalent to 1 / 4 of the full sampling rate data volume, the circuit scale of the de-embedding module can be 1 / 16 of the circuit scale of the de-embedding module required to process the full sampling rate data. Therefore, the scale of the de-embedding module circuit can be reduced, which helps to reduce the size of the broadband digital trigger system and also reduces the power consumption of the broadband digital trigger system.

[0127] In one embodiment, N is 4 and M is 2. Figure 5 The interleaved analog-to-digital conversion module 302 includes four analog-to-digital converters. The first signal output by analog-to-digital converter 1, the second signal output by analog-to-digital converter 2, the third signal output by analog-to-digital converter 3, and the fourth signal output by analog-to-digital converter 4 can be input into the 2x filtering and extraction module.

[0128] The output signal of the analog front end is sampled by four analog-to-digital converters and the first signal with inconsistent clock phases is obtained. s For the interleaved analog-to-digital conversion module, the sampling rate of each first signal is f s / 4. For the 2x filter extraction module, the received signal is equivalent to sampling the signal output by the analog front end at a rate of f s To avoid aliasing during decimation by 2, the first signal after the combination can be subjected to a cutoff frequency of f. s / 4 low-pass filter, filter out f s / 4~f s / 2 frequency band signal. Then the filtered signal is decimated by 2 times. The first sampling rate of the signal after decimation by 2 can be regarded as f s / 2.

[0129] After 2x filtering and extraction, the amount of data entering the de-embedding module is equivalent to the sampling rate f s The signal obtained by sampling the measured signal is 1 / 2 of the data volume. The signal obtained after decimation by 2 is de-embedded.

[0130] Since the amount of data processed by the de-embedding module is equivalent to 1 / 2 of the full sampling rate data, the circuit scale corresponding to the de-embedding module can be 1 / 4 of the circuit scale required to process the full sampling rate data. Therefore, the scale of the de-embedding module circuit can be reduced, which is conducive to reducing the volume of the broadband digital trigger system and reducing power consumption.

[0131] In some embodiments, the broadband digital trigger system further includes a sampling module 306, a storage module 307, and a display module 308; wherein the sampling module 306 is configured to collect each first signal; and in response to the trigger judgment module 305 outputting a trigger instruction, the sampling module 306 stores each first signal collected in the current cycle in the storage module 307; wherein each first signal has its own corresponding clock phase;

[0132] The display module 308 is used to extract the first signals from the storage module 307 according to their phases, integrate the first signals, calibrate them and output them as display signals. For example, the integration of the first signals can be done by sorting the first signals according to their respective clock phases.

[0133] When the trigger determination module 305 issues a trigger instruction, scanning can be initiated. The scanning signal is synchronized with the measured signal. Therefore, the first signal sampled in the current cycle is stored in the storage module 307 by the sampling module 306, and then displayed by the display module 308. It is understood that the display module 308 can de-embed (also known as calibrate or compensate) the signal stored in the storage module 307 before displaying it.

[0134] The broadband digital triggering system provided by the present disclosure is described above with reference to the accompanying drawings. The following accompanying drawings illustrate the broadband digital triggering method provided by the present disclosure. The broadband digital triggering system described above can implement the broadband digital triggering method provided by the present disclosure. Features described in the following method embodiments and features described in the above broadband digital triggering system embodiments can be cross-referenced.

[0135] Please refer to Figure 6 , Figure 6 A schematic flow chart of a broadband digital triggering method provided by an embodiment of the present disclosure is shown in FIG. Figure 6 As shown, the method includes the following steps:

[0136] S601: Perform time-interleaved sampling on the measured signal to obtain multiple first signals.

[0137] In this embodiment, the broadband digital triggering method can be used in signal measurement equipment (e.g., an oscilloscope). In the signal measurement equipment, an analog front end can be used to contact a component under test to obtain a signal passing through the component under test. The signal passing through the component can be the measured signal. The component can be a component in various devices, such as a communication device. The measured signal can be a high-speed signal.

[0138] Multiple analog-to-digital converters in an interleaved analog-to-digital conversion module can be used to perform time-interleaved sampling on the output signal of the analog front end. The multiple analog-to-digital converters in the interleaved analog-to-digital conversion module each have a fixed clock phase. The multiple analog-to-digital converters with fixed clock phases synchronously sample the output signal of the analog front end to obtain multiple first signals. Using multiple analog-to-digital converters to perform interleaved sampling on the output signal of the analog front end can reduce the sampling rate of each analog-to-digital converter while maintaining a high sampling rate for the interleaved analog-to-digital conversion module.

[0139] For a bandwidth of f s For a broadband digital trigger system, if the broadband digital trigger system has N analog-to-digital converters, the sampling rate of the first signal sampled by each channel is f s / N, since multiple analog-to-digital converters have their own clock phases, the sampling rate of the broadband digital trigger system bandwidth is f s It is divided into N parts. The bandwidth of each part is f s / N.

[0140] S602: Filter and extract at least a portion of the first signal to obtain a filtered and extracted signal, and de-embed the filtered and extracted signal to obtain a second signal.

[0141] In some implementations, filtering and extracting at least a portion of the first signal includes the following steps:

[0142] First, filtering at least a portion of the first signal;

[0143] Next, at least a portion of the filtered first signal is extracted to obtain a filtered and extracted signal.

[0144] In some embodiments, a low-pass filter may be used to filter at least a portion of the first signal, and the cutoff frequency of the low-pass filter may be related to the first sampling rate corresponding to the filtered and extracted signal.

[0145] For example, the cutoff frequency may be half of the first sampling rate of the signal after filtering and extraction.

[0146] Since at least a portion of the first signal is filtered using a low-pass filter, a filtered at least portion of the first signal is obtained. Decimation is performed on the filtered at least portion of the first signal one or more times to achieve M-fold filtering and decimation of the at least portion of the first signal. In these embodiments, filtering before decimation can avoid aliasing during the decimation process.

[0147] In some implementations, two first signals among the multiple first signals may be combined according to their respective corresponding clock phases to be filtered and extracted, and then the filtered and extracted signals may be de-embedded to obtain the second signal.

[0148] In these embodiments, multiple first signals can be selected and combined to obtain 2f s Taking four first signals as an example, the first signal and the third signal can be selected and combined according to their respective clock phases to perform filtering and extraction.

[0149] In one example, a low-pass filter with a preset cutoff frequency can be used to low-pass filter the combined signal of the two first signals. After filtering, components above the cutoff frequency can be removed. Decimation by a factor of M can be performed on the filtered signal, where M can be an integer greater than or equal to 2.

[0150] Taking 4 channels of first signals as an example, the sampling rate of each channel of first signals is f s / 4, the sampling rate of the signal after the combination of the first signal of the first channel and the first signal of the third channel is f s / 2, the above M can be 2, and the first sampling rate of the signal after 2 times filtering and decimation can be f s / 4, the preset cutoff frequency of the above low-pass filter is f s / 8.

[0151] In some embodiments, the spectrum of each of the N first signals overlaps about a mirror symmetry point. The mirror symmetry point can be a sampling rate point of the first signal. The attenuation is relatively large, for example, the attenuation exceeds 60%. ~f s / 2 signal and Overlapping together. The attenuation is relatively large. For the signal in this frequency band, Therefore, the above low-pass filter can be used to Take the example of using 4 analog-to-digital converters to perform time-interleaved sampling on the output signal of the front-end module. and 0~f s / 8 are aliased together, and the broadband digital trigger system The attenuation of the frequency band is large. The above low-pass filter can filter frequency band signal.

[0152] The filtered and extracted signal can be de-embedded, for example, using a preset de-embedding filter to obtain a second signal. The preset de-embedding filter can have compensation parameters corresponding to multiple frequencies. De-embedding can compensate for the effects of the broadband digital trigger system's frequency response on the measured signal, as well as for external influences on the measured signal. This results in an accurate signal, which helps ensure accurate trigger judgment.

[0153] S603: Perform filtering and interpolation on the second signal to obtain a third signal.

[0154] Specifically, the second signal may be subjected to K-fold filtering and interpolation to obtain the third signal; K is greater than 1.

[0155] In one example, K can be related to the sampling rate of the second signal and the sampling rate of the wideband digital trigger system. The sampling rate of the third signal obtained by interpolating the second signal by K times can be greater than or equal to the sampling rate of the wideband digital trigger system. Alternatively, it can be less than the sampling rate of the wideband digital trigger system. If the sampling rate of the third signal is greater than or equal to the sampling rate of the wideband digital trigger system, trigger condition determination based on the third signal can improve the time accuracy of the trigger determination.

[0156] S604: Determine whether a trigger condition is met according to the third signal, and issue a trigger instruction in response to the trigger condition being met.

[0157] For example, the third signal can be compared with a preset signal to obtain a comparison result, and whether the third signal meets the trigger condition can be determined based on the comparison result. The comparison of the third signal with the preset signal can include, for example, comparing the amplitude of the third signal with that of the preset signal, comparing the difference between the start time, end time, and slope of the rising and / or falling edges of the third signal and the preset signal, or comparing the duration of the third signal with that of the preset signal.

[0158] The trigger condition here is related to the trigger mode, and the trigger condition can be configured according to the specific trigger mode.

[0159] After the third signal meets the trigger condition, a trigger instruction is issued, which instructs the start of scanning and displaying the measured signal.

[0160] In this embodiment, at least two of the first signals outputted by the multi-channel analog-to-digital converter are filtered and extracted, and the filtered and extracted signals are compensated, thereby reducing the amount of data for compensation processing and the scale of the digital circuit for compensating the signal.

[0161] In some embodiments, the method further comprises the steps of:

[0162] First, each channel of the first signal is collected; and in response to a trigger instruction, each channel of the first signal collected in this cycle is stored in a storage module; wherein each channel of the first signal has its own corresponding phase;

[0163] Secondly, the first signals of various channels are extracted from the storage module according to the phase, and the first signals of various channels are integrated and calibrated to output as display signals.

[0164] The above-mentioned acquisition of the first signal can be performed by a sampling module. The sampling module can periodically acquire each first signal. After receiving a trigger instruction, the sampling module stores each first signal acquired in this period in the storage module.

[0165] The display module can retrieve one or more cycles of each first signal from the storage module for display. If the first signal has not been compensated, the display module can also integrate the first signals retrieved from the storage module, then de-embed (also known as compensate) the integrated first signal, and output the de-embedded signal as a display signal.

[0166] The above embodiment realizes displaying the above signal after the output signal of the analog front end meets the trigger condition, so that the user can observe the above signal.

[0167] The present disclosure also provides an electronic device, wherein the device is integrated Figure 3 、 Figure 4 、 Figure 5 or Figure 6 The broadband digital trigger system provided by the illustrated embodiment. The electronic device mentioned above may be a signal measuring device, for example, an oscilloscope, a signal analyzer, or other signal measuring devices.

[0168] The above description is merely a preferred embodiment of the present disclosure and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of the present disclosure is not limited to technical solutions formed by specific combinations of the aforementioned technical features. It also encompasses other technical solutions formed by any combination of the aforementioned technical features or their equivalents, without departing from the scope of the above disclosure. For example, a technical solution formed by replacing the aforementioned features with (but not limited to) technical features with similar functions disclosed in this disclosure.

[0169] Although several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination.

[0170] Although the subject matter has been described in language specific to structural features and methodological acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claims.

Claims

1. A broadband digital trigger system comprising: Analog front end, used to receive the signal under test; an interleaved analog-to-digital conversion module, comprising a plurality of analog-to-digital converters, wherein the plurality of analog-to-digital converters are configured to perform interleaved sampling on the output signal of the analog front end to obtain a plurality of first signals; an extraction and de-embedding module, configured to filter and extract at least a portion of the first signal to obtain a filtered and extracted signal, and de-embed the filtered and extracted signal to obtain a second signal; a filtering and interpolation module, configured to perform K-fold filtering and interpolation on the second signal to obtain a third signal, where K>1; and wherein a sampling rate of the third signal is greater than or equal to a sampling rate of the broadband digital trigger system; a trigger judgment module, configured to determine whether a trigger condition is satisfied according to the third signal, and issue a trigger instruction in response to satisfying the trigger condition; The extraction and de-embedding module includes a filtering extraction module and a de-embedding module, wherein: The signal input end of the filtering and decimation module is connected to the output ends of two analog-to-digital converters among the multiple analog-to-digital converters, and the filtering and decimation module is used to receive the first signals respectively output by the two analog-to-digital converters using a low-pass filter with a preset cutoff frequency, filter the first signals respectively output by the two analog-to-digital converters according to their respective timings, and perform M-fold decimation on the filtered first signals to obtain the filtered and decimated signals, where M is an integer greater than or equal to 2; Alternatively, the signal input end of the filtering and decimation module is connected to the output end of each of the analog-to-digital converters, and the filtering and decimation module is configured to sequentially receive the first signals output by each of the analog-to-digital converters after sampling according to its respective clock phase using a low-pass filter having a preset cutoff frequency; filter each received first signal, and perform M-fold decimation on the filtered first signal to obtain the filtered and decimated signal, where M is an integer greater than or equal to 2; and the cutoff frequency of the low-pass filter is half of the first sampling rate corresponding to the filtered and decimated signal. The de-embedding module is used to receive the filtered and extracted signal, and de-embed the filtered and extracted signal using a preset de-embedding filter to obtain the second signal; the preset de-embedding filter has multiple compensation coefficients corresponding to multiple frequencies.

2. The broadband digital trigger system according to claim 1, characterized in that: The system further includes a sampling module, a storage module, and a display module; wherein the sampling module is used to collect the first signals of each channel; and in response to the trigger judgment module outputting a trigger instruction, the first signals of each channel collected in the current cycle are stored in the storage module; wherein each first signal has its own corresponding phase; The display module is used to extract the first signals of each channel from the storage module according to the phase, integrate the first signals of each channel, calibrate them and output them as display signals.

3. The broadband digital trigger system according to claim 1, characterized in that: The extraction and de-embedding modules are implemented based on digital processing devices.

4. A broadband digital triggering method, applied to the broadband digital triggering system according to any one of claims 1 to 3, characterized in that: include: Performing time-interleaved sampling on the measured signal to obtain multiple first signals; Filtering and extracting at least a portion of the first signal to obtain a filtered and extracted signal, and de-embedding the filtered and extracted signal to obtain a second signal; Performing K-fold filtering and interpolation on the second signal to obtain a third signal, where K>1; determining whether a trigger condition is satisfied according to the third signal, and issuing a trigger instruction in response to satisfying the trigger condition; The filtering and extracting at least a portion of the first signal to obtain a filtered and extracted signal includes: filtering the at least part of the first signal using a low-pass filter having a preset cutoff frequency; decimating at least a portion of the filtered first signal by a factor of M to obtain the filtered decimated signal, where M is an integer greater than or equal to 2; and de-embedding the filtered decimated signal to obtain a second signal, comprising: De-embedding the filtered and extracted signal using a preset de-embedding filter; wherein two first signals among the multiple first signals are filtered and extracted according to their respective time sequences; Alternatively, after sampling the multiple first signals according to their respective clock phases, filtering and extracting are performed on each first signal.

5. The method according to claim 4, characterized in that The method further comprises: Collecting each first signal; and storing each first signal collected in this cycle in a storage module in response to a trigger instruction; wherein each first signal has its own corresponding phase; The first signals of various channels are extracted from the storage module according to the phase, and the first signals of various channels are integrated, calibrated and output as display signals.

6. An electronic device comprising the broadband digital trigger system according to any one of claims 1 to 3.

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