A pre-regulator circuit

Abstract

The application relates to the technical field of integrated circuits, in particular to a pre-stabilization circuit. The pre-stabilization circuit comprises a voltage input end, a voltage output end, a pre-stabilization output unit, a driving PMOS tube, a junction field effect tube, an adjusting resistor and a ground end. The voltage input end is connected with the gate and the source of the driving PMOS tube; the voltage output end is connected with the drain of the driving PMOS tube and one end of the pre-stabilization output unit; the gate of the junction field effect tube is connected with the ground end; the drain of the junction field effect tube is connected with the gate of the driving PMOS tube; the source of the junction field effect tube is connected with one end of the adjusting resistor; the other end of the adjusting resistor and the other end of the pre-stabilization output unit are both connected with the ground end. The application can reduce the static power consumption of the overall circuit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a pre-regulated voltage circuit. Background Technology

[0002] The pre-regulator circuit, as a power supply unit in a chip, is a fundamental module in integrated circuits. It converts external high-voltage input into internal low-voltage power, which is then used as a foundation for building various low-voltage modules.

[0003] Typically, the pre-regulator circuit utilizes a combination of Zener diode D0 and MOSFET Q1. (See reference [link to relevant documentation] for details.) Figure 1 The pre-regulator circuit generates a low-voltage power supply by reverse-breaking the Zener diode D0, resulting in a voltage equal to the Zener diode D0 regulated voltage minus the gate-source voltage drop of the MOSFET Q1. Its output voltage depends on the regulated voltage after the Zener diode D0 breaks down. This pre-regulator circuit has relatively high static power consumption. Summary of the Invention

[0004] The technical problem to be solved by the embodiments of the present invention is to provide a pre-regulatory circuit to solve the problem of high static power consumption of pre-regulatory circuits in the prior art.

[0005] This invention discloses a pre-regulatory circuit, including a voltage input terminal, a voltage output terminal, a pre-regulatory output unit, a driving PMOS transistor, a junction field-effect transistor (JFET), an adjusting resistor, and a ground terminal. The voltage input terminal is connected to the gate and source of the driving PMOS transistor. The voltage output terminal is connected to the drain of the driving PMOS transistor and one end of the pre-regulatory output unit. The gate of the JFET is connected to the ground terminal, the drain of the JFET is connected to the gate of the driving PMOS transistor, the source of the JFET is connected to one end of the adjusting resistor, and the other end of the adjusting resistor and the other end of the pre-regulatory output unit are both connected to the ground terminal.

[0006] Optionally, the pre-regulator circuit further includes a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor. The gate of the first NMOS transistor is connected to its own drain, the gate of the second NMOS transistor, and the other end of the pre-regulator output unit. The sources of the first NMOS transistor and the second NMOS transistor are both connected to ground. The drain of the second NMOS transistor is connected to the drain of the first PMOS transistor. The gate of the first PMOS transistor is connected to its own drain and the gate of the second PMOS transistor. The sources of the first PMOS transistor and the second PMOS transistor are both connected to the voltage input terminal. The drain of the second PMOS transistor is connected to the gate of the driving PMOS transistor.

[0007] Optionally, the pre-regulatory circuit further includes an overvoltage protection unit, which is connected to the voltage output terminal and the gate of the driving PMOS transistor, respectively.

[0008] Optionally, the overvoltage protection unit includes a Zener diode, a third NMOS transistor, and a fourth NMOS transistor. The negative terminal of the Zener diode is connected to the voltage output terminal, and the positive terminal is connected to the drain and gate of the third NMOS transistor and the gate of the fourth NMOS transistor. The drain of the fourth NMOS transistor is connected to the drain of the first PMOS transistor, and the sources of the third NMOS transistor and the fourth NMOS transistor are both connected to ground.

[0009] Optionally, the pre-regulated output unit includes a third PMOS transistor, a fourth PMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The source of the third PMOS transistor is connected to the voltage output terminal, the gate of the third PMOS transistor is connected to its own drain and the source of the fourth PMOS transistor, the gate of the fourth PMOS transistor is connected to its own drain and the drain and gate of the fifth NMOS transistor, the source of the fifth NMOS transistor is connected to the drain and gate of the sixth NMOS transistor, and the source of the sixth NMOS transistor is connected to the drain of the first NMOS transistor.

[0010] Optionally, the driving PMOS transistor is a high-voltage PMOS transistor, and the first NMOS transistor, the second NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are all low-voltage NMOS transistors, and the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are all low-voltage PMOS transistors.

[0011] Optionally, the pre-regulatory circuit further includes a compensation circuit unit, one end of which is connected to the voltage input terminal and the other end of which is connected to the gate of the driving PMOS transistor.

[0012] Optionally, the compensation circuit unit includes a compensation capacitor and a compensation resistor, the compensation capacitor and the compensation resistor are connected in series, the other end of the compensation capacitor is connected to the voltage input terminal, and the other end of the compensation resistor is connected to the gate of the driving PMOS transistor.

[0013] Optionally, the pre-regulatory circuit further includes a high-voltage NMOS transistor, the gate of which is connected to the voltage output terminal, the source of which is connected to the drain of the second NMOS transistor, and the drain of which is connected to the drain of the first PMOS transistor.

[0014] Optionally, the pre-regulatory circuit further includes a filter capacitor, one end of which is connected to the voltage output terminal and the other end is connected to ground.

[0015] Compared with the prior art, the beneficial effects of the pre-regulatory circuit provided in this embodiment of the invention are as follows: by setting a voltage input terminal, a voltage output terminal, a pre-regulatory output unit, a driving PMOS transistor, a junction field-effect transistor (JFET), an adjusting resistor, and a ground terminal, the voltage input terminal is connected to the gate and source of the driving PMOS transistor, the voltage output terminal is connected to the drain of the driving PMOS transistor and one end of the pre-regulatory output unit, the gate of the JFET is connected to the ground terminal, the drain of the JFET is connected to the gate of the driving PMOS transistor, the other end of the adjusting resistor and the other end of the pre-regulatory output unit are both connected to the ground terminal, the source of the JFET is connected to one end of the adjusting resistor, and the other end of the adjusting resistor and the other end of the pre-regulatory output unit are both connected to the ground terminal, and by connecting the JFET and the adjusting resistor in series, the gate-to-source voltage is determined by the difference between the gate voltage and the source voltage of the JFET, thereby realizing the regulation of the static current and reducing the static power consumption of the overall circuit. Attached Figure Description

[0016] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. In the accompanying drawings:

[0017] Figure 1 This is a circuit diagram of an existing pre-regulator circuit;

[0018] Figure 2 This is a circuit diagram of the pre-stabilized voltage circuit provided in an embodiment of the present invention;

[0019] Figure 3 This is a schematic diagram of the pre-stabilized voltage circuit provided in an embodiment of the present invention.

[0020] The labels for the attached figures are as follows:

[0021] D0, Zener diode; Q1, MOSFET.

[0022] 10 Voltage input terminal; 20 Voltage output terminal; 30 Pre-regulated output unit; 40 Ground terminal; 50 Overvoltage protection unit; 60 Compensation circuit unit; PLDM1 Driver PMOS transistor; JFET1 Junction Field-Effect Transistor; R1 Adjustment resistor; R2 Compensation resistor; NM1 First NMOS transistor; NM2 Second NMOS transistor; NM3 Third NMOS transistor; NM4 Fourth NMOS transistor; NM5 Fifth NMOS transistor; NM6 Sixth NMOS transistor; PM1 First PMOS transistor; PM2 Second PMOS transistor; PM3 Third PMOS transistor; PM4 Fourth PMOS transistor; NLDM1 High-voltage NMOS transistor; D1 Zener diode; C1 Compensation capacitor; C2 Filter capacitor. Detailed Implementation

[0023] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0024] This invention provides a pre-regulatory circuit, such as... Figure 2 and Figure 3 As shown, the pre-regulator circuit includes a voltage input terminal 10, a voltage output terminal 20, a pre-regulator output unit 30, a driving PMOS transistor PLDM1, a junction field-effect transistor JFET1, an adjustment resistor R1, and a ground terminal 40. The voltage input terminal 10 is connected to the gate and source of the driving PMOS transistor PLDM1. The voltage output terminal 20 is connected to the drain of the driving PMOS transistor PLDM1 and one end of the pre-regulator output unit 30. The gate of the junction field-effect transistor JFET1 is connected to the ground terminal 40. The drain of the junction field-effect transistor JFET1 is connected to the gate of the driving PMOS transistor PLDM1. The source of the junction field-effect transistor JFET1 is connected to one end of the adjustment resistor R1. The other end of the adjustment resistor R1 and the other end of the pre-regulator output unit 30 are both connected to the ground terminal 40.

[0025] This application includes a voltage input terminal 10, a voltage output terminal 20, a pre-regulated output unit 30, a driving PMOS transistor PLDM1, a junction field-effect transistor (JFET1), an adjustment resistor R1, and a ground terminal 40. The voltage input terminal 10 is connected to the gate and source of the driving PMOS transistor PLDM1. The voltage output terminal 20 is connected to the drain of the driving PMOS transistor PLDM1 and one end of the pre-regulated output unit 30. The gate of the JFET1 is connected to the ground terminal 40, and the drain of the JFET1 is connected to the driving PMOS transistor PLDM1. The gate of M1, the other end of the regulating resistor R1, and the other end of the pre-regulated output unit 30 are all connected to ground 40. The source of the junction field-effect transistor JFET1 is connected to one end of the regulating resistor R1, and the other end of the regulating resistor R1 and the other end of the pre-regulated output unit 30 are all connected to ground 40. By connecting the junction field-effect transistor JFET1 in series with the regulating resistor R1, the gate-to-source voltage is determined by the difference between the gate voltage and the source voltage of the junction field-effect transistor JFET1, thereby achieving the regulation of the static current and reducing the static power consumption of the overall circuit.

[0026] The JFET1 is a type of field-effect transistor with three electrodes: gate, drain, and source. The gate structure of the JFET is similar to that of a PN junction diode. There are two types of JFETs: N-channel and P-channel. In this embodiment, an N-channel JFET is specifically used. In an N-channel JFET, an N-type channel exists between the gate and source. When the gate voltage is zero, the channel is conductive. When a negative voltage is applied to the gate, this negative voltage reduces the conductivity of the channel, thereby controlling the current between the source and drain.

[0027] The source of the junction field-effect transistor (JFET1) is connected to a regulating resistor R1. The voltage drop across R1 generates VGS, the bias voltage for JFET1. The gate current of JFET1 is again zero, and the source voltage is determined by the drain current and the regulating resistor R1. Connecting JFET1 in series with the regulating resistor R1 also achieves better linear regulation and output voltage accuracy in the pre-regulator circuit.

[0028] Voltage input terminal 10 is used to input voltage, and voltage output terminal 20 is used to output voltage, providing power supply voltage to the connected circuit module.

[0029] The driving PMOS transistor is a high-voltage PMOS transistor, which can withstand higher voltages, and the pre-regulator circuit can withstand even higher voltages.

[0030] Further, refer to Figure 2 and Figure 3 The pre-regulator circuit also includes a first NMOS transistor NM1, a second NMOS transistor NM2, a first PMOS transistor PM1, and a second PMOS transistor PM2. The gate of the first NMOS transistor NM1 is connected to its own drain, the gate of the second NMOS transistor NM2, and the other end of the pre-regulator output unit 30. The sources of the first NMOS transistor NM1 and the second NMOS transistor NM2 are both connected to ground terminal 40. The drain of the second NMOS transistor NM2 is connected to the drain of the first PMOS transistor PM1. The gate of the first PMOS transistor PM1 is connected to its own drain and the gate of the second PMOS transistor PM2. The sources of the first PMOS transistor PM1 and the second PMOS transistor PM2 are both connected to voltage input terminal 10. The drain of the second PMOS transistor PM2 is connected to the gate of the driving PMOS transistor PLDM1.

[0031] By configuring a first NMOS transistor NM1, a second NMOS transistor NM2, a first PMOS transistor PM1, and a second PMOS transistor PM2, and forming a negative feedback loop with the driving PMOS transistor PLDM1, when the voltage at the voltage output terminal 20 changes, the gate voltages of the first NMOS transistor NM1 and the second NMOS transistor NM2 in the negative feedback loop follow the voltage change at the voltage output terminal 20, while the gate voltages of the first PMOS transistor PM1 and the second PMOS transistor PM2 change in the opposite direction to the voltage at the voltage output terminal 20. This, in turn, affects the gate voltage of the driving PMOS transistor PLDM1, thereby regulating the voltage change at the voltage output terminal 20, making the output voltage more stable and accurate, and improving the robustness and stability of the circuit.

[0032] In practical implementation, the first NMOS transistor NM1 and the second NMOS transistor NM2 are low-voltage NMOS transistors. Low-voltage NMOS transistors typically have lower on-resistance, which means that their voltage drop and power consumption are lower when they are on, thereby reducing circuit power consumption. Low on-resistance also helps to reduce heat generation, making the circuit more stable and reliable when operating at higher currents. In addition, low-voltage NMOS transistors can achieve faster switching speeds, improving the circuit's response speed.

[0033] Both the first PMOS transistor PM1 and the second PMOS transistor PM2 are low-voltage PMOS transistors. Similar to low-voltage NMOS transistors, low-voltage PMOS transistors also have low on-resistance. This means that in the on-state, their voltage drop and power consumption are low. Low on-resistance helps reduce heat generation, making the circuit more stable and reliable when operating at higher currents. In addition, low-voltage PMOS transistors can achieve faster switching speeds, improving the circuit's response speed.

[0034] By using low-voltage NMOS transistors and low-voltage PMOS transistors, the power consumption of the circuit can be further reduced effectively.

[0035] refer to Figure 2 and Figure 3 In this embodiment, the pre-regulatory circuit also includes an overvoltage protection unit 50, which is connected to the voltage output terminal 20 and the gate of the driving PMOS transistor PLDM1.

[0036] By setting the overvoltage protection unit 50, the output voltage of the voltage output terminal 20 can be monitored. Once the output voltage of the voltage output terminal 20 exceeds the expected voltage, it will be fed back to the front end through the overvoltage protection unit 50, thereby affecting the driving of the PMOS transistor PLDM1, so as to avoid the output voltage of the voltage output terminal 20 being too high, and thus avoid damaging the subsequent circuit.

[0037] Specifically, refer to Figure 2 and Figure 3 The overvoltage protection unit 50 includes a Zener diode D1, a third NMOS transistor NM3, and a fourth NMOS transistor NM4. The negative terminal of the Zener diode D1 is connected to the voltage output terminal 20, and the positive terminal is connected to the drain and gate of the third NMOS transistor NM3 and the gate of the fourth NMOS transistor NM4. The drain of the fourth NMOS transistor NM4 is connected to the drain of the first PMOS transistor PM1. The sources of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are both connected to the ground terminal 40.

[0038] A reverse-connected Zener diode D1, along with the third NMOS transistor NM3 and the fourth NMOS transistor NM4, forms an overvoltage protection circuit. When the power supply voltage at the voltage input terminal 10 changes rapidly or the load changes rapidly, a surge voltage is generated in the output voltage VDD at the voltage output terminal 20. This surge voltage causes the Zener diode D1 to conduct, thereby generating a conduction current. This current is transmitted through a current mirror composed of the third NMOS transistor NM3 and the fourth NMOS transistor NM4, and a current mirror composed of the first PMOS transistor PM1 and the second PMOS transistor PM2. As a result, the second PMOS transistor PM2 has a pull-up current, which pulls up the gate voltage of the driving PMOS transistor PLDM1, causing the driving PMOS transistor PLDM1 to turn off, thus preventing overvoltage of the output voltage VDD. When the surge voltage disappears, the Zener diode D1 turns off, and the pull-up current of the second PMOS transistor PM2 disappears. The circuit resumes stable operation by relying on the negative feedback loop formed by the first NMOS transistor NM1, the second NMOS transistor NM2, the first PMOS transistor PM1, the second PMOS transistor PM2, and the driving PMOS transistor PLDM1.

[0039] In practice, the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are also low-voltage NMOS transistors, which have lower on-resistance and reduce the power consumption of the circuit.

[0040] refer to Figure 2 and Figure 3 In this embodiment, the pre-regulated output unit 30 includes a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth NMOS transistor NM5, and a sixth NMOS transistor NM6. The source of the third PMOS transistor PM3 is connected to the voltage output terminal 20. The gate of the third PMOS transistor PM3 is connected to its own drain and the source of the fourth PMOS transistor PM4. The gate of the fourth PMOS transistor PM4 is connected to its own drain and the drain and gate of the fifth NMOS transistor NM5. The source of the fifth NMOS transistor NM5 is connected to the drain and gate of the sixth NMOS transistor NM6. The source of the sixth NMOS transistor NM6 is connected to the drain of the first NMOS transistor NM1.

[0041] The output voltage of voltage output terminal 20 is the sum of the source and drain voltage differences of the third PMOS transistor PM3 (diode-connected), the source and drain voltage differences of the fourth PMOS transistor PM4, the source and drain voltage differences of the fifth NMOS transistor NM5, the source and drain voltage differences of the sixth NMOS transistor NM6, and the source and drain voltage differences of the first NMOS transistor NM1.

[0042] By setting the third PMOS transistor PM3, the fourth PMOS transistor PM4, the fifth NMOS transistor NM5, and the sixth NMOS transistor NM6, the gate and drain are disconnected, forming a diode connection. In this connection method, when the gate voltage is higher than the drain voltage, the diode will conduct, discharging the excess voltage through the diode, thereby limiting the rise of the drain voltage. The output voltage will not deviate significantly with voltage changes, achieving a certain degree of voltage regulation, realizing regulated output, improving the circuit's surge suppression capability, making it less susceptible to environmental interference, and providing high output voltage accuracy.

[0043] In practice, the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are both low-voltage NMOS transistors, and the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 are both low-voltage NMOS transistors. The power consumption of the pre-regulated output unit 30 is low, and thus the overall power consumption of the entire pre-regulated circuit is low.

[0044] refer to Figure 2 and Figure 3 In this embodiment, the pre-regulatory circuit also includes a compensation circuit unit 60. One end of the compensation circuit unit 60 is connected to the voltage input terminal 10, and the other end is connected to the gate of the driving PMOS transistor PLDM1.

[0045] By setting up the compensation circuit unit 60, the driving PMOS transistor PLDM1 can be effectively protected, preventing sudden changes in the gate voltage of the driving PMOS transistor PLDM1, and improving the working stability and frequency response characteristics of the driving PMOS transistor PLDM1.

[0046] Specifically, the compensation circuit unit 60 includes a compensation capacitor C1 and a compensation resistor R2. The compensation capacitor C1 and the compensation resistor R2 are connected in series. The other end of the compensation capacitor C1 is connected to the voltage input terminal 10, and the other end of the compensation resistor R2 is connected to the gate of the driving PMOS transistor PLDM1.

[0047] By connecting the compensation capacitor C1 and the compensation resistor R2 in series, the compensation resistor R2 can stabilize the operating state of the PMOS transistor PLDM1 and prevent excessive current from damaging the PMOS transistor PLDM1. The compensation capacitor C1 is a component that can store charge. During the operation of the PMOS transistor PLDM1, when the voltage between the gate and source of the PMOS transistor PLDM1 changes, the addition of the compensation capacitor C1 helps to buffer the voltage change, making the operation of the PMOS transistor PLDM1 more stable. In summary, the series-connected compensation capacitor C1 and compensation resistor R2 can improve the stability of the entire circuit loop.

[0048] In this embodiment, reference Figure 2 and Figure 3 The pre-regulatory circuit also includes a high-voltage NMOS transistor NLDM1. The gate of the high-voltage NMOS transistor NLDM1 is connected to the voltage output terminal 20. The source of the high-voltage NMOS transistor NLDM1 is connected to the drain of the second NMOS transistor NM2. The drain of the high-voltage NMOS transistor NLDM1 is connected to the drain of the first PMOS transistor PM1.

[0049] By setting a high-voltage NMOS transistor NLDM1, high and low voltage isolation can be achieved, which can effectively protect the pre-regulator circuit from the influence of high-voltage circuits, thereby improving the stability and reliability of the entire circuit system. In the integrated circuits used, it can effectively reduce signal interference between different voltage domains and improve the circuit's anti-interference capability.

[0050] refer to Figure 2 and Figure 3 The pre-regulator circuit also includes a filter capacitor C2, one end of which is connected to the voltage output terminal 20, and the other end is connected to the ground terminal 40. The filter capacitor C2 can filter the voltage output by the pre-regulator output unit 30, thereby improving the power supply rejection ratio.

[0051] Combination Figure 2 and Figure 3 The working principle of the pre-regulator circuit in this embodiment of the invention is as follows:

[0052] The output voltage is determined by the sum of the source (S) and drain (D) voltage differences of the diode-connected MOS transistor in the pre-regulated output unit 30. When the input voltage VIN is lower than 5V, the gate of the driving PMOS transistor PLDM1 is 0V, directly pulling the output voltage VDD of the voltage output terminal 20 to the input voltage VIN of the voltage input terminal 10, thus following the input voltage. When the input voltage VIN is higher than 5V, due to the effect of the negative feedback loop, the output voltage VDD can stably output a 5V voltage.

[0053] The pre-regulator circuit of this invention uses integrated devices suitable for various mainstream BCD processes, facilitating integration. It has three external interfaces: voltage input terminal 10, voltage output terminal 20, and ground terminal 40. The entire circuit uses only one driving PMOS transistor PLDM1 to achieve regulated output and voltage following, greatly saving layout area. At the same time, with only three branches from voltage input terminal 10 to ground terminal 40, its quiescent current is extremely low.

[0054] The pre-regulated circuit of this invention was built using a 40V BCD process and verified by Candence simulation. The pre-regulated circuit proposed in this invention can operate between 1V and 40V. When the input voltage is less than 5V, the output voltage follows the input voltage. When the input voltage is greater than 5V, the output voltage can be stably maintained at 5V. The overall power consumption of the circuit is only 200nA.

[0055] It should be understood that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Those skilled in the art can modify the technical solutions described in the above embodiments, or make equivalent substitutions for some of the technical features; and all such modifications and substitutions should fall within the protection scope of the appended claims of the present invention.

Claims

1. A pre-regulated voltage circuit, characterized in that, The device includes a voltage input terminal, a voltage output terminal, a pre-regulated output unit, a driving PMOS transistor, a junction field-effect transistor (JFET), an adjustment resistor, and a ground terminal. The voltage input terminal is connected to the source of the driving PMOS transistor, the voltage output terminal is connected to the drain of the driving PMOS transistor and one end of the pre-regulated output unit, the gate of the JFET is connected to the ground terminal, the drain of the JFET is connected to the gate of the driving PMOS transistor, the source of the JFET is connected to one end of the adjustment resistor, and the other end of the adjustment resistor is connected to the ground terminal. The pre-regulator circuit further includes a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor. The gate of the first NMOS transistor is connected to its own drain, the gate of the second NMOS transistor, and the other end of the pre-regulator output unit. The sources of the first NMOS transistor and the second NMOS transistor are both connected to ground. The drain of the second NMOS transistor is connected to the drain of the first PMOS transistor. The gate of the first PMOS transistor is connected to its own drain and the gate of the second PMOS transistor. The sources of the first PMOS transistor and the second PMOS transistor are both connected to the voltage input terminal. The drain of the second PMOS transistor is connected to the gate of the driving PMOS transistor.

2. The pre-regulator circuit according to claim 1, characterized in that, The pre-regulatory circuit also includes an overvoltage protection unit, which is connected to the voltage output terminal.

3. The pre-regulator circuit according to claim 2, characterized in that, The overvoltage protection unit includes a Zener diode, a third NMOS transistor, and a fourth NMOS transistor. The negative terminal of the Zener diode is connected to the voltage output terminal, and the positive terminal is connected to the drain and gate of the third NMOS transistor and the gate of the fourth NMOS transistor. The drain of the fourth NMOS transistor is connected to the drain of the first PMOS transistor, and the sources of the third NMOS transistor and the fourth NMOS transistor are both connected to ground.

4. The pre-regulator circuit according to claim 1, characterized in that, The pre-regulated output unit includes a third PMOS transistor, a fourth PMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The source of the third PMOS transistor is connected to the voltage output terminal, and the gate of the third PMOS transistor is connected to its own drain and the source of the fourth PMOS transistor. The gate of the fourth PMOS transistor is connected to its own drain and the drain and gate of the fifth NMOS transistor. The source of the fifth NMOS transistor is connected to the drain and gate of the sixth NMOS transistor, and the source of the sixth NMOS transistor is connected to the drain of the first NMOS transistor.

5. The pre-regulator circuit according to claim 4, characterized in that, The driving PMOS transistor is a high-voltage PMOS transistor, while the first, second, fifth, and sixth NMOS transistors are all low-voltage NMOS transistors, and the first, second, third, and fourth PMOS transistors are all low-voltage PMOS transistors.

6. The pre-regulator circuit according to claim 1, characterized in that, The pre-regulatory circuit also includes a compensation circuit unit, one end of which is connected to the voltage input terminal and the other end is connected to the gate of the driving PMOS transistor.

7. The pre-regulator circuit according to claim 6, characterized in that, The compensation circuit unit includes a compensation capacitor and a compensation resistor. The compensation capacitor and the compensation resistor are connected in series. The other end of the compensation capacitor is connected to the voltage input terminal, and the other end of the compensation resistor is connected to the gate of the driving PMOS transistor.

8. The pre-regulator circuit according to claim 1, characterized in that, The pre-regulatory circuit further includes a high-voltage NMOS transistor disposed between the first PMOS transistor and the second NMOS transistor. The gate of the high-voltage NMOS transistor is connected to the voltage output terminal, the source of the high-voltage NMOS transistor is connected to the drain of the second NMOS transistor, and the drain of the high-voltage NMOS transistor is connected to the drain of the first PMOS transistor.

9. The pre-regulator circuit according to any one of claims 1-8, characterized in that, The pre-regulator circuit also includes a filter capacitor, one end of which is connected to the voltage output terminal and the other end is connected to ground.

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