A decoding control circuit and memory

Abstract

An embodiment of the present disclosure provides a decoding control circuit and a memory, the decoding control circuit including: a first sampling circuit for receiving a first clock signal and a first chip select clock signal to obtain a target chip select clock signal; a second sampling circuit for receiving a mode control signal, a first chip select signal and a first clock signal to obtain a first group of chip select enable signals and a second group of chip select enable signals; a sampling judgment circuit for receiving the first group of chip select enable signals, the second group of chip select enable signals, a fourth clock signal and a target chip select clock signal to obtain a normal command decoding sampling signal and a non-target chip command decoding sampling signal; the decoding sampling circuit for outputting a normal command decoding signal when the normal command decoding sampling signal is valid, or outputting a non-target chip command decoding signal when the non-target chip command decoding sampling signal is valid.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a decoding control circuit and a memory. Background Art

[0002] With the continuous development of semiconductor technology, people have placed increasingly higher demands on data transmission speeds when manufacturing and using computers and other devices. To achieve faster data transmission speeds, a series of devices such as memories that can transmit data at double the data rate (DDR) have emerged.

[0003] In dynamic random access memory (DRAM) chips, the command / address (CMD / ADD, or CA) signal can be sampled and decoded as both an address and an instruction. Currently, the 2T CMD and NT ODT CMD signals in DRAM chips use different chip select pulse widths and correspond to different operational functions. However, existing instruction decoding schemes cannot accurately distinguish between the two types of instruction decoding. Summary of the Invention

[0004] The present disclosure provides a decoding control circuit and a memory, which can distinguish between 2T CMD and NT ODT CMD instructions and accurately decode them, and can also solve the problem that the decoded commands cannot fully cover the whole instruction set.

[0005] In a first aspect, an embodiment of the present disclosure provides a decoding control circuit, which includes a first sampling circuit, a second sampling circuit, a sampling judgment circuit and a decoding sampling circuit; wherein: the first sampling circuit is used to receive a first clock signal and a first chip select clock signal, and samples and delays the first chip select clock signal according to the first clock signal to obtain a second chip select clock signal; and performs an OR logic operation on the first chip select clock signal and the second chip select clock signal to obtain a target chip select clock signal; the second sampling circuit is used to receive a mode control signal, a first chip select signal and a first clock signal; delays the first clock signal to generate a second clock signal and a third clock signal, and the second clock signal and the third clock signal are in anti-phase relationship with each other; and according to the mode control signal, through the second clock signal and the third clock signal The first chip select signal is sampled and delayed respectively to generate a first group of chip select enable signals and a second group of chip select enable signals; the sampling judgment circuit is used to receive the first group of chip select enable signals, the second group of chip select enable signals, the fourth clock signal and the target chip select clock signal, and perform logical operations according to the first group of chip select clock signals, the second group of chip select clock signals, the fourth clock signal and the target chip select clock signal to generate a normal command decoding sampling signal and a non-target chip command decoding sampling signal; the decoding sampling circuit includes a normal command decoding sampling circuit and a non-target chip command decoding sampling circuit, the normal command decoding sampling circuit is used to output a normal command decoding signal when the normal command decoding sampling signal is valid, and the non-target chip command decoding sampling circuit is used to output a non-target chip command decoding signal when the non-target chip command decoding sampling signal is valid.

[0006] In some embodiments, the first clock signal includes a first clock even signal and a first clock odd signal, and the first chip select clock signal includes a first chip select clock odd signal and a first chip select clock even signal; the first sampling circuit includes a first sampling logic circuit and a second sampling logic circuit; wherein: the first sampling logic circuit is used to sample and delay the first chip select clock odd signal according to the first clock even signal to obtain a first sub-chip select clock signal; and perform an OR logic operation on the first chip select clock odd signal and the first sub-chip select clock signal to obtain a first target chip select clock signal; the second sampling logic circuit is used to sample and delay the first chip select clock even signal according to the first clock odd signal to obtain a second sub-chip select clock signal; and perform an OR logic operation on the first chip select clock even signal and the second sub-chip select clock signal to obtain a second target chip select clock signal.

[0007] In some embodiments, the decoding control circuit also includes a signal input circuit; wherein: the signal input circuit is used to receive an initial chip select signal, the first clock even signal and the first clock odd signal, sample and process the initial chip select signal through the first clock even signal to obtain a first chip select sampling signal, and sample and process the first chip select sampling signal through the first clock odd signal to obtain the first chip select clock odd signal; and sample and process the initial chip select signal through the first clock odd signal to obtain a second chip select sampling signal, and sample and process the second chip select sampling signal through the first clock even signal to obtain the first chip select clock even signal.

[0008] In some embodiments, the first sampling logic circuit includes a first sub-sampling circuit, a first delay circuit, and a first OR gate; wherein: the first sub-sampling circuit is used to sample the first chip select clock odd signal according to the first clock even signal to generate a first intermediate sampling signal; the first delay circuit is used to delay the first intermediate sampling signal to generate the first sub-chip select clock signal; the first OR gate is used to perform an OR logic operation on the first sub-chip select clock signal and the first chip select clock odd signal to obtain the first target chip select clock signal; the second sampling logic circuit includes a second sub-sampling circuit, a second delay circuit, and a second OR gate; wherein: the second sub-sampling circuit is used to sample the first chip select clock even signal according to the first clock odd signal to generate a second intermediate sampling signal; the second delay circuit is used to delay the second intermediate sampling signal to generate the second sub-chip select clock signal; the second OR gate is used to perform an OR logic operation on the second sub-chip select clock signal and the first chip select clock even signal to obtain the second target chip select clock signal.

[0009] In some embodiments, the first chip select signal includes a first chip select even signal, the mode control signal includes a first mode control signal and a second mode control signal, the second clock signal includes a second clock even signal and a second clock odd signal, and the third clock signal includes a third clock even signal and a third clock odd signal; the second sampling circuit includes a third sampling logic circuit, a fourth sampling logic circuit, and a fifth sampling logic circuit; wherein: the third sampling logic circuit is used to receive the first clock odd signal and perform delayed logic processing on the first clock odd signal to generate a second clock odd signal and a third clock odd signal; the fourth sampling logic circuit is used to receive the first clock even signal and delay the first clock even signal logical processing to generate a second clock even signal and a third clock even signal; the fifth sampling logic circuit is used to sample the first chip select even signal according to the second clock odd signal to obtain a third intermediate sampling signal; perform delayed logical processing according to the second mode control signal, the third intermediate sampling signal, the second clock odd signal and the third clock odd signal to obtain the first group of chip select enable signals; and perform sampling processing on the third intermediate sampling signal according to the second clock even signal to obtain a fourth intermediate sampling signal; perform delayed logical processing according to the first mode control signal, the fourth intermediate sampling signal, the second clock even signal and the third clock even signal to obtain the second group of chip select enable signals.

[0010] In some embodiments, the third sampling logic circuit includes a third delay circuit, a fourth delay circuit, and a fifth delay circuit; wherein: the third delay circuit is used to delay the first clock odd signal to obtain a first clock delayed odd signal; the fourth delay circuit is used to perform a delayed logic operation on the first clock delayed odd signal to generate the second clock odd signal; the fifth delay circuit is used to perform a delayed logic operation on the first clock delayed odd signal to generate the third clock odd signal; the fourth sampling logic circuit includes a sixth delay circuit, a seventh delay circuit, and an eighth delay circuit; wherein: the sixth delay circuit is used to delay the first clock even signal to obtain a first clock delayed even signal; the seventh delay circuit is used to perform a delayed logic operation on the first clock delayed even signal to generate the second clock even signal; the eighth delay circuit is used to perform a delayed logic operation on the first clock delayed even signal to generate the third clock even signal.

[0011] In some embodiments, the fourth delay circuit includes an even number of first NOT gates connected in series, and the fifth delay circuit includes a first transistor circuit and a second NOT gate connected in series; wherein the delay time of the fourth delay circuit is equal to the delay time of the fifth delay circuit; the seventh delay circuit includes an even number of third NOT gates connected in series, and the eighth delay circuit includes a second transistor circuit and a fourth NOT gate connected in series; wherein the delay time of the seventh delay circuit is equal to the delay time of the eighth delay circuit.

[0012] In some embodiments, the first transistor circuit includes a first transistor and a second transistor; wherein: the first end of the first transistor and the first end of the second transistor are both connected to the output end of the third delay circuit, the gate end of the first transistor is connected to the power supply voltage, and the gate end of the second transistor is connected to the ground voltage; the second end of the first transistor and the second end of the second transistor are both connected to the input end of the second NOT gate, and the output end of the second NOT gate is used to output the third clock odd signal; the second transistor circuit includes a third transistor and a fourth transistor; wherein: the first end of the third transistor and the first end of the fourth transistor are both connected to the output end of the sixth delay circuit; the gate end of the third transistor is connected to the power supply voltage; the gate end of the fourth transistor is connected to the ground voltage; the second end of the third transistor and the second end of the fourth transistor are both connected to the input end of the fourth NOT gate, and the output end of the fourth NOT gate is used to output the third clock even signal.

[0013] In some embodiments, the fifth sampling logic circuit includes a third sub-sampling circuit, a first enabling circuit, a fourth sub-sampling circuit, and a second enabling circuit; wherein: the third sub-sampling circuit is used to sample the first chip select even signal according to the second clock odd signal to obtain the third intermediate sampling signal; the first enabling circuit is used to perform a logical NOR operation on the third intermediate sampling signal and the second mode control signal to obtain a first chip select enable signal, and perform a delayed logical operation on the first chip select enable signal according to the second clock odd signal and the third clock odd signal to obtain a first chip select disable signal; the first chip select enable signal and the first chip select disable signal are respectively delayed and processed. The first chip select enable signal and the second chip select enable signal constitute the first group of chip select enable signals; the fourth sub-sampling circuit is used to perform an inverting operation on the third intermediate sampling signal, and then sample and process the inverted third intermediate sampling signal through the second even clock signal to obtain the fourth intermediate sampling signal; the second enabling circuit is used to perform a non-OR logic operation on the fourth intermediate sampling signal and the first mode control signal to obtain a second chip select enable signal, and perform delayed logic processing on the second chip select enable signal according to the second even clock signal and the third even clock signal to obtain a second chip select disable signal; the second chip select enable signal and the second chip select disable signal constitute the second group of chip select enable signals.

[0014] In some embodiments, the first enabling circuit includes a first NOR gate and a ninth delay circuit; wherein: the first NOR gate is configured to perform a NOR logic operation on the second mode control signal and the third intermediate sampling signal to obtain the first chip select enable signal;

[0015] The ninth delay circuit is configured to perform delayed logic processing on the first chip select enable signal using the second clock odd signal and the third clock odd signal to obtain the first chip select disable signal. The fourth sub-sampling circuit includes a fifth NOT gate and a fifth sub-sampling circuit, wherein the fifth NOT gate is configured to perform a NOT logic operation on the third intermediate sampling signal to obtain the inverted third intermediate sampling signal. The fifth sub-sampling circuit is configured to sample the inverted third intermediate sampling signal using the second clock even signal to obtain the fourth intermediate sampling signal. The second enable circuit includes a second NOR gate and a tenth delay circuit, wherein the second NOR gate is configured to perform a NOR logic operation on the fourth intermediate sampling signal and the first mode control signal to obtain the second chip select enable signal. The tenth delay circuit is configured to perform delayed logic processing on the second chip select enable signal using the second clock even signal and the third clock even signal to obtain the second chip select disable signal.

[0016] In some embodiments, the ninth delay circuit includes a third transistor circuit and a first delay sub-circuit, and the third transistor circuit includes a fifth transistor and a sixth transistor; wherein: the first input terminal of the first NOR gate is used to receive the second mode control signal, the second input terminal of the first NOR gate is used to receive the third intermediate sampling signal, the output terminal of the first NOR gate is used to output the first chip select enable signal, and the first terminal of the fifth transistor and the first terminal of the sixth transistor are both connected to the output terminal of the first NOR gate, the gate terminal of the fifth transistor inputs the second clock odd signal, and the gate terminal of the sixth transistor inputs the third clock odd signal; the second terminal of the fifth transistor and the second terminal of the sixth transistor are both connected to the input terminal of the first delay sub-circuit, and the output terminal of the first delay sub-circuit is used to output the first chip select enable signal. enable signal; the tenth delay circuit includes a fourth transistor circuit and a second delay sub-circuit, and the fourth transistor circuit includes a seventh transistor and an eighth transistor; wherein: the first input terminal of the second NOR gate is used to receive the fourth intermediate sampling signal, the second input terminal of the second NOR gate is used to receive the first mode control signal, the output terminal of the second NOR gate is used to output the second chip select enable signal, and the first terminal of the seventh transistor and the first terminal of the eighth transistor are both connected to the output terminal of the second NOR gate, the gate terminal of the seventh transistor inputs the second clock even signal, and the gate terminal of the eighth transistor inputs the third clock even signal; the second terminal of the seventh transistor and the second terminal of the eighth transistor are both connected to the input terminal of the second delay sub-circuit, and the output terminal of the second delay sub-circuit is used to output the second chip select disable signal.

[0017] In some embodiments, the first transistor, the third transistor, the sixth transistor, and the eighth transistor are NMOS transistors; and the second transistor, the fourth transistor, the fifth transistor, and the seventh transistor are PMOS transistors.

[0018] In some embodiments, the fourth clock signal includes a fourth clock odd signal and a fourth clock even signal; the second sampling circuit also includes an eleventh delay circuit and a twelfth delay circuit; wherein: the eleventh delay circuit is used to delay the third clock odd signal to obtain the fourth clock odd signal; the twelfth delay circuit is used to delay the third clock even signal to obtain the fourth clock even signal.

[0019] In some embodiments, the sampling judgment circuit includes a first sampling judgment circuit and a second sampling judgment circuit; wherein: the first sampling judgment circuit is used to perform a logical operation based on the first group of chip select enable signals, the second group of chip select enable signals, the fourth clock odd signal, the fourth clock even signal, the first target chip select clock signal and the second target chip select clock signal to generate the non-target chip command decoding sampling signal; the second sampling judgment circuit is used to perform a logical operation based on the first group of chip select enable signals, the second group of chip select enable signals, the fourth clock odd signal, the fourth clock even signal, the first target chip select clock signal and the second target chip select clock signal to generate the normal command decoding sampling signal.

[0020] In some embodiments, the first sampling judgment circuit includes a first sub-sampling judgment circuit, a second sub-sampling judgment circuit and a sixth OR gate; wherein: the first sub-sampling judgment circuit is used to perform a logic operation on the first chip select enable signal, the first chip select disable signal, the fourth clock odd signal and the first target chip select clock signal to obtain a fifth intermediate sampling signal; the second sub-sampling judgment circuit is used to perform a logic operation on the second chip select enable signal, the second chip select disable signal, the fourth clock even signal and the second target chip select clock signal to obtain a sixth intermediate sampling signal; the sixth OR gate is used to perform an OR logic operation on the fifth intermediate sampling signal and the sixth intermediate sampling signal to obtain the non-target chip command translation signal. code sampling signal; the second sampling judgment circuit includes a third sub-sampling judgment circuit, a fourth sub-sampling judgment circuit and a seventh OR gate; wherein: the third sub-sampling judgment circuit is used to perform a logic operation on the first chip select enable signal, the first chip select disable signal, the fourth clock odd signal and the first target chip select clock signal to obtain a seventh intermediate sampling signal; the fourth sub-sampling judgment circuit is used to perform a logic operation on the second chip select enable signal, the second chip select disable signal, the fourth clock even signal and the second target chip select clock signal to obtain an eighth intermediate sampling signal; the seventh OR gate is used to perform an OR logic operation on the seventh intermediate sampling signal and the eighth intermediate sampling signal to obtain the normal command decoding sampling signal.

[0021] In some embodiments, the first sub-sampling determination circuit includes a third OR gate, a third AND gate, and a fourth AND gate; wherein: the third OR gate is configured to perform an OR logic operation on the first chip select enable signal and the first chip select disable signal to obtain a first intermediate sub-sampling signal; the third AND gate is configured to perform an AND logic operation on the fourth clock odd signal and the first intermediate sub-sampling signal to obtain a second intermediate sub-sampling signal; the fourth AND gate is configured to perform an AND logic operation on the second intermediate sub-sampling signal and the first target chip select clock signal to obtain the fifth intermediate sampling signal; and the second sub-sampling determination circuit includes a fourth OR gate, a fifth AND gate, and a sixth AND gate; wherein: the fourth OR gate is configured to perform an OR logic operation on the second chip select enable signal and the second chip select disable signal to obtain a third intermediate sub-sampling signal; the fifth AND gate is configured to perform an AND logic operation on the fourth clock even signal and the third intermediate sub-sampling signal to obtain a fourth intermediate sub-sampling signal; and the sixth AND gate is configured to perform an AND logic operation on the fourth intermediate sub-sampling signal and the second target chip select clock signal to obtain the sixth intermediate sampling signal.

[0022] In some embodiments, the third sub-sampling determination circuit includes an eighth OR gate, a seventh AND gate, and a ninth OR gate; wherein: the eighth OR gate is configured to perform an OR logic operation on the first chip select enable signal and the first chip select disable signal to obtain a fifth intermediate sub-sampling signal; the seventh AND gate is configured to perform an AND logic operation on the fourth clock odd signal and the fifth intermediate sub-sampling signal to obtain a sixth intermediate sub-sampling signal; the ninth OR gate is configured to perform an OR logic operation on the sixth intermediate sub-sampling signal and the first target chip select clock signal to obtain the seventh intermediate sub-sampling signal; and the fourth sub-sampling determination circuit includes a tenth OR gate, an eighth AND gate, and an eleventh OR gate; wherein: the tenth OR gate is configured to perform an OR logic operation on the second chip select enable signal and the second chip select disable signal to obtain a seventh intermediate sub-sampling signal; the eighth AND gate is configured to perform an AND logic operation on the fourth clock even signal and the seventh intermediate sub-sampling signal to obtain an eighth intermediate sub-sampling signal; and the eleventh OR gate is configured to perform an OR logic operation on the eighth intermediate sub-sampling signal and the second target chip select clock signal to obtain the eighth intermediate sampling signal.

[0023] In some embodiments, the common command decoding and sampling circuit includes a common command decoding circuit and a common command sampling circuit; wherein: the common command decoding circuit is used to receive the chip select signal to be processed, the command address signal to be processed, the mode control signal and the first chip select clock signal, and perform logic operations on the chip select signal to be processed, the command address signal to be processed, the mode control signal and the first chip select clock signal to obtain the common command signal to be decoded; the common command sampling circuit is used to receive the common command signal to be decoded and the common command decoding sampling signal, and sample the common command signal to be decoded according to the common command decoding sampling signal to obtain the common command decoding signal; the non-target chip command decoding ... The sampling circuit includes a non-target chip command decoding circuit and a non-target chip command sampling circuit; wherein: the non-target chip command decoding circuit is used to receive the chip select signal to be processed, the command address signal to be processed, the mode control signal and the first chip select clock signal, and perform logical operations on the chip select signal to be processed, the command address signal to be processed, the mode control signal and the first chip select clock signal to obtain the non-target chip command signal to be decoded; the non-target chip command sampling circuit is used to receive the non-target chip command signal to be decoded and the non-target chip command decoding sampling signal, and sample the non-target chip command signal to be decoded according to the non-target chip command decoding sampling signal to obtain the non-target chip command decoding signal.

[0024] In a second aspect, an embodiment of the present disclosure provides a semiconductor memory, which includes the decoding control circuit as described in the first aspect.

[0025] In some embodiments, the memory is a dynamic random access memory DRAM chip and complies with DDR5 memory specifications.

[0026] The disclosed embodiments provide a decoding control circuit and a memory. A target chip select clock signal can be obtained through sampling logic processing of a first clock signal and a first chip select clock signal. A first group of chip select enable signals and a second group of chip select enable signals can be generated based on a mode control signal. A logical operation is then performed based on the target chip select clock signal, the first group of chip select clock signals, and the second group of chip select clock signals to generate a common command decoding sampling signal and a non-target chip command decoding sampling signal. Thus, during command decoding, if the common command decoding sampling signal is valid, a common command decoding signal is output; if the non-target chip command decoding sampling signal is valid, a non-target chip command decoding signal is output. This allows accurate distinction between the two instructions, 2T CMD and NT ODT CMD, during decoding, and addresses the issue of incomplete coverage of the two instructions, thereby eliminating glitch issues associated with instruction sampling and decoding in related technologies. This effectively avoids the issue of incorrect operations resulting from instruction decoding errors, ultimately improving memory performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a signal timing diagram of two clock cycle commands;

[0028] Figure 2 1. It is a schematic diagram of the structure of a signal sampling circuit;

[0029] Figure 3 This is a comparison diagram of two chip select signals with different pulse widths;

[0030] Figure 4 A schematic diagram of the structure of an instruction decoder;

[0031] Figure 5 This is a signal timing diagram of a decoding control circuit;

[0032] Figure 6 A schematic diagram of the structure of a decoding control circuit provided in an embodiment of the present disclosure Figure 1 ;

[0033] Figure 7 A schematic diagram of the structure of a decoding control circuit provided in an embodiment of the present disclosure Figure 2 ;

[0034] Figure 8 A schematic diagram of the structure of a decoding control circuit provided in an embodiment of the present disclosure Figure 3 ;

[0035] Figure 9 A schematic diagram of the structure of a decoding control circuit provided in an embodiment of the present disclosure Figure 4 ;

[0036] Figure 10 A schematic diagram of the structure of a decoding control circuit provided in an embodiment of the present disclosure Figure 5 ;

[0037] Figure 11 A schematic diagram of the structure of a decoding control circuit provided in an embodiment of the present disclosure Figure 6 ;

[0038] Figure 12 A schematic diagram of the structure of a decoding control circuit provided in an embodiment of the present disclosure Figure 7 ;

[0039] Figure 13 A schematic diagram of the structure of a decoding control circuit provided in an embodiment of the present disclosure Figure 8 ;

[0040] Figure 14 A schematic diagram of the structure of a decoding control circuit provided in an embodiment of the present disclosure Figure 9 ;

[0041] Figure 15 A schematic diagram of the structure of a decoding control circuit provided in an embodiment of the present disclosure Figure 9 ;

[0042] Figure 16 A schematic diagram of the structure of a decoding control circuit provided in an embodiment of the present disclosure Figure 10 ;

[0043] Figure 17 A schematic diagram of the structure of a decoding control circuit provided in an embodiment of the present disclosure Figure 10 one;

[0044] Figure 18 A schematic diagram of the structure of a decoding control circuit provided in an embodiment of the present disclosure Figure 10 two;

[0045] Figure 19 A schematic diagram of the structure of a decoding control circuit provided in an embodiment of the present disclosure Figure 10 three;

[0046] Figure 20 A schematic diagram of the structure of a decoding control circuit provided in an embodiment of the present disclosure Figure 10 Four;

[0047] Figure 21 A signal timing diagram of a decoding control circuit provided in an embodiment of the present disclosure Figure 1 ;

[0048] Figure 22A signal timing diagram of a decoding control circuit provided in an embodiment of the present disclosure Figure 2 ;

[0049] Figure 23 A schematic diagram of the composition structure of a semiconductor memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are only used to explain the relevant disclosure and are not intended to limit the disclosure. It should also be noted that for ease of description, only the portions relevant to the relevant disclosure are shown in the drawings.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0052] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0053] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0054] The following are explanations of professional terms involved in the embodiments of this disclosure and the corresponding relationships between some terms:

[0055] Dynamic Random Access Memory (DRAM);

[0056] Synchronous Dynamic Random Access Memory (SDRAM);

[0057] Double Data Rate (DDR);

[0058] Fourth generation DDR (DDR4);

[0059] Fifth generation DDR (5th DDR, DDR5);

[0060] Command address input (Command / Address, CMD / ADD or CA for short);

[0061] Clock Input (CLK);

[0062] Chip Select Input (CS);

[0063] Buffer / Repeater (RPT);

[0064] On-Die Termination (ODT)

[0065] Command Decoder (CMD DEC);

[0066] D-type flip-flop (Data Flip-Flop or Delay Flip-Flop, DFF);

[0067] Process, voltage, temperature (PVT);

[0068] Double clock cycle instruction (2TckCommand, 2T CMD);

[0069] Non-Target On-Die Termination Command (NT ODTCMD).

[0070] It can be understood that, taking the DDR5 DRAM design as an example, the CA input can be sampled as both an address and an instruction for sampling and decoding. Among them, CA here is a general term for various DRAM command address signals, which may include command signals such as row address strobe (RAS), column address strobe (CAS), write command (WE), activate command (ACT), and may also include address signals such as A13 to A0. In addition, in actual applications, the command address signal includes several address signals, which may be determined according to the specifications of the DRAM, and the embodiments of the present disclosure do not impose any restrictions.

[0071] In 2T CMD mode of DDR5 DRAM, see Figure 1 , which shows the signal timing diagram of two clock cycle commands. Figure 1In the figure, CK_t and CK_c are a pair of complementary clock signals, CA[13:0] is the CA signal input, CMD is the instruction / command signal obtained after decoding the CA signal, and CS_n is the chip select signal indicating that the CA signal is valid. Figure 1 As shown in the figure, CA[13:0] is a signal that lasts for two clock cycles. CA of the first and second clock cycles need to be sampled as address signals, and CA of the first clock cycle also needs to be sampled and decoded as a command signal. Specifically, in DDR5 DRAM, CA[4:0] of the first clock cycle is sampled and decoded as a command signal.

[0072] For example, see Figure 2 , which shows a schematic diagram of the structure of a signal sampling circuit. Figure 2 As shown, the signal sampling circuit 10 may include a first receiver 101, a second receiver 102, a third receiver 103, a first sampling circuit 104, a second sampling circuit 105, a third sampling circuit 106, a fourth sampling circuit 107, a fifth sampling circuit 108, a sixth sampling circuit 109, a first buffer 110, a first AND gate 111, a second buffer 112, a second AND gate 113, an instruction decoder 114, and an OR gate 115. The first sampling circuit 104, the second sampling circuit 105, the fifth sampling circuit 108, and the sixth sampling circuit 109 may be composed of D-type flip-flops, and the third sampling circuit 106 and the fourth sampling circuit 107 may be composed of D-type flip-flops and inverters.

[0073] exist Figure 2In the example, the input signals of the first receiver 101 are the initial command address signal (represented by CA[13:0]) and the reference signal (represented by VREFCA), and the output signal is the first command address signal (represented by CA). The input signals of the second receiver 102 are the initial chip select signal (represented by CS_n) and the reference signal (represented by VREFCA), and the output signal is the first chip select signal (represented by PCS). The input signals of the third receiver 103 are a pair of complementary clock signals (represented by CK_t and CK_c), and the output signals are the first even clock signal (represented by PCLK_E) and the first odd clock signal (represented by PCLK_O). It should be noted that the third receiver 103 also has frequency division processing capabilities. Therefore, the frequency of the PCLK_E signal and the PCLK_O signal is half of the frequency of the CK_t signal or the CK_c signal, that is, the clock period of the PCLK_E signal and the PCLK_O signal is twice the clock period of the CK_t signal or the CK_c signal, and the phase difference is 180 degrees. In addition, it should be noted that CA[13:0] here represents a group of signals, collectively referred to as CA[0], CA[1], ..., CA

[13] . Accordingly, the first receiver 101 actually includes 14 receiving circuits, as well as output lines, and even includes the subsequent sampling circuit. There are also 14 long routing paths, which correspond one-to-one to CA[0], CA[1], ..., CA

[13] .

[0074] Then, the first command address signal is sampled and processed by the first sampling circuit 104 using the PCLK_E signal to obtain a second address even signal (represented by CA[13:0]_1T_E), and the second address even signal includes the even signal of the instruction to be processed (represented by CA[4:0]_1T_E); the first command address signal is sampled and processed by the second sampling circuit 105 using the PCLK_O signal to obtain a second address odd signal (represented by CA[13:0]_1T_O), and the second address odd signal includes the odd signal of the instruction to be processed. (represented by CA[4:0]_1T_O); through the third sampling circuit 106, the first chip select signal is sampled and inverted using the PCLK_E signal to obtain a chip select even signal to be processed (represented by PCS_E); through the fourth sampling circuit 107, the first chip select signal is sampled and inverted using the PCLK_O signal to obtain a chip select odd signal to be processed (represented by PCS_O); and then through the fifth sampling circuit 108, the PCS_E signal is sampled and processed using the PCLK_O signal to obtain a first chip select clock odd signal ( The first chip select clock signal is sampled and processed by the sixth sampling circuit 109 using the PCLK_E signal to obtain a first chip select clock even signal (represented by PCS_ED); the first buffer 110 and the first AND gate 111 perform a logic operation on the PCLK_E signal and the PCS_ED signal to obtain a chip select clock even signal (represented by CS_CLK_E); the second buffer 112 and the second AND gate 113 perform a logic operation on the PCLK_O signal and the PCS_OD signal to obtain a chip select clock odd signal. signal (represented by CS_CLK_O); then, through the instruction decoder 114, the CS_CLK_E signal and the CS_CLK_O signal are used to decode and sample CA[4:0]_1T_E, CA[4:0]_1T_O, PCS_OD and PCS_ED to obtain the instruction even signal (represented by CMD_E) and the instruction odd signal (represented by CMD_O); finally, the CMD_E signal and the CMD_O signal are subjected to an OR logic operation through the OR gate 115 to obtain the target instruction signal (represented by CMD).In addition, it should be noted that the CA[13:0]_1T_E signal is not a single signal, but represents a group of signals, namely CA

[13] _1T_E to CA[0]_1T_E, and the CA[4:0]_1T_E signal is CA[0]_1T_E, CA[1]_1T_E, CA[2]_1T_E, CA[3]_1T_E, CA[4]_1T_E in the CA[13:0]_1T_E signal. 5 signals; the CA[13:0]_1T_O signal is not a single signal, but represents a group of signals, namely CA

[13] _1T_O to CA[0]_1T_O, and the CA[4:0]_1T_O signal is the 5 signals CA[0]_1T_O, CA[1]_1T_O, CA[2]_1T_O, CA[3]_1T_O, and CA[4]_1T_O in the CA[13:0]_1T_O signal.

[0075] Thus, taking DDR5 DRAM as an example, the initial clock signal (represented by CK_t / CK_c) is divided into PCLK_E and PCLK_O signals after the receiver, and then the CA signal is sampled. Since the 2T CMD in DDR5 requires the CA signal of the first clock cycle as the instruction and address, and the CA signal of the second clock cycle as the remaining address, the DDR5 design requires two-stage sampling, which is then used as the address of the two clock cycles. For instructions, the first-stage CA signal is used for combinational logic, and then the second-stage sampling is performed to align with the sampled address signal of the second cycle. Since the instruction signal needs to maintain a pulse width, the PCS_OD / ED signals obtained after the two-stage sampling are used to perform an AND logic operation to generate the CMD_E / O signals, which are then obtained through an OR operation to obtain the CMD signal.

[0076] In DDR5 DRAM, there are single-cycle mode (represented by 1N MODE) and double-cycle mode (represented by 2N MODE), and there are two command signals in DDR5: 2T CMD signal and NT ODT CMD signal. Among them, 2T CMD signal can also be called 2-cycle Command signal or 2T CMD signal. Figure 3 As shown, for the 2T CMD signal, its corresponding chip select signal is represented by CS0_n, and its pulse width is the preset clock cycle; for the NT ODT CMD signal, its corresponding chip select signal is represented by CS1_n, and its pulse width is twice the preset clock cycle.

[0077] That is to say, the CS_CLK_O / CS_CLK_E signal generated by the simple PCS_ED / PCS_OD and PCLK_E / PCLK_O combination logic is used to perform instruction sampling, and then the AND logic is performed with PCS_ED / PCS_OD to generate a pulse CMD signal. However, the difference between the 2T CMD signal and the NT ODT CMD signal is that the pulse width of the CS_n signal is low (that is, the second cycle of the CS_n signal of the 2T CMD signal is high, and the second cycle of the CS_n signal of the NT ODT CMD signal is low). If the above-mentioned signal sampling circuit 10 is directly used, the 2T CMD signal and the NT ODT CMD signal may have an error decoding problem. In addition, since the NT ODT CMD signal and the 2T CMD signal need to be sampled by PCS_OD / OE after being decoded by the instruction decoder 114, the sampled signal will have a deviation (glicth). For example, in 1N Mode, Figure 4 As shown, since the information (CS and CA) input to the instruction decoder 114 and PCS_OD / OE are sampled and output by PCLK_O and PCLK_E respectively, the decoded signal is not completely aligned with the PCS signal, causing a deviation in the signal when the gate circuit is combined with the logic; that is, since the information input to the instruction decoder 114 and CS_BLOCK_O / E are sampled and output by PCLK_E / PCLK_O respectively, there will be a difference of 1T CK, so the decoded signal of the instruction decoder 114 is not completely aligned with the CS_BLOCK signal, resulting in the decoded command not being completely covered. Figure 5 As shown, CS_E and CS1_E are both one clock cycle (ie, 1T CK) behind PCS_OD, so the decoded command cannot be completely covered by PCS_OD, resulting in instruction decoding errors and the execution of incorrect operations.

[0078] Based on this, an embodiment of the present disclosure provides a decoding control circuit, which includes a first sampling circuit, a second sampling circuit, a sampling judgment circuit and a decoding sampling circuit; wherein: the first sampling circuit is used to receive a first clock signal and a first chip select clock signal, and samples and delays the first chip select clock signal according to the first clock signal to obtain a second chip select clock signal; and performs an OR logic operation on the first chip select clock signal and the second chip select clock signal to obtain a target chip select clock signal; the second sampling circuit is used to receive a mode control signal, a first chip select signal and a first clock signal; delays the first clock signal to generate a second clock signal and a third clock signal, and the second clock signal and the third clock signal are in anti-phase relationship with each other; and according to the mode control signal, through the second clock signal and the third clock signal The first chip select signal is sampled and delayed respectively to generate a first group of chip select enable signals and a second group of chip select enable signals; the sampling judgment circuit is used to receive the first group of chip select enable signals, the second group of chip select enable signals, the fourth clock signal and the target chip select clock signal, and perform logical operations according to the first group of chip select clock signals, the second group of chip select clock signals, the fourth clock signal and the target chip select clock signal to generate a normal command decoding sampling signal and a non-target chip command decoding sampling signal; the decoding sampling circuit includes a normal command decoding sampling circuit and a non-target chip command decoding sampling circuit, the normal command decoding sampling circuit is used to output a normal command decoding signal when the normal command decoding sampling signal is valid, and the non-target chip command decoding sampling circuit is used to output a non-target chip command decoding signal when the non-target chip command decoding sampling signal is valid. In this way, the sampling judgment circuit generates a common command decoding sampling signal and a non-target chip command decoding sampling signal based on the input target chip select clock signal, the fourth clock signal, the first group of chip select enable signals, and the second group of chip select enable signals, and inputs the common command decoding sampling signal and the non-target chip command decoding sampling signal into the decoding sampling circuit. As a result, the decoding sampling circuit can output a common command decoding signal when the common command decoding sampling signal is valid, or output a non-target chip command decoding signal when the non-target chip command decoding sampling signal is valid. In this way, accurate distinction between the two instructions, 2T CMD and NT ODT CMD, can be achieved during decoding. The problem that the two instructions, 2T CMD and NT ODTCMD, cannot be fully covered can also be solved. Furthermore, the glitch phenomenon caused by instruction sampling and decoding in the related art can be eliminated, and the problem of incorrect operation being executed due to instruction decoding errors can be effectively avoided. Finally, the memory performance is improved.

[0079] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0080] In one embodiment of the present disclosure, see Figure 6, which shows a schematic diagram of the structure of a decoding control circuit 20 provided by an embodiment of the present disclosure. Figure 6 As shown, the decoding control circuit 20 includes a first sampling circuit 21, a second sampling circuit 22, a sampling judgment circuit 23 and a decoding sampling circuit 24; wherein:

[0081] The first sampling circuit 21 is configured to receive the first clock signal and the first chip select clock signal, sample and delay the first chip select clock signal according to the first clock signal to obtain a second chip select clock signal, and perform an OR logic operation on the first chip select clock signal and the second chip select clock signal to obtain a target chip select clock signal;

[0082] The second sampling circuit 22 is configured to receive a mode control signal, a first chip select signal, and a first clock signal; delay the first clock signal to generate a second clock signal and a third clock signal, wherein the second clock signal and the third clock signal are in anti-phase relation to each other; and sample and delay the first chip select signal according to the mode control signal, the second clock signal, and the third clock signal to generate a first group of chip select enable signals and a second group of chip select enable signals;

[0083] The sampling judgment circuit 23 is used to receive the first group of chip select enable signals, the second group of chip select enable signals, the fourth clock signal and the target chip select clock signal, perform logic operations based on the first group of chip select clock signals, the second group of chip select clock signals, the fourth clock signal and the target chip select clock signal, and generate a normal command decoding sampling signal and a non-target chip command decoding sampling signal;

[0084] The decoding sampling circuit 24 includes a normal command decoding sampling circuit and a non-target chip command decoding sampling circuit. The normal command decoding sampling circuit is used to output a normal command decoding signal when the normal command decoding sampling signal is valid, and the non-target chip command decoding sampling circuit is used to output a non-target chip command decoding signal when the non-target chip command decoding sampling signal is valid.

[0085] It should be noted that in the disclosed embodiments, the decoding control circuit 20 is used for sampling and decoding address and instruction signals and can be applied in a variety of circuit scenarios. The disclosed embodiments will be explained and illustrated using the CA signal in a DRAM chip for address and instruction sampling and decoding, but this does not constitute a limitation.

[0086] It should also be noted that, in the embodiment of the present disclosure, the normal command decoding signal may be the Command signal in the DDR5 DRAM chip. Since the effective pulse of the signal lasts for two clock cycles, it may be referred to as the 2T CMD signal (or the NormalCMD signal). The Command signal may include a read command signal, a write command signal, a refresh command signal, a precharge command signal, and an activation command signal, etc. The non-target chip command decoding signal may be the Non-TargetODT Command signal in the DDR5 DRAM chip, which may be referred to as the NT ODT CMD signal.

[0087] In the embodiment of the present disclosure, the sampling judgment circuit 23 generates a common command decoding sampling signal and a non-target chip command decoding sampling signal according to the input target chip selection clock signal, the fourth clock signal, the first group of chip selection enable signals and the second group of chip selection enable signals, and inputs the common command decoding sampling signal and the non-target chip command decoding sampling signal to the decoding sampling circuit 24. The decoding sampling circuit 24 may include a common command decoding sampling circuit and a non-target chip command decoding sampling circuit ( Figure 6 (not shown), thereby enabling the decoding and sampling circuit to output a normal command decoding signal when the normal command decoding sampling signal is valid, or to output a non-target chip command decoding signal when the non-target chip command decoding sampling signal is valid, thereby enabling separate decoding of 2T CMD and NT ODT CMD. In this way, not only can the two instructions 2T CMD and NT ODT CMD be accurately distinguished, but invalid signals after the two instructions are respectively decoded can also be completely covered, thereby eliminating the glitch phenomenon caused by instruction sampling and decoding in the related art.

[0088] In some embodiments, Figure 6 As shown in the first sampling circuit 21, Figure 7 As shown, the first sampling circuit 21 may include a first sampling logic circuit 211 and a second sampling logic circuit 212; wherein:

[0089] The first sampling logic circuit 211 is configured to sample and delay the first chip select clock odd signal according to the first clock even signal to obtain a first sub-chip select clock signal; and perform an OR logic operation on the first chip select clock odd signal and the first sub-chip select clock signal to obtain a first target chip select clock signal;

[0090] The second sampling logic circuit 212 is used to sample and delay the first chip select clock even signal according to the first clock odd signal to obtain a second sub-chip select clock signal; and perform an OR logic operation on the first chip select clock even signal and the second sub-chip select clock signal to obtain a second target chip select clock signal.

[0091] Here, the first clock signal includes a first even clock signal and a first odd clock signal. The first even clock signal can be represented by CLK_ET, and the first odd clock signal can be represented by CLK_OT. Specifically, the external clock CK_t / CK_c is divided into the first even clock signal CLK_ET and the first odd clock signal CLK_OT after the receiver. The clock period of each of the first odd clock signal and the first even clock signal is twice the preset clock period, and the phase difference between the first odd clock signal and the first even clock signal is 180 degrees.

[0092] It should be noted that, in the embodiment of the present disclosure, the first chip select clock signal includes a first chip select clock odd signal and a first chip select clock even signal. The first chip select clock odd signal can be represented by CS_BLOCK_O, and the first chip select clock even signal can be represented by CS_BLOCK_E. The second chip select clock signal includes a first sub-chip select clock signal and a second sub-chip select clock signal. The first sub-chip select clock signal can be represented by CS_BLOCK_OD, and the second sub-chip select clock signal can be represented by CS_BLOCK_ED.

[0093] It should also be noted that in the embodiments of the present disclosure, the mode control signal can include two modes, specifically, 1N mode and 2N mode. 1N represents the signal in 1N mode, and 2N represents the signal in 2N mode. Specifically, the target chip select clock signal includes a first target chip select clock signal and a second target chip select clock signal. The first target chip select clock signal can be represented by CS_BLOCK_1N, and the second target chip select clock signal can be represented by CS_BLOCK_2N.

[0094] It is worth noting that the first clock even signal CLK_ET in the embodiment of the present disclosure corresponds to PCLK_E in the above embodiment, and the first clock odd signal CLK_OT corresponds to PCLK_O in the above embodiment; the first chip select clock odd signal CS_BLOCK_O corresponds to PCS_OD in the above embodiment; and the first chip select clock even signal CS_BLOCK_E corresponds to PCS_ED in the above embodiment.

[0095] In the embodiments of the present disclosure, taking the clock signal as an example, E represents EVEN and O represents ODD. EVEN and ODD represent the even and odd clock signals after frequency division. In 1N mode, EVEN and ODD are sampled alternately; in 2N mode, only EVEN or ODD is sampled.

[0096] In some embodiments, Figure 7 Based on the first sampling logic circuit 211 and the second sampling logic circuit 212, as shown Figure 8 As shown, the first sampling logic circuit 211 may include a first sub-sampling circuit 311, a first delay circuit 312 and a first OR gate 313; wherein: the first sub-sampling circuit 311 is used to sample the first chip select clock odd signal CS_BLOCK_O according to the first clock even signal CLK_ET to generate a first intermediate sampling signal CS_BLOCK_O>; the first delay circuit 312 is used to delay the first intermediate sampling signal CS_BLOCK_O> to generate a first sub-chip select clock signal CS_BLOCK_OD; the first OR gate 313 is used to perform an OR logic operation on the first sub-chip select clock signal CS_BLOCK_OD and the first chip select clock odd signal CS_BLOCK_O to obtain a first target chip select clock signal CS_BLOCK_1N.

[0097] The second sampling logic circuit 212 may include a second sub-sampling circuit 314, a second delay circuit 315, and a second OR gate 316; wherein: the second sub-sampling circuit 314 is used to sample the first chip select clock even signal CS_BLOCK_E according to the first clock odd signal CLK_OT to generate a second intermediate sampling signal CS_BLOCK_E>; the second delay circuit 315 is used to delay the second intermediate sampling signal CS_BLOCK_E> to generate a second sub-chip select clock signal CS_BLOCK_ED; and the second OR gate 316 is used to perform an OR logic operation on the second sub-chip select clock signal CS_BLOCK_ED and the first chip select clock even signal CS_BLOCK_E to obtain a second target chip select clock signal CS_BLOCK_2N.

[0098] It should be noted that in the embodiment of the present disclosure, the first intermediate sampling signal can be represented by CS_BLOCK_O>; the second intermediate sampling signal can be represented by CS_BLOCK_E>. The first sub-chip select clock signal can be represented by CS_BLOCK_OD; the second sub-chip select clock signal can be represented by CS_BLOCK_ED.

[0099] It should also be noted that, in the disclosed embodiment, the first delay circuit 312 and the second delay circuit 315 not only have a delay function but also enhance signal driving capability. Specifically, with respect to the first sub-chip select clock signal CS_BLOCK_OD and the first intermediate sampling signal CS_BLOCK_O>, the first sub-chip select clock signal CS_BLOCK_OD not only has a time delay compared to the first intermediate sampling signal CS_BLOCK_O>, but also has a stronger driving capability. Similarly, with respect to the second sub-chip select clock signal CS_BLOCK_ED and the second intermediate sampling signal CS_BLOCK_E>, the second sub-chip select clock signal CS_BLOCK_ED not only has a time delay compared to the second intermediate sampling signal CS_BLOCK_E>, but also has a stronger driving capability.

[0100] It should also be noted that if Figure 8 As shown, both the first sub-sampling circuit 311 and the second sub-sampling circuit 314 may include a flip-flop. Here, the flip-flop may be a D-type flip-flop. Specifically, in the first sub-sampling circuit 311, the clock terminal of the D-type flip-flop is connected to the first even clock signal CLK_ET, the input terminal of the D-type flip-flop is connected to the first chip select clock odd signal CS_BLOCK_O, and the output terminal of the D-type flip-flop is used to output the first intermediate sampling signal CS_BLOCK_O>. In the second sub-sampling circuit 314, the clock terminal of the D-type flip-flop is connected to the first odd clock signal CLK_OT, the input terminal of the D-type flip-flop is connected to the first chip select clock even signal CS_BLOCK_E, and the output terminal of the D-type flip-flop is used to output the second intermediate sampling signal CS_BLOCK_E>.

[0101] It is worth noting that the first sampling circuit 21 may include an odd circuit and an even circuit. Figure 7 and Figure 8 Only the even circuit in the first sampling circuit 21 is shown; the odd circuit in the first sampling circuit 21 is similar to the even circuit, and the difference between the two is that the odd and even of the input signals are opposite, which will not be repeated here.

[0102] In some embodiments, as Figure 9 As shown, the decoding control circuit may further include a signal input circuit 70; wherein:

[0103] The signal input circuit 70 is used to receive an initial chip select signal, a first clock even signal and a first clock odd signal, sample and process the initial chip select signal through the first clock even signal to obtain a first chip select sampling signal, and sample and process the first chip select sampling signal through the first clock odd signal to obtain a first chip select clock odd signal; and sample and process the initial chip select signal through the first clock odd signal to obtain a second chip select sampling signal, and sample and process the second chip select sampling signal through the first clock even signal to obtain a first chip select clock even signal.

[0104] Please continue to refer to Figure 9 The signal input circuit 70 may include a first flip-flop 711, a second flip-flop 712, a third flip-flop 713, and a fourth flip-flop 714, and the first flip-flop 711, the second flip-flop 712, the third flip-flop 713, and the fourth flip-flop 714 may all be composed of D-type flip-flops. The first flip-flop 711 has a clock terminal connected to the first clock even signal, an input terminal connected to the initial chip select signal, and an output terminal for outputting the first chip select sampling signal. The second flip-flop 712 has a clock terminal connected to the first clock odd signal, an input terminal connected to the first chip select sampling signal, and an output terminal for outputting the first chip select clock odd signal. The third flip-flop 713 has a clock terminal connected to the first clock odd signal, an input terminal connected to the initial chip select signal, and an output terminal for outputting the second chip select sampling signal. The fourth flip-flop 714 has a clock terminal connected to the first clock even signal, an input terminal connected to the second chip select sampling signal, and an output terminal for outputting the first chip select clock even signal.

[0105] In some embodiments, Figure 6 As shown in the second sampling circuit 22, based on Figure 10 As shown, the second sampling circuit 22 may include a third sampling logic circuit 41, a fourth sampling logic circuit 42 and a fifth sampling logic circuit 43; wherein:

[0106] The third sampling logic circuit 41 is configured to receive the first clock odd signal and perform delayed logic processing on the first clock odd signal to generate a second clock odd signal and a third clock odd signal;

[0107] a fourth sampling logic circuit 42, configured to receive the first clock even signal and perform delay logic processing on the first clock even signal to generate a second clock even signal and a third clock even signal;

[0108] The fifth sampling logic circuit 43 is configured to perform sampling processing on the first chip select even signal according to the second clock odd signal to obtain a third intermediate sampling signal; perform delay logic processing on the second mode control signal, the third intermediate sampling signal, the second clock odd signal, and the third clock odd signal to obtain a first group of chip select enable signals; and perform sampling processing on the third intermediate sampling signal according to the second clock even signal to obtain a fourth intermediate sampling signal; and perform delay logic processing on the first mode control signal, the fourth intermediate sampling signal, the second clock even signal, and the third clock even signal to obtain a second group of chip select enable signals.

[0109] It should be noted that, in the embodiment of the present disclosure, the second clock signal may include a second clock odd signal and a second clock even signal, the second clock odd signal may be represented by PCLK_O_FAST, and the second clock even signal may be represented by PCLK_E_FAST. The third clock signal may include a third clock odd signal and a third clock even signal, the third clock odd signal may be represented by PCLKB_O_FAST, and the third clock even signal may be represented by PCLKB_E_FAST.

[0110] It should also be noted that in the embodiment of the present disclosure, the mode control signal includes a first mode control signal and a second mode control signal. The first mode control signal can be represented by EN_1N, and the second mode control signal can be represented by EN_2N. EN_1N and EN_2N are level signals, indicating whether the current DRAM is in 1N mode or 2N mode, that is, when EN_1N=1, it indicates 1N mode; EN_2N=1, it indicates 2N mode. The third intermediate sampling signal can be represented by PCS_E>. The first chip select even signal can be represented by PCS_E. The first group of chip select enable signals includes the PCS_EN1N signal and the PCS_DIS1N signal, and the second group of chip select enable signals includes the PCS_EN2N signal and the PCS_DIS2N signal.

[0111] In some embodiments, see Figure 11 , the third sampling logic circuit 41 may include a third delay circuit 411, a fourth delay circuit 412 and a fifth delay circuit 413; wherein:

[0112] The third delay circuit 411 is used to delay the first clock odd signal to obtain a first clock delayed odd signal; the fourth delay circuit 412 is used to perform a delayed logic operation on the first clock delayed odd signal to generate a second clock odd signal; the fifth delay circuit 413 is used to perform a delayed logic operation on the first clock delayed odd signal to generate a third clock odd signal.

[0113] In some embodiments, see Figure 11, the fourth sampling logic circuit 42 may include a sixth delay circuit 421, a seventh delay circuit 422 and an eighth delay circuit 423; wherein:

[0114] The sixth delay circuit 421 is used to delay the first clock even signal to obtain a first clock delayed even signal; the seventh delay circuit 422 is used to perform a delayed logic operation on the first clock delayed even signal to generate a second clock even signal; the eighth delay circuit 423 is used to perform a delayed logic operation on the first clock delayed even signal to generate a third clock even signal.

[0115] In a specific embodiment, Figure 11 Based on the third sampling logic circuit 41 and the fourth sampling logic circuit 42, as shown Figure 12 As shown, the fourth delay circuit 412 may include an even number of first NOT gates 4121 connected in series, the fifth delay circuit 413 may include a first transistor circuit 4131 and a second NOT gate 4132 connected in series; the seventh delay circuit 422 may include an even number of third NOT gates 4221 connected in series, and the eighth delay circuit 423 includes a second transistor circuit 4231 and a fourth NOT gate 4232 connected in series.

[0116] It should be noted that, in the embodiment of the present disclosure, the delay time of the fourth delay circuit 412 is equal to the delay time of the fifth delay circuit 413 , and the delay time of the seventh delay circuit 422 is equal to the delay time of the eighth delay circuit 423 .

[0117] In a more specific embodiment, please refer to Figure 12 , the first transistor circuit 4131 may include a first transistor and a second transistor; wherein:

[0118] The first end of the first transistor and the first end of the second transistor are both connected to the output end of the third delay circuit 411, the gate end of the first transistor is connected to the power supply voltage (VDD), and the gate end of the second transistor is connected to the ground voltage (VSS); the second end of the first transistor and the second end of the second transistor are both connected to the input end of the second NOT gate 4132, and the output end of the second NOT gate 4132 is used to output the third clock odd signal.

[0119] The second transistor circuit 4231 may include a third transistor and a fourth transistor; wherein: the first end of the third transistor and the first end of the fourth transistor are both connected to the output end of the sixth delay circuit 421; the gate end of the third transistor is connected to the power supply voltage; the gate end of the fourth transistor is connected to the ground voltage; the second end of the third transistor and the second end of the fourth transistor are both connected to the input end of the fourth NOT gate 4232, and the output end of the fourth NOT gate 4232 is used to output a third clock even signal.

[0120] It should also be noted that, in the embodiment of the present disclosure, the first transistor and the third transistor may be NMOS, and the second transistor and the fourth transistor may be PMOS.

[0121] In some embodiments, please refer to Figure 11 The fifth sampling logic circuit 43 may include a third sub-sampling circuit 431, a first enabling circuit 432, a fourth sub-sampling circuit 433 and a second enabling circuit 434; wherein:

[0122] The third sub-sampling circuit 431 is configured to sample the first chip select even signal according to the second clock odd signal to obtain a third intermediate sampling signal;

[0123] a first enabling circuit 432 configured to perform a NOR logic operation on the third intermediate sampling signal and the second mode control signal to obtain a first chip select enable signal, and perform delayed logic processing on the first chip select enable signal according to the second clock odd signal and the third clock odd signal to obtain a first chip select disable signal; wherein the first chip select enable signal and the first chip select disable signal constitute a first group of chip select enable signals;

[0124] The fourth sub-sampling circuit 433 is configured to perform an inversion operation on the third intermediate sampling signal and then sample the inverted third intermediate sampling signal using the second even clock signal to obtain a fourth intermediate sampling signal.

[0125] The second enable circuit 434 is configured to perform a logical NOR operation on the fourth intermediate sampling signal and the first mode control signal to obtain a second chip select enable signal, and to perform delayed logical processing on the second chip select enable signal based on the second clock even signal and the third clock even signal to obtain a second chip select disable signal. The second chip select enable signal and the second chip select disable signal constitute a second set of chip select enable signals. The fourth intermediate sampling signal can be represented by PCS_EN.

[0126] In a specific embodiment, Figure 11 As shown in the fifth sampling logic circuit 43, based on Figure 13 As shown, the first enabling circuit 432 may include a first NOR gate 4321 and a ninth delay circuit 4322; wherein:

[0127] A first NOR gate 4321 is configured to perform a NOR logic operation on the second mode control signal EN_2N and the third intermediate sampling signal PCS_E> to obtain a first chip select enable signal PCS_EN1N;

[0128] The ninth delay circuit 4322 is configured to perform delayed logic processing on the first chip select enable signal PCS_EN1N through the second clock odd signal PCLK_O_FAST and the third clock odd signal PCLKB_O_FAST to obtain a first chip select disable signal PCS_DIS1N.

[0129] like Figure 13 As shown, the fourth sub-sampling circuit 433 may include a fifth NOT gate 4331 and a fifth sub-sampling circuit 4332; wherein:

[0130] a fifth NOT gate 4331 , configured to perform a NOT logic operation on the third intermediate sampling signal PCS_E> to obtain an inverted third intermediate sampling signal PCS_E>;

[0131] The fifth sub-sampling circuit 4332 is configured to sample the inverted third intermediate sampling signal PCS_E> through the second even clock signal PCLK_E_FAST to obtain a fourth intermediate sampling signal PCS_EN.

[0132] like Figure 13 As shown, the second enabling circuit 434 may include a second NOR gate 4341 and a tenth delay circuit 4342; wherein:

[0133] The second NOR gate 4341 is used to perform a NOR logic operation on the fourth intermediate sampling signal PCS_EN and the first mode control signal EN_1N to obtain a second chip select enable signal PCS_EN2N;

[0134] The tenth delay circuit 4342 is configured to perform delayed logic processing on the second chip select enable signal PCS_EN2N through the second even clock signal PCLK_E_FAST and the third even clock signal PCLKB_E_FAST to obtain a second chip select disable signal PCS_DIS2N.

[0135] Here, the first chip select enable signal may be represented by PCS_EN1N, the first chip select disable signal may be represented by PCS_DIS1N, the second chip select enable signal may be represented by PCS_EN2N, and the second chip select disable signal may be represented by PCS_DIS2N.

[0136] The third sub-sampling circuit 431 and the fifth sub-sampling circuit 4332 are level triggers, so that the signal can be successfully sampled, thereby improving the success rate of sampling.

[0137] In some embodiments, please refer to Figure 13 , the ninth delay circuit 4322 may include a third transistor circuit 4323 and a first delay sub-circuit 4324, and the third transistor circuit 4323 includes a fifth transistor and a sixth transistor; wherein:

[0138] The first input terminal of the first NOR gate 4321 is used to receive the second mode control signal EN_2N, the second input terminal of the first NOR gate 4321 is used to receive the third intermediate sampling signal PCS_E>, the output terminal of the first NOR gate 4321 is used to output the first chip select enable signal PCS_EN1N, and the first terminal of the fifth transistor and the first terminal of the sixth transistor are both connected to the output terminal of the first NOR gate 4321, the gate terminal of the fifth transistor inputs the second clock odd signal PCLK_O_FAST, and the gate terminal of the sixth transistor inputs the third clock odd signal PCLKB_O_FAST; the second terminal of the fifth transistor and the second terminal of the sixth transistor are both connected to the input terminal of the first delay sub-circuit 4324, and the output terminal of the first delay sub-circuit 4324 is used to output the first chip select disable signal PCS_DIS1N.

[0139] like Figure 13 As shown, the tenth delay circuit 4342 may include a fourth transistor circuit 4343 and a second delay sub-circuit 4344, and the fourth transistor circuit 4343 includes a seventh transistor and an eighth transistor; wherein:

[0140] The first input terminal of the second NOR gate 4341 is used to receive the fourth intermediate sampling signal PCS_EN, the second input terminal of the second NOR gate 4341 is used to receive the first mode control signal EN_1N, the output terminal of the second NOR gate 4341 is used to output the second chip select enable signal PCS_EN2N, and the first terminal of the seventh transistor and the first terminal of the eighth transistor are both connected to the output terminal of the second NOR gate 4341, the gate terminal of the seventh transistor inputs the second clock even signal PCLK_E_FAST, and the gate terminal of the eighth transistor inputs the third clock even signal PCLKB_E_FAST; the second terminal of the seventh transistor and the second terminal of the eighth transistor are both connected to the input terminal of the second delay sub-circuit 4344, and the output terminal of the second delay sub-circuit 4344 is used to output the second chip select disable signal PCS_DIS2N.

[0141] In some embodiments, the first transistor, the third transistor, the sixth transistor, and the eighth transistor are NMOS transistors; and the second transistor, the fourth transistor, the fifth transistor, and the seventh transistor are PMOS transistors.

[0142] In some embodiments, please refer to Figure 14The second sampling circuit 22 also includes an eleventh delay circuit 44 and a twelfth delay circuit 45; wherein: the eleventh delay circuit 44 is used to delay the third clock odd signal PCLKB_O_FAST to obtain a fourth clock odd signal PCLKB_O_FASTD; the twelfth delay circuit 45 is used to delay the third clock even signal PCLKB_E_FAST to obtain a fourth clock even signal PCLKB_E_FASTD.

[0143] Here, the fourth clock signal includes a fourth clock odd signal and a fourth clock even signal; the fourth clock odd signal can be represented by PCLKB_O_FASTD, and the fourth clock even signal can be represented by PCLKB_E_FASTD.

[0144] It is worth noting that, similar to the first sampling circuit 21, the second sampling circuit 22 may also include an odd circuit and an even circuit. Figures 11 to 14 Only the even circuit in the second sampling circuit 22 is shown; the odd circuit in the second sampling circuit 22 is similar to the even circuit, and the difference between the two is that the odd and even of the input signal are opposite, which will not be repeated here.

[0145] In some embodiments, Figure 6 Based on the sampling judgment circuit 23 shown, as Figure 15 As shown, the sampling judgment circuit 23 may include a first sampling judgment circuit 51 and a second sampling judgment circuit 52; wherein:

[0146] The first sampling judgment circuit 51 is used to perform a logic operation according to the first group of chip select enable signals, the second group of chip select enable signals, the fourth clock odd signal, the fourth clock even signal, the first target chip select clock signal and the second target chip select clock signal to generate a non-target chip command decoding sampling signal;

[0147] The second sampling judgment circuit 52 is used to perform logic operations based on the first group of chip select enable signals, the second group of chip select enable signals, the fourth clock odd signal, the fourth clock even signal, the first target chip select clock signal and the second target chip select clock signal to generate a normal command decoding sampling signal.

[0148] Here, the non-target chip command decoding sampling signal can be represented by PCLIK_B_ODT, and the normal command decoding sampling signal can be represented by PCLIK_B_OD. It should be noted that the circuit structures of the first sampling judgment circuit 51 and the second sampling judgment circuit 52 are slightly different. The former is used to generate the non-target chip command decoding sampling signal, and the latter is used to generate the normal command decoding sampling signal.

[0149] In some embodiments, Figure 15Based on the first sampling judgment circuit 51 and the second sampling judgment circuit 52, as shown in FIG. Figure 16 As shown, the first sampling judgment circuit 51 includes a first sub-sampling judgment circuit 511, a second sub-sampling judgment circuit 512 and a sixth OR gate 513; wherein:

[0150] The first sub-sampling judgment circuit 511 is configured to perform a logic operation on the first chip select enable signal, the first chip select disable signal, the fourth clock odd signal, and the first target chip select clock signal to obtain a fifth intermediate sampling signal;

[0151] The second sub-sampling judgment circuit 512 is configured to perform a logic operation on the second chip select enable signal, the second chip select disable signal, the fourth clock even signal, and the second target chip select clock signal to obtain a sixth intermediate sampling signal;

[0152] The sixth OR gate 513 is configured to perform an OR logic operation on the fifth intermediate sampling signal and the sixth intermediate sampling signal to obtain a non-target chip command decoding sampling signal.

[0153] In a specific embodiment, please refer to Figure 17 The first sub-sampling judgment circuit 511 may include a third OR gate 5111, a third AND gate 5112, and a fourth AND gate 5113; wherein:

[0154] The third OR gate 5111 is used to perform an OR logic operation on the first chip select enable signal PCS_EN1N and the first chip select disable signal PCS_DIS1N to obtain a first intermediate sub-sampling signal. The third AND gate 5112 is used to perform an AND logic operation on the fourth clock odd signal PCLKB_O_FASTD and the first intermediate sub-sampling signal to obtain a second intermediate sub-sampling signal. The fourth AND gate 5113 is used to perform an AND logic operation on the second intermediate sub-sampling signal and the first target chip select clock signal CS_BLOCK_1N to obtain a fifth intermediate sampling signal.

[0155] The second sub-sampling determination circuit 512 may include a fourth OR gate 5121, a fifth AND gate 5122, and a sixth AND gate 5123. The fourth OR gate 5121 is configured to perform an OR logic operation on the second chip select enable signal PCS_EN2N and the second chip select disable signal PCS_DIS2N to obtain a third intermediate sub-sampling signal. The fifth AND gate 5122 is configured to perform an AND logic operation on the fourth clock even signal PCLKB_E_FASTD and the third intermediate sub-sampling signal to obtain a fourth intermediate sub-sampling signal. The sixth AND gate 5123 is configured to perform an AND logic operation on the fourth intermediate sub-sampling signal and the second target chip select clock signal CS_BLOCK_2N to obtain a sixth intermediate sampling signal.

[0156] It should be noted that, in the embodiment of the present disclosure, in the first sampling judgment circuit 51, the fifth intermediate sampling signal and the sixth intermediate sampling signal can be generated through the logical processing of the first sub-sampling judgment circuit 511 and the second sub-sampling judgment circuit 512; then, the fifth intermediate sampling signal and the sixth intermediate sampling signal are subjected to an OR logical operation via the sixth OR gate 513, and finally the non-target chip command decoding sampling signal (represented by PCLIK_B_ODT) can be obtained.

[0157] In some embodiments, see Figure 16 The second sampling judgment circuit 52 may include a third sub-sampling judgment circuit 521, a fourth sub-sampling judgment circuit 522 and a seventh OR gate 523; wherein:

[0158] The third sub-sampling judgment circuit 521 is configured to perform a logic operation on the first chip select enable signal, the first chip select disable signal, the fourth clock odd signal, and the first target chip select clock signal to obtain a seventh intermediate sampling signal;

[0159] The fourth sub-sampling judgment circuit 522 is configured to perform a logic operation on the second chip select enable signal, the second chip select disable signal, the fourth clock even signal, and the second target chip select clock signal to obtain an eighth intermediate sampling signal;

[0160] The seventh OR gate 523 is used to perform an OR logic operation on the seventh intermediate sampling signal and the eighth intermediate sampling signal to obtain a common command decoding sampling signal.

[0161] In a specific embodiment, please continue to refer to Figure 17 The third sub-sampling judgment circuit 521 may include an eighth OR gate 5211, a seventh AND gate 5212, and a ninth OR gate 5213; wherein:

[0162] The eighth OR gate 5211 is used to perform an OR logic operation on the first chip select enable signal PCS_EN1N and the first chip select disable signal PCS_DIS1N to obtain a fifth intermediate sub-sampling signal. The seventh AND gate 5212 is used to perform an AND logic operation on the fourth clock odd signal PCLKB_O_FASTD and the fifth intermediate sub-sampling signal to obtain a sixth intermediate sub-sampling signal. The ninth OR gate 5213 is used to perform an OR logic operation on the sixth intermediate sub-sampling signal and the first target chip select clock signal CS_BLOCK_1N to obtain a seventh intermediate sampling signal.

[0163] The fourth sub-sampling determination circuit 522 may include a tenth OR gate 5221, an eighth AND gate 5222, and an eleventh OR gate 5223. The tenth OR gate 5221 is configured to perform an OR logic operation on the second chip select enable signal PCS_EN2N and the second chip select disable signal PCS_DIS2N to obtain a seventh intermediate sub-sampling signal. The eighth AND gate 5222 is configured to perform an AND logic operation on the fourth even clock signal PCLKB_E_FASTD and the seventh intermediate sub-sampling signal to obtain an eighth intermediate sub-sampling signal. The eleventh OR gate 5223 is configured to perform an OR logic operation on the eighth intermediate sub-sampling signal and the second target chip select clock signal CS_BLOCK_2N to obtain an eighth intermediate sampling signal.

[0164] It should also be noted that, in the embodiment of the present disclosure, in the second sampling judgment circuit 52, through the logic processing of the third sub-sampling judgment circuit 521 and the fourth sub-sampling judgment circuit 522, a seventh intermediate sampling signal and an eighth intermediate sampling signal can be generated; then, a logical OR operation is performed on the seventh intermediate sampling signal and the eighth intermediate sampling signal via the seventh OR gate 523, and finally a normal command decoding sampling signal (represented by PCLIK_B_OD) can be obtained.

[0165] It is worth noting that the sampling judgment circuit 23 can also include two types of circuits: odd circuits and even circuits. Figures 15 to 17 Only the even circuit in the sampling judgment circuit 23 is shown; the odd circuit in the sampling judgment circuit 23 is similar to the even circuit, and the difference between the two is that the parity of the input signal is opposite, which will not be repeated here.

[0166] In short, in the embodiment of the present disclosure, the sampling judgment circuit 23 generates a normal command decoding sampling signal corresponding to the 2T CMD signal and a non-target chip command decoding sampling signal corresponding to the NT ODT CMD signal, thereby accurately distinguishing the 2T CMD and NT ODT CMD instructions during subsequent decoding. In addition, the invalid signals after the 2T CMD and NT ODT CMD instructions are decoded are completely covered, thereby eliminating the glitch phenomenon caused by instruction sampling and decoding in the related art, and avoiding the problem of incorrect operation execution due to instruction decoding errors.

[0167] In some embodiments, Figure 7 Based on the decoding sampling circuit 24 shown, as Figure 18 As shown, the decoding sampling circuit 24 may include a general command decoding sampling circuit 61 and a non-target chip command decoding sampling circuit 62. Figure 18 As shown, the common command decoding and sampling circuit 61 may include a common command decoding circuit 611 and a common command sampling circuit 612; wherein:

[0168] The common command decoding circuit 611 is configured to receive a chip select signal to be processed, an address signal of a command to be processed, a mode control signal, and a first chip select clock signal, and perform a logic operation on the chip select signal to be processed, the address signal of the command to be processed, the mode control signal, and the first chip select clock signal to obtain a common command signal to be decoded;

[0169] The common command sampling circuit 612 is configured to receive a common command signal to be decoded and a common command decoding sampling signal, and sample the common command signal to be decoded according to the common command decoding sampling signal to obtain a common command decoding signal.

[0170] It should be noted that in the embodiment of the present disclosure, the pending command address signal may be composed of a pending command address even signal and a pending command address odd signal, wherein the pending command address even signal is represented by CA[4:0]_E and CA[4:0]_2T_E; the pending command address odd signal is represented by CA[4:0]_O and CA[4:0]_2T_O. Here, it should be noted that CA[4:0]_E is not a single signal, but represents a group of command address signals, namely the five signals CA[0]_E to CA[4]_E; CA[4:0]_2T_E also represents a group of command address signals, namely the five signals CA[0]_2T_E to CA[4]_2T_E; CA[4:0]_O is not a single signal, but represents a group of command address signals, namely the five signals CA[0]_O to CA[4]_O; CA[4:0]_2T_O also represents a group of command address signals, namely the five signals CA[0]_2T_O to CA[4]_2T_O.

[0171] Furthermore, Figure 9 Based on the signal input circuit 70 shown, please refer to Figure 20 The signal input circuit 70 may further include a first signal input sub-circuit 701 and a second signal input sub-circuit 702 .

[0172] like Figure 20As shown, the first signal input sub-circuit 701 is used to receive the command address signal to be processed CA[4:0], the first even clock signal CLK_ET and the first odd clock signal CLK_OT, and samples the command address signal to be processed CA[4:0] through the first even clock signal CLK_ET to obtain the command address even signal to be processed CA[4:0]_E in the 1N mode, and samples the command address even signal to be processed CA[4:0]_E in the 1N mode through the first even clock signal CLK_ET to obtain the command address even signal to be processed CA[4:0]_2T_E in the 2N mode; at the same time, the command address signal to be processed CA[4:0] is sampled through the first odd clock signal CLK_OT to obtain the command address odd signal to be processed CA[4:0]_O in the 1N mode, and the command address odd signal to be processed CA[4:0]_O in the 1N mode is sampled through the first odd clock signal CLK_OT to obtain the command address odd signal to be processed CA[4:0]_2T_O in the 2N mode.

[0173] In a specific embodiment, continue to refer to Figure 20 The first signal input sub-circuit 701 may include a fifth flip-flop 715, a sixth flip-flop 716, a seventh flip-flop 717, and an eighth flip-flop 718, and the fifth flip-flop 715, the sixth flip-flop 716, the seventh flip-flop 717, and the eighth flip-flop 718 may all be D-type flip-flops; wherein:

[0174] The fifth flip-flop 715 has a clock terminal connected to the first even clock signal CLK_ET, an input terminal connected to the pending command address signal CA[4:0], and an output terminal for outputting the pending command address even signal CA[4:0]_E in 1N mode. The sixth flip-flop 716 has a clock terminal connected to the first even clock signal CLK_ET, an input terminal connected to the pending command address even signal CA[4:0]_E in 1N mode, and an output terminal for outputting the pending command address even signal CA[4:0]_2T_E in 2N mode. The seventh flip-flop 717 has a clock terminal connected to the first odd clock signal CLK_OT, an input terminal connected to the pending command address signal CA[4:0], and an output terminal for outputting the pending command address odd signal CA[4:0]_O in 1N mode. The clock end of the eighth flip-flop 718 is connected to the first clock odd signal CLK_OT, the input end is connected to the pending command address odd signal CA[4:0]_O in the 1N mode, and the output end is used to output the pending command address odd signal CA[4:0]_2T_O in the 2N mode.

[0175] like Figure 20As shown, the second signal input sub-circuit 702 is used to receive the chip select signal to be processed CS, the first clock even signal CLK_ET and the first clock odd signal CLK_OT, and to sample and process the chip select signal to be processed CS through the first clock even signal CLK_ET to obtain the chip select even signal to be processed CS_E in the 1N mode, and to sample and process the chip select even signal to be processed CS_E in the 1N mode through the first clock even signal CLK_ET to obtain the chip select even signal to be processed CS_2T_E in the 2N mode; at the same time, the chip select signal to be processed CS is sampled and processed through the first clock odd signal CLK_OT to obtain the chip select odd signal to be processed CS_O in the 1N mode, and the chip select odd signal to be processed CS_O in the 1N mode is sampled and processed through the first clock odd signal CLK_OT to obtain the chip select odd signal to be processed CS_2T_O in the 2N mode.

[0176] In a specific embodiment, continue to refer to Figure 20 The second signal input sub-circuit 702 may include a ninth flip-flop 719, a tenth flip-flop 720, an eleventh flip-flop 721, and a twelfth flip-flop 722, and the ninth flip-flop 719, the tenth flip-flop 720, the eleventh flip-flop 721, and the twelfth flip-flop 722 may all be D-type flip-flops; wherein:

[0177] The ninth flip-flop 719 has a clock terminal connected to the first even clock signal CLK_ET, an input terminal connected to the chip select signal CS to be processed, and an output terminal for outputting the chip select even signal CS_E to be processed in the 1N mode. The tenth flip-flop 720 has a clock terminal connected to the first even clock signal CLK_ET, an input terminal connected to the chip select even signal CS_E to be processed in the 1N mode, and an output terminal for outputting the chip select even signal CS_2T_E to be processed in the 2N mode. The eleventh flip-flop 721 has a clock terminal connected to the first odd clock signal CLK_OT, an input terminal connected to the chip select signal CS to be processed, and an output terminal for outputting the chip select odd signal CS_O to be processed in the 1N mode. The twelfth flip-flop 722 has a clock terminal connected to the first even clock signal CLK_ET, an input terminal connected to the chip select odd signal CS_O to be processed in the 1N mode, and an output terminal for outputting the chip select odd signal CS_2T_O to be processed in the 2N mode.

[0178] To summarize, the initial clock signals CK_t / CK_c are first divided into the parity clocks CLK_ET / OT after the receiver. CS_E is then sampled from the initial chip select signal CS_n using the parity clocks CLK_ET / OT. In DDR5, the 2T CMD and NT ODT CMD signals use the first cycle of their chip select (CA) signals as commands and addresses, while the second cycle serves as the remaining address information. Therefore, the DDR5 design requires two-stage DFF sampling, which then uses each cycle as address information. For commands, the first-stage CA is used for combinational logic decoding, specifically CS_E / O and CS_2T_E / O. The initial command address signal can be represented by CA[13:0], and the initial chip select signal can be represented by CA[13:0].

[0179] It should also be noted that different signals have corresponding decoding and sampling circuits, each of which includes both odd and even circuits. For example, 2T CMD signals include read command signals, write command signals, refresh command signals, precharge command signals, and activate command signals. The read command signal has a corresponding decoding and sampling circuit, and its corresponding decoding and sampling circuit includes both odd and even circuits; the write command signal has a corresponding decoding and sampling circuit, and its corresponding decoding and sampling circuit includes both odd and even circuits, and so on. The following describes the decoding and sampling circuit corresponding to one of the 2T CMD signals. The decoding circuits corresponding to the other signals are similar and are not further described here.

[0180] In some embodiments, Figure 18 As shown in the ordinary command decoding sampling circuit 61, Figure 19 As shown, the common command decoding and sampling circuit 61 includes a first common command decoding and sampling circuit 61a and a second common command decoding and sampling circuit 61b. Here, the first common command decoding and sampling circuit 61a includes a first common command decoding circuit 611a and a first common command sampling circuit 612a; the second common command decoding and sampling circuit 61b includes a second common command decoding circuit 611b and a second common command sampling circuit 612b.

[0181] The first common command decoding circuit 611a includes a first sub-command decoding circuit 6111a and a second sub-command decoding circuit 6112a, and the first common command sampling circuit 612a includes a first sub-command sampling circuit 6121a and a second sub-command sampling circuit 6122a. The first sub-ordinary command decoding circuit 6111a is used to receive the command address even signal CA[4:0]_E to be processed, the chip select even signal CS_E to be processed, the first mode control signal EN_1N and the first chip select clock odd signal CS_BLOCK_O to be processed in the 1N mode, and perform logical operations on the command address even signal CA[4:0]_E to be processed, the chip select even signal CS_E to be processed, the first mode control signal EN_1N and the first chip select clock odd signal CS_BLOCK_O to obtain the ordinary command even signal CMDB_E to be decoded in the 1N mode; the first sub-ordinary command sampling circuit 6121a is used to sample the ordinary command even signal CMDB_E to be decoded in the 1N mode with the ordinary command decoding sampling signal PCLIK_B_OD to obtain the ordinary command decoding even signal CMDB_ED in the 1N mode. The second sub-ordinary command decoding circuit 6112a is used to receive the command address even signal CA[4:0]_2T_E to be processed, the chip select odd signal CS_2T_E to be processed, the second mode control signal EN_2N and the first chip select clock even signal CS_BLOCK_E, and perform logical operations on the command address even signal CA[4:0]_2T_E to be processed, the chip select odd signal CS_2T_E to be processed, the second mode control signal EN_2N and the first chip select clock even signal CS_BLOCK_E to obtain the ordinary command even signal CMDB_2T_E to be decoded in the 2N mode; the second sub-ordinary command sampling circuit 6122a is used to sample the ordinary command even signal CMDB_2T_E to be decoded in the 2N mode with the ordinary command decoding sampling signal PCLIK_B_OD to obtain the ordinary command decoding even signal CMDB_2T_ED in the 2N mode.

[0182] Please continue to refer to Figure 19The second normal command decoding circuit 611b may include a third sub-normal command decoding circuit 6111b and a fourth sub-normal command decoding circuit 6112b, and the second normal command sampling circuit 612b includes a third sub-normal command sampling circuit 6121b and a fourth sub-normal command sampling circuit 6122b. The third sub-ordinary command decoding circuit 6111b is used to receive the command address odd signal CA[4:0]_O to be processed, the chip select odd signal CS_O to be processed, the first mode control signal EN_1N and the first chip select clock even signal CS_BLOCK_E, and perform logical operations on the command address odd signal CA[4:0]_O to be processed, the chip select odd signal CS_O to be processed, the first mode control signal EN_1N and the first chip select clock even signal CS_BLOCK_E to obtain the ordinary command odd signal CMDB_O to be decoded in the 1N mode; the third sub-ordinary command sampling circuit 6121b is used to sample the ordinary command odd signal CMDB_O to be decoded in the 1N mode of the ordinary command decoding sampling signal PCLIK_B_OD to obtain the ordinary command decoding odd signal CMDB_O in the 1N mode. The fourth sub-ordinary command decoding circuit 6112b is used to receive the command address odd signal CA[4:0]_2T_O to be processed, the chip select even signal CS_2T_O to be processed, the second mode control signal EN_2N and the first chip select clock odd signal CS_BLOCK_O, and perform logical operations on the command address odd signal CA[4:0]_2T_O to be processed, the chip select even signal CS_2T_O to be processed, the second mode control signal EN_2N and the first chip select clock odd signal CS_BLOCK_O to obtain the ordinary command odd signal CMDB_2T_O to be decoded in the 2N mode; the fourth sub-ordinary command sampling circuit 6122b is used to sample the ordinary command odd signal CMDB_2T_O to be decoded in the 2N mode using the ordinary command decoding sampling signal PCLIK_B_OD to obtain the ordinary command decoding odd signal CMDB_2T_OD in the 2N mode.

[0183] Since only one of the normal command decoding even signal CMDB_ED in 1N mode, the normal command decoding even signal CMDB_2T_ED in 2N mode, the normal command decoding odd signal CMDB_OD in 1N mode, and the normal command decoding odd signal CMDB_2T_OD in 2N mode is valid, these four signals are input into the fifth OR gate 63 for OR logic operation to output the final normal command decoding signal.

[0184] In addition, the first sub-command decoding circuit 6111a, the second sub-command sampling circuit 6122a, the third sub-command decoding circuit 6111b and the fourth sub-command decoding circuit 6112b are all composed of three NAND gates and one NOR gate and other logic components. Figure 19 shown.

[0185] Furthermore, if Figure 18 As shown, the non-target chip command decoding sampling circuit 62 includes a non-target chip command decoding circuit 621 and a non-target chip command sampling circuit 622; wherein: the non-target chip command decoding circuit 621 is used to receive the chip select signal to be processed, the command address signal to be processed, the mode control signal and the first chip select clock signal, and perform logical operations on the chip select signal to be processed, the command address signal to be processed, the mode control signal and the first chip select clock signal to obtain the non-target chip command signal to be decoded; the non-target chip command sampling circuit 622 is used to receive the non-target chip command signal to be decoded and the non-target chip command decoding sampling signal, and sample the non-target chip command signal to be decoded according to the non-target chip command decoding sampling signal to obtain the non-target chip command decoding signal.

[0186] It should be noted that the circuit structure of the non-target chip command decoding and sampling circuit 62 is similar to that of the ordinary command decoding and sampling circuit 61 , and will not be described in detail here.

[0187] It should also be noted that both the present embodiment and the related art use CS and CA[4:0] as combinational logic to decode the corresponding command (according to the Spec Command Truth Table). The difference is that in the related art, the CS_BLOCK_E / O signal output after the second cycle of CS sampling in the decoding circuit is directly transmitted to the decoding circuit to limit (block) the command decoded by the combination; while the present embodiment uses CS_BLOCK_E / O as logic to block the two pulse CLK sampling clocks originally transmitted to the decoding control circuit 20 to distinguish between NormalCMD and NT ODT CMD.

[0188] Thus, in the embodiment of the present disclosure, the decoding sampling circuit 24 can output a normal command decoding signal when the normal command decoding sampling signal is valid, or output a non-target chip command decoding signal when the non-target chip command decoding sampling signal is valid. In this way, the embodiment of the present disclosure uses the generated target chip select clock signal (CS_BLOCK_1N / 2N) signal to cover the two pulse sampling clocks transmitted to the decoding sampling circuit, thereby accurately distinguishing the sampling decoding of 2T CMD and NT ODT CMD, and also solving the problem that the two instructions 2T CMD and NT ODT CMD cannot be completely covered, thereby eliminating the glitch phenomenon caused by instruction sampling and decoding in the related art.

[0189] In another embodiment of the present disclosure, based on Figure 6 The decoding control circuit 20 shown, Figure 21 and Figure 22Figure 1 shows a schematic diagram of the signal timing of the decoding control circuit corresponding to 2TCMD in 1N mode. Figure 21 and Figure 22 In the figure, the first clock even signal is represented by CLK_ET, the first clock odd signal is represented by CLK_OT, the first chip select clock odd signal is represented by CS_BLOCK_O, the first intermediate sampling signal is represented by CS_BLOCK_O>, the first sub-chip select clock signal is represented by CS_BLOCK_OD, the first target chip select clock signal is represented by CS_BLOCK_1N, the first chip select clock even signal is represented by CS_BLOCK_E, the second intermediate sampling signal is represented by CS_BLOCK_E>, the second sub-chip select clock signal is represented by CS_BLOCK_ED, the second target chip select clock signal is represented by CS_BLOCK_2N, the first mode control signal is represented by EN_1N, the first chip select disable signal is represented by PCS_DIS1N, the fourth clock odd signal is represented by PCLKB_O_FASTD, the second mode control signal is represented by EN_2N, the second chip select disable signal is represented by PCS_DIS2N, and the fourth clock even signal is represented by PCLKB_E_FASTD.

[0190] In the disclosed embodiment, CS_n of the first cycle of a 2T CMD / NT ODT CMD is sampled by CLK_ET and output as PCS_E. In 1N mode, CS_n of its second cycle is sampled by CLK_OT with an increment of DFF. The two are logically ORed together to generate a signal that overwrites PCLKB_O_FASTD, thereby generating two pulse clocks used by the decoding control circuit for instruction sampling and decoding in 1N mode. Similarly, in 2N mode, CS_n of the second cycle of a 2T CMD / NT ODT CMD is sampled by CLK_ET with an increment of DFF. The two are logically ORed together to overwrite PCLKB_E_FASTD, thereby generating two pulse clocks used by the decoding control circuit for instruction sampling and decoding in 2N mode.

[0191] like Figure 21As shown, in 1N mode, the CS_BLOCK_O signal sampled and outputted during the second cycle of CS_n is incremented by one DFF level, sampled and outputted by CLK_ET, and then ORed to generate CS_BLOCK_1N. Similarly, in 2N mode, the CS_BLOCK_E signal sampled and outputted during the second cycle of CS_n is incremented by one DFF level, sampled and outputted by CLK_OT, and then ORed to generate CS_BLOCK_2N. Due to the fact that CS_n is low during the second cycle of NT ODTCMD, the CS_BLOCK_1N / 2N signals are used to cover the two pulse clocks used for instruction sampling and decoding in the decode control circuit. This allows 2T CMD and NTODT CMD to be decoded separately without affecting each other. Furthermore, the decoded information at the decode control circuit input and CS_BLOCK_1N / 2N are sampled and outputted simultaneously by CLK_ET / OT, preventing the simultaneous decoding of two different commands.

[0192] That is, in the 1N mode, after PCS_EN1N and PCS_DIS1N are subjected to an OR logic operation through the third OR gate 5111, the first intermediate sub-sampling signal ( Figure 21 The first intermediate sub-sampling signal generated is a signal with a width greater than 2T and less than 3T. After performing AND-NOR on this signal and PCLKB_O_FASTD, a valid clock signal of one and a half cycles can be obtained, so that the second intermediate sub-sampling signal output by the third AND gate 5112 can be completely covered by the first target chip select clock signal CS_BLOCK_1N, generating Figure 17 Similarly, in the 2N mode, PCS_EN2N and PCS_DIS2N are subjected to an OR logic operation through the fourth OR gate 5121 to generate the third intermediate sub-sampling signal ( Figure 21 The generated third intermediate sub-sampling signal is a signal with a width greater than 2T and less than 3T. After performing AND-NOR on this signal and PCLKB_E_FASTD, a valid clock signal of one and a half cycles can be obtained, so that the fourth intermediate sub-sampling signal output by the fifth AND gate 5122 can be completely covered by the second target chip select clock signal CS_BLOCK_2N, generating the following: Figure 17 PCLIK_B_ODT in.

[0193] It should be noted that, since the decoding information at the input of the decoding sampling circuit and CS_BLOCK_1N / 2N are sampled and outputted by CLK_ET / OT at the same time, the 2T CMD and NT ODT CMD signals in 1N mode and 2N mode are decoded at the same time, that is, Figure 17In the circuit, at the same time, only PCLIK_B_ODT outputs in 1N mode or only PCLIK_B_ODT outputs in 2N mode.

[0194] Furthermore, since the CS_BLOCK signals (i.e., CS_BLOCK_1N and CS_BLOCK_2N) are connected to the NAND gate input of the NT ODT CMD (first sampling judgment circuit 51) and the NOR gate input of the 2T CMD (second sampling judgment circuit 52), if the current command is a 2T CMD, the CS_BLOCK_1N / 2N signals are low-level signals. Consequently, the NT ODT CMD sampling clock output signal PCLK_B_ODT is low-level signals, overriding the two clocks (PCLKB_O_FASTD and PCLKB_E_FASTD) used to capture the decoded command in the NT ODT CMD decoding circuit. At this point, the overridden output is zero, and the decoded NT ODT CMD cannot be properly output without clock capture. Conversely, the 2T CMD sampling clock PCLK_B_OD is normally output, enabling the decoded command to be captured, thereby distinguishing between the 2T CMD and the NT ODT CMD.

[0195] The present disclosure adds a DFF trigger to sample PCS_E / O and then uses NOR logic to add a high-level pulse to CS, thereby generating two pulsed CLK sampling clocks for decoding by the decoding control circuit 20. Next, based on the fact that CS_n is high in the second cycle of 2T CMD and low in the second cycle of NT ODT, the CS_BLOCK_O / E signals output from CS_n in the second cycle are sampled in 1N / 2N mode. A DFF trigger is added, and the signals are sampled again by CLK_ET and CLK_OT, respectively. Then, NOR logic is used to generate CS_BLOCK_1N / 2N signals. These two signals generated by this logic are used to overwrite the two pulsed CLK sampling clocks transmitted to the decoding control circuit 20, achieving separate decoding of 2T CMD and NT ODT CMD without affecting each other. Furthermore, because the decoded information at the input of the decoding control circuit 20 and CS_BLOCK_1N / 2N are sampled and output simultaneously by CLE_ET / OT, incomplete coverage is avoided, eliminating erroneous instruction sampling and decoding.

[0196] like Figure 22As shown, in 1N mode, the input information of the decoding control circuit 20 and CS_BLOCK_O / E are sampled and output by CLK_OT and CLK_ET respectively, resulting in a 1T CK difference. Therefore, the information input to the decoding control circuit 20 and the CS_BLOCK signal are not completely aligned, resulting in the decoding command not being fully covered, and a glitch phenomenon may occur. With the decoding control circuit 20 provided in the present disclosure, CS_n of the first cycle of 2T CMD / NTODT CMD is sampled and output as PCS_E by CLK_ET. In 1N mode, CS_n of the second cycle increases by one level DFF and is sampled by CLK_OT. The two are logically ORed to generate a signal to overwrite PCLKB_O_FASTD, generating two pulse clocks used by the decoding control circuit 20 for instruction sampling and decoding in 1N mode. Next, the CS_BLOCK_O signal, sampled and output by CS_n in the second cycle, undergoes a DFF step, is sampled and output by CLK_ET, and then outputs CS_BLOCK_1N through an OR logic process. Due to the fact that CS_n is Low in the second cycle of NT ODT CMD, the CS_BLOCK_1N signal is used to overlap the two pulse clocks used for instruction sampling and decoding in the decode control circuit. Because the decoded information at the decode control circuit's input and the CS_BLOCK_1N signal are sampled and output simultaneously by CLK_ET / OT, incomplete overlap is avoided, eliminating the glitch phenomenon caused by instruction sampling and decoding in related technologies.

[0197] That is to say, the CS_BLOCK_O signal and the signal CS_BLOCK_O> output after adding one level of DFF sampling are respectively connected to the NT ODT CMD and 2T CMD command sampling clock generation circuits after the OR logic. If the current command is 2TCMD, the CS_BLOCK_1N / 2N signal is low, then the NT ODT CMD sampling clock output signal PCLK_B_ODT is low, which can cover the two pulse clock signals within the dotted vertical line range in the ODT CMD decoding circuit. The clock signal is originally used to collect and decode commands. At this time, it is covered and the output is zero. Then the decoded ODT CMD clock-free collection cannot be output normally. On the contrary, the sampling clock PCLK_B_OD of 2T CMD is output normally, and the decoding command can be collected, thereby distinguishing 2TCMD from NT ODT CMD.

[0198] In another embodiment of the present disclosure, see Figure 23 , which shows a schematic diagram of the composition structure of a semiconductor memory 220 provided by an embodiment of the present disclosure. Figure 23 As shown, the semiconductor memory 220 may include the decoding control circuit 20 according to any one of the aforementioned embodiments.

[0199] In the embodiment of the present disclosure, the memory may be a DRAM chip.

[0200] DRAM chips can comply with not only DDR, DDR2, DDR3, DDR4, DDR5, and DDR6 memory specifications, but also LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, and LPDDR6 memory specifications, without limitation. For example, in a specific embodiment, the DRAM chip can comply with the DDR5 memory specification.

[0201] It should be noted that the embodiments of the present disclosure mainly relate to the relevant circuits for input signal sampling and instruction decoding in integrated circuit design. In the DRAM chip, the CA input serves as the control and regulation circuit after instruction and address sampling and decoding respectively. The embodiments of the present disclosure solve the problem of distinguishing NT ODT CMD and 2T CMD sampling and decoding in DDR5. Among them, the particularity that the CS_n signal of the second cycle of 2T CMD is a high level, while the CS_n signal of the second cycle of NT ODT CMD is a low level can be used here to increase the DFF sampling of the second cycle CS_n signal, and then generate the target chip select clock signal (CS_BLOCK_1N / 2N) signal through the OR-NOR logic to cover the two pulse sampling clocks transmitted to the decoding sampling circuit, thereby being able to distinguish 2T CMD and NT ODT CMD sampling and decoding without affecting each other.

[0202] In addition, it should be noted that the technical solution of the embodiment of the present disclosure can be applied to the control circuit of CA signal sampling and decoding in DRAM chips, but is not limited to this scope. Other related circuits for input signal sampling and instruction decoding can adopt this design.

[0203] Thus, in the embodiment of the present disclosure, the semiconductor memory 220 includes the decoding control circuit 20. Therefore, it can not only accurately distinguish and decode the two instructions 2T CMD and NT ODT CMD, but also completely cover the invalid signals after the two instructions are decoded, thereby eliminating the glitch phenomenon caused by instruction sampling and decoding in the related art.

[0204] The above are only preferred embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure.

[0205] It should be noted that, in this disclosure, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0206] The serial numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments.

[0207] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0208] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0209] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0210] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A decoding control circuit, characterized in that: The decoding control circuit includes a first sampling circuit, a second sampling circuit, a sampling judgment circuit and a decoding sampling circuit; wherein: The first sampling circuit is configured to receive a first clock signal and a first chip select clock signal, sample and delay the first chip select clock signal according to the first clock signal to obtain a second chip select clock signal; and perform an OR logic operation on the first chip select clock signal and the second chip select clock signal to obtain a target chip select clock signal; The second sampling circuit is configured to receive a mode control signal, a first chip select signal, and a first clock signal; delay the first clock signal to generate a second clock signal and a third clock signal, wherein the second clock signal and the third clock signal are in anti-phase relationship with each other; and sample and delay the first chip select signal according to the mode control signal, the second clock signal, and the third clock signal to generate a first group of chip select enable signals and a second group of chip select enable signals; The sampling judgment circuit is used to receive the first group of chip select enable signals, the second group of chip select enable signals, the fourth clock signal and the target chip select clock signal, perform a logic operation based on the first group of chip select clock signals, the second group of chip select clock signals, the fourth clock signal and the target chip select clock signal, and generate a normal command decoding sampling signal and a non-target chip command decoding sampling signal; The decoding sampling circuit includes a normal command decoding sampling circuit and a non-target chip command decoding sampling circuit. The normal command decoding sampling circuit is used to output a normal command decoding signal when the normal command decoding sampling signal is valid, and the non-target chip command decoding sampling circuit is used to output a non-target chip command decoding signal when the non-target chip command decoding sampling signal is valid.

2. The decoding control circuit according to claim 1, wherein: The first clock signal includes a first clock even signal and a first clock odd signal, and the first chip select clock signal includes a first chip select clock odd signal and a first chip select clock even signal; The first sampling circuit includes a first sampling logic circuit and a second sampling logic circuit; wherein: The first sampling logic circuit is configured to sample and delay the first chip select clock odd signal according to the first clock even signal to obtain a first sub-chip select clock signal; and perform an OR logic operation on the first chip select clock odd signal and the first sub-chip select clock signal to obtain a first target chip select clock signal; The second sampling logic circuit is used to sample and delay the first chip select clock even signal according to the first clock odd signal to obtain a second sub-chip select clock signal; and perform an OR logic operation on the first chip select clock even signal and the second sub-chip select clock signal to obtain a second target chip select clock signal.

3. The decoding control circuit according to claim 2, wherein: The decoding control circuit further includes a signal input circuit; wherein: The signal input circuit is used to receive an initial chip select signal, the first clock even signal and the first clock odd signal, sample and process the initial chip select signal through the first clock even signal to obtain a first chip select sampling signal, and sample and process the first chip select sampling signal through the first clock odd signal to obtain the first chip select clock odd signal; and sample and process the initial chip select signal through the first clock odd signal to obtain a second chip select sampling signal, and sample and process the second chip select sampling signal through the first clock even signal to obtain the first chip select clock even signal.

4. The decoding control circuit according to claim 2, wherein: The first sampling logic circuit includes a first sub-sampling circuit, a first delay circuit and a first OR gate; wherein: The first sub-sampling circuit is configured to sample the first chip select clock odd signal according to the first clock even signal to generate a first intermediate sampling signal; The first delay circuit is configured to perform delay processing on the first intermediate sampling signal to generate the first sub-chip select clock signal; The first OR gate is configured to perform an OR logic operation on the first sub-chip select clock signal and the first chip select clock odd signal to obtain the first target chip select clock signal; The second sampling logic circuit includes a second sub-sampling circuit, a second delay circuit and a second OR gate; wherein: The second sub-sampling circuit is configured to sample the first chip select clock even signal according to the first clock odd signal to generate a second intermediate sampling signal; The second delay circuit is used to delay the second intermediate sampling signal to generate the second sub-chip select clock signal; The second OR gate is used to perform an OR logic operation on the second sub-chip select clock signal and the first chip select clock even signal to obtain the second target chip select clock signal.

5. The decoding control circuit according to claim 4, characterized in that: The first chip select signal includes a first chip select even signal, the mode control signal includes a first mode control signal and a second mode control signal, the second clock signal includes a second clock even signal and a second clock odd signal, and the third clock signal includes a third clock even signal and a third clock odd signal; The second sampling circuit includes a third sampling logic circuit, a fourth sampling logic circuit and a fifth sampling logic circuit; wherein: The third sampling logic circuit is configured to receive the first clock odd signal and perform delay logic processing on the first clock odd signal to generate a second clock odd signal and a third clock odd signal; The fourth sampling logic circuit is configured to receive the first clock even signal and perform delayed logic processing on the first clock even signal to generate a second clock even signal and a third clock even signal; The fifth sampling logic circuit is configured to sample the first chip select even signal according to the second clock odd signal to obtain a third intermediate sampling signal; perform delayed logic processing according to the second mode control signal, the third intermediate sampling signal, the second clock odd signal, and the third clock odd signal to obtain the first group of chip select enable signals; and sample the third intermediate sampling signal according to the second clock even signal to obtain a fourth intermediate sampling signal; and perform delayed logic processing according to the first mode control signal, the fourth intermediate sampling signal, the second clock even signal, and the third clock even signal to obtain the second group of chip select enable signals.

6. The decoding control circuit according to claim 5, characterized in that: The third sampling logic circuit includes a third delay circuit, a fourth delay circuit and a fifth delay circuit; wherein: The third delay circuit is used to delay the first clock odd signal to obtain a first clock delayed odd signal; The fourth delay circuit is configured to perform a delayed logic operation on the first clock delayed odd signal to generate the second clock odd signal; The fifth delay circuit is configured to perform a delayed logic operation on the first clock delayed odd signal to generate the third clock odd signal; The fourth sampling logic circuit includes a sixth delay circuit, a seventh delay circuit and an eighth delay circuit; wherein: The sixth delay circuit is configured to delay the first clock even signal to obtain a first clock delayed even signal; The seventh delay circuit is configured to perform a delayed logic operation on the first clock delayed even signal to generate the second clock even signal; The eighth delay circuit is used to perform a delayed logic operation on the first clock delayed even signal to generate the third clock even signal.

7. The decoding control circuit according to claim 6, characterized in that: The fourth delay circuit includes an even number of first NOT gates connected in series, and the fifth delay circuit includes a first transistor circuit and a second NOT gate connected in series; wherein the delay time of the fourth delay circuit is equal to the delay time of the fifth delay circuit; The seventh delay circuit includes an even number of third NOT gates connected in series, and the eighth delay circuit includes a second transistor circuit and a fourth NOT gate connected in series; wherein the delay time of the seventh delay circuit is equal to the delay time of the eighth delay circuit.

8. The decoding control circuit according to claim 7, wherein: The first transistor circuit includes a first transistor and a second transistor; wherein: The first terminal of the first transistor and the first terminal of the second transistor are both connected to the output terminal of the third delay circuit, the gate terminal of the first transistor is connected to the power supply voltage, and the gate terminal of the second transistor is connected to the ground voltage; The second end of the first transistor and the second end of the second transistor are both connected to the input end of the second NOT gate, and the output end of the second NOT gate is used to output the third clock odd signal; The second transistor circuit includes a third transistor and a fourth transistor; wherein: The first end of the third transistor and the first end of the fourth transistor are both connected to the output end of the sixth delay circuit; the gate end of the third transistor is connected to the power supply voltage; and the gate end of the fourth transistor is connected to the ground voltage. The second end of the third transistor and the second end of the fourth transistor are both connected to the input end of the fourth NOT gate, and the output end of the fourth NOT gate is used to output the third clock even signal.

9. The decoding control circuit according to claim 8, characterized in that: The fifth sampling logic circuit includes a third sub-sampling circuit, a first enabling circuit, a fourth sub-sampling circuit and a second enabling circuit; wherein: The third sub-sampling circuit is configured to sample the first chip select even signal according to the second clock odd signal to obtain the third intermediate sampling signal; the first enabling circuit is configured to perform a logical operation of NOR on the third intermediate sampling signal and the second mode control signal to obtain a first chip select enable signal, and perform delayed logical processing on the first chip select enable signal according to the second clock odd signal and the third clock odd signal to obtain a first chip select disable signal; the first chip select enable signal and the first chip select disable signal constitute the first group of chip select enable signals; the fourth sub-sampling circuit is configured to perform an inversion operation on the third intermediate sampling signal and then sample the inverted third intermediate sampling signal using the second even clock signal to obtain the fourth intermediate sampling signal; The second enabling circuit is configured to perform a logical OR operation on the fourth intermediate sampling signal and the first mode control signal to obtain a second chip select enable signal, and perform delayed logical processing on the second chip select enable signal according to the second clock even signal and the third clock even signal to obtain a second chip select disable signal; the second chip select enable signal and the second chip select disable signal constitute the second group of chip select enable signals.

10. The decoding control circuit according to claim 9, characterized in that: The first enabling circuit includes a first NOR gate and a ninth delay circuit; wherein: The first NOR gate is used to perform a NOR logic operation on the second mode control signal and the third intermediate sampling signal to obtain the first chip select enable signal; The ninth delay circuit is configured to perform delayed logic processing on the first chip select enable signal using the second clock odd signal and the third clock odd signal to obtain the first chip select disable signal; The fourth sub-sampling circuit includes a fifth NOT gate and a fifth sub-sampling circuit; wherein: The fifth NOT gate is configured to perform a NOT logic operation on the third intermediate sampling signal to obtain an inverted third intermediate sampling signal; The fifth sub-sampling circuit is configured to sample the inverted third intermediate sampling signal using the second even clock signal to obtain the fourth intermediate sampling signal; The second enabling circuit includes a second NOR gate and a tenth delay circuit; wherein: The second NOR gate is used to perform a NOR logic operation on the fourth intermediate sampling signal and the first mode control signal to obtain the second chip select enable signal; The tenth delay circuit is used to perform delayed logic processing on the second chip select enable signal through the second clock even signal and the third clock even signal to obtain the second chip select disable signal.

11. The decoding control circuit according to claim 10, wherein: The ninth delay circuit includes a third transistor circuit and a first delay sub-circuit, and the third transistor circuit includes a fifth transistor and a sixth transistor; wherein: The first input terminal of the first NOR gate is used to receive the second mode control signal, the second input terminal of the first NOR gate is used to receive the third intermediate sampling signal, the output terminal of the first NOR gate is used to output the first chip select enable signal, and the first terminal of the fifth transistor and the first terminal of the sixth transistor are both connected to the output terminal of the first NOR gate, the gate terminal of the fifth transistor is input with the second clock odd signal, and the gate terminal of the sixth transistor is input with the third clock odd signal; The second end of the fifth transistor and the second end of the sixth transistor are both connected to the input end of the first delay sub-circuit, and the output end of the first delay sub-circuit is used to output the first chip select disable signal; The tenth delay circuit includes a fourth transistor circuit and a second delay sub-circuit, and the fourth transistor circuit includes a seventh transistor and an eighth transistor; wherein: The first input terminal of the second NOR gate is used to receive the fourth intermediate sampling signal, the second input terminal of the second NOR gate is used to receive the first mode control signal, the output terminal of the second NOR gate is used to output the second chip select enable signal, and the first terminal of the seventh transistor and the first terminal of the eighth transistor are both connected to the output terminal of the second NOR gate, the gate terminal of the seventh transistor is input with the second even clock signal, and the gate terminal of the eighth transistor is input with the third even clock signal; The second end of the seventh transistor and the second end of the eighth transistor are both connected to the input end of the second delay sub-circuit, and the output end of the second delay sub-circuit is used to output the second chip select disable signal.

12. The decoding control circuit according to claim 11, wherein: The first transistor, the third transistor, the sixth transistor and the eighth transistor are NMOS; The second transistor, the fourth transistor, the fifth transistor, and the seventh transistor are PMOS transistors.

13. The decoding control circuit according to claim 5, characterized in that: The fourth clock signal includes a fourth clock odd signal and a fourth clock even signal; The second sampling circuit further includes an eleventh delay circuit and a twelfth delay circuit; wherein: an eleventh delay circuit, configured to delay the third clock odd signal to obtain the fourth clock odd signal; The twelfth delay circuit is used to delay the third clock even signal to obtain the fourth clock even signal.

14. The decoding control circuit according to claim 9, wherein: The sampling judgment circuit includes a first sampling judgment circuit and a second sampling judgment circuit; wherein: The first sampling judgment circuit is used to perform a logic operation according to the first group of chip select enable signals, the second group of chip select enable signals, the fourth clock odd signal, the fourth clock even signal, the first target chip select clock signal and the second target chip select clock signal to generate the non-target chip command decoding sampling signal; The second sampling judgment circuit is used to perform logical operations based on the first group of chip select enable signals, the second group of chip select enable signals, the fourth clock odd signal, the fourth clock even signal, the first target chip select clock signal and the second target chip select clock signal to generate the normal command decoding sampling signal.

15. The decoding control circuit according to claim 14, wherein: The first sampling judgment circuit includes a first sub-sampling judgment circuit, a second sub-sampling judgment circuit and a sixth OR gate; wherein: The first sub-sampling judgment circuit is configured to perform a logic operation on the first chip select enable signal, the first chip select disable signal, the fourth clock odd signal, and the first target chip select clock signal to obtain a fifth intermediate sampling signal; The second sub-sampling judgment circuit is configured to perform a logic operation on the second chip select enable signal, the second chip select disable signal, the fourth clock even signal, and the second target chip select clock signal to obtain a sixth intermediate sampling signal; The sixth OR gate is used to perform an OR logic operation on the fifth intermediate sampling signal and the sixth intermediate sampling signal to obtain the non-target chip command decoding sampling signal; The second sampling judgment circuit includes a third sub-sampling judgment circuit, a fourth sub-sampling judgment circuit and a seventh OR gate; wherein: The third sub-sampling judgment circuit is configured to perform a logic operation on the first chip select enable signal, the first chip select disable signal, the fourth clock odd signal, and the first target chip select clock signal to obtain a seventh intermediate sampling signal; The fourth sub-sampling judgment circuit is configured to perform a logic operation on the second chip select enable signal, the second chip select disable signal, the fourth clock even signal, and the second target chip select clock signal to obtain an eighth intermediate sampling signal; The seventh OR gate is used to perform an OR logic operation on the seventh intermediate sampling signal and the eighth intermediate sampling signal to obtain the normal command decoding sampling signal.

16. The decoding control circuit according to claim 15, characterized in that: The first sub-sampling judgment circuit includes a third OR gate, a third AND gate and a fourth AND gate; wherein: The third OR gate is configured to perform an OR logic operation on the first chip select enable signal and the first chip select disable signal to obtain a first intermediate sub-sampling signal; The third AND gate is configured to perform an AND logic operation on the fourth clock odd signal and the first intermediate sub-sampling signal to obtain a second intermediate sub-sampling signal; The fourth AND gate is configured to perform an AND logic operation on the second intermediate sub-sampling signal and the first target chip select clock signal to obtain the fifth intermediate sampling signal; The second sub-sampling judgment circuit includes a fourth OR gate, a fifth AND gate and a sixth AND gate; wherein: The fourth OR gate is configured to perform an OR logic operation on the second chip select enable signal and the second chip select disable signal to obtain a third intermediate sub-sampling signal; The fifth AND gate is configured to perform an AND logic operation on the fourth clock even signal and the third intermediate sub-sampling signal to obtain a fourth intermediate sub-sampling signal; The sixth AND gate is configured to perform an AND logic operation on the fourth intermediate sub-sampling signal and the second target chip select clock signal to obtain the sixth intermediate sampling signal.

17. The decoding control circuit according to claim 15, wherein: The third sub-sampling judgment circuit includes an eighth OR gate, a seventh AND gate and a ninth OR gate; wherein: The eighth OR gate is configured to perform an OR logic operation on the first chip select enable signal and the first chip select disable signal to obtain a fifth intermediate sub-sampling signal; The seventh AND gate is configured to perform an AND logic operation on the fourth clock odd signal and the fifth intermediate sub-sampling signal to obtain a sixth intermediate sub-sampling signal; The ninth OR gate is configured to perform an OR logic operation on the sixth intermediate sub-sampling signal and the first target chip select clock signal to obtain the seventh intermediate sampling signal; The fourth sub-sampling judgment circuit includes a tenth OR gate, an eighth AND gate, and an eleventh OR gate; wherein: The tenth OR gate is configured to perform an OR logic operation on the second chip select enable signal and the second chip select disable signal to obtain a seventh intermediate sub-sampling signal; The eighth AND gate is configured to perform an AND logic operation on the fourth even clock signal and the seventh intermediate sub-sampling signal to obtain an eighth intermediate sub-sampling signal; The eleventh OR gate is configured to perform an OR logic operation on the eighth intermediate sub-sampling signal and the second target chip select clock signal to obtain the eighth intermediate sampling signal.

18. The decoding control circuit according to claim 14, wherein: The common command decoding and sampling circuit includes a common command decoding circuit and a common command sampling circuit; wherein: The common command decoding circuit is configured to receive a chip select signal to be processed, a command address signal to be processed, the mode control signal, and the first chip select clock signal, and perform a logic operation on the chip select signal to be processed, the command address signal to be processed, the mode control signal, and the first chip select clock signal to obtain a common command signal to be decoded; The common command sampling circuit is configured to receive the common command signal to be decoded and the common command decoding sampling signal, and sample the common command signal to be decoded according to the common command decoding sampling signal to obtain the common command decoding signal; The non-target chip command decoding and sampling circuit includes a non-target chip command decoding circuit and a non-target chip command sampling circuit; wherein: The non-target chip command decoding circuit is used to receive a chip select signal to be processed, a command address signal to be processed, the mode control signal and the first chip select clock signal, and perform a logic operation on the chip select signal to be processed, the command address signal to be processed, the mode control signal and the first chip select clock signal to obtain a non-target chip command signal to be decoded; The non-target chip command sampling circuit is used to receive the non-target chip command signal to be decoded and the non-target chip command decoding sampling signal, and sample the non-target chip command signal to be decoded according to the non-target chip command decoding sampling signal to obtain the non-target chip command decoding signal.

19. A memory, characterized in that: The method comprises the decoding control circuit according to any one of claims 1 to 18.

20. The memory according to claim 19, wherein The memory is a dynamic random access memory DRAM chip and complies with DDR5 memory specifications.

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