Semiconductor device and method for forming the same

Abstract

The present invention discloses a semiconductor device and a method for forming the same. The semiconductor device may include a substrate having a source region and a drain region, and a gate disposed above the substrate and between the source region and the drain region. A first interlayer dielectric (ILD) layer may be at least partially disposed above the substrate and the gate. A conductive field plate may be disposed above the first ILD layer. At least one drain contact may extend through the first ILD layer above the drain region and may be coupled to the conductive field plate. A drain trap structure may be disposed in the first ILD layer and adjacent to the drain region, the drain trap structure having a trench including an air gap, wherein the drain trap structure is laterally spaced from a sidewall of the gate.

Description

[0001] This invention is a divisional application of the patent application with Chinese patent application number 202110971798.4, invention name “Semiconductor device and method for forming the same”, and application date August 24, 2021. Technical Field

[0002] The present invention generally relates to semiconductor devices, and more particularly to metal oxide semiconductor field effect transistor devices and methods of forming the same. Background Art

[0003] Metal oxide semiconductor field effect transistor (MOSFET) devices have been widely used in various applications, such as power amplifiers and radio frequency (RF) switches in telecommunication devices such as smartphones. An ideal MOS device has a breakdown voltage as high as possible and a fast switching speed, while keeping the on-resistance as low as possible. However, the processing techniques used to achieve these parameters are often conflicting and therefore present a critical trade-off as it relates to the ultimate performance of the MOS device. For example, the breakdown voltage of the device can be increased by reducing the doping level in the drift well, but this reduction in the doping level in the drift well increases the on-resistance of the device. Therefore, the key to device design is to increase the breakdown voltage without increasing the on-resistance, or to reduce the on-resistance without reducing the breakdown voltage of the device.

[0004] It is desirable to provide a MOSFET device having high breakdown voltage, high switching speed, and low on-resistance and a method of forming the same. Summary of the Invention

[0005] Embodiments generally relate to semiconductor devices and methods for forming the same. According to various embodiments, a semiconductor device may include a substrate having a source region and a drain region, and a gate disposed over the substrate and between the source region and the drain region. A first interlevel dielectric (ILD) layer may be at least partially disposed over the substrate and the gate. A conductive field plate may be disposed over the first ILD layer. At least one drain contact may extend through the first ILD layer over the drain region and may be coupled to the conductive field plate. A drain captive structure may be disposed in the first ILD layer and adjacent to the drain region, the drain captive structure having a trench including an air gap, wherein the drain captive structure is laterally spaced apart from sidewalls of the gate.

[0006] According to various embodiments, a method of forming a semiconductor device is provided. The method may include providing a substrate having a source region and a drain region, a gate disposed above the substrate and between the source region and the drain region, and a first interlayer dielectric (ILD) layer disposed at least partially above the substrate and the gate. At least one drain contact extending through the first ILD layer may be formed above the drain region. The method may also include forming a conductive field plate on the first ILD layer, and forming a drain trap structure in the first ILD layer adjacent to the drain region, the drain trap structure having a trench including an air gap. The drain trap structure may be laterally spaced from a sidewall of the gate.

[0007] These and other advantages and features of the embodiments disclosed herein will become apparent by reference to the following description and accompanying drawings.In addition, it should be understood that the features of the various embodiments described herein are not mutually exclusive and can exist in various combinations and permutations. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In the accompanying drawings, similar reference characters generally refer to the same parts throughout the different views. Additionally, the drawings are not necessarily drawn to scale, with emphasis generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the invention are described with reference to the following:

[0009] Figure 1A is a cross-sectional view of an embodiment of the device;

[0010] Figure 1B is a top view of an embodiment of the device;

[0011] Figure 1C is a cross-sectional view of another embodiment of the device;

[0012] Figure 1D An exemplary SEM image of the device showing an air gap in the drain trap structure; and

[0013] Figures 2A to 2D A cross-sectional view illustrating one embodiment of steps for forming a device.

[0014] Explanation of symbols

[0015] 100 semiconductor devices

[0016] 105 substrate

[0017] 107 Device Trap

[0018] 113 Drain region

[0019] 115 Source region

[0020] 117 Second source region

[0021] 122 Gate

[0022] 122a first side wall

[0023] 122b second side wall

[0024] 124 Second Gate

[0025] 124a first side wall

[0026] 124b second side wall

[0027] 1401 Main Trap

[0028] 1402 Second Main Trap

[0029] 145 Well connection

[0030] 147 Second well connection

[0031] 150 Drift Trap

[0032] 160 first interlayer dielectric (ILD) layer

[0033] 1601 Silicide Blocking Layer

[0034] 1602 Silicide Blocking Layer

[0035] 161 Etch stop layer

[0036] 162 drain contacts

[0037] 164 body contacts

[0038] 166 body contacts

[0039] 177 Conductive Field Plate

[0040] 177a First plate section

[0041] 177b Second plate section

[0042] 179 plate opening

[0043] 180 Drain capture structure

[0044] 182 Grooves

[0045] 183 Air Gap

[0046] 184 First Ring Barrier

[0047] 186 Second Ring Barrier

[0048] 190 active area

[0049] 192 Second interlayer dielectric (ILD) layer

[0050] 197 Dielectric Part

[0051] 210 Patterned mask. DETAILED DESCRIPTION

[0052] The following detailed description is made with reference to the accompanying drawings, which illustrate specific details and embodiments in which various embodiments may be implemented. These embodiments are described in sufficient detail to enable those skilled in the art to practice them. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The various embodiments are not necessarily mutually exclusive, as some embodiments may be combined with one or more other embodiments to form new embodiments.

[0053] The various aspects of the present invention and certain features, advantages and details thereof are explained more fully below with reference to the non-limiting examples shown in the accompanying drawings. Descriptions of known materials, manufacturing tools, processing techniques, etc. are omitted so as not to unnecessarily obscure the present invention in detail. However, it should be understood that while indicating various aspects of the present invention, the detailed description and specific examples are given only as illustrations and not as limitations. According to the present invention, various replacements, modifications, additions and / or arrangements within the spirit and / or scope of the basic inventive concept will be apparent to those skilled in the art.

[0054] Approximating language, as used in this specification and claims, may be used to modify any quantitative representation that is permissibly variable without resulting in a change in the basic function to which it is related. Thus, a value modified by one or more terms (e.g., "about") is not limited to the precise value specified. In some cases, approximating language may correspond to the instrumental precision of a measurement.

[0055] The terms used herein are only used to describe specific examples and are not intended to limit the present invention. As used herein, unless the context clearly indicates otherwise, the singular forms "one", "an" and "the" are also intended to include plural forms. It should be further understood that the terms "include" (and any form of include), "have" (and any form of have), "comprise" (and any form of include) are open-ended linking verbs. Therefore, a method or device that "includes", "has", "comprises" one or more steps or elements has the one or more steps or elements, but is not limited to having only the one or more steps or elements. Similarly, the step of the method or element of the device that "includes", "has", "comprises" one or more features has the one or more features, but is not limited to having only the one or more features. In addition, a device or structure configured in a particular manner is configured at least in this manner, but may also be configured in an unlisted manner.

[0056] As used herein, the term "connected" when used to refer to two physical elements refers to a direct connection between the two physical elements. However, the term "coupled" can mean a direct connection or a connection through one or more intermediate elements.

[0057] As used herein, the terms "may" and "might be" indicate the possibility of an occurrence under a set of circumstances; the possession of a particular property, characteristic, or function; and / or qualify a verb by expressing one or more capabilities or possibilities associated with the qualifying verb. Thus, the use of "may" and "might be" indicates that the modified term is clearly appropriate, capable, or suitable for the indicated capability, function, or usage, while taking into account that the modified term may sometimes be inappropriate, incapable, or unsuitable in certain circumstances. For example, in some circumstances, an event or capability is expected, while in other circumstances, the event or capability is unlikely to occur. This distinction is reflected in the terms "may" and "might be."

[0058] Embodiments of the present invention generally relate to semiconductor devices or integrated circuits (ICs). More specifically, some embodiments relate to transistor devices having high switching performance. The transistor devices may be metal oxide semiconductor field effect transistors, such as extended drain metal oxide semiconductor (EDMOS) transistors. Other suitable transistor devices may also be useful. Such devices may be incorporated into or used with, for example, RF switches and power amplifiers.

[0059] Figure 1A A cross-sectional view of an embodiment of a semiconductor device 100 is shown. For example, the device may be an integrated circuit (IC). Other types of devices may also be useful. As shown, the device may include a substrate 105. Substrate 105 may be a semiconductor substrate, such as a silicon substrate. Other types of substrates may also be used, such as silicon germanium, germanium, gallium arsenide, or crystal-on-insulator (COI), such as silicon-on-insulator (SOI).

[0060] The substrate 105 may include a device well 107. For example, the device well 107 may be a high voltage (HV) device well. The device well 107 may be provided for devices operating in a high voltage range (e.g., in a voltage range of approximately 5 V to approximately 20 V). Other suitable voltage values may also be useful.

[0061] The drain region 113 and the source region 115 may be disposed in the substrate 105. The drain region may be an extended drain region. The drain region 113 and the source region 115 may be doped with a first polarity type dopant for a first polarity type transistor. For example, the first polarity type dopant may be a p-type dopant for a PMOS. Alternatively, the first polarity type dopant may be an n-type dopant for an NMOS. In a non-limiting example, the p-type dopant may include boron (B), aluminum (Al), indium (In), or a combination thereof, and the n-type dopant may include phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof. The drain region 113 and the source region 5 may be heavily doped regions.

[0062] A (first) gate 122 may be disposed above the substrate. The gate 122 may be disposed between the drain region 113 and the source region 115. The gate 122 may include a first sidewall 122a and a second sidewall 122b. The gate 122 may include a gate electrode above a gate dielectric. In a non-limiting example, the gate dielectric may be formed from an oxide layer such as silicon oxide, and the gate electrode may be formed from polysilicon. It may also be useful to provide other types of materials for the gate electrode and the gate dielectric. The gate 122 may also include gate spacers (not shown) on the sidewalls of the gate electrode. In a non-limiting example, the gate spacers may be dielectric spacers, such as silicon oxide spacers. Other suitable types of dielectric materials may also be useful, such as silicon nitride or a combination of dielectric materials or layers.

[0063] According to various embodiments, the drain region 113 may be spaced apart from the first sidewall 122a of the gate. The source region 115 may be disposed adjacent to the second sidewall 122b of the gate. In some embodiments, a silicide blocking layer 1601 may be disposed over the substrate between the gate 122 and the drain region 113. For example, the silicide blocking layer 1601 may extend from the first sidewall 122a of the gate 122 to the drain region 113. In some embodiments, the silicide blocking layer 1601 may extend over at least a portion of the gate 122.

[0064] A body well 1401 may be disposed in the substrate 105. The body well 1401 may be disposed proximate the second sidewall 122b of the gate 122 and extend at least partially below the first portion of the gate 122. For example, the body well 1401 may extend beyond the source region 115 and may underlap below the first side of the gate 122. As shown, the body well 1401 may surround the source region 115. For example, the body well 1401 may be lightly or moderately doped with a second polarity dopant for a first polarity type transistor. The second polarity type may be different from or opposite to the first polarity type. For example, if the first polarity type dopant is an n-type dopant, the second polarity type dopant may be a p-type dopant. Alternatively, if the first polarity type dopant is a p-type dopant, the second polarity type dopant may be an n-type dopant. For example, the body well 140 may include a p-type dopant for an n-type transistor or an n-type dopant for a p-type transistor.

[0065] A well tap 145 may be disposed within and in communication with a body well 1401 in the substrate. The body well 1401 may surround the well tap 145. The well tap 145 may be used to bias the body well 1401. The well tap 145 may be disposed adjacent to the source region 115. In some embodiments, the well tap 145 may be adjacent to the source region 115. In other embodiments, the well tap 145 may be spaced apart from the source region 115. The well tap 145 may have the same polarity type as the body well 1401. For example, the well tap 145 may be doped with a second polarity type dopant for a first polarity type transistor. For example, the well tap 145 may be doped with a p-type dopant for an n-type transistor. Alternatively, the well tap 145 may be doped with an n-type dopant for a p-type transistor. In a non-limiting embodiment, the well tap 145 may be a heavily doped region, similar to the source and drain regions.

[0066] According to various embodiments, the substrate 105 may further include a second source region 117. A second gate 124 may be further disposed on the substrate between the source region 117 and the drain region 113. The drain region 113 may be shared by the gates 122 and 124. For example, the second source region 117 may be heavily doped with a dopant of the first polarity type. The second gate 124 may include a first sidewall 124a and a second sidewall 124b. Similar to the gate 122, the second gate 124 may include a gate electrode above a gate dielectric and gate spacers (not shown) above the sidewalls of the gate electrode. The drain region 113 may be spaced apart from the first sidewall 124a of the gate. The second source region 117 may be disposed adjacent to the second sidewall 124b of the gate. In some embodiments, a silicide blocking layer 1602 may be disposed on the substrate between the second gate 124 and the drain region 113. For example, the silicide blocking layer 1602 may extend from the first sidewall 124a of the gate 124 to the drain region 113. In some embodiments, the silicide blocking layer 1602 may extend over at least a portion of the second gate 124. Similarly, the second body well 1402 may be disposed proximate the second sidewall 124b of the second gate 124 and at least partially extend below the first portion of the second gate 124. For example, the second body well 1402 may extend beyond the second source region 117 and may overlap below the first side of the second gate 124. As shown, the second body well 1402 may surround the second source region 117. The second well connection 147 may be disposed within the second body well 1402 in the substrate. The second body well 1402 may surround the second well connection 147. The second well connection 147 may be disposed proximate the second source region 117. For example, the second well connection 147 may be heavily doped with dopants of the second polarity type.

[0067] In some embodiments, metal silicide contacts may be provided on the gate, source region, drain region, and well connection (not shown). Silicide contacts may include, for example, or include, but are not limited to, nickel-based silicide, cobalt silicide (CoSi), and combinations thereof. Other suitable types of metal silicide contacts may also be useful. Silicide contacts may be used to reduce contact resistance and facilitate contact with back-end-of-line (BEOL) interconnects.

[0068] A drift well or region 150 may be disposed in the substrate 105. The drift well 150 may surround the drain region 113 and extend at least partially below the second portion of the gate 122 (and the second gate 124). The depth or bottom of the drift well 150 may be deeper than the distance from the body well 1401 and the second body well 1402 to the substrate surface. For example, the depth may depend on the design voltage of the device. The portion of the substrate below the gate 122 disposed between the source region 115 and the drift well 150 may form a channel region. Similarly, the portion of the substrate below the second gate 124 disposed between the second source region 117 and the drift well 150 may form a channel region. The drift well 150 may include a first polarity type dopant for a first polarity type transistor. For example, the drift well 150 may include an n-type dopant for an n-type transistor or a p-type dopant for a p-type transistor. The dopant concentration of the drift well 150 may be lower than the dopant concentration of the drain region 113. For example, the drift well 150 may be lightly doped. For example, the doping concentration of the drift well 150 may depend on factors such as the breakdown voltage and / or R ON Performance and other device requirements.

[0069] According to various embodiments, inner edges of the body wells 140 (body well 1401 and second body well 1402) below the gates 122 and 124 may be adjacent to an edge of the drift well 150. Other configurations of the body well 140 and the drift well 150 are also possible.

[0070] In some embodiments, device well 107 may surround or enclose body well 140, drift well 150, source region 115, second source region 117, and drain region 113. The depth or bottom of device well 107 may be below body well 140 and drift well 150. For example, device well 107 may include a second polarity type dopant for a first polarity type device. For example, device well 107 may include a p-type dopant for an n-type transistor. Alternatively, device well 107 may include an n-type dopant for a p-type transistor. Device well 107 may be lightly doped.

[0071] An interlayer dielectric (ILD) layer may be disposed over the substrate 105. The ILD may include an ILD layer including interconnects. Figure 1A As shown, a first ILD layer 160 may be disposed over the substrate 105. In a non-limiting example, the dielectric layer may be formed during back-end-of-line (BEOL) processing. The first ILD layer 160 may be formed of a dielectric material, such as silicon oxide in a non-limiting example. Other suitable types of dielectric materials may also be used. An etch stop layer 161, such as silicon nitride, may be disposed between the substrate 105 and the first ILD layer 160.

[0072] The first ILD layer 160 may include at least one drain contact 162 coupled to the drain region 113, and body contacts 164 and 166 coupled to the well connection 145 and the second well connection 147, respectively. The at least one drain contact 162 may extend through the first ILD layer 160 over the drain region 113 and may be coupled to the conductive field plate 177. The body contacts 164 and 166 may extend through the first ILD layer 160 over the well connection 145 and the second well connection 147, respectively, and may be coupled to the conductive field plate 177. In other embodiments, the first ILD layer 160 may further include a source contact (not shown) coupled to the source region 115 and the second source region 117. The body contacts and the source contacts may have the same or different biases. In the case where the body contact and the source contact have different bias voltages, the source region 115 and the well connection 145 can be separated by an isolation region. Similarly, the second source region 117 and the second well connection 147 can also be separated by another isolation region. For example, the drain contact 162 and the body contacts 164 and 166 (as well as the source contact) can be formed of a conductive material such as copper (Cu), aluminum (Al), etc. Other suitable types of conductive materials are also possible.

[0073] As shown, a conductive field plate 177 may be disposed above the first dielectric layer 170. The conductive field plate 177 may include a plate opening 179. The conductive field plate 177 may have a first plate portion 177a and a second plate portion 177b. The first plate portion 177a and the second plate portion 177b may be separated by the plate opening 179. The plate opening 179 may provide a relatively small spacing between the first plate portion 177a and the second plate portion 177b. In a non-limiting example, the width w of the plate opening 179 may be between about 150 nm and about 200 nm.

[0074] According to various embodiments, a drain trap structure 180 may be disposed in the first ILD layer 170 and adjacent to the drain region 113. The drain trap structure 180 may have a trench 182 that includes or contains an air gap 183 in the first ILD layer 160. The drain region 113 may partially overlap below the drain trap structure 180. Figure 1A As shown, the drain trap structure 180 can be laterally spaced apart from the sidewalls 122a and 122b of the gate 122. For example, the drain trap structure 180 can be offset by a predetermined distance from the first sidewall 122a of the gate 122. Similarly, the drain trap structure 180 can be laterally spaced apart from the sidewalls 124a and 124b of the second gate 124. For example, the drain trap structure 180 can be offset by a predetermined distance from the first sidewall 124a of the second gate 124.

[0075] According to various embodiments, the air gap 183 of the drain trap structure 180 may be configured to surround the drain contact 162. The drain trap structure 180 may include a first ring-type barrier 184 and a second ring-type barrier 186 defining a trench 182. The first ring-type barrier 184 and the second ring-type barrier 186 may each surround the drain contact 162. The first ring-type barrier 184 may be separated from the drain contact by a dielectric material. For example, each of the first ring-type barrier 184 and the second ring-type barrier 186 may be a rectangular ring-type barrier. However, it will be appreciated that other shapes, such as a circle or a polygon, may also be used. Each of the first ring-type barrier 184 and the second ring-type barrier 186 may be continuous and may have a closed configuration (e.g., a closed loop). The first ring-type barrier 184 and the second ring-type barrier 186 may serve as a dummy or shield to prevent portions of the dielectric material of the first ILD layer 160 from being etched during formation of the air gap in the first ILD layer 160.

[0076] According to various embodiments, the first and second annular shields 184 and 186 and the drain contact 162 (as well as the body contacts 164 and 166) can be formed of the same conductive material. In some embodiments, the conductive field plate 177 can also be formed of the same conductive material as the first and second annular shields 184 and 186 and the drain contact 162. For example, the conductive material can be a metal such as Cu or Al. In other embodiments, the conductive field plate 177, the first and second annular shields 184 and 186 and the drain contact 162 can be formed of different materials.

[0077] Figure 1B Shown Figure 1A FIG1 is a top view of an embodiment of a semiconductor device 100. A well connection, a source region, a drain region, a drift well, a second source region, and a second well connection can be formed in an active region 190 in a substrate. For ease of illustration, a conductive field plate 177 is depicted in solid lines, while a plate opening 179 in the conductive field plate 177 is depicted in dashed lines. The plate opening 179 can be relatively small and have a sufficient width to enable removal of dielectric material in the trench of the drain trap structure.

[0078] According to various embodiments, the conductive field plate 177 may extend to substantially cover the active region 195 of the device. The conductive field plate 177 may be an extended field plate. For example, the conductive field plate 177 may extend from the source side of the device to the drain side. The first plate portion 177a may cover the top surface of the body contacts 164 and 166 and the second annular barrier 186. The second plate portion 177b may cover the drain contact 162 and the top surface of the first annular barrier 184. Providing an extended field plate may increase the breakdown voltage of the device without increasing the on-resistance. For example, providing a field plate extending from the source region (and the second source region) to the drain region helps increase the breakdown voltage of the transistor by depleting charge carriers in the drift region and reducing the surface electric field of the transistor.

[0079] refer to Figure 1C , a second ILD layer 192 may be disposed over the first ILD layer 160. As shown, the second ILD layer 192 may be disposed over the conductive field plate 177. The second ILD layer 192 may be formed of a dielectric material, such as an oxide, a nitride, or a combination thereof. Other suitable types of dielectric materials are also possible. According to various embodiments, the plate opening 179 of the conductive field plate 177 squeezes the dielectric material of the second ILD layer 192 to seal the air gap of the drain trap structure 180. For example, in a non-limiting example, the plate opening 179 may have a relatively small width ranging from approximately 150 nm to approximately 200 nm, so that the dielectric material of the second ILD layer 192 deposited over the conductive field plate 177 does not extend beyond the plate opening 179. As shown, a closed or squeezed dielectric portion 197 is formed in the plate opening 179. The closed dielectric portion 197 partially fills the plate opening 179 to seal the air gap 183 and does not extend beyond the plate opening 179.

[0080] The sealing dielectric portion 197 can be formed by depositing the dielectric material of the second ILD layer 192 using a high-density plasma (HDP) process. For example, the second ILD layer 192 can be formed over the conductive field plate 177 using an HDP chemical vapor deposition (CVD) process. In the case where the second ILD layer 192 is formed of a combination of nitride and oxide, the second ILD layer 192 can be formed by depositing the nitride (e.g., high-pressure plasma enhanced CVD) followed by depositing the oxide using an HDP process. The HDP process is used to deposit dielectric material (e.g., oxide) to seal the plate opening 179, while forming an air gap or void 183 in the trench 182 and in the space of the plate opening 179 below the sealed dielectric portion 197. During the deposition of the dielectric material (e.g., oxide) of the second ILD layer 192 using the HDP process, air gaps 183 may be formed based on a deposition to sputtering (D / S) ratio of the HDP process, a width of the plate opening 179 (e.g., a critical dimension of the pitch of the conductive field plates 177), and a thickness of the conductive field plates 177. The D / S ratio of the HDP process, the width of the plate opening 179, and the thickness of the conductive field plates 177 may be selected such that the dielectric material of the second ILD layer 192 does not enter the trenches 182 of the first dielectric layer 160 during deposition, forming air gaps 183 in the trenches 182 and in the space of the plate opening 179 below the sealed dielectric portion 197. In other words, the dielectric material of the second ILD layer 192 does not “fall” into the trenches 182 of the first dielectric layer 160 based on the process conditions used for deposition (i.e., an HDP process for deposition with a higher D / S ratio, a small width of the plate opening 179, and a thickness of the conductive field plate 177).

[0081] The deposition of the dielectric material of the second ILD layer 192 using the HDP process can be performed with a relatively high D / S ratio to ensure that the air gaps 183 are formed in the trenches 182 and that the dielectric material of the second ILD layer 192 does not "fall" into the trenches 182 during deposition. The D / S ratio of the HDP process may depend on the width of the plate opening 179 (e.g., the critical dimension of the pitch of the conductive field plates 177) and the thickness of the conductive field plates 177. In a non-limiting example, if the thickness of the conductive field plates 177 is approximately 5 μm, the D / S ratio of the HDP process used to deposit the dielectric material of the second ILD layer 192 may be approximately 4 or greater. In the event that the dielectric material of the second ILD layer 192 falls into the trenches 182 during deposition over the plate opening 179, when the air gaps 183 are formed in the trenches 182, they are small and may remain in the trenches 182. Figure 1DAn exemplary SEM image of the device 100 with an air gap 183 in the drain trap structure 180 is shown.

[0082] According to various embodiments, an etch-back process may be performed after depositing oxide on the conductive field plate 177. Oxide deposition using an HDP process and etching the back side may be alternately performed over the conductive field plate 177 having a small or narrow plate opening 179. When the deposition duration (deposition time) increases and the etching duration (etch time) decreases, the dielectric material (oxide) of the second ILD layer 192 does not fill the trench 182, and an air gap 183 may be formed in the trench 182 and in the plate opening 179 below the sealed dielectric portion 197. In other words, the air gap 183 may be formed by controlling deposition and etching in the geometrically narrow plate opening 179 of the conductive field plate 177.

[0083] The second ILD layer 192 may also include via contacts and conductive lines interconnected to the conductive field plate 177 .

[0084] According to various embodiments, a drain trap structure having a trench filled with air in a first ILD layer (or ILD) to form an air gap may reduce or decrease the gate-drain capacitance C gd (gate-drain capacitance) and gate charge (gate charge) Q g Providing a transistor device with low gate-drain capacitance increases the switching speed of the transistor device. Furthermore, a low gate charge may be required to operate the transistor device. Furthermore, providing a conductive field plate may increase the breakdown voltage of the device without increasing the on-resistance. Thus, transistor devices according to various embodiments may advantageously have a high breakdown voltage, a low forward voltage drop, and a fast switching speed.

[0085] Figure 2A-2D A cross-sectional view of an embodiment of a process 200 for forming a semiconductor device is shown. For example, the device is similar to Figures 1A to 1C Therefore, the description of common elements may be omitted or not described in detail.

[0086] refer to Figure 2A , providing a substrate 105. The substrate 105 can be a semiconductor substrate, such as a silicon substrate in a non-limiting embodiment. The substrate can be at least partially processed. As shown, the substrate is in a processing stage, wherein at least a portion of an ILD layer has been formed over the substrate during BEOL processing. For example, a first ILD layer 160 has been formed over the substrate, covering the gate 122 and the second gate 124. The first ILD layer 160 can be formed by chemical vapor deposition (CVD). Other techniques for forming the first ILD layer 160 are also possible.

[0087] Drain contact 162 and body contacts 164 and 166 can be formed in first ILD layer 160. For example, a via opening can be formed in first ILD layer 160 using masking and etching techniques to expose well connections 145 and 147 and drain region 113. After forming the via opening, a conductive material can be deposited to fill the via opening. The conductive material can be formed, for example, by electroplating, such as electroplating or electroless plating. Other types of conductive layers or formation techniques may also be applicable. A planarization process such as chemical mechanical polishing (CMP) can be performed to remove excess conductive material, thereby forming drain contact 162 and body contacts 164 and 166 in first ILD layer 160.

[0088] According to various embodiments, a first annular barrier 184 and a second annular barrier 186 may be formed in the first ILD layer 160. The first annular barrier 184 and the second annular barrier 186 may be formed to define the trench 182 of the drain trap structure. For example, openings corresponding to the first annular barrier 184 and the second annular barrier 186 may be formed in the first ILD layer 160 using masking and etching techniques, and a conductive material may be deposited to fill the openings. A planarization process (e.g., CMP) may be performed to remove excess conductive material, thereby forming the first annular barrier 184 and the second annular barrier 186 in the first ILD layer 160. In some embodiments, the first annular barrier 184 and the second annular barrier 186 may be formed in the same process step as the drain contact 162 and the body contacts 164 and 166.

[0089] A conductive field plate 177 may be formed over the first ILD layer 160. The conductive field plate 177 may be formed by depositing a conductive material over the first ILD layer 160. A plate opening 179 may be formed in the conductive field plate 177, for example, by masking and etching techniques. The plate opening may be formed to expose the dielectric material in the trench 182.

[0090] refer to Figure 2B A patterned mask 210 (e.g., a photoresist layer) may be formed over the conductive field plate 177 to cover the conductive field plate 177 while exposing a portion of the dielectric material in the plate opening 179 and the first ILD layer 160. For example, the photoresist may be patterned by exposing it to an exposure source using a reticle having a desired pattern. After exposure, the photoresist may be developed to transfer the pattern of the reticle to the photoresist. The patterned photoresist may then be used as an etching mask to remove the dielectric material of the first ILD layer 160 in the trench 182.

[0091] According to various embodiments, the dielectric material in the trench 182 may be removed through the plate opening 179. For example, etching may be performed using vapor hydrofluoric acid (VHF) to remove the dielectric material in the trench 182 through the plate opening 179. Figure 2C As shown, trenches 182 may be filled with air. After removing the dielectric material in trenches 182, for example, in the case of a photoresist layer, the patterned mask may be removed by ashing.

[0092] A second ILD layer 192 may be formed over the conductive field plate 177, and a closed or extruded dielectric portion 197 may be formed in the plate opening 179 to seal the air gap 183 of the drain trap structure in the first ILD layer 160. The plate opening 179 extrudes the dielectric material of the second ILD layer 192 to form the closed dielectric portion 197. For example, the second ILD layer 192 may be deposited by plasma-enhanced CVD using a high-density plasma (HDP) process.

[0093] The HDP process is a plasma CVD process that includes simultaneous deposition and sputtering components and, in a non-limiting example, may use a plasma with an ion density of approximately 1011ions / cm3 or greater. In a non-limiting example, the relative levels of the combined deposition and sputtering characteristics of a high-density plasma may depend on factors such as the flow rate used to provide the gas mixture, the source power level used to maintain the plasma, and the bias power applied to the substrate. The combination of these factors can be quantified using D / S to characterize the process:

[0094]

[0095] The D / S ratio increases with increasing deposition volume and decreases with increasing sputtering volume. In the definition of D / S, the "net deposition rate" refers to the deposition rate measured when deposition and sputtering occur simultaneously. The "blanket sputter rate" is the sputtering rate measured when the process recipe is run without deposition gas; the pressure in the process chamber is adjusted to the pressure during deposition and the sputtering rate is measured on the blanket thermal oxide.

[0096] The enclosed dielectric portion 197 can be formed by depositing the dielectric material of the second ILD layer 192 over the conductive field plate 179 using an HDP process with a higher D / S ratio. In the case where the second ILD layer 192 is formed of a combination of nitride and oxide, the second ILD layer 192 can be formed by depositing the nitride and then depositing the oxide using an HDP process. For example, the deposition of the nitride can be performed using high pressure plasma enhanced CVD, such that the nitride material is aligned along the sidewalls of the plate opening 179 and / or the trench 182, but does not fill the space within the trench 182 and the plate opening 179. For example, the deposition of the oxide can be performed using an HDP process with a higher D / S ratio. According to various embodiments, an etch-back process can be performed after the oxide is deposited on the conductive field plate 177. The oxide deposition and etch-back using the HDP process can be performed alternately on a conductive field plate 177 having a small or narrow plate opening 179. When the duration of deposition (deposition time) increases and the duration of etching (etch time) decreases, the dielectric material of the second ILD layer 192 does not fill the trench 182, and an air gap 183 may be formed in the trench 182 and in the plate opening 179 under the sealed dielectric portion 197. In other words, the air gap 183 may be formed by controlling the deposition and etching of the dielectric material of the second ILD layer 192 over the geometrically narrow plate opening 179 of the conductive field plate 177. The second ILD layer may then be planarized, for example, using a CMP process.

[0097] Furthermore, conductive vias and conductive lines (not shown) may be formed in the second ILD layer 192. An optional thermal treatment may be performed after depositing the second ILD layer 192. Additional processes may be performed to complete the device. Such processes may include forming additional interconnect metal layers, final passivation, dicing, packaging, testing, and the like.

[0098] The present invention may be embodied in other specific forms without departing from the spirit or essential characteristics of the present invention. The above embodiments are therefore to be considered in all respects as illustrative rather than limiting of the invention described herein. The scope of the present invention is therefore indicated by the appended claims rather than by the foregoing description, and all variations that come within the meaning and range of equivalence of the claims are intended to be embraced therein.

Claims

1. A semiconductor device comprising: a substrate having a source region and a drain region; a gate disposed on the substrate and located between the source region and the drain region; a first interlayer dielectric (ILD) layer at least partially disposed over the substrate and the gate; a conductive field plate disposed above the first interlayer dielectric layer, wherein the conductive field plate includes a first plate portion and a second plate portion separated by a plate opening; at least one drain contact extending through the first interlayer dielectric layer above the drain region and physically coupled to the conductive field plate; a drain trap structure disposed in the first interlayer dielectric layer and partially overlying the drain region, the drain trap structure comprising a first annular barrier and a second annular barrier, wherein the first annular barrier and the second annular barrier each surround the at least one drain contact and define a trench between the first annular barrier and the second annular barrier, wherein the trench includes an air gap, and wherein the drain trap structure is laterally spaced from a sidewall of the gate; The first plate portion overlaps with and directly contacts the second annular barrier, and the second plate portion is a continuous plate that overlaps with and directly contacts the at least one drain contact and the first annular barrier.

2. The device according to claim 1, wherein The air gap is disposed between the first annular barrier and the second annular barrier around the at least one drain contact in a continuous loop.

3. The device according to claim 1, wherein The first annular barrier is separated from the at least one drain contact by a dielectric material.

4. The device according to claim 1, wherein The first annular barrier, the second annular barrier and the at least one drain contact are formed of a same conductive material.

5. The device according to claim 1, wherein The substrate further includes a second source region and a second gate disposed above the substrate and located between the second source region and the drain region.

6. The device according to claim 1, further comprising a second interlayer dielectric layer disposed above the conductive field plate, wherein The plate opening includes a sealing portion of the dielectric material of the second interlayer dielectric layer to seal the air gap in the drain trap structure.

7. The device according to claim 1, wherein The drain region overlaps below the first annular barrier.

8. The device of claim 1 , further comprising a body well, a well connection, and a drift well disposed in the substrate, wherein The body well surrounds the source region and is connected to the well and extends at least partially under the first portion of the gate, and the drift well surrounds the drain region and extends at least partially under the second portion of the gate.

9. The device according to claim 8, wherein The body well is adjacent to the drift well.

10. The device according to claim 1, wherein The first annular shield and the second annular shield each have a respective ring portion disposed between the at least one drain contact and the gate and wherein the first plate portion extends continuously from the source region to the second annular shield on the gate.

11. The device according to claim 10, wherein The first plate portion and the second plate portion are coplanar, wherein the first plate portion depends from the second annular barrier and the second plate portion is located on the drain region and extends continuously from the at least one drain contact to the first annular barrier and depends from the first annular barrier, wherein the plate opening is directly disposed on the air gap and comprises an annular shape, and wherein a width of the air gap is defined by the first annular barrier and the second annular barrier and a width of the plate opening is narrower than a width of the air gap.

12. The apparatus according to claim 11, further comprising: A well connection laterally adjoins the source region; as well as A body contact extends through the first interlayer dielectric layer, the body contact physically coupling the well to the first plate portion.

13. The device according to claim 12, wherein The at least one drain contact includes a plurality of drain contacts, and wherein the first annular barrier directly contacts the drain region, and wherein the body contact is one of a plurality of body contacts extending through the first interlayer dielectric layer, the plurality of body contacts physically coupling the well to the first plate portion.

14. A method of forming a semiconductor device, comprising: Providing a substrate having a source region and a drain region, a gate disposed over the substrate and between the source region and the drain region, and a first interlayer dielectric (ILD) layer disposed at least partially over the substrate and the gate; forming at least one drain contact extending through the first interlayer dielectric layer over the drain region; forming a conductive field plate over the first interlayer dielectric layer, wherein the conductive field plate comprises a first plate portion and a second plate portion separated by a plate opening; and forming a drain trap structure in the first interlayer dielectric layer and partially disposed over the drain region, the drain trap structure comprising a first annular barrier and a second annular barrier, wherein the first annular barrier and the second annular barrier each surround the at least one drain contact and define a trench between the first annular barrier and the second annular barrier, wherein the trench includes an air gap, and wherein the drain trap structure is laterally spaced from a sidewall of the gate; The first plate portion overlaps with and directly contacts the second annular barrier, and the second plate portion is a continuous plate that overlaps with and directly contacts the at least one drain contact and the first annular barrier.

15. The method according to claim 14, wherein The air gap is disposed between the first annular barrier and the second annular barrier around the at least one drain contact in a continuous loop.

16. The method according to claim 14, wherein The first annular barrier is separated from the at least one drain contact by a dielectric material.

17. The method according to claim 14, wherein: The first annular barrier, the second annular barrier and the at least one drain contact are formed of a same conductive material.

18. The method according to claim 14, wherein The substrate further includes a second source region and a second gate disposed above the substrate and located between the second source region and the drain region.

19. The method according to claim 14, further comprising a second interlayer dielectric layer disposed above the conductive field plate, wherein The plate opening includes a sealing portion of the dielectric material of the second interlayer dielectric layer to seal the air gap in the drain trap structure.

20. The method according to claim 14, wherein The drain region overlaps below the first annular barrier.

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