Dual-injection avalanche transistor and method of manufacturing the same

Abstract

This invention provides a dual-injection avalanche transistor and its fabrication method, which solves the problems of existing avalanche transistors having high on-state voltage drop and losses due to the need to maintain a high-field-strength collisional ionization region, and the impact of temperature rise caused by on-state losses on performance under high-repetition-rate operation. The transistor includes a collector region n... + Substrate layer, collector region n0 epitaxial layer, p-type base region layer, n + Launch zone layer, multiple p + Field ring, and located in the collector area n + The collector region p between the substrate layer and the collector region n0 epitaxial layer + The injection layer, the top of the collector region n0 epitaxial layer has multiple first annular grooves, p + The field ring is located within the first annular groove, with its top flush with the top of the epitaxial layer of the collector region n0. Collector region p + p of the injection layer + Doping concentration greater than collector region n + substrate n + Doping concentration, n + n of the launch zone layer + The doping concentration is greater than the p-type doping concentration of the p-type base layer, n + n of the launch zone layer + Doping concentration and p + p of the field ring + The doping concentration is related to the collector region n + substrate n + The doping concentrations are on the same order of magnitude.

Description

Technical Field

[0001] This invention relates to a transistor, specifically to a dual-injection avalanche transistor and its fabrication method. Background Technology

[0002] High repetition rate (HRPR) ultrafast semiconductor switches are the core devices for generating high repetition rate ultrawideband pulses, determining the performance level of high repetition rate ultrawideband systems. Ultrawideband pulse sources based on solid-state pulse power devices feature high repetition rates, compact size, light weight, and high reliability, thus enabling modularization, miniaturization, and arraying. Compared to gas switches, semiconductor switches offer higher operating frequencies, higher stability, greater controllability, and smaller size.

[0003] Currently, the following semiconductor switching devices are mainly used when constructing solid-state high repetition rate ultrawideband pulse sources: drift step recovery diode (DSRD), silicon avalanche steepening switch (SAS), photoconductive switch (PCSS), fast ionization switch (FID), and avalanche transistor switch (ABJT). Among them, when using avalanche transistor switches to construct Marx circuits, the output pulse leading edge reaches the hundreds of picoseconds, the repetition frequency is above hundreds of kilohertz, and it is easy to modularize and array for synthesis. Therefore, avalanche transistor switches are the preferred choice for constructing solid-state high repetition rate ultrawideband pulse sources.

[0004] Traditional avalanche transistors (APTs) are mostly NPN type. Their conduction process involves electrons injected into the emitter region undergoing collisional ionization in the collector region, generating electron-hole plasma. During conduction, APTs require maintaining a high electric field in the collisional ionization region, resulting in high on-state voltage drop and conduction losses. The temperature rise caused by conduction losses at high repetition rates degrades the performance of APTs or even causes them to fail, severely limiting the improvement of their repetition rate and performance. Summary of the Invention

[0005] The purpose of this invention is to solve the technical problems of existing avalanche transistors, which require maintaining a high field strength collisional ionization region during conduction, resulting in high conduction voltage drop and conduction loss, and the temperature rise caused by conduction loss under high repetition frequency operation, which leads to performance degradation or even failure of avalanche transistors. The invention provides a dual-injection avalanche transistor and its fabrication method.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] A dual-injection avalanche transistor includes a collector electrode and a collector n arranged sequentially from bottom to top. + Substrate layer, collector region n0 epitaxial layer, and p-type base region layer, n +The system comprises an emitter layer, an annular base electrode, and a plate-shaped emitter electrode; a first cavity is provided at the top center of the current collector n0 epitaxial layer; the p-type base layer is a plate structure with a second cavity, and the p-type base layer is disposed within the first cavity; the n + The emission region layer is disposed within the second concave cavity, n + The tops of both the emitter layer and the p-type base layer are flush with the top of the collector region n0 epitaxial layer; the base electrode is disposed on the top of the p-type base layer; the emitter electrode is disposed on the top of the n0 epitaxial layer. + The top of the launch zone layer; its special feature is:

[0008] It also includes the collector region p + Injection layer and multiple p + Field environment;

[0009] The current collection area p + The injection layer is set in the collector region n + Between the substrate layer and the collector region n0 epitaxial layer;

[0010] The top of the current collector region n0 epitaxial layer is coaxially disposed with multiple first annular grooves on the outside of the p-type base region layer. + The field rings are respectively disposed in multiple first ring grooves, and the p + The top of the field ring is flush with the top of the collector region n0 epitaxial layer;

[0011] The current collection area p + p of the injection layer + Doping concentration greater than collector region n + substrate n + Doping concentration; the n0 doping concentration of the epitaxial layer of the collector region n0 is less than that of the collector region n + substrate n + Doping concentration; the p-type doping concentration of the p-type base layer is greater than the n0 doping concentration of the collector region n0 epitaxial layer and less than the collector region n0 doping concentration. + substrate n + Doping concentration; the n + n of the launch zone layer + The doping concentration is greater than the p-type doping concentration of the p-type base layer; the n + n of the launch zone layer + Doping concentration and p + p of the field ring + The doping concentration is related to the collector region n + substrate n + The doping concentrations are on the same order of magnitude.

[0012] Furthermore, the current collector region p + An n is provided between the injection layer and the collector region n0 epitaxial layer. +Epitaxial layer;

[0013] The n + n of the epitaxial layer + Doping concentration and collector region p + p of the injection layer + The doping concentrations are on the same order of magnitude; the n + The thickness of the epitaxial layer is smaller than that of the collector region p. + Thickness of the injection layer.

[0014] Furthermore, the current collector region p + The injection layer consists of multiple discrete ring-shaped p + The injection region is configured such that multiple second annular grooves are coaxially arranged on the top of the n+ substrate layer of the collector region, and multiple discrete annular p+ injection regions are respectively arranged in the multiple second annular grooves, and the top of the p+ injection layer of the collector region is flush with the top of the n+ substrate layer of the collector region.

[0015] Furthermore, the current collection region n + substrate n + Doping concentration, n + n of the launch zone layer + Doping concentration and p + p of the field ring + The doping concentration is 1×10 19 cm -3 ~9×10 19 cm -3 The current collector region p + p of the injection layer + The doping concentration is the collector region n + substrate n + The doping concentration is 2 to 10 times that of the original doping concentration; the n0 doping concentration of the n0 epitaxial layer in the collector region is 1 × 10⁻⁶. 14 cm -3 ~9×10 14 cm -3 The p-type doping concentration of the p-type base layer is 1×10⁻⁶. 17 cm -3 ~9×10 17 cm -3 .

[0016] Furthermore, the width of the base region electrode is smaller than the width of the top of the p-type base region layer; the width of the emitter region electrode is smaller than n. + Width of the launch zone layer.

[0017] Furthermore, the base electrode, emitter electrode, and collector electrode are all made of metal; the collector region n + The substrate is made of silicon wafer.

[0018] The present invention also provides a method for fabricating the above-mentioned dual-injection avalanche transistor, characterized in that it includes the following steps:

[0019] Step 1: Select a collector region n with n-type doped elements. + Substrate layer; in collector region n + p-type doped ions are implanted into the interior of the substrate to form a collector region p + Injection layer; the collector region p + p of the injection layer + Doping concentration greater than collector region n + substrate n + Doping concentration;

[0020] Step 2: Using epitaxial technology, in the collector region p + A collector region n0 epitaxial layer is prepared on top of the implantation layer; the doping element of the collector region n0 epitaxial layer is an n-type dopant, and the n0 doping concentration is less than that of the collector region n. + substrate n + Doping concentration;

[0021] Step 3: Using mask implantation, p-type dopant ions are implanted into the current collector region n0 epitaxial layer prepared in step 2, sequentially forming a p-type base layer and multiple coaxial p-type dopant ions located outside the p-type base layer. + Field ring; p-type base region layer and p + The top of the field ring is flush with the top of the collector region n0 epitaxial layer;

[0022] The p-type doping concentration of the p-type base layer is greater than the n0 doping concentration of the collector region n0 epitaxial layer and less than the collector region n0 doping concentration. + substrate n + Doping concentration; the p + p of the field ring + Doping concentration and collector region n + substrate n + The doping concentrations are on the same order of magnitude;

[0023] Step 4: Using mask implantation, n-type doped ions are implanted into the p-type base layer formed in step 3 to form n-type doped ions. + The n-layer emission region; + The top of the emitter layer is flush with the top of the collector region n0 epitaxial layer; the n + n of the launch zone layer + Doping concentration and collector region n + substrate n + The doping concentrations are on the same order of magnitude;

[0024] Step 5: An electrode layer is fabricated on top of the current collector region n0 epitaxial layer prepared in Step 2. This is achieved by etching with a mask to form a base electrode located on top of the p-type base region layer. + Emitter electrode at the top of the emitter layer; thinned collector region n + The bottom of the substrate layer is continued until the preset thickness is met;

[0025] Step 6: In the thinned current collector region n + Collector electrodes are fabricated at the bottom of the substrate, and the substrate is diced to obtain a discrete dual-injection avalanche transistor.

[0026] Furthermore, step 2 also includes the step of preparing an n+ epitaxial layer;

[0027] Step 2 is as follows:

[0028] Using epitaxial technology, in the collector region p + The top of the injection layer is prepared sequentially from bottom to top using n + Epitaxial layer, collector region n0 epitaxial layer; the n + The doping element of the epitaxial layer is an n-type dopant, n + Doping concentration and collector region p + p of the injection layer + The doping concentration is on the same order of magnitude, and its thickness is smaller than that of the collector region p. + The thickness of the implanted layer; the doping element of the collector region n0 epitaxial layer is an n-type dopant, and the n0 doping concentration is less than that of the collector region n + substrate n + Doping concentration.

[0029] Further, step 1 specifically involves selecting a collector region n with n-type doped elements. + Substrate layer; implanted via mask in the collector region n + p-type dopant ions are implanted into the interior of the substrate layer to form multiple discrete ring-shaped p-type dopant ions. + Injection region; the annular p + The top of the injection region and the collector region n + The top of the substrate is flush with its p + Doping concentration greater than collector region n + substrate n + Doping concentration.

[0030] Furthermore, in steps 1 and 2, the n-type dopant element is arsenic;

[0031] In steps 1 and 3, the p-type doped ion is a boron ion;

[0032] In step 4, the n-type doped ion is an arsenic ion;

[0033] In step 5, an electrode layer is prepared on top of the current collector region n0 epitaxial layer prepared in step 2 using a metallization process.

[0034] In step 6, a metallization process is used to apply metallization to the thinned collector region n. + The current collector electrode is fabricated at the bottom of the substrate.

[0035] The beneficial effects of this invention are:

[0036] 1. This invention provides a dual-injection avalanche transistor and its fabrication method, wherein, in the collector region n + A p+ injection layer is added between the substrate layer and the n0 epitaxial layer to form a hole injection region. Compared to traditional avalanche transistors, which rely on electron-hole plasma generated by electron collision ionization to maintain a low-field quasi-neutral region after conduction, the avalanche transistor of this invention relies on the added hole injection region to provide holes after conduction. These holes, together with the electrons provided by the emitter region, maintain the low-field quasi-neutral region. Therefore, it can effectively reduce the high electric field distribution in the collector region, thereby reducing the transistor's on-state voltage (i.e., lower on-state voltage drop), reducing switching losses, improving the problem of high temperature rise under high repetition rate operation, and improving the transistor's operational reliability. The hole injection region can also provide more initial holes for collision ionization during the conduction process of the avalanche transistor, thereby accelerating the conduction speed of the avalanche transistor.

[0037] 2. In this invention, the collector region p + An n-type epitaxial layer is set between the injection layer and the collector region n0. + Epitaxial layers can increase the operating voltage of dual-injection avalanche transistors.

[0038] 3. In this invention, discrete ring p + The injection region can increase the operating voltage of a dual-injection avalanche transistor. Attached Figure Description

[0039] Figure 1 This is a cross-sectional schematic diagram of the dual-injection avalanche transistor in Embodiment 1 of the present invention;

[0040] Figure 2 This is a cross-sectional schematic diagram of the dual-injection avalanche transistor in Embodiment 2 of the present invention;

[0041] Figure 3 This is a cross-sectional schematic diagram of the dual-injection avalanche transistor in Embodiment 3 of the present invention;

[0042] Figure 4 This is an example circuit diagram of the conduction performance test application of the dual-injection avalanche transistor embodiment of the present invention;

[0043] Figure 5 This is a graph showing the output pulse curves of the dual-injection avalanche transistor in Embodiment 3 of the present invention and a conventional avalanche transistor;

[0044] Figure 6 The graph shows the conduction characteristics of the dual-injection avalanche transistor in Embodiment 3 of the present invention and a conventional avalanche transistor.

[0045] Figure 7 This is a switching power consumption curve of the dual-injection avalanche transistor in Embodiment 3 of the present invention and a conventional avalanche transistor;

[0046] Figure 8 This is a switching energy loss curve of the dual-injection avalanche transistor in Embodiment 3 of the present invention and a conventional avalanche transistor;

[0047] Figure 9 This is a temperature rise curve of the dual-injection avalanche transistor in Embodiment 3 of the present invention and a conventional avalanche transistor.

[0048] Explanation of reference numerals in the attached figures:

[0049] 1-Collector region n + Substrate, 2-collector region p + Injection layer, 20-ring p + Injection region, 3-collector region n0 epitaxial layer, 4-p-type base region layer, 5-n + Launch region layer, 6-p + Field ring, 7-base electrode, 8-emitter electrode, 9-collector electrode, 10-n + Epitaxial layer. Detailed Implementation

[0050] Example 1

[0051] like Figure 1 As shown, a dual-injection avalanche transistor includes a collector electrode 9 and a collector region n arranged sequentially from bottom to top. + Substrate layer 1, collector region n0, epitaxial layer 3, p-type base layer 4, n + Emitter layer 5, annular base electrode 7, plate-shaped emitter electrode 8, collector region p + Injection layer 2 and three p + Field ring 6. Specifically, a first cavity is provided at the top center of the collector region n0 epitaxial layer 3, and the p-type base region layer 4 is a plate structure with a second cavity. The p-type base region layer 4 is disposed in the first cavity of the collector region n0 epitaxial layer 3. + The launch zone layer 5 is located within the second recessed cavity, n + The tops of both emitter layer 5 and p-type base layer 4 are flush with the top of collector region n0 epitaxial layer 3. Base electrode 7 is disposed on top of p-type base layer 4, and the width of base electrode 7 is smaller than the width of the top of p-type base layer 4. Emitter electrode 8 is disposed on n0. + At the top of emitter layer 5, the width of emitter electrode 8 is less than n.+ Width of emitter layer 5. Collector region p. + Injection layer 2 is set in collector region n + Between substrate layer 1 and collector region n0 epitaxial layer 3. Three first annular grooves are coaxially disposed on the top of collector region n0 epitaxial layer 3 outside the p-type base region layer 4. + Field rings 6 are respectively disposed in the three first ring grooves of the epitaxial layer 3 of the collector region n0, and the three p + The top of the field ring 6 is flush with the top of the epitaxial layer 3 of the collector region n0. In this embodiment, the base electrode 7, emitter electrode 8, and collector electrode 9 are all made of metal; the collector region n0... + Substrate layer 1 is made of silicon wafer; collector region n + n of substrate layer 1 + Doping concentration, n+ emitter layer 5 + Doping concentration and p + p of the 6th ring + The doping concentration is 1×10 19 cm -3 ; collector region p + p of injection layer 2 + The doping concentration is the collector region n + Substrate layer 1 n + The doping concentration is twice that of the original layer; the n0 doping concentration of the n0 epitaxial layer 3 in the collector region is 1×10⁻⁶. 14 cm -3 The p-type doping concentration of p-type base layer 4 is 1×10⁻⁶. 17 cm -3 .

[0052] This embodiment also provides a method for fabricating the above-mentioned dual-injection avalanche transistor, including the following steps:

[0053] Step 1: Select arsenic as the dopant element, n + Doping concentration of 1×10 19 cm -3 The silicon wafer is used as the collector region n + Substrate layer 1; in collector region n + Boron ions are implanted into the interior of substrate layer 1 to form the current collector region p. + Injection layer 2; collector region p + p of injection layer 2 + The doping concentration is the collector region n + Substrate layer 1 n + The doping concentration is twice that of the implanted material, with an implantation thickness of approximately 1 μm to 3 μm.

[0054] Step 2: Using an epitaxial process, prepare a collector region n0 epitaxial layer 3 on top of the collector region p+ implantation layer 2; the dopant element of the collector region n0 epitaxial layer 3 is arsenic, and the n0 doping concentration is 1×10⁻⁶.14 cm -3 Its thickness is approximately 20μm~25μm.

[0055] Step 3: Boron ions are implanted into the current collector region n0 epitaxial layer 3 prepared in step 2 using a mask implantation method, sequentially forming a p-type base layer 4 and three coaxial p-type base layers located outside the p-type base layer 4. + Field ring 6; p-type base region layer 4 and p + The top of the field ring 6 is flush with the top of the epitaxial layer 3 of the collector region n0;

[0056] The p-type base layer 4 has a side length of approximately 260 μm and a depth of approximately 5 μm, with a p-type doping concentration of 1 × 10⁻⁶. 17 cm -3 ;p + p of the 6th ring + Doping concentration of 1×10 19 cm -3 ; Each p + The width of field ring 6 is approximately 10 μm, and the depth is approximately 5 μm. Two adjacent p + The spacing between field rings 6 is approximately 10 μm, and the p-type base layer 4 and the p-type base layer 4 are adjacent to the p-type base layer 4. + The spacing between the field rings 6 is approximately 10 μm.

[0057] Step 4: Arsenic ions are implanted into the interior of the p-type base layer 4 formed in step 3 using a mask implantation method to form an n-type base layer. + Launch zone layer 5; n + The top of the emitter layer 5 is flush with the top of the collector layer n0 epitaxial layer 3; + The emitter layer 5 has a side length of approximately 170 μm and a depth of approximately 2 μm. + Doping concentration of 1×10 19 cm -3 .

[0058] Step 5: Using a metallization process, an electrode layer is fabricated on top of the current collector region n0 epitaxial layer 3 prepared in step 2. This is then etched using a mask to form the base electrode 7 located on top of the p-type base region layer 4. + Emitter electrode 8 at the top of emitter layer 5; thinned collector region n + From the bottom of substrate 1 to the top of epitaxial layer 3 up to collector region n0 + The thickness between the bottom layers of substrate 1 is 150 μm ~ 250 μm.

[0059] Step 6: Using a metallization process, in the thinned collector region n + Collector electrode 9 is fabricated at the bottom of substrate 1, and then diced to obtain a separate dual-injection avalanche transistor with a size of 620μm×620μm.

[0060] Example 2

[0061] like Figure 2 As shown, the dual-injection avalanche transistor in this embodiment has a similar structure to the dual-injection avalanche transistor in Embodiment 1, with the difference being:

[0062] collector region p + An n is also provided between the injection layer 2 and the epitaxial layer 3 of the collector region n0. + Epitaxial layer 10, n + n of epitaxial layer 10 + The doping concentration is the collector region n + Substrate 1n + 10 times the doping concentration, n + The thickness of epitaxial layer 10 is less than that of collector region p. + The thickness of injection layer 2, n + The thickness of the epitaxial layer 10 is 0.9 μm. In this embodiment, the collector region n + n of substrate layer 1 + Doping concentration, n+ emitter layer 5 + Doping concentration and p + p of the 6th ring + The doping concentration is 9×10 19 cm -3 ; collector region p + p of injection layer 2 + The doping concentration is the collector region n + Substrate layer 1 n + The doping concentration is 10 times that of the previous layer; the n0 doping concentration of the n0 epitaxial layer 3 in the collector region is 9 × 10⁻⁶. 14 cm -3 The p-type doping concentration of p-type base layer 4 is 9 × 10⁻⁶. 17 cm -3 .

[0063] The fabrication method of the dual-injection avalanche transistor in this embodiment is similar to that in Embodiment 1, except that:

[0064] In step 1, arsenic is selected as the dopant element, n + Doping concentration is 9×10 19 cm -3 The silicon wafer is used as the collector region n + Substrate layer 1; collector region p + p of injection layer 2 + The doping concentration is the collector region n + Substrate layer 1 n + 10 times the doping concentration.

[0065] Step 2 specifically involves: using an epitaxial process, sequentially fabricating n layers from bottom to top on the top of the p+ implantation layer 2 in the collector region. + Epitaxial layer 10, collector region n0, epitaxial layer 3; n + The doping element of epitaxial layer 10 is arsenic, n + The doping concentration is the collector region n + Substrate layer 1 n + Ten times the doping concentration, its thickness is smaller than that of the collector region p. + The thickness of implanted layer 2 is 0.9 μm; the dopant element of epitaxial layer 3 in the collector region n0 is arsenic, and the n0 doping concentration is 9 × 10⁻⁶. 14 cm -3 Its thickness is approximately 20μm~25μm.

[0066] In step 3, the p-type doping concentration of the p-type base layer 4 is 9 × 10⁻⁶. 17 cm -3 ;p + p of the 6th ring + Doping concentration is 9×10 19 cm -3 .

[0067] In step 4, n+ emitter layer 5 + Doping concentration is 9×10 19 cm -3 .

[0068] Example 3

[0069] like Figure 3 As shown, the dual-injection avalanche transistor in this embodiment has a similar structure to the dual-injection avalanche transistor in Embodiment 1, with the difference being:

[0070] collector region p + Injection layer 2 consists of four discrete annular p + The injection region 20 is formed, and four second annular grooves are coaxially disposed on the top of the collector region n+ substrate layer 1. Four discrete annular p+ injection regions 20 are respectively disposed in the four second annular grooves, and the top of the collector region p+ injection layer 2 is flush with the top of the collector region n+ substrate layer 1. In this embodiment, the collector region n + n of substrate layer 1 + Doping concentration, n+ emitter layer 5 + Doping concentration and p + p of the 6th ring + The doping concentration is 5×10 19 cm -3 ; Ring p + p in injection zone 20 + The doping concentration is the collector region n + Substrate layer 1 n +Five times the doping concentration; the n0 doping concentration of the n0 epitaxial layer 3 in the collector region is 5 × 10⁻⁶. 14 cm -3 The p-type doping concentration of p-type base layer 4 is 5 × 10⁻⁶. 17 cm -3 .

[0071] This embodiment also provides a method for fabricating the above-mentioned dual-injection avalanche transistor, characterized by comprising the following steps:

[0072] Step 1: Select arsenic as the dopant element, n + Doping concentration is 5×10 19 cm -3 The silicon wafer is used as the collector region n + Substrate layer 1; The collector region n is implanted using a mask method. + Boron ions were implanted into the interior of substrate layer 1 to form four discrete and coaxial ring p-type structures. + Injection zone 20; circumferential p + The top of injection region 20 and collector region n + The top of substrate 1 is flush with its p + The doping concentration is the collector region n + Substrate layer 1 n + Five times the doping concentration, with an implantation thickness of approximately 1 μm to 3 μm, each ring p + The width of injection region 20 and the two adjacent annular p + The spacing between injection regions 20 is approximately 15 μm.

[0073] Step 2: Using an epitaxial process, prepare a collector region n0 epitaxial layer 3 on top of the collector region p+ implantation layer 2; the dopant element of the collector region n0 epitaxial layer 3 is arsenic, and the n0 doping concentration is 5 × 10⁻⁶. 14 cm -3 Its thickness is approximately 20μm~25μm.

[0074] Step 3: Boron ions are implanted into the current collector region n0 epitaxial layer 3 prepared in step 2 using a mask implantation method, sequentially forming a p-type base layer 4 and three coaxial p-type base layers located outside the p-type base layer 4. + Field ring 6; p-type base region layer 4 and p + The top of the field ring 6 is flush with the top of the epitaxial layer 3 of the collector region n0;

[0075] The p-type base layer 4 has a side length of approximately 260 μm and a depth of approximately 5 μm, with a p-type doping concentration of 5 × 10⁻⁶. 17 cm -3 ;p + p of the 6th ring + Doping concentration is 5×10 19 cm -3; Each p + The width of field ring 6 is approximately 10 μm, and the depth is approximately 5 μm. Two adjacent p + The spacing between field rings 6 is approximately 10 μm, and the p-type base layer 4 and the p-type base layer 4 are adjacent to the p-type base layer 4. + The spacing between the field rings 6 is approximately 10 μm.

[0076] Step 4: Arsenic ions are implanted into the interior of the p-type base layer 4 formed in step 3 using a mask implantation method to form an n-type base layer. + Launch zone layer 5; n + The top of emitter layer 5 is the top of collector region n0 epitaxial layer 3; the side length of emitter layer 5 is approximately 170 μm, and the depth is approximately 2 μm. + Doping concentration is 5×10 19 cm -3 .

[0077] Step 5: Using a metallization process, an electrode layer is fabricated on top of the current collector region n0 epitaxial layer 3 prepared in step 2. This is then etched using a mask to form the base electrode 7 located on top of the p-type base region layer 4. + Emitter electrode 8 at the top of emitter layer 5; thinned collector region n + From the bottom of substrate 1 to the top of epitaxial layer 3 up to collector region n0 + The thickness between the bottom layers of substrate 1 is 150 μm ~ 250 μm.

[0078] Step 6: Using a metallization process, in the thinned collector region n + Collector electrode 9 is fabricated at the bottom of substrate 1, and then diced to obtain a separate dual-injection avalanche transistor with a size of 620μm×620μm.

[0079] To verify that the dual-injection avalanche transistor provided in this embodiment can achieve the effects of reducing conduction losses and accelerating conduction speed, TCAD simulation software was used to simulate and analyze the dual-injection avalanche transistor device of this embodiment. The settings are as follows... Figure 4The application circuit shown includes a DC bias voltage source Vcc, an energy storage capacitor C0, a charging isolation resistor Rc, a discharge load transmission line TL3, a dual-injection avalanche transistor T1 (in this embodiment), an emitter voltage divider resistor Re, a trigger pulse feed transmission line TL1, and an emitter voltage measurement transmission line TL2. The base and emitter of the avalanche transistor T1 are configured to be short-circuited. Utilizing capacitor energy storage, the DC bias voltage source Vcc applies a voltage to the dual-injection avalanche transistor T1 through the charging isolation resistor Rc. The energy storage capacitor C0, the dual-injection avalanche transistor T1, the emitter voltage divider resistor Re, and the discharge load transmission line TL3 form a discharge circuit. When a negative polarity pulse is applied to the base and emitter terminals through TL1, the dual-injection avalanche transistor T1 turns on and outputs a pulse to the discharge load transmission line TL3, with a voltage of [voltage value missing]. u L , u e The emitter voltage is the voltage after voltage division by the emitter voltage divider resistor Re, measured by... u e The on-state voltage drop, switching power consumption, and energy loss of the dual-injection avalanche transistor T1 can be calculated.

[0080] Figure 5 The figures show the output pulse curves of a dual-injection avalanche transistor and a conventional avalanche transistor according to an embodiment of the present invention. Curve T1 represents the output pulse curve of the dual-injection avalanche transistor provided in this embodiment, and curve T2 represents the output pulse curve of a conventional avalanche transistor, serving as a control group. As can be seen from curves T1 and T2 in the figures, the dual-injection avalanche transistor provided in this embodiment is essentially the same as the conventional avalanche transistor in terms of output pulse width and output pulse amplitude.

[0081] Figure 6 The graphs show the turn-on characteristics of the dual-injection avalanche transistor and the conventional avalanche transistor according to an embodiment of the present invention. Figure 6 Curve T1 is the turn-on characteristic curve of the dual-injection avalanche transistor provided in this embodiment. Figure 6 Curve T2 in the figure represents the turn-on characteristic curve of a conventional avalanche transistor, serving as a control group. As can be seen from curves T1 and T2 in the figure, the dual-injection avalanche transistor provided in this embodiment has a faster turn-on speed and a lower on-state voltage drop after turn-on compared to a conventional avalanche transistor.

[0082] Figure 7 This is a switching power consumption curve of the dual-injection avalanche transistor and a conventional avalanche transistor according to an embodiment of the present invention, wherein, Figure 7 Curve T1 is the switching power consumption curve of the dual-injection avalanche transistor in this embodiment of the invention. Figure 7Curve T2 in the figure represents the switching power consumption curve of a conventional avalanche transistor, serving as a control group. As can be seen from curves T1 and T2 in the figure, the dual-injection avalanche transistor of this embodiment has a relatively high switching power consumption before conduction, but the switching power consumption and peak power consumption are significantly reduced after conduction.

[0083] Figure 8 This is a graph showing the switching energy loss curves of a dual-injection avalanche transistor and a conventional avalanche transistor according to an embodiment of the present invention. Figure 8 Curve T1 is the switching energy loss curve of the dual-injection avalanche transistor in this embodiment of the invention. Figure 8 Curve T2 in the figure represents the switching energy loss curve of a conventional avalanche transistor, serving as a control group. As can be seen from curves T1 and T2 in the figure, the switching energy loss of the dual-injection avalanche transistor in this embodiment of the invention is significantly reduced.

[0084] Figure 9 The diagram shows the device temperature rise curves of the dual-injection avalanche transistor and the conventional avalanche transistor according to an embodiment of the present invention. Figure 9 Curve T1 is the device temperature rise curve of the dual-injection avalanche transistor in this embodiment of the invention. Figure 9 Curve T2 in the figure represents the device temperature rise curve of a conventional avalanche transistor, serving as a control group. As can be seen from curves T1 and T2 in the figure, the device temperature rise of the dual-injection avalanche transistor in this embodiment of the invention is significantly reduced.

[0085] It should be noted that the performance characterization diagrams of the dual-injection avalanche transistors in Embodiments 1 and 2 are similar to those in Embodiment 3, and the performance characterization diagrams of the dual-injection avalanche transistors in Embodiment 3 can be referred to.

[0086] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present invention should be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A dual-injection avalanche transistor, comprising a collector electrode (9) and a collector n arranged sequentially from bottom to top. + Substrate layer (1), collector region n0 epitaxial layer (3), and p-type base region layer (4), n + Emitter layer (5), annular base electrode (7), plate-shaped emitter electrode (8); a first cavity is provided at the top center of the collector region n0 epitaxial layer (3), the p-type base layer (4) is a plate structure with a second cavity, and the p-type base layer (4) is disposed in the first cavity; the n + The emission layer (5) is disposed within the second cavity, n + The tops of the emitter layer (5) and the p-type base layer (4) are flush with the top of the collector region n0 epitaxial layer (3); the base electrode (7) is disposed on the top of the p-type base layer (4); the emitter electrode (8) is disposed on the top of the n0 epitaxial layer. + The top of the emission layer (5); characterized in that: It also includes the collector region p + Injection layer (2) and multiple p + Field ring (6); The current collection area p + The injection layer (2) is set in the collector region n + Between the substrate layer (1) and the collector region n0 epitaxial layer (3); The top of the current collector region n0 epitaxial layer (3) is coaxially provided with multiple first annular grooves outside the p-type base region layer (4). + The field rings (6) are respectively disposed in multiple first ring grooves, and the p + The top of the field ring (6) is flush with the top of the collector region n0 epitaxial layer (3); The current collection area p + p of the injection layer (2) + Doping concentration greater than collector region n + n of substrate layer (1) + Doping concentration; the n0 doping concentration of the collector region n0 epitaxial layer (3) is less than that of the collector region n + n of substrate layer (1) + Doping concentration; the p-type doping concentration of the p-type base layer (4) is greater than the n0 doping concentration of the collector region n0 epitaxial layer (3) and less than the collector region n0 doping concentration. + n of substrate layer (1) + Doping concentration; the n + n of the emission region layer (5) + The doping concentration is greater than the p-type doping concentration of the p-type base layer (4); the n + n of the emission region layer (5) + Doping concentration and p + p of the field ring (6) + The doping concentration is related to the collector region n + n of substrate layer (1) + The doping concentrations are on the same order of magnitude.

2. The dual-injection avalanche transistor according to claim 1, characterized in that: The current collection area p + An n-type epitaxial layer is provided between the injection layer (2) and the collector region n0 epitaxial layer (3). + Epitaxial layer (10); The n + n of the epitaxial layer (10) + Doping concentration and collector region p + p of the injection layer (2) + The doping concentrations are on the same order of magnitude; the n + The thickness of the epitaxial layer (10) is less than that of the collector region p. + The thickness of the injection layer (2).

3. The dual-injection avalanche transistor according to claim 1, characterized in that: The current collection area p + The injection layer (2) consists of multiple discrete ring p + The injection region (20) is formed, and the collector region n + The top of the substrate layer (1) is coaxially provided with multiple second annular grooves and multiple discrete annular p + The injection region (20) is respectively set in multiple second annular grooves, and the collector region p + The top of the injection layer (2) and the collector region n + The top of the substrate (1) is flush.

4. The dual-injection avalanche transistor according to claim 1, 2, or 3, characterized in that: The current collection area n + n of substrate layer (1) + Doping concentration, n + n of the emission region layer (5) + Doping concentration and p + p of the field ring (6) + The doping concentration is 1×10 19 cm -3 ~9×10 19 cm -3 The current collector region p + p of the injection layer (2) + The doping concentration is the collector region n + Substrate layer (1) n + The doping concentration is 2 to 10 times that of the original doping concentration; the n0 doping concentration of the collector region n0 epitaxial layer (3) is 1×10 14 cm -3 ~9×10 14 cm -3 The p-type doping concentration of the p-type base layer (4) is 1×10⁻⁶. 17 cm -3 ~9×10 17 cm -3 .

5. The dual-injection avalanche transistor according to claim 4, characterized in that: The width of the base region electrode (7) is smaller than the width of the top of the p-type base region layer (4); the width of the emitter electrode (8) is smaller than the width of the n-type base region layer. + The width of the emission layer (5).

6. The dual-injection avalanche transistor according to claim 5, characterized in that: The base electrode (7), emitter electrode (8), and collector electrode (9) are all made of metal; the collector electrode (9) + The substrate (1) is made of silicon wafer material.

7. A method for fabricating a dual-injection avalanche transistor according to any one of claims 1-6, characterized in that, Includes the following steps: Step 1: Select a collector region n with n-type doped elements. + Substrate (1); in collector region n + p-type doped ions are implanted into the interior of the substrate layer (1) to form the collector region p. + Injection layer (2); the collector region p + p of the injection layer (2) + Doping concentration greater than collector region n + n of substrate layer (1) + Doping concentration; Step 2: Using epitaxial technology, in the collector region p + A collector region n0 epitaxial layer (3) is prepared on top of the implantation layer (2); the doping element of the collector region n0 epitaxial layer (3) is an n-type doping element, and the n0 doping concentration is less than that of the collector region n + n of substrate layer (1) + Doping concentration; Step 3: By means of mask implantation, p-type doped ions are implanted into the epitaxial layer (3) of the current collector region n0 prepared in step 2, thereby forming a p-type base layer (4) and multiple p-type doped ions located on the outside of the p-type base layer (4) and coaxially. + Field ring (6); p-type base region layer (4) and p + The top of the field ring (6) is flush with the top of the collector region n0 epitaxial layer (3); The p-type doping concentration of the p-type base layer (4) is greater than the n0 doping concentration of the collector region n0 epitaxial layer (3) and less than the collector region n0 doping concentration. + n of substrate layer (1) + Doping concentration; the p + p of the field ring (6) + Doping concentration and collector region n + n of substrate layer (1) + The doping concentrations are on the same order of magnitude; Step 4: By means of mask implantation, n-type doped ions are implanted into the p-type base layer (4) formed in step 3 to form n + The n-phase layer (5); + The top of the emitter layer (5) is flush with the top of the collector region n0 epitaxial layer (3); the n + n of the emission region layer (5) + Doping concentration and collector region n + n of substrate layer (1) + The doping concentrations are on the same order of magnitude; Step 5: An electrode layer is prepared on top of the current collector region n0 epitaxial layer (3) prepared in step 2. The electrode is formed by etching with a mask to create a base electrode (7) located on top of the p-type base region layer (4). + Emitter electrode (8) at the top of emitter layer (5); thinned collector region n + The bottom of the substrate layer (1) is reached until the preset thickness is met; Step 6: In the thinned current collector region n + Collector electrode (9) is prepared at the bottom of substrate (1), and diced to obtain a separate dual-injection avalanche transistor.

8. The method for fabricating a dual-injection avalanche transistor according to claim 7, characterized in that, Step 2 also includes preparing n + Steps for the epitaxial layer (10); Step 2 is as follows: Using epitaxial technology, in the collector region p + The top of the injection layer (2) is prepared from bottom to top with n + Epitaxial layer (10), collector region n0 epitaxial layer (3); the n + The doping element of the epitaxial layer (10) is an n-type dopant, n + Doping concentration and collector region p + p of the injection layer (2) + The doping concentration is on the same order of magnitude, and its thickness is smaller than that of the collector region p. + The thickness of the implantation layer (2); the doping element of the collector region n0 epitaxial layer (3) is an n-type doping element, and the n0 doping concentration is less than that of the collector region n + n of substrate layer (1) + Doping concentration.

9. The method for fabricating a dual-injection avalanche transistor according to claim 7, characterized in that, Step 1 is as follows: Select the collector region n with n-type doped elements + Substrate (1); by mask implantation, in the collector region n + p-type doped ions are implanted into the interior of the substrate layer (1) to form multiple discrete ring p-type doped ions. + Injection region (20); the annular p + The top of the injection region (20) and the collector region n + The top of the substrate layer (1) is flush with its p + Doping concentration greater than collector region n + n of substrate layer (1) + Doping concentration.

10. The method for fabricating a dual-injection avalanche transistor according to claim 8 or 9, characterized in that: In steps 1 and 2, the n-type dopant element is arsenic; In steps 1 and 3, the p-type doped ion is a boron ion; In step 4, the n-type doped ion is an arsenic ion; In step 5, an electrode layer is prepared on top of the current collector region n0 epitaxial layer (3) prepared in step 2 using a metallization process; In step 6, a metallization process is used to apply metallization to the thinned collector region n. + The collector electrode (9) is prepared at the bottom of the substrate layer (1).

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