An SOI lateral power semiconductor device

Abstract

The application provides an SOI lateral power semiconductor device, and belongs to the technical field of power semiconductor devices.The application provides an SOI lateral power semiconductor device with a gate electrode plate, a channel is introduced above the gate electrode plate by arranging the gate electrode plate in the buried oxygen layer below the gate electrode, a current path is added, and the current conduction capacity of the device is improved.In addition, different design schemes are provided: the drift region electrode plate is arranged in the buried oxygen layer below the drift region to reduce the specific on-resistance;the partial-SOI lateral power semiconductor device with the gate electrode plate and the drift region electrode plate is provided to reduce the self-heating effect.The application provides the power semiconductor device with high current conduction capacity and low specific on-resistance for the SOI lateral power semiconductor device.

Description

Technical Field

[0001] The present invention belongs to the field of power semiconductors, and more particularly, relates to a lateral power semiconductor device based on SOI technology. Background Art

[0002] Laterally double-diffused metal oxide semiconductor (LDMOS) devices are widely used in various modern electronic devices due to their mature technology, easy integration, and relatively high breakdown voltage. Silicon-on-insulator (SOI) technology, with its advantages of low leakage current, good isolation performance, and low parasitic effects, has led to the widespread use of lateral power semiconductor devices in power management and RF amplifiers.

[0003] To ensure a high breakdown voltage, traditional SOI-LDMOS is often designed with a long, lightly doped drift region. The trade-off between breakdown voltage and specific on-resistance results in a high specific on-resistance. The current in the channel region also limits the current conduction capability of the entire device. The ever-evolving intelligent power IC requires the design of more efficient power devices.

[0004] Devices using a plate formed in a buried oxide layer have been proposed. For example, US Patent No. 7763518 B2 uses an induced back gate in a vertical SOI BJT and uses the minority carrier inversion layer as an intrinsic collector.

[0005] Therefore, in response to this technical background requirement, the present invention proposes an SOI lateral power semiconductor device with a gate plate and a drift region plate, aiming to increase the current conduction capability of the device and reduce the specific on-resistance by applying a bias potential to the plate. Summary of the Invention

[0006] Based on SOI technology, the present invention provides a lateral power semiconductor device with high current conduction capability and low specific on-resistance. More specifically, the device is a SOI-LDMOS device. This device deposits a positive plate in a buried oxide layer and leads it to the surface to connect to a potential, thereby inducing a new channel above the buried oxide layer with a gate plate located below the gate, thereby increasing the current conduction path. Simultaneously, the drift region plate located below the drift region can also attract majority carriers in the drift region to reduce the specific on-resistance. The gate plate located below the gate can be connected to the same potential as the gate or to a separate potential, but its potential must be sufficient to invert the induced channel. The drift region plate potential in the drift region is independently controlled, with its bias potential being greater than the gate plate potential below the gate and less than the drain metal potential to prevent internal electric field imbalance.

[0007] In order to achieve the above-mentioned purpose of the invention, the technical solution of the present invention is as follows:

[0008] The present invention provides a first SOI lateral power semiconductor device, comprising a substrate 110 of a second doping type, a first buried oxide layer 108 disposed on the substrate 110, and a first gate plate 111 disposed in the first buried oxide layer 108;

[0009] A drift region 107 of the first doping type is disposed above the first buried oxide layer 108. A body region 106 of the second doping type is disposed on the left side of the drift region 107 of the first doping type, and a drain region 109 of the first doping type is disposed on the right side. A first source region 105 of the first doping type and a second source region 118 of the second doping type are disposed in the body region 106 of the second doping type, wherein the first source region 105 of the first doping type and the second source region 118 of the second doping type are arranged tangentially in the body direction.

[0010] A gate oxide layer 103 is provided on the surface of the drift region 107 of the first doping type, a source metal 101 is provided above the first source region 105 of the first doping type and the second source region 118 of the second doping type, wherein the source metal 101 is in contact with the first source region 105 of the first doping type and the second source region 118 of the second doping type, a drain metal 104 is located above the drain region 109 of the first doping type, wherein the drain metal 104 is in contact with the drain region 109 of the first doping type, a left boundary of the gate oxide layer 103 is tangent to the right boundary of the first source region 105 of the first doping type, and the right boundary exceeds the right boundary of the body region 106 of the second doping type, and a gate 102 is provided on the gate oxide layer 103 and is located directly above the first gate plate 111;

[0011] The first gate plate 111 and the gate 102 are connected to the same potential, or are controlled separately. The bias voltage of the first gate plate 111 must ensure that the channel above the first gate plate 111 can be turned on.

[0012] As a preferred embodiment, a first drift region plate 112 is provided in the first buried oxide layer 108 , wherein the first gate plate 111 is located directly below the gate 102 , and the first drift region plate 112 is located on the right side of the first gate plate 111 and below the drift region 107 of the first doping type;

[0013] The potential of the first drift region plate 112 is independently controlled, and its bias potential is greater than the potential of the first gate plate 111 and less than the potential of the drain metal 104 .

[0014] The present invention also provides a second SOI lateral power semiconductor device, comprising a substrate 110 of a second doping type, a drift region 107 of a first doping type disposed within the substrate 110 of the second doping type, a body region 106 of a second doping type and a first partial buried oxide layer 113 disposed on the left side of the drift region 107 of the first doping type, and a drain region 109 of the first doping type disposed on the right side thereof;

[0015] A first source region 105 of the first doping type and a second source region 118 of the second doping type are disposed in the body region 106 of the second doping type, wherein the first source region 105 of the first doping type and the second source region 118 of the second doping type are arranged tangentially in the body direction;

[0016] A gate oxide layer 103 is provided on the surface of the drift region 107 of the first doping type, a source metal 101 is provided above the first source region 105 of the first doping type and the second source region 118 of the second doping type, wherein the source metal 101 is in contact with the first source region 105 of the first doping type and the second source region 118 of the second doping type, a drain metal 104 is located above the drain region 109 of the first doping type, wherein the drain metal 104 is in contact with the drain region 109 of the first doping type, a left boundary of the gate oxide layer 103 is tangent to the right boundary of the first source region 105 of the first doping type, and the right boundary exceeds the right boundary of the body region 106 of the second doping type, and a gate 102 is provided on the gate oxide layer 103;

[0017] The first portion of the buried oxide layer 113 extends beyond the first source region 105 of the first doping type on the left side and beyond the body region 106 of the second doping type on the right side. The lower side is located above the bottom of the first source region 105 of the first doping type, so as to ensure that an additional channel can be induced under the first portion of the buried oxide layer 113.

[0018] A first gate plate 111 is provided in the first portion of the buried oxide layer 113 , and the first gate plate 111 is located directly below the gate 102 ;

[0019] The first gate plate 111 and the gate 102 are connected to the same potential, or are controlled separately. The bias voltage of the first gate plate 111 must ensure that the channel above the gate plate can be turned on.

[0020] The present invention provides a third SOI lateral power semiconductor device, comprising a substrate 110 of a second doping type, a drift region 107 of a first doping type disposed within the substrate 110 of the second doping type, a body region 106 of a second doping type and a second partial buried oxide layer 120 disposed on the left side of the drift region 107 of the first doping type, and a drain region 109 of the first doping type disposed on the right side thereof;

[0021] A first source region 105 of the first doping type and a second source region 118 of the second doping type are disposed in the body region 106 of the second doping type, wherein the first source region 105 of the first doping type and the second source region 118 of the second doping type are arranged tangentially in the body direction;

[0022] A gate oxide layer 103 is provided on the surface of the drift region 107 of the first doping type, a source metal 101 is provided above the first source region 105 of the first doping type and the second source region 118 of the second doping type, wherein the source metal 101 is in contact with the first source region 105 of the first doping type and the second source region 118 of the second doping type, a drain metal 104 is located above the drain region 109 of the first doping type, wherein the drain metal 104 is in contact with the drain region 109 of the first doping type, a left boundary of the gate oxide layer 103 is tangent to the right boundary of the first source region 105 of the first doping type, and the right boundary exceeds the right boundary of the body region 106 of the second doping type, and a gate 102 is provided on the gate oxide layer 103;

[0023] The left side of the second portion of the buried oxide layer 120 exceeds the first source region 105 of the first doping type, the right side exceeds the body region 106 of the second doping type, and the bottom side is located above the bottom of the first source region 105 of the first doping type, so as to ensure that one more channel can be induced under the second portion of the buried oxide layer 120;

[0024] A first gate plate 111 and a first drift region plate 112 are provided in the second portion of the buried oxide layer 120 , wherein the first gate plate 111 is located directly below the gate 102 , and the first drift region plate 112 is located to the right of the first gate plate 111 and within the drift region 107 of the first doping type;

[0025] The first gate plate 111 and the gate 102 are connected to the same potential, or are controlled separately. The bias voltage of the first gate plate 111 must ensure that the channel above and below the gate plate can be smoothly turned on.

[0026] The potential of the first drift region plate 112 is independently controlled, and its bias potential is greater than the potential of the first gate plate 111 and less than the potential of the drain metal 104 .

[0027] The present invention provides a fourth SOI lateral power semiconductor device, comprising a substrate 110 of a second doping type, a drift region 107 of a first doping type disposed within the substrate 110 of the second doping type, a body region 106 of a second doping type and a first partial buried oxide layer 113 disposed on the left side of the drift region 107 of the first doping type, and a drain region 109 of the first doping type disposed on the right side of the drift region 107 of the first doping type;

[0028] A first source region 105 of the first doping type, a second source region 118 of the second doping type, and a well region 119 of the first doping type are provided in the body region 106 of the second doping type to prevent the first source region 105 of the first doping type and the second source region 118 of the second doping type from being unable to diffuse under the first portion of the buried oxide layer 113. The first source region 105 of the first doping type and the second source region 118 of the second doping type are located inside the well region 119 of the first doping type, and their right boundaries are tangent to the right boundary of the well region 119 of the first doping type, wherein the first source region 105 of the first doping type and the second source region 118 of the second doping type are arranged tangentially in the body direction.

[0029] A gate oxide layer 103 is provided on the surface of the drift region 107 of the first doping type, a source metal 101 is provided above the first source region 105 of the first doping type and the second source region 118 of the second doping type, wherein the source metal 101 is in contact with the first source region 105 of the first doping type and the second source region 118 of the second doping type, a drain metal 104 is located above the drain region 109 of the first doping type, wherein the drain metal 104 is in contact with the drain region 109 of the first doping type, a left boundary of the gate oxide layer 103 is tangent to the right boundary of the first source region 105 of the first doping type, and the right boundary exceeds the right boundary of the body region 106 of the second doping type, and a gate 102 is provided on the gate oxide layer 103;

[0030] The first portion of the buried oxide layer 113 extends beyond the first doping type well region 119 on the left side and beyond the second doping type body region 106 on the right side. The lower side of the first portion of the buried oxide layer 113 is located below the bottom of the first doping type first source region 105 and above the bottom of the first doping type well region 119.

[0031] A first gate plate 111 is provided in the first portion of the buried oxide layer 113 , and the first gate plate 111 is located directly below the gate 102 ;

[0032] The first gate plate 111 and the gate 102 are connected to the same potential, or are controlled separately. The bias voltage of the first gate plate 111 must ensure that the channel above the gate plate can be turned on.

[0033] The present invention provides a fifth SOI lateral power semiconductor device, comprising a substrate 110 of a second doping type, a drift region 107 of a first doping type disposed within the substrate 110 of the second doping type, a body region 106 of a second doping type and a second partial buried oxide layer 120 disposed on the left side of the drift region 107 of the first doping type, and a drain region 109 of the first doping type disposed on the right side thereof;

[0034] The first source region 105 of the first doping type, the second source region 118 of the second doping type and the well region 119 of the first doping type are arranged in the body region 106 of the second doping type to prevent the first source region 105 of the first doping type and the second source region 118 of the second doping type from diffusing below the first buried oxide layer 113, the first source region 105 of the first doping type and the second source region 118 of the second doping type are arranged in the well region 119 of the first doping type and the right boundary of the first source region 105 of the first doping type and the second source region 118 of the second doping type is tangent to the right boundary of the well region 119 of the first doping type, and the first source region 105 of the first doping type and the second source region 118 of the second doping type are arranged in the body direction;

[0035] The drift region 107 of the first doping type is provided with the gate oxide layer 103, the source metal 101 is arranged above the first source region 105 of the first doping type and the second source region 118 of the second doping type, the drain metal 104 is arranged above the drain region 109 of the first doping type, the left boundary of the gate oxide layer 103 is tangent to the right boundary of the first source region 105 of the first doping type, the right boundary exceeds the right boundary of the body region 106 of the second doping type, and the gate 102 is arranged on the gate oxide layer 103;

[0036] The second buried oxide layer 120 exceeds the well region 119 of the first doping type on the left side, exceeds the body region 106 of the second doping type on the right side and is located below the bottom of the first source region 105 of the first doping type and above the bottom of the well region 119 of the first doping type on the lower side;

[0037] The first gate plate 111 and the first drift region plate 112 are arranged in the second buried oxide layer 120, the first gate plate 111 is arranged directly below the gate 102, the first drift region plate 112 is arranged on the right side of the first gate plate 111 and in the drift region 107 of the first doping type;

[0038] The first gate plate 111 is at the same potential as the gate 102 or is separately controlled, and the bias voltage of the first gate plate 111 needs to ensure that the channel above the gate plate can be turned on;

[0039] The first drift region plate 112 is separately controlled in potential, and the bias potential is greater than the potential of the first gate plate 111 and less than the potential of the drain metal 104.

[0040] The sixth SOI lateral power semiconductor device is provided, which comprises a substrate 110 of a second doping type, a second buried oxide layer 115 arranged on the substrate, and a second gate plate 114 arranged in the second buried oxide layer 115.

[0041] A drift region 107 of the first doping type is disposed above the second buried oxide layer 115 . A body region 106 of the second doping type and a first portion of the buried oxide layer 113 are disposed on the left side of the drift region 107 of the first doping type, and a drain region 109 of the first doping type is disposed on the right side.

[0042] A first source region 105 of the first doping type, a second source region 118 of the second doping type, and a well region 119 of the first doping type are provided in the body region 106 of the second doping type, wherein the first source region 105 of the first doping type and the second source region 118 of the second doping type are arranged tangentially in the body direction, the first source region 105 of the first doping type and the second source region 118 of the second doping type are located inside the well region 119 of the first doping type, and the right boundaries of the first source region 105 and the second source region 118 of the second doping type are tangential to the right boundary of the well region 119 of the first doping type, wherein the upper boundary of the second buried oxide layer 115 exceeds the lower boundary of the well region 119 of the first doping type, so as to ensure that one more channel can be induced on the upper side of the second buried oxide layer 115;

[0043] A gate oxide layer 103 is provided on the surface of the drift region 107 of the first doping type, a source metal 101 is provided above the first source region 105 of the first doping type and the second source region 118 of the second doping type, wherein the source metal 101 is in contact with the first source region 105 of the first doping type and the second source region 118 of the second doping type, a drain metal 104 is located above the drain region 109 of the first doping type, wherein the drain metal 104 is in contact with the drain region 109 of the first doping type, a left boundary of the gate oxide layer 103 is tangent to the right boundary of the first source region 105 of the first doping type, and the right boundary exceeds the right boundary of the body region 106 of the second doping type, and a gate 102 is provided above the gate oxide layer 103;

[0044] The left boundary of the first portion of the buried oxide layer 113 exceeds the first source region 105 of the first doping type, the right side exceeds the body region 106 of the second doping type, and the bottom side is located above the bottom of the first source region 105 of the first doping type;

[0045] A first gate plate 111 is provided in the first portion of the buried oxide layer 113 , wherein the first gate plate 111 is located directly below the gate 102 and directly above the second gate plate;

[0046] The second gate plate 114 is connected to the same potential as the first gate plate 111, wherein the first gate plate 111 is connected to the same potential as the gate 102, or is controlled separately. The bias voltage of the first gate plate 111 must ensure that the channel above the gate plate can be turned on.

[0047] The present invention provides a seventh SOI lateral power semiconductor device, comprising a substrate 110 of a second doping type, a second buried oxide layer 115 disposed on the substrate, and a second gate plate 114 and a second drift region plate 116 disposed in the second buried oxide layer 115;

[0048] A drift region 107 of the first doping type is disposed above the second buried oxide layer 115 . A body region 106 of the second doping type and a second portion of the buried oxide layer 120 are disposed on the left side of the drift region 107 of the first doping type, and a drain region 109 of the first doping type is disposed on the right side.

[0049] A first source region 105 of the first doping type, a second source region 118 of the second doping type, and a well region 119 of the first doping type are provided in the body region 106 of the second doping type, wherein the first source region 105 of the first doping type and the second source region 118 of the second doping type are arranged tangentially in the body direction, the first source region 105 of the first doping type and the second source region 118 of the second doping type are located inside the well region 119 of the first doping type, and the right boundaries of the first source region 105 and the second source region 118 of the second doping type are tangential to the right boundary of the well region 119 of the first doping type, wherein the upper boundary of the second buried oxide layer 115 exceeds the lower boundary of the well region 119 of the first doping type to ensure that an additional channel can be induced on the upper side of the second buried oxide layer 115; the second gate plate 114 is located directly below the first gate plate 111, and the left and right boundaries are also tangential to the first gate plate 111;

[0050] A gate oxide layer 103 is provided on the surface of the drift region 107 of the first doping type, a source metal 101 is provided above the first source region 105 of the first doping type and the second source region 118 of the second doping type, wherein the source metal 101 is in contact with the first source region 105 of the first doping type and the second source region 118 of the second doping type, a drain metal 104 is located above the drain region 109 of the first doping type, wherein the drain metal 104 is in contact with the drain region 109 of the first doping type, and a gate 102 is provided above the gate oxide layer 103;

[0051] The left boundary of the second portion of the buried oxide layer 120 exceeds the first source region 105 of the first doping type, the right side exceeds the body region 106 of the second doping type, and the bottom side is located above the bottom of the first source region 105 of the first doping type;

[0052] A first gate plate 111 and a first drift region plate 112 are provided in the second portion of the buried oxide layer 120 , wherein the first gate plate 111 is located directly below the gate 102 and directly above the second gate plate 114 , and the first drift region plate 112 is located on the right side of the first gate plate 111 , directly above the second drift region plate 116 , and within the drift region 107 of the first doping type;

[0053] The second gate electrode plate 114 is at the same potential as the first gate electrode plate 111, wherein the first gate electrode plate 111 is at the same potential as the gate 102 or is separately controlled, and the bias voltage of the first gate electrode plate 111 ensures that the channel above the gate electrode plate can be turned on.

[0054] The second drift region electrode plate 116 is at the same potential as the first drift region electrode plate 112, wherein the potential of the first drift region electrode plate 112 is separately controlled, and the bias potential is greater than the potential of the first gate electrode plate 111 and less than the potential of the drain metal 104.

[0055] The eighth SOI lateral power semiconductor device is provided, which comprises a substrate 110 of a second doping type, a second buried oxide layer 115 arranged on the substrate, and a second gate electrode plate 114 arranged in the second buried oxide layer 115.

[0056] A drift region 107 of a first doping type is arranged above the second buried oxide layer 115, a body region 106 of a second doping type and a first partially buried oxide layer 113 are arranged in the left side of the drift region 107 of the first doping type, and a drain region 109 of the first doping type is arranged in the right side of the drift region 107 of the first doping type.

[0057] A first source region 105 of the first doping type, a second source region 118 of the second doping type, and a well region 119 of the first doping type are arranged in the body region 106 of the second doping type, wherein the first source region 105 of the first doping type and the second source region 118 of the second doping type are arranged in a tangential direction in the body region, the first source region 105 of the first doping type and the second source region 118 of the second doping type are located inside the well region 119 of the first doping type, and the right boundary of the first source region 105 of the first doping type is tangential to the right boundary of the well region 119 of the first doping type, wherein the upper boundary of the second buried oxide layer 115 exceeds the lower boundary of the well region 119 of the first doping type, so as to ensure that one more channel can be induced on the upper side of the second buried oxide layer 115.

[0058] A gate oxide layer 103 is arranged on the surface of the drift region 107 of the first doping type, a source metal 101 is arranged above the first source region 105 of the first doping type and the second source region 118 of the second doping type, wherein the source metal 101 is in contact with the first source region 105 of the first doping type and the second source region 118 of the second doping type, a drain metal 104 is arranged above the drain region 109 of the first doping type, wherein the drain metal 104 is in contact with the drain region 109 of the first doping type, the left boundary of the gate oxide layer 103 is tangential to the right boundary of the first source region 105 of the first doping type, the right boundary exceeds the right boundary of the body region 106 of the second doping type, and a gate 102 is arranged above the gate oxide layer 103.

[0059] The left boundary of the first portion of the buried oxide layer 113 exceeds the first source region 105 of the first doping type, the right boundary exceeds the body region 106 of the second doping type, and the bottom boundary is located below the bottom of the first source region 105 of the first doping type;

[0060] A first gate plate 111 is provided in the first portion of the buried oxide layer 113 , wherein the first gate plate 111 is located directly below the gate 102 and directly above the second gate plate;

[0061] The second gate plate 114 is connected to the same potential as the first gate plate 111, wherein the first gate plate 111 is connected to the same potential as the gate 102, or is controlled separately. The bias voltage of the first gate plate 111 must ensure that the channel above the gate plate can be turned on.

[0062] The present invention provides a ninth SOI lateral power semiconductor device, comprising a substrate 110 of a second doping type, a second buried oxide layer 115 disposed on the substrate, and a second gate plate 114 and a second drift region plate 116 disposed in the second buried oxide layer 115;

[0063] A drift region 107 of the first doping type is disposed above the second buried oxide layer 115 . A body region 106 of the second doping type and a second portion of the buried oxide layer 120 are disposed on the left side of the drift region 107 of the first doping type, and a drain region 109 of the first doping type is disposed on the right side.

[0064] A first source region 105 of the first doping type, a second source region 118 of the second doping type, and a well region 119 of the first doping type are provided in the body region 106 of the second doping type, wherein the first source region 105 of the first doping type and the second source region 118 of the second doping type are arranged tangentially in the body direction, the first source region 105 of the first doping type and the second source region 118 of the second doping type are located inside the well region 119 of the first doping type, and the right boundaries of the first source region 105 and the second source region 118 of the second doping type are tangential to the right boundary of the well region 119 of the first doping type, wherein the upper boundary of the second buried oxide layer 115 exceeds the lower boundary of the well region 119 of the first doping type to ensure that an additional channel can be induced on the upper side of the second buried oxide layer 115; the second gate plate 114 is located directly below the first gate plate 111, and the left and right boundaries are also tangential to the first gate plate 111;

[0065] The first doped type drift region 107 is provided with a gate oxide layer 103 on the surface, the first doped type first source region 105 and the second doped type second source region 118 are provided with a source metal 101 above, wherein the source metal 101 is in contact with the first doped type first source region 105 and the second doped type second source region 118, and a drain metal 104 is above the first doped type drain region 109, wherein the drain metal 104 is in contact with the first doped type drain region 109, and a gate 102 is above the gate oxide layer 103;

[0066] The left boundary of the second partial buried oxide layer 120 exceeds the first doped type first source region 105, the right side exceeds the second doped type body region 106, and the lower side is below the bottom of the first doped type first source region 105;

[0067] The second partial buried oxide layer 120 is provided with a first gate plate 111 and a first drift region plate 112, wherein the first gate plate 111 is directly below the gate 102 and directly above the second gate plate, and the first drift region plate 112 is to the right of the first gate plate 111, directly above the second drift region plate 116 and in the first doped type drift region 107;

[0068] The second gate plate 114 is at the same potential as the first gate plate 111, wherein the first gate plate 111 is at the same potential as the gate 102 or is separately controlled, and the bias voltage of the first gate plate 111 needs to ensure that the channel above the gate plate can be turned on;

[0069] The second drift region plate 116 is at the same potential as the first drift region plate 112, wherein the potential of the first drift region plate 112 is separately controlled, and the bias potential is greater than the potential of the first gate plate 111 and less than the potential of the drain metal 104.

[0070] The principle of the application is as follows:

[0071] As shown in FIG. 3(a), by designing a gate plate in the buried oxide layer, the gate plate and the drift region plate are led out in the manner shown in FIG. 2(b) and led out to the surface, and the top view of the device is shown in FIG. 3(b), the gate plate directly below the gate can be at the same potential as the gate or can be separately controlled, a body region above the gate plate forms an inversion layer through an external potential, a new channel is introduced, a new conductive path is added, and thus the current conduction capacity is increased; the potential of the drift region plate below the drift region is separately controlled, the bias potential is greater than the potential of the channel gate plate and less than the potential of the drain metal, the potential balance in the body is maintained, and the drift region surface above the drift region plate can attract more electrons, and thus the specific on-resistance is reduced.

[0072] The full SOI structure has a lower heat conduction capacity due to the buried oxide layer, such as Figure 4, setting the buried oxide layer as a partial buried oxide layer to reduce its self-heating effect, and at the same time introducing a new channel under the gate plate to increase its current conduction capability.

[0073] As shown in FIG8( a ), a double buried oxide layer structure is provided. By applying an external bias potential to the gate plate, three new channels can be introduced into the SOI-LDMOS of the present invention, which greatly increases its conductive path and greatly improves its current conducting capability.

[0074] The beneficial effect of the present invention is that the gate plate and the drift region plate are provided in the SOI-LDMOS, which can greatly improve the current conduction capability of the device and reduce the specific on-resistance. Figure 12 This technical solution can greatly reduce the specific on-resistance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] Figure 1(a) is a schematic diagram of the structure of a traditional SOI lateral power semiconductor device.

[0076] Figure 1(b) is a schematic diagram of the interdigitated layout of a traditional SOI lateral power semiconductor device.

[0077] FIG2( a ) is a schematic diagram of an SOI lateral power semiconductor device provided in Example 1 of the present invention.

[0078] FIG2( b ) is a schematic diagram of a gate plate connection method for a SOI lateral power semiconductor device provided in Example 1 of the present invention.

[0079] FIG2( c ) is a schematic diagram of an interdigitated layout of a SOI lateral power semiconductor device provided in Example 1 of the present invention.

[0080] FIG3( a ) is a schematic diagram of an SOI lateral power semiconductor device provided in Example 2 of the present invention.

[0081] FIG3( b ) is a schematic diagram of an interdigitated layout of a SOI lateral power semiconductor device provided in Example 2 of the present invention.

[0082] Figure 4 This is a schematic diagram of an SOI lateral power semiconductor device provided in Example 3 of the present invention.

[0083] Figure 5 This is a schematic diagram of an SOI lateral power semiconductor device provided in Example 4 of the present invention.

[0084] Figure 6 This is a schematic diagram of an SOI lateral power semiconductor device provided in Example 5 of the present invention.

[0085] Figure 7 This is a schematic diagram of an SOI lateral power semiconductor device provided in Example 6 of the present invention.

[0086] FIG8( a ) is a schematic diagram of an SOI lateral power semiconductor device provided in Example 7 of the present invention.

[0087] FIG8( b ) is a schematic diagram of a gate plate connection method for a SOI lateral power semiconductor device provided in Example 7 of the present invention.

[0088] FIG8( c ) is a schematic diagram of an interdigitated layout of a SOI lateral power semiconductor device provided in Example 7 of the present invention.

[0089] Figure 9 Schematic diagram of an SOI lateral power semiconductor device provided in Example 8 of the present invention.

[0090] Figure 10 Schematic diagram of an SOI lateral power semiconductor device provided in Example 9 of the present invention.

[0091] Figure 11 Schematic diagram of an SOI lateral power semiconductor device provided in Example 9 of the present invention.

[0092] Figure 12 Schematic diagram of IV characteristics of Example 2 of the present invention compared with traditional SOI-LDMOS.

[0093] 101 is the source metal, 102 is the gate, 103 is the gate oxide layer, 104 is the drain metal, 105 is the first source region, 106 is the body region, 107 is the drift region, 108 is the first buried oxide layer, 109 is the drain region, 110 is the substrate, 111 is the first gate plate, 112 is the first drift region plate, 113 is the first partial buried oxide layer, 114 is the second gate plate, 115 is the second buried oxide layer, 116 is the second drift region plate, 117 is the first thick buried oxide layer, 118 is the second source region, 119 is the well region, 120 is the second partial buried oxide layer, and 121 is the second thick buried oxide layer. DETAILED DESCRIPTION

[0094] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0095] In the following embodiments, the gate 102 , the first gate plate 111 , the first drift region plate 112 , the second gate plate 114 and the second drift region plate 116 may be metal electrodes or polysilicon electrodes.

[0096] The first type of doping is N-type doping and the second type of doping is P-type doping; or the first type of doping is P-type doping and the second type of doping is N-type doping. The following embodiments are described as if the first type of doping is N-type doping and the second type of doping is P-type doping.

[0097] Example 1

[0098] An SOI lateral power semiconductor device is shown in FIG2( a ), comprising a substrate 110 of a second doping type, a first buried oxide layer 108 disposed on the substrate 110 , and a first gate plate 111 disposed in the first buried oxide layer 108 ;

[0099] A drift region 107 of the first doping type is disposed above the first buried oxide layer 108. A body region 106 of the second doping type is disposed on the left side of the drift region 107 of the first doping type, and a drain region 109 of the first doping type is disposed on the right side. A first source region 105 of the first doping type and a second source region 118 of the second doping type are disposed in the body region 106 of the second doping type, wherein the first source region 105 of the first doping type and the second source region 118 of the second doping type are arranged tangentially in the body direction.

[0100] A gate oxide layer 103 is provided on the surface of the drift region 107 of the first doping type, a source metal 101 is provided above the first source region 105 of the first doping type and the second source region 118 of the second doping type, wherein the source metal 101 is in contact with the first source region 105 of the first doping type and the second source region 118 of the second doping type, a drain metal 104 is located above the drain region 109 of the first doping type, wherein the drain metal 104 is in contact with the drain region 109 of the first doping type, a left boundary of the gate oxide layer 103 is tangent to the right boundary of the first source region 105 of the first doping type, and the right boundary exceeds the right boundary of the body region 106 of the second doping type, and a gate 102 is provided on the gate oxide layer 103 and is located directly above the first gate plate 111;

[0101] The first gate plate 111 and the gate 102 are connected to the same potential, or are controlled separately. The bias voltage of the first gate plate 111 must ensure that the channel above the first gate plate 111 can be turned on.

[0102] In this technical solution, the first gate plate 111 is connected to the surface from the buried oxide layer as shown in FIG2(b). A top view of the device of the present invention is shown in FIG2(c). By applying a bias voltage, an inversion layer can be formed in the body region 106 on the surface of the first buried oxide layer 108 above the first gate plate 111, thereby opening a new channel. If the first gate plate 111 and the gate 102 are connected to the same potential, the original channel and the new channel can be opened and closed at the same time.

[0103] In this technical solution, a first gate plate 111 is provided in the first buried oxide layer 108 to introduce a new channel, thereby achieving higher current conduction capability.

[0104] Example 2

[0105] An SOI lateral power semiconductor device is shown in FIG3( a ), comprising a substrate 110 of a second doping type, on which a first buried oxide layer 108 is disposed;

[0106] A drift region 107 of the first doping type is disposed above the first buried oxide layer 108. A body region 106 of the second doping type is disposed on the left side of the drift region 107 of the first doping type, and a drain region 109 of the first doping type is disposed on the right side. A first source region 105 of the first doping type and a second source region 118 of the second doping type are disposed in the body region 106 of the second doping type, wherein the first source region 105 of the first doping type and the second source region 118 of the second doping type are arranged tangentially in the body direction.

[0107] A gate oxide layer 103 is provided on the surface of the drift region 107 of the first doping type, a source metal 101 is provided above the first source region 105 of the first doping type and the second source region 118 of the second doping type, wherein the source metal 101 is in contact with the first source region 105 of the first doping type and the second source region 118 of the second doping type, a drain metal 104 is located above the drain region 109 of the first doping type, wherein the drain metal 104 is in contact with the drain region 109 of the first doping type, a left boundary of the gate oxide layer 103 is tangent to the right boundary of the first source region 105 of the first doping type, and the right boundary exceeds the right boundary of the body region 106 of the second doping type, and a gate 102 is provided on the gate oxide layer 103;

[0108] A first gate plate 111 and a first drift region plate 112 are provided in the first buried oxide layer 108 , wherein the first gate plate 111 is located directly below the gate 102 , and the first drift region plate 112 is located to the right of the first gate plate 111 and below the drift region 107 of the first doping type;

[0109] The first gate plate 111 and the gate 102 are connected to the same potential, or are controlled separately. The bias voltage of the first gate plate 111 must ensure that the channel above the first gate plate 111 can be turned on.

[0110] The potential of the first drift region plate 112 is independently controlled, and its bias potential is greater than the potential of the first gate plate 111 and less than the potential of the drain metal 104 .

[0111] In this technical solution, the first gate electrode 111 and the first drift region electrode are both led out to the surface in parallel with the first gate electrode 111 in the same manner as the first gate electrode 111 as shown in Figure 2(b). The top view of the device of the present invention is shown in Figure 3(b).

[0112] In this technical solution, a first gate plate 111 is provided in the first buried oxide layer 108 to introduce a new channel, thereby achieving higher current conduction capability.

[0113] In this technical solution, a first drift region plate 112 is provided in the first buried oxide layer 108 , and the drift region 107 on the surface of the first buried oxide layer 108 above the first drift region plate 112 attracts more electrons, thereby achieving lower specific on-resistance.

[0114] In this technical solution, the IV characteristic diagram compared with the traditional SOI-LDMOS is as follows Figure 12 As shown, its specific on-resistance is reduced by about half.

[0115] Example 3

[0116] A SOI lateral power semiconductor device such as Figure 4 As shown, it includes a substrate 110 of the second doping type, a drift region 107 of the first doping type is provided in the substrate 110 of the second doping type, a body region 106 of the second doping type and a first partial buried oxide layer 113 are provided on the left side of the drift region 107 of the first doping type, and a drain region 109 of the first doping type is provided on the right side;

[0117] A first source region 105 of the first doping type and a second source region 118 of the second doping type are disposed in the body region 106 of the second doping type, wherein the first source region 105 of the first doping type and the second source region 118 of the second doping type are arranged tangentially in the body direction;

[0118] A gate oxide layer 103 is provided on the surface of the drift region 107 of the first doping type, a source metal 101 is provided above the first source region 105 of the first doping type and the second source region 118 of the second doping type, wherein the source metal 101 is in contact with the first source region 105 of the first doping type and the second source region 118 of the second doping type, a drain metal 104 is located above the drain region 109 of the first doping type, wherein the drain metal 104 is in contact with the drain region 109 of the first doping type, a left boundary of the gate oxide layer 103 is tangent to the right boundary of the first source region 105 of the first doping type, and the right boundary exceeds the right boundary of the body region 106 of the second doping type, and a gate 102 is provided on the gate oxide layer 103;

[0119] The first portion of the buried oxide layer 113 extends beyond the first source region 105 of the first doping type on the left side and beyond the body region 106 of the second doping type on the right side. The lower side is located above the bottom of the first source region 105 of the first doping type, so as to ensure that an additional channel can be induced under the first portion of the buried oxide layer 113.

[0120] A first gate plate 111 is provided in the first portion of the buried oxide layer 113 , and the first gate plate 111 is located directly below the gate 102 ;

[0121] The first gate plate 111 and the gate 102 are connected to the same potential, or are controlled separately. The bias voltage of the first gate plate 111 must ensure that the channel above the gate plate can be turned on.

[0122] In this technical solution, a first gate plate 111 is set in the first partial buried oxide layer 113. By applying an external bias voltage, an inversion layer can be formed in the body region 106 on the surface of the first partial buried oxide layer 113 above and below the first gate plate 111. The introduction of two new channels can achieve higher current conduction capability.

[0123] Example 4

[0124] A SOI lateral power semiconductor device such as Figure 5 As shown, it includes a substrate 110 of the second doping type, a drift region 107 of the first doping type is provided in the substrate 110 of the second doping type, a body region 106 of the second doping type and a second partial buried oxide layer 120 are provided on the left side of the drift region 107 of the first doping type, and a drain region 109 of the first doping type is provided on the right side;

[0125] A first source region 105 of the first doping type and a second source region 118 of the second doping type are disposed in the body region 106 of the second doping type, wherein the first source region 105 of the first doping type and the second source region 118 of the second doping type are arranged tangentially in the body direction;

[0126] A gate oxide layer 103 is provided on the surface of the drift region 107 of the first doping type, a source metal 101 is provided above the first source region 105 of the first doping type and the second source region 118 of the second doping type, wherein the source metal 101 is in contact with the first source region 105 of the first doping type and the second source region 118 of the second doping type, a drain metal 104 is located above the drain region 109 of the first doping type, wherein the drain metal 104 is in contact with the drain region 109 of the first doping type, a left boundary of the gate oxide layer 103 is tangent to the right boundary of the first source region 105 of the first doping type, and the right boundary exceeds the right boundary of the body region 106 of the second doping type, and a gate 102 is provided on the gate oxide layer 103;

[0127] The left side of the second portion of the buried oxide layer 120 exceeds the first source region 105 of the first doping type, the right side exceeds the body region 106 of the second doping type, and the bottom side is located above the bottom of the first source region 105 of the first doping type, so as to ensure that one more channel can be induced under the second portion of the buried oxide layer 120;

[0128] A first gate plate 111 and a first drift region plate 112 are provided in the second portion of the buried oxide layer 120 , wherein the first gate plate 111 is located directly below the gate 102 , and the first drift region plate 112 is located to the right of the first gate plate 111 and within the drift region 107 of the first doping type;

[0129] The first gate plate 111 and the gate 102 are connected to the same potential, or are controlled separately. The bias voltage of the first gate plate 111 must ensure that the channel above and below the gate plate can be smoothly turned on.

[0130] The potential of the first drift region plate 112 is independently controlled, and its bias potential is greater than the potential of the first gate plate 111 and less than the potential of the drain metal 104 .

[0131] In this technical solution, the first gate plate 111 in the second partial buried oxide layer 120 can form an inversion layer above the first gate plate 111 and the body region 106 on the surface of the second partial buried oxide layer 120 below it by applying an external bias voltage. The introduction of two new channels can achieve higher current conduction capability.

[0132] In this technical solution, the first drift region plate 112 in the second partial buried oxide layer 120 can attract more electrons to the drift region 107 on the surface of the second partial buried oxide layer 120 above and below the first drift region plate 112 by applying an external bias voltage, thereby achieving a lower specific on-resistance.

[0133] Example 5

[0134] A SOI lateral power semiconductor device such as Figure 6 As shown, it includes a substrate 110 of the second doping type, a drift region 107 of the first doping type is provided in the substrate 110 of the second doping type, a body region 106 of the second doping type and a first partial buried oxide layer 113 are provided on the left side of the drift region 107 of the first doping type, and a drain region 109 of the first doping type is provided on the right side of the drift region 107 of the first doping type;

[0135] A first source region 105 of the first doping type, a second source region 118 of the second doping type, and a well region 119 of the first doping type are provided in the body region 106 of the second doping type to prevent the first source region 105 of the first doping type and the second source region 118 of the second doping type from being unable to diffuse under the first portion of the buried oxide layer 113. The first source region 105 of the first doping type and the second source region 118 of the second doping type are located inside the well region 119 of the first doping type, and their right boundaries are tangent to the right boundary of the well region 119 of the first doping type, wherein the first source region 105 of the first doping type and the second source region 118 of the second doping type are arranged tangentially in the body direction.

[0136] A gate oxide layer 103 is provided on the surface of the drift region 107 of the first doping type, a source metal 101 is provided above the first source region 105 of the first doping type and the second source region 118 of the second doping type, wherein the source metal 101 is in contact with the first source region 105 of the first doping type and the second source region 118 of the second doping type, a drain metal 104 is located above the drain region 109 of the first doping type, wherein the drain metal 104 is in contact with the drain region 109 of the first doping type, a left boundary of the gate oxide layer 103 is tangent to the right boundary of the first source region 105 of the first doping type, and the right boundary exceeds the right boundary of the body region 106 of the second doping type, and a gate 102 is provided on the gate oxide layer 103;

[0137] The first portion of the buried oxide layer 113 extends beyond the first doping type well region 119 on the left side and beyond the second doping type body region 106 on the right side. The lower side of the first portion of the buried oxide layer 113 is located below the bottom of the first doping type first source region 105 and above the bottom of the first doping type well region 119.

[0138] A first gate plate 111 is provided in the first portion of the buried oxide layer 113 , and the first gate plate 111 is located directly below the gate 102 ;

[0139] The first gate plate 111 and the gate 102 are connected to the same potential, or are controlled separately. The bias voltage of the first gate plate 111 must ensure that the channel above the gate plate can be turned on.

[0140] In this technical solution, a first gate plate 111 is set in the first partial buried oxide layer 113. By applying an external bias voltage, an inversion layer can be formed in the body region 106 on the surface of the first partial buried oxide layer 113 above and below the first gate plate 111. The introduction of two new channels can achieve higher current conduction capability.

[0141] Example 6

[0142] A SOI lateral power semiconductor device such as Figure 7As shown, it includes a substrate 110 of the second doping type, a drift region 107 of the first doping type is provided in the substrate 110 of the second doping type, a body region 106 of the second doping type and a second partial buried oxide layer 120 are provided on the left side of the drift region 107 of the first doping type, and a drain region 109 of the first doping type is provided on the right side;

[0143] A first source region 105 of the first doping type, a second source region 118 of the second doping type, and a well region 119 of the first doping type are provided in the body region 106 of the second doping type to prevent the first source region 105 of the first doping type and the second source region 118 of the second doping type from being unable to diffuse under the first portion of the buried oxide layer 113. The first source region 105 of the first doping type and the second source region 118 of the second doping type are located inside the well region 119 of the first doping type, and their right boundaries are tangent to the right boundary of the well region 119 of the first doping type, wherein the first source region 105 of the first doping type and the second source region 118 of the second doping type are arranged tangentially in the body direction.

[0144] A gate oxide layer 103 is provided on the surface of the drift region 107 of the first doping type, a source metal 101 is provided above the first source region 105 of the first doping type and the second source region 118 of the second doping type, wherein the source metal 101 is in contact with the first source region 105 of the first doping type and the second source region 118 of the second doping type, a drain metal 104 is located above the drain region 109 of the first doping type, wherein the drain metal 104 is in contact with the drain region 109 of the first doping type, a left boundary of the gate oxide layer 103 is tangent to the right boundary of the first source region 105 of the first doping type, and the right boundary exceeds the right boundary of the body region 106 of the second doping type, and a gate 102 is provided on the gate oxide layer 103;

[0145] The second portion of the buried oxide layer 120 extends beyond the first doping type well region 119 on the left side and beyond the second doping type body region 106 on the right side. The lower side of the second portion of the buried oxide layer 120 is located below the bottom of the first doping type first source region 105 and above the bottom of the first doping type well region 119.

[0146] A first gate plate 111 and a first drift region plate 112 are provided in the second portion of the buried oxide layer 120 , wherein the first gate plate 111 is located directly below the gate 102 , and the first drift region plate 112 is located to the right of the first gate plate 111 and within the drift region 107 of the first doping type;

[0147] The first gate plate 111 and the gate 102 are connected to the same potential, or are controlled separately. The bias voltage of the first gate plate 111 must ensure that the channel above the gate plate can be turned on.

[0148] The potential of the first drift region plate 112 is independently controlled, and its bias potential is greater than the potential of the first gate plate 111 and less than the potential of the drain metal 104 .

[0149] In this technical solution, the first gate plate 111 in the second partial buried oxide layer 120 can form an inversion layer in the body region 106 on the surface of the second partial buried oxide layer 120 above and below the first gate plate 111 by applying an external bias voltage. The introduction of two new channels can achieve higher current conduction capability.

[0150] In this technical solution, the first drift region plate 112 in the second partial buried oxide layer 120 can attract more electrons to the drift region 107 on the surface of the second partial buried oxide layer 120 above and below the first drift region plate 112 by applying an external bias voltage, thereby achieving a lower specific on-resistance.

[0151] Example 7

[0152] An SOI lateral power semiconductor device is shown in FIG8( a ), comprising a substrate 110 of a second doping type, a second buried oxide layer 115 disposed on the substrate, and a second gate plate 114 disposed in the second buried oxide layer 115 ;

[0153] A drift region 107 of the first doping type is disposed above the second buried oxide layer 115 . A body region 106 of the second doping type and a first portion of the buried oxide layer 113 are disposed on the left side of the drift region 107 of the first doping type, and a drain region 109 of the first doping type is disposed on the right side.

[0154] A first source region 105 of the first doping type, a second source region 118 of the second doping type, and a well region 119 of the first doping type are provided in the body region 106 of the second doping type, wherein the first source region 105 of the first doping type and the second source region 118 of the second doping type are arranged tangentially in the body direction, the first source region 105 of the first doping type and the second source region 118 of the second doping type are located inside the well region 119 of the first doping type, and the right boundaries of the first source region 105 and the second source region 118 of the second doping type are tangential to the right boundary of the well region 119 of the first doping type, wherein the upper boundary of the second buried oxide layer 115 exceeds the lower boundary of the well region 119 of the first doping type, so as to ensure that one more channel can be induced on the upper side of the second buried oxide layer 115;

[0155] A gate oxide layer 103 is provided on the surface of the drift region 107 of the first doping type, a source metal 101 is provided above the first source region 105 of the first doping type and the second source region 118 of the second doping type, wherein the source metal 101 is in contact with the first source region 105 of the first doping type and the second source region 118 of the second doping type, a drain metal 104 is located above the drain region 109 of the first doping type, wherein the drain metal 104 is in contact with the drain region 109 of the first doping type, a left boundary of the gate oxide layer 103 is tangent to the right boundary of the first source region 105 of the first doping type, and the right boundary exceeds the right boundary of the body region 106 of the second doping type, and a gate 102 is provided above the gate oxide layer 103;

[0156] The left boundary of the first portion of the buried oxide layer 113 exceeds the first source region 105 of the first doping type, the right side exceeds the body region 106 of the second doping type, and the bottom side is located above the bottom of the first source region 105 of the first doping type;

[0157] A first gate plate 111 is provided in the first portion of the buried oxide layer 113 , wherein the first gate plate 111 is located directly below the gate 102 and directly above the second gate plate;

[0158] The second gate plate 114 is connected to the same potential as the first gate plate 111, wherein the first gate plate 111 is connected to the same potential as the gate 102, or is controlled separately. The bias voltage of the first gate plate 111 must ensure that the channel above the gate plate can be turned on.

[0159] In this technical solution, the first gate plate 111 and the second gate plate 114 are connected to the surface from the buried oxide layer as shown in Figure 8(b). A top view of the device of the present invention is shown in Figure 8(c). By applying a bias voltage, an inversion layer is formed in the body region 106 above the first gate plate 111 and below the first portion of the buried oxide layer 113, thereby opening a new channel. If the first gate plate 111 and the gate 102 are connected to the same potential, the original channel and the new channel can be opened and closed at the same time.

[0160] In this technical solution, the second gate plate 114 and the first gate plate 111 are connected to the same potential, which can form an inversion layer in the body region 106 on the surface of the second buried oxide layer 115 above the second gate plate 114, open a new channel, and achieve higher current conduction capability.

[0161] Example 8

[0162] A SOI lateral power semiconductor device such as Figure 9 As shown, it includes a substrate 110 of a second doping type, a second buried oxide layer 115 is provided on the substrate, and a second gate plate 114 and a second drift region plate 116 are provided in the second buried oxide layer 115;

[0163] A drift region 107 of the first doping type is disposed above the second buried oxide layer 115 . A body region 106 of the second doping type and a second portion of the buried oxide layer 120 are disposed on the left side of the drift region 107 of the first doping type, and a drain region 109 of the first doping type is disposed on the right side.

[0164] A first source region 105 of the first doping type, a second source region 118 of the second doping type, and a well region 119 of the first doping type are provided in the body region 106 of the second doping type, wherein the first source region 105 of the first doping type and the second source region 118 of the second doping type are arranged tangentially in the body direction, the first source region 105 of the first doping type and the second source region 118 of the second doping type are located inside the well region 119 of the first doping type, and the right boundaries of the first source region 105 and the second source region 118 of the second doping type are tangential to the right boundary of the well region 119 of the first doping type, wherein the upper boundary of the second buried oxide layer 115 exceeds the lower boundary of the well region 119 of the first doping type to ensure that an additional channel can be induced on the upper side of the second buried oxide layer 115; the second gate plate 114 is located directly below the first gate plate 111, and the left and right boundaries are also tangential to the first gate plate 111;

[0165] A gate oxide layer 103 is provided on the surface of the drift region 107 of the first doping type, a source metal 101 is provided above the first source region 105 of the first doping type and the second source region 118 of the second doping type, wherein the source metal 101 is in contact with the first source region 105 of the first doping type and the second source region 118 of the second doping type, a drain metal 104 is located above the drain region 109 of the first doping type, wherein the drain metal 104 is in contact with the drain region 109 of the first doping type, and a gate 102 is provided above the gate oxide layer 103;

[0166] The left boundary of the second portion of the buried oxide layer 120 exceeds the first source region 105 of the first doping type, the right side exceeds the body region 106 of the second doping type, and the bottom side is located above the bottom of the first source region 105 of the first doping type;

[0167] A first gate plate 111 and a first drift region plate 112 are provided in the second portion of the buried oxide layer 120 , wherein the first gate plate 111 is located directly below the gate 102 and directly above the second gate plate. The first drift region plate 112 is located on the right side of the first gate plate 111 , directly above the second drift region plate 116 , and within the drift region 107 of the first doping type.

[0168] The second gate plate 114 is connected to the same potential as the first gate plate 111, wherein the first gate plate 111 is connected to the same potential as the gate 102, or is controlled separately. The bias voltage of the first gate plate 111 must ensure that the channel above the gate plate can be turned on;

[0169] The second drift region plate 116 and the first drift region plate 112 are connected to the same potential, wherein the potential of the first drift region plate 112 is independently controlled, and its bias potential is greater than the potential of the first gate plate 111 and less than the potential of the drain metal 104 .

[0170] In this technical solution, the first drift region plate 112 and the second drift region plate 116 are also led out to the surface in parallel with the second gate plate 114 in the same way as the first gate plate 111 and the second gate plate 114 as shown in Figure 8(b), and the top view of the device of the present invention is consistent with that shown in Figure 3(b).

[0171] In this technical solution, a first gate electrode 111 is set in the second partial buried oxide layer 120. By applying an external bias voltage, the body region 106 on the surface of the second partial buried oxide layer 120 above and below the first gate electrode 111 can form an inversion layer. The introduction of two new channels can achieve higher current conduction capability.

[0172] In this technical solution, the first drift region plate 112 in the second partial buried oxide layer 120 can attract more electrons to the drift region 107 on the surface of the second partial buried oxide layer 120 above and below the first drift region plate 112 by applying an external bias voltage, thereby achieving a lower specific on-resistance.

[0173] In this technical solution, the second gate plate 114 and the first gate plate 111 are connected to the same potential, which can form an inversion layer in the body region 106 on the surface of the second buried oxide layer 115 above the second gate plate 114, open a new channel, and achieve higher current conduction capability.

[0174] In this technical solution, the second drift region plate 114 and the first drift region plate 112 are connected to the same bias potential, which can enable the drift region 107 on the surface of the second buried oxide layer 115 above the second drift region plate 116 to attract more electrons, thereby achieving lower specific on-resistance.

[0175] Example 9

[0176] A SOI lateral power semiconductor device such as Figure 10 As shown, it includes a substrate 110 of a second doping type, a second buried oxide layer 115 is provided on the substrate, and a second gate plate 114 is provided in the second buried oxide layer 115;

[0177] A drift region 107 of the first doping type is disposed above the second buried oxide layer 115 . A body region 106 of the second doping type and a first portion of the buried oxide layer 113 are disposed on the left side of the drift region 107 of the first doping type, and a drain region 109 of the first doping type is disposed on the right side.

[0178] A first source region 105 of the first doping type, a second source region 118 of the second doping type, and a well region 119 of the first doping type are provided in the body region 106 of the second doping type, wherein the first source region 105 of the first doping type and the second source region 118 of the second doping type are arranged tangentially in the body direction, the first source region 105 of the first doping type and the second source region 118 of the second doping type are located inside the well region 119 of the first doping type, and the right boundaries of the first source region 105 and the second source region 118 of the second doping type are tangential to the right boundary of the well region 119 of the first doping type, wherein the upper boundary of the second buried oxide layer 115 exceeds the lower boundary of the well region 119 of the first doping type, so as to ensure that one more channel can be induced on the upper side of the second buried oxide layer 115;

[0179] A gate oxide layer 103 is provided on the surface of the drift region 107 of the first doping type, a source metal 101 is provided above the first source region 105 of the first doping type and the second source region 118 of the second doping type, wherein the source metal 101 is in contact with the first source region 105 of the first doping type and the second source region 118 of the second doping type, a drain metal 104 is located above the drain region 109 of the first doping type, wherein the drain metal 104 is in contact with the drain region 109 of the first doping type, a left boundary of the gate oxide layer 103 is tangent to the right boundary of the first source region 105 of the first doping type, and the right boundary exceeds the right boundary of the body region 106 of the second doping type, and a gate 102 is provided above the gate oxide layer 103;

[0180] The left boundary of the first portion of the buried oxide layer 113 exceeds the first source region 105 of the first doping type, the right boundary exceeds the body region 106 of the second doping type, and the bottom boundary is located below the bottom of the first source region 105 of the first doping type;

[0181] A first gate plate 111 is provided in the first portion of the buried oxide layer 113 , wherein the first gate plate 111 is located directly below the gate 102 and directly above the second gate plate;

[0182] The second gate plate 114 is connected to the same potential as the first gate plate 111, wherein the first gate plate 111 is connected to the same potential as the gate 102, or is controlled separately. The bias voltage of the first gate plate 111 must ensure that the channel above the gate plate can be turned on.

[0183] In this technical solution, a first gate plate 111 is set in the first partial buried oxide layer 113. By applying an external bias voltage, the body region 106 on the surface of the first partial buried oxide layer 113 above and below the first gate plate 111 can form an inversion layer, introducing two new channels.

[0184] In this technical solution, the second gate plate 114 and the first gate plate 111 are connected to the same potential, which can form an inversion layer in the body region 106 on the surface of the second buried oxide layer 115 above the second gate plate 114, introduce a new channel, and achieve higher current conduction capability.

[0185] Example 10

[0186] A SOI lateral power semiconductor device such as Figure 11 As shown, it includes a substrate 110 of a second doping type, a second buried oxide layer 115 is provided on the substrate, and a second gate plate 114 and a second drift region plate 116 are provided in the second buried oxide layer 115;

[0187] A drift region 107 of the first doping type is disposed above the second buried oxide layer 115 . A body region 106 of the second doping type and a second portion of the buried oxide layer 120 are disposed on the left side of the drift region 107 of the first doping type, and a drain region 109 of the first doping type is disposed on the right side.

[0188] A first source region 105 of the first doping type, a second source region 118 of the second doping type, and a well region 119 of the first doping type are provided in the body region 106 of the second doping type, wherein the first source region 105 of the first doping type and the second source region 118 of the second doping type are arranged tangentially in the body direction, the first source region 105 of the first doping type and the second source region 118 of the second doping type are located inside the well region 119 of the first doping type, and the right boundaries of the first source region 105 and the second source region 118 of the second doping type are tangential to the right boundary of the well region 119 of the first doping type, wherein the upper boundary of the second buried oxide layer 115 exceeds the lower boundary of the well region 119 of the first doping type to ensure that an additional channel can be induced on the upper side of the second buried oxide layer 115; the second gate plate 114 is located directly below the first gate plate 111, and the left and right boundaries are also tangential to the first gate plate 111;

[0189] A gate oxide layer 103 is provided on the surface of the drift region 107 of the first doping type, a source metal 101 is provided above the first source region 105 of the first doping type and the second source region 118 of the second doping type, wherein the source metal 101 is in contact with the first source region 105 of the first doping type and the second source region 118 of the second doping type, a drain metal 104 is located above the drain region 109 of the first doping type, wherein the drain metal 104 is in contact with the drain region 109 of the first doping type, and a gate 102 is provided above the gate oxide layer 103;

[0190] The left boundary of the second portion of the buried oxide layer 120 exceeds the first source region 105 of the first doping type, the right side exceeds the body region 106 of the second doping type, and the bottom side is located below the bottom of the first source region 105 of the first doping type;

[0191] A first gate plate 111 and a first drift region plate 112 are provided in the second portion of the buried oxide layer 120 , wherein the first gate plate 111 is located directly below the gate 102 and directly above the second gate plate, and the first drift region plate 112 is located to the right of the first gate plate 111 , directly above the second drift region plate 116 , and within the drift region 107 of the first doping type.

[0192] The second gate plate 114 is connected to the same potential as the first gate plate 111, wherein the first gate plate 111 is connected to the same potential as the gate 102, or is controlled separately. The bias voltage of the first gate plate 111 must ensure that the channel above the gate plate can be turned on;

[0193] The second drift region plate 116 and the first drift region plate 112 are connected to the same potential, wherein the potential of the first drift region plate 112 is independently controlled, and its bias potential is greater than the potential of the first gate plate 111 and less than the potential of the drain metal 104 .

[0194] In this technical solution, a first gate electrode 111 is set in the second part of the buried oxide layer 120. By applying an external bias voltage, an inversion layer can be formed in the body region 106 on the surface of the second part of the buried oxide layer 120 above and below the first gate electrode 111, introducing two new channels, and achieving higher current conduction capability.

[0195] In this technical solution, the second gate plate 114 and the first gate plate 111 are connected to the same potential, which can form an inversion layer in the body region 106 on the surface of the second buried oxide layer 115 above the second gate plate 114, introduce a new channel, and achieve higher current conduction capability.

[0196] In this technical solution, the first drift region plate 112 of the second partial buried oxide layer 120 can attract more electrons to the drift region 107 on the surface of the second partial buried oxide layer 120 above and below the first drift region plate 112 by applying an external bias voltage, thereby achieving a lower specific on-resistance.

[0197] In this technical solution, the second drift region plate 114 and the first drift region plate 112 are connected to the same bias potential, which can enable the drift region 107 on the surface of the second buried oxide layer 115 above the second drift region plate 116 to attract more electrons, thereby achieving lower specific on-resistance.

[0198] In the above ten embodiments, the basic effect obtained is that, compared with the traditional SOI lateral power semiconductor device, it has higher current conduction capability and lower specific on-resistance.

[0199] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A SOI lateral power semiconductor device, characterized in that: It comprises a substrate (110) of a second doping type, a first buried oxide layer (108) is provided on the substrate (110), and a first gate electrode (111) is provided in the first buried oxide layer (108); A drift region (107) of a first doping type is provided above the first buried oxide layer (108); a body region (106) of a second doping type is provided on the left side of the drift region (107) of the first doping type, and a drain region (109) of the first doping type is provided on the right side; a first source region (105) of the first doping type and a second source region (118) of the second doping type are provided in the body region (106) of the second doping type, wherein the first source region (105) of the first doping type and the second source region (118) of the second doping type are arranged tangentially in the body direction; A gate oxide layer (103) is provided on the surface of the drift region (107) of the first doping type, a source metal (101) is provided above the first source region (105) of the first doping type and the second source region (118) of the second doping type, wherein the source metal (101) is in contact with the first source region (105) of the first doping type and the second source region (118) of the second doping type, a drain metal (104) is located above the drain region (109) of the first doping type, wherein the drain metal (104) is in contact with the drain region (109) of the first doping type, a left boundary of the gate oxide layer (103) is tangent to a right boundary of the first source region (105) of the first doping type, and a right boundary exceeds a right boundary of the body region (106) of the second doping type, and a gate (102) is provided on the gate oxide layer (103) and is located directly above the first gate plate (111); The first gate plate (111) and the gate (102) are connected to the same potential, or are controlled separately, and the bias voltage of the first gate plate (111) must ensure that the channel above the first gate plate (111) can be turned on; A first drift region plate (112) is provided in the first buried oxide layer (108), wherein the first gate plate (111) is located directly below the gate (102), and the first drift region plate (112) is located on the right side of the first gate plate (111) and below the drift region (107) of the first doping type; The potential of the first drift region plate (112) is independently controlled, and its bias potential is greater than the potential of the first gate plate (111) and less than the potential of the drain metal (104).

2. A SOI lateral power semiconductor device, characterized in that: A second doping type substrate (110) is provided, a first doping type drift region (107) is provided in the second doping type substrate (110), a second doping type body region (106) and a first portion of a buried oxide layer (113) are provided on the left side of the first doping type drift region (107), and a first doping type drain region (109) is provided on the right side; A first source region (105) of the first doping type and a second source region (118) of the second doping type are provided in the body region (106) of the second doping type, wherein the first source region (105) of the first doping type and the second source region (118) of the second doping type are arranged tangentially in the body direction; A gate oxide layer (103) is provided on the surface of the drift region (107) of the first doping type, a source metal (101) is provided above the first source region (105) of the first doping type and the second source region (118) of the second doping type, wherein the source metal (101) is in contact with the first source region (105) of the first doping type and the second source region (118) of the second doping type, a drain metal (104) is located above the drain region (109) of the first doping type, wherein the drain metal (104) is in contact with the drain region (109) of the first doping type, a left boundary of the gate oxide layer (103) is tangent to a right boundary of the first source region (105) of the first doping type, and a right boundary exceeds a right boundary of the body region (106) of the second doping type, and a gate (102) is provided on the gate oxide layer (103); The first portion of the buried oxide layer (113) extends beyond the first source region (105) of the first doping type on the left side and beyond the body region (106) of the second doping type on the right side, and the lower side is located above the bottom of the first source region (105) of the first doping type, so as to ensure that an additional channel can be sensed below the first portion of the buried oxide layer (113); A first gate electrode (111) is provided in the first portion of the buried oxide layer (113), and the first gate electrode (111) is located directly below the gate (102); The first gate plate (111) and the gate (102) are connected to the same potential, or are controlled separately. The bias voltage of the first gate plate (111) must ensure that the channel above the gate plate can be opened.

3. A SOI lateral power semiconductor device, characterized in that: A second doping type substrate (110) is provided, a first doping type drift region (107) is provided in the second doping type substrate (110), a second doping type body region (106) and a second portion of a buried oxide layer (120) are provided on the left side of the first doping type drift region (107), and a first doping type drain region (109) is provided on the right side; A first source region (105) of the first doping type and a second source region (118) of the second doping type are provided in the body region (106) of the second doping type, wherein the first source region (105) of the first doping type and the second source region (118) of the second doping type are arranged tangentially in the body direction; A gate oxide layer (103) is provided on the surface of the drift region (107) of the first doping type, a source metal (101) is provided above the first source region (105) of the first doping type and the second source region (118) of the second doping type, wherein the source metal (101) is in contact with the first source region (105) of the first doping type and the second source region (118) of the second doping type, a drain metal (104) is located above the drain region (109) of the first doping type, wherein the drain metal (104) is in contact with the drain region (109) of the first doping type, a left boundary of the gate oxide layer (103) is tangent to a right boundary of the first source region (105) of the first doping type, and a right boundary exceeds a right boundary of a body region (106) of the second doping type, and a gate (102) is provided on the gate oxide layer (103); The left side of the second portion of the buried oxide layer (120) exceeds the first source region (105) of the first doping type, the right side exceeds the body region (106) of the second doping type, and the bottom side is located above the bottom of the first source region (105) of the first doping type, so as to ensure that an additional channel can be sensed on the bottom side of the second portion of the buried oxide layer (120); A first gate electrode (111) and a first drift region electrode (112) are provided in the second portion of the buried oxide layer (120), wherein the first gate electrode (111) is located directly below the gate (102), and the first drift region electrode (112) is located on the right side of the first gate electrode (111) and within the drift region (107) of the first doping type; The first gate plate (111) and the gate (102) are connected to the same potential, or are controlled separately, and the bias voltage of the first gate plate (111) must ensure that the channel above and below the gate plate can be smoothly opened; The potential of the first drift region plate (112) is independently controlled, and its bias potential is greater than the potential of the first gate plate (111) and less than the potential of the drain metal (104).

4. A SOI lateral power semiconductor device, characterized in that: A second doping type substrate (110) is provided, a first doping type drift region (107) is provided in the second doping type substrate (110), a second doping type body region (106) and a first portion of a buried oxide layer (113) are provided on the left side of the first doping type drift region (107), and a first doping type drain region (109) is provided on the right side of the first doping type drift region (107); A first source region (105) of the first doping type, a second source region (118) of the second doping type, and a well region (119) of the first doping type are provided in the body region (106) of the second doping type to prevent the first source region (105) of the first doping type and the second source region (118) of the second doping type from being unable to diffuse below the first portion of the buried oxide layer (113); the first source region (105) of the first doping type and the second source region (118) of the second doping type are located inside the well region (119) of the first doping type, and the right boundary is tangent to the right boundary of the well region (119) of the first doping type, wherein the first source region (105) of the first doping type and the second source region (118) of the second doping type are arranged tangent to each other in the body direction; A gate oxide layer (103) is provided on the surface of the drift region (107) of the first doping type, a source metal (101) is provided above the first source region (105) of the first doping type and the second source region (118) of the second doping type, wherein the source metal (101) is in contact with the first source region (105) of the first doping type and the second source region (118) of the second doping type, a drain metal (104) is located above the drain region (109) of the first doping type, wherein the drain metal (104) is in contact with the drain region (109) of the first doping type, a left boundary of the gate oxide layer (103) is tangent to a right boundary of the first source region (105) of the first doping type, and a right boundary exceeds a right boundary of a body region (106) of the second doping type, and a gate (102) is provided on the gate oxide layer (103); The first portion of the buried oxide layer (113) extends beyond the first doping type well region (119) on the left side and beyond the second doping type body region (106) on the right side, and the lower side is located below the bottom of the first doping type first source region (105) and above the bottom of the first doping type well region (119); A first gate electrode (111) is provided in the first portion of the buried oxide layer (113), and the first gate electrode (111) is located directly below the gate (102); The first gate plate (111) and the gate (102) are connected to the same potential, or are controlled separately. The bias voltage of the first gate plate (111) must ensure that the channel above the gate plate can be opened.

5. A SOI lateral power semiconductor device, characterized in that: A second doping type substrate (110) is provided, a first doping type drift region (107) is provided in the second doping type substrate (110), a second doping type body region (106) and a second portion of a buried oxide layer (120) are provided on the left side of the first doping type drift region (107), and a first doping type drain region (109) is provided on the right side; A first source region (105) of the first doping type, a second source region (118) of the second doping type, and a well region (119) of the first doping type are provided in the body region (106) of the second doping type to prevent the first source region (105) of the first doping type and the second source region (118) of the second doping type from being unable to diffuse below the first portion of the buried oxide layer (113); the first source region (105) of the first doping type and the second source region (118) of the second doping type are located inside the well region (119) of the first doping type, and the right boundary is tangent to the right boundary of the well region (119) of the first doping type, wherein the first source region (105) of the first doping type and the second source region (118) of the second doping type are arranged tangent to each other in the body direction; A gate oxide layer (103) is provided on the surface of the drift region (107) of the first doping type, a source metal (101) is provided above the first source region (105) of the first doping type and the second source region (118) of the second doping type, wherein the source metal (101) is in contact with the first source region (105) of the first doping type and the second source region (118) of the second doping type, a drain metal (104) is located above the drain region (109) of the first doping type, wherein the drain metal (104) is in contact with the drain region (109) of the first doping type, a left boundary of the gate oxide layer (103) is tangent to a right boundary of the first source region (105) of the first doping type, and a right boundary exceeds a right boundary of a body region (106) of the second doping type, and a gate (102) is provided on the gate oxide layer (103); The second portion of the buried oxide layer (120) extends beyond the first doping type well region (119) on the left side and beyond the second doping type body region (106) on the right side, and the lower side is located below the bottom of the first doping type first source region (105) and above the bottom of the first doping type well region (119); A first gate electrode (111) and a first drift region electrode (112) are provided in the second portion of the buried oxide layer (120), wherein the first gate electrode (111) is located directly below the gate (102), and the first drift region electrode (112) is located on the right side of the first gate electrode (111) and within the drift region (107) of the first doping type; The first gate plate (111) and the gate (102) are connected to the same potential, or are controlled separately, and the bias voltage of the first gate plate (111) must ensure that the channel above the gate plate can be opened; The potential of the first drift region plate (112) is independently controlled, and its bias potential is greater than the potential of the first gate plate (111) and less than the potential of the drain metal (104).

6. A SOI lateral power semiconductor device, characterized in that: It comprises a substrate (110) of a second doping type, a second buried oxide layer (115) is provided on the substrate, and a second gate electrode (114) is provided in the second buried oxide layer (115); A first doping type drift region (107) is provided above the second buried oxide layer (115); a second doping type body region (106) and a first portion of the buried oxide layer (113) are provided on the left side of the first doping type drift region (107); and a first doping type drain region (109) is provided on the right side. A first source region (105) of the first doping type, a second source region (118) of the second doping type, and a well region (119) of the first doping type are provided in the body region (106) of the second doping type, wherein the first source region (105) of the first doping type and the second source region (118) of the second doping type are arranged tangentially in the body direction, the first source region (105) of the first doping type and the second source region (118) of the second doping type are located inside the well region (119) of the first doping type, and the right boundaries are tangential to the right boundary of the well region (119) of the first doping type, wherein the upper boundary of the second buried oxide layer (115) exceeds the lower boundary of the well region (119) of the first doping type, so as to ensure that one more channel can be sensed on the upper side of the second buried oxide layer (115); A gate oxide layer (103) is provided on the surface of the drift region (107) of the first doping type, a source metal (101) is provided above the first source region (105) of the first doping type and the second source region (118) of the second doping type, wherein the source metal (101) is in contact with the first source region (105) of the first doping type and the second source region (118) of the second doping type, a drain metal (104) is located above the drain region (109) of the first doping type, wherein the drain metal (104) is in contact with the drain region (109) of the first doping type, a left boundary of the gate oxide layer (103) is tangent to a right boundary of the first source region (105) of the first doping type, and a right boundary exceeds a right boundary of a body region (106) of the second doping type, and a gate (102) is provided above the gate oxide layer (103); The left boundary of the first portion of the buried oxide layer (113) exceeds the first source region (105) of the first doping type, the right side exceeds the body region (106) of the second doping type, and the bottom side is located above the bottom of the first source region (105) of the first doping type; A first gate electrode (111) is provided in the first portion of the buried oxide layer (113), wherein the first gate electrode (111) is located directly below the gate (102) and directly above the second gate electrode; The second gate plate (114) and the first gate plate (111) are connected to the same potential, wherein the first gate plate (111) and the gate (102) are connected to the same potential, or are controlled separately, and the bias voltage of the first gate plate (111) needs to ensure that the channel above the gate plate can be opened.

7. A SOI lateral power semiconductor device, characterized in that: It comprises a substrate (110) of a second doping type, a second buried oxide layer (115) being provided on the substrate, and a second gate electrode plate (114) and a second drift region electrode plate (116) being provided in the second buried oxide layer (115); A first doping type drift region (107) is provided above the second buried oxide layer (115); a second doping type body region (106) and a second portion of the buried oxide layer (120) are provided on the left side of the first doping type drift region (107); and a first doping type drain region (109) is provided on the right side; A first source region (105) of the first doping type, a second source region (118) of the second doping type, and a well region (119) of the first doping type are provided in the body region (106) of the second doping type, wherein the first source region (105) of the first doping type and the second source region (118) of the second doping type are arranged tangentially in the body direction, the first source region (105) of the first doping type and the second source region (118) of the second doping type are located inside the well region (119) of the first doping type, and the right boundaries are tangential to the right boundary of the well region (119) of the first doping type, wherein the upper boundary of the second buried oxide layer (115) exceeds the lower boundary of the well region (119) of the first doping type to ensure that one more channel can be sensed on the upper side of the second buried oxide layer (115); the second gate plate (114) is located directly below the first gate plate (111), and the left and right boundaries are also tangential to the first gate plate (111); A gate oxide layer (103) is provided on the surface of a first doping type drift region (107), a source metal (101) is provided above a first source region (105) of the first doping type and a second source region (118) of the second doping type, wherein the source metal (101) is in contact with the first source region (105) of the first doping type and the second source region (118) of the second doping type, a drain metal (104) is located above a first doping type drain region (109), wherein the drain metal (104) is in contact with the first doping type drain region (109), and a gate (102) is provided above the gate oxide layer (103); The left boundary of the second portion of the buried oxide layer (120) exceeds the first source region (105) of the first doping type, the right side exceeds the body region (106) of the second doping type, and the bottom side is located above the bottom of the first source region (105) of the first doping type; A first gate electrode (111) and a first drift region electrode (112) are provided in the second portion of the buried oxide layer (120), wherein the first gate electrode (111) is located directly below the gate (102) and directly above the second gate electrode (114), and the first drift region electrode (112) is located on the right side of the first gate electrode (111), directly above the second drift region electrode (116), and within the drift region (107) of the first doping type; The second gate plate (114) and the first gate plate (111) are connected to the same potential, wherein the first gate plate (111) and the gate (102) are connected to the same potential, or are controlled separately, and the bias voltage of the first gate plate (111) must ensure that the channel above the gate plate can be opened; The second drift region plate (116) and the first drift region plate (112) are connected to the same potential, wherein the potential of the first drift region plate (112) is controlled separately, and its bias potential is greater than the potential of the first gate plate (111) and less than the potential of the drain metal (104).

8. A SOI lateral power semiconductor device, characterized in that: It comprises a substrate (110) of a second doping type, a second buried oxide layer (115) is provided on the substrate, and a second gate electrode (114) is provided in the second buried oxide layer (115); A first doping type drift region (107) is provided above the second buried oxide layer (115); a second doping type body region (106) and a first portion of the buried oxide layer (113) are provided on the left side of the first doping type drift region (107); and a first doping type drain region (109) is provided on the right side. A first source region (105) of the first doping type, a second source region (118) of the second doping type, and a well region (119) of the first doping type are provided in the body region (106) of the second doping type, wherein the first source region (105) of the first doping type and the second source region (118) of the second doping type are arranged tangentially in the body direction, the first source region (105) of the first doping type and the second source region (118) of the second doping type are located inside the well region (119) of the first doping type, and the right boundaries are tangential to the right boundary of the well region (119) of the first doping type, wherein the upper boundary of the second buried oxide layer (115) exceeds the lower boundary of the well region (119) of the first doping type, so as to ensure that one more channel can be sensed on the upper side of the second buried oxide layer (115); A gate oxide layer (103) is provided on the surface of a first doping type drift region (107), a first doping type first source region (105) and a second doping type second source region (118), a source metal (101) is provided above the source metal (101), wherein the source metal (101) is in contact with the first doping type first source region (105) and the second doping type second source region (118), a drain metal (104) is located above the first doping type drain region (109), wherein the drain metal (104) is in contact with the first doping type drain region (109), a left boundary of the gate oxide layer (103) is tangent to a right boundary of the first doping type first source region (105), and a right boundary exceeds a right boundary of the second doping type body region (106), and a gate (102) is provided above the gate oxide layer (103); The left boundary of the first portion of the buried oxide layer (113) exceeds the first source region (105) of the first doping type, the right boundary exceeds the body region (106) of the second doping type, and the lower boundary is located below the bottom of the first source region (105) of the first doping type; A first gate electrode (111) is provided in the first portion of the buried oxide layer (113), wherein the first gate electrode (111) is located directly below the gate (102) and directly above the second gate electrode; The second gate plate (114) and the first gate plate (111) are connected to the same potential, wherein the first gate plate (111) and the gate (102) are connected to the same potential, or are controlled separately, and the bias voltage of the first gate plate (111) needs to ensure that the channel above the gate plate can be opened.

9. A SOI lateral power semiconductor device, characterized in that: It comprises a substrate (110) of a second doping type, a second buried oxide layer (115) being provided on the substrate, and a second gate electrode plate (114) and a second drift region electrode plate (116) being provided in the second buried oxide layer (115); A first doping type drift region (107) is provided above the second buried oxide layer (115); a second doping type body region (106) and a second portion of the buried oxide layer (120) are provided on the left side of the first doping type drift region (107); and a first doping type drain region (109) is provided on the right side; A first source region (105) of the first doping type, a second source region (118) of the second doping type, and a well region (119) of the first doping type are provided in the body region (106) of the second doping type, wherein the first source region (105) of the first doping type and the second source region (118) of the second doping type are arranged tangentially in the body direction, the first source region (105) of the first doping type and the second source region (118) of the second doping type are located inside the well region (119) of the first doping type, and the right boundaries are tangential to the right boundary of the well region (119) of the first doping type, wherein the upper boundary of the second buried oxide layer (115) exceeds the lower boundary of the well region (119) of the first doping type to ensure that one more channel can be sensed on the upper side of the second buried oxide layer (115); the second gate plate (114) is located directly below the first gate plate (111), and the left and right boundaries are also tangential to the first gate plate (111); A gate oxide layer (103) is provided on the surface of a drift region (107) of the first doping type, a source metal (101) is provided above a first source region (105) of the first doping type and a second source region (118) of the second doping type, wherein the source metal (101) is in contact with the first source region (105) of the first doping type and the second source region (118) of the second doping type, a drain metal (104) is located above a drain region (109) of the first doping type, wherein the drain metal (104) is in contact with the drain region (109) of the first doping type, and a gate (102) is provided above the gate oxide layer (103); The left boundary of the second portion of the buried oxide layer (120) exceeds the first source region (105) of the first doping type, the right side exceeds the body region (106) of the second doping type, and the lower side is located below the bottom of the first source region (105) of the first doping type; A first gate electrode (111) and a first drift region electrode (112) are provided in the second portion of the buried oxide layer (120), wherein the first gate electrode (111) is located directly below the gate (102) and directly above the second gate electrode, and the first drift region electrode (112) is located on the right side of the first gate electrode (111), directly above the second drift region electrode (116), and within the drift region (107) of the first doping type; The second gate plate (114) and the first gate plate (111) are connected to the same potential, wherein the first gate plate (111) and the gate (102) are connected to the same potential, or are controlled separately, and the bias voltage of the first gate plate (111) must ensure that the channel above the gate plate can be opened; The second drift region plate (116) and the first drift region plate (112) are connected to the same potential, wherein the potential of the first drift region plate (112) is controlled separately, and its bias potential is greater than the potential of the first gate plate (111) and less than the potential of the drain metal (104).

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