Vertical LED chip and preparation method thereof

Abstract

The present invention discloses a vertical LED chip and its fabrication method, relating to the field of semiconductor optoelectronic devices. The fabrication method comprises the following steps: providing an epitaxial wafer; forming a dielectric layer, a metal reflective layer, and a bonding layer; bonding the chip to a second substrate; removing the first substrate; removing the N-type contact layer in the area corresponding to the electrode body to form an electrode body hole, the electrode body hole being larger than the electrode body; forming an N-electrode, with the electrode body formed within the electrode body hole; retaining the N-type contact layer below the electrode extension strip and removing the N-type contact layer in other areas; forming a photoresist layer; roughening the N-type semiconductor layer; removing any remaining photoresist layer; and forming a P-electrode on the side of the second substrate away from the bonding layer. Implementation of the present invention can improve the production yield and reliability of vertical LED chips.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor optoelectronic devices, and in particular to a vertical LED chip and a preparation method thereof. Background Art

[0002] In current AlGaInP-based red-yellow or AlGaInAs-based infrared LED chips with reverse polarity vertical thin-film structures, the N-type electrode metal layer and the N-type GaAs ohmic contact layer undergo an annealing process to form a metal-semiconductor ohmic contact. To improve electrode robustness and optimize the current injection path, the N-type GaAs ohmic contact layer is removed below the electrode wire pad area, leaving only the N-type GaAs ohmic contact layer below the electrode fingers. The conventional process involves first etching the N-type GaAs ohmic contact layer to the same shape as the electrode fingers, then fabricating the electrodes. Photolithography is then used to align the electrode fingers with the N-type GaAs ohmic contact layer pattern, ensuring they overlap and encapsulate, protecting the N-type GaAs ohmic contact layer from corrosion by acidic and alkaline solutions in subsequent processing steps. However, with increasing demands for LED chip luminous efficiency, LED chip designs require corresponding reductions in electrode finger width and light shielding, leading to increasingly stringent requirements for the alignment accuracy of the electrode fingers and the N-type GaAs ohmic contact layer pattern. Alignment deviation can lead to high VF of LED chips (abnormal photoelectric parameters) and finger warping (abnormal appearance and reliability). Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a vertical LED chip and a preparation method thereof, which can reduce the electrode alignment accuracy requirements, improve production yield, and enhance reliability.

[0004] To solve the above problems, the present invention provides a method for preparing a vertical LED chip, wherein the vertical LED chip includes an N electrode, wherein the N electrode includes an electrode body and an electrode extension strip, wherein the electrode extension strip is connected to the periphery of the electrode body. The preparation method comprises the following steps:

[0005] S1. Providing an epitaxial wafer, wherein the epitaxial wafer includes a first substrate and an N-type contact layer, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer sequentially stacked on the first substrate;

[0006] S2. forming a dielectric layer, a metal reflective layer and a bonding layer in sequence on the P-type semiconductor layer;

[0007] S3, bonding the epitaxial wafer obtained in step S2 to the second substrate;

[0008] S4, removing the first substrate to expose the N-type contact layer;

[0009] S5, removing the N-type contact layer in the area corresponding to the electrode body to form an electrode body hole, wherein the size of the electrode body hole is larger than the size of the electrode body;

[0010] S6. Forming an N-type electrode on the epitaxial wafer obtained in step S5, wherein the electrode body is formed in the electrode body hole, and the electrode extension strip is at least partially located on the N-type contact layer;

[0011] S7, retaining the N-type contact layer below the electrode extension strip and removing the N-type contact layer in other areas;

[0012] S8, forming a photoresist layer on the epitaxial wafer obtained in step S7, and performing photolithography and development so that the photoresist layer wraps the electrode body and the electrode extension strip;

[0013] S9, performing a roughening process on the N-type semiconductor layer;

[0014] S10, removing the remaining photoresist layer;

[0015] S11. Form a P electrode on a side of the second substrate away from the bonding layer.

[0016] As an improvement of the above technical solution, the N-electrode includes an ohmic metal layer, a bonding wire metal layer and an etching stopper layer sequentially stacked on the N-type contact layer; and / or

[0017] In step S7, the N-type contact layer is removed by etching using the etching stop layer as a mask.

[0018] As an improvement of the above technical solution, in step S10, the photoresist layer and the etching stop layer are removed.

[0019] As an improvement to the above technical solution, an electrode fixing layer is further provided between the N-type contact layer and the N-type semiconductor layer, which is used to improve the adhesion of the ohmic metal layer;

[0020] In step S7, the electrode fixing layer and the N-type contact layer below the electrode extension strip and the electrode fixing layer below the electrode body are retained, and the electrode fixing layer and the N-type contact layer in other areas are removed.

[0021] As an improvement of the above technical solution, the ohmic metal layer is an Au layer, a Ni layer, an AuGe layer or an AuGeNi layer, and its thickness is 0.1 μm to 0.5 μm;

[0022] The bonding wire metal layer is one or more of an Au layer, a Pt layer, a Ti layer, an Al layer or an AlCu layer, and has a thickness of 0.5 μm to 4 μm; and / or

[0023] The etching stop layer is one or more of a Ti layer, a TiW layer, a SiO2 layer, and an Al2O3 layer, and has a thickness of 0.1 μm to 1 μm; and / or

[0024] The dielectric layer is one or more of a SiO2 layer, a MgF2 layer, a TiO2 layer, and a Ti2O5 layer; and its thickness is 0.1 μm to 1 μm; and / or

[0025] The metal reflective layer is one or more of an Au layer, an Ag layer, and an Al layer, and has a thickness of 100 nm to 500 nm.

[0026] The bonding layer is one or more of an Au layer, an Ag layer, a Cu layer, an In layer, a Pb layer or a Sn layer, and has a thickness of 300 nm to 800 nm.

[0027] As an improvement of the above technical solution, the electrode fixing layer is an N-type GaInP layer with a thickness of 1 nm to 10 nm.

[0028] As an improvement to the above technical solution, the N-type contact layer is an N-type GaAs layer; and / or

[0029] The N-type semiconductor layer includes an N-type AlGaAs roughening layer and an N-type AlGaAs confinement layer sequentially stacked on the N-type contact layer; and / or

[0030] The P-type semiconductor layer includes a P-type AlGaAs confinement layer, a P-type AlGaAs current spreading layer and a P-type GaP window layer sequentially stacked on the active layer; and / or

[0031] The first substrate is a GaAs substrate; and / or

[0032] The second substrate is a P-type silicon wafer; and / or

[0033] The epitaxial wafer further includes an N-type GaAs buffer layer and an N-type GaInP etching stop layer which are sequentially arranged between the first substrate and the N-type contact layer.

[0034] As an improvement of the above technical solution, in step S4, the first substrate, the N-type GaAs buffer layer and the N-type GaInP etching dielectric layer are removed to expose the N-type GaAs layer.

[0035] As an improvement to the above technical solution, the electrode body is circular, and its diameter is 50 μm to 120 μm; and / or

[0036] The electrode extension strip is in the shape of a long strip, and its width is 3 μm to 10 μm; and / or

[0037] The cross section of the electrode main body hole is circular, and the diameter thereof is 52 μm to 130 μm.

[0038] Correspondingly, the present invention also discloses a vertical LED chip, which is prepared by the above-mentioned method for preparing the vertical LED chip.

[0039] The implementation of the present invention has the following beneficial effects:

[0040] 1. In the present invention's method for fabricating a vertical chip, an electrode body hole larger than the electrode body is first formed in the N-type contact layer. The electrode body is then formed within the hole, and an electrode extension strip is simultaneously formed around it. The N-type contact layer is then removed except for the area below the electrode extension strip. This method utilizes the larger electrode body for alignment, significantly reducing the requirements for pattern alignment accuracy. This ensures perfect alignment between the electrode extension strip and the underlying N-type contact layer, avoiding anomalies such as excessive reverse voltage and warping caused by alignment deviations, thereby improving the production yield and reliability of vertical LED chips.

[0041] 2. In the present invention's method for fabricating a vertical LED chip, an N-type electrode with an etch-stop layer on its surface is employed. When removing the N-type contact layer, the N-type electrode is directly etched away using the N-type electrode as a mask. This avoids undercutting of the photoresist layer formed in step S8, effectively preserving the photoresist layer intact on the N-type electrode. This effectively protects the N-type electrode structure during roughening of the N-type semiconductor layer, preventing the electrode extension strip from falling off and failing, further improving production yield and reliability.

[0042] 3. In the present invention's method for fabricating a vertical LED chip, an electrode-stabilizing layer is introduced between the N-type contact layer and the N-type semiconductor layer, enhancing the electrode's adhesion and ensuring a more stable bond. Furthermore, the electrode-stabilizing layer is removed using the etch-stop layer as a mask, preventing undercutting of the photoresist layer, protecting the electrode structure, and improving production yield and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 is a schematic cross-sectional structural diagram of an epitaxial wafer in one embodiment of the present invention;

[0044] Figure 2 is a schematic cross-sectional structural diagram of the epitaxial wafer after step S5 in one embodiment of the present invention;

[0045] Figure 3 1 is a schematic diagram of a top view of the epitaxial wafer after step S5 in one embodiment of the present invention;

[0046] Figure 4 is a schematic cross-sectional structural diagram of the epitaxial wafer after step S6 in one embodiment of the present invention;

[0047] Figure 5 is a schematic cross-sectional structural diagram of an epitaxial wafer after step S7 in one embodiment of the present invention;

[0048] Figure 6 1 is a schematic diagram of a top view of the epitaxial wafer after step S7 in one embodiment of the present invention;

[0049] Figure 7 is a schematic cross-sectional structural diagram of the epitaxial wafer after step S8 in one embodiment of the present invention;

[0050] Figure 8 is a schematic cross-sectional view of a vertical LED chip in one embodiment of the present invention;

[0051] In the figure, 1 is an epitaxial wafer, 11 is a first substrate, 12 is an N-type contact layer, 121 is an electrode body hole, 13 is an N-type semiconductor layer, 131 is an N-type AlGaAs roughening layer, 132 is an N-type AlGaAs confinement layer, 14 is an active layer, 15 is a P-type semiconductor layer, 151 is a P-type AlGaAs confinement layer, 152 is a P-type AlGaAs current spreading layer, 153 is a P-type GaP window layer, 16 is an N-type GaAs buffer layer, 17 is an N-type GaInP corrosion stop layer, 18 is an electrode fixing layer, 2 is a dielectric layer, 3 is a metal reflective layer, 4 is a bonding layer, 5 is a second substrate, 6 is an N-electrode, 61 is an electrode body, 62 is an electrode extension strip, 63 is an ohmic metal layer, 64 is a bonding wire metal layer, and 65 is an etching stop layer; 7 is a photoresist layer, and 8 is a P-electrode. DETAILED DESCRIPTION

[0052] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is described in further detail below.

[0053] The present invention provides a method for preparing a vertical LED chip, which comprises the following steps:

[0054] S1: Provide epitaxial wafers;

[0055] Ginseng Figure 1The epitaxial wafer 1 includes a first substrate 11, and an N-type contact layer 12, an N-type semiconductor layer 13, an active layer 14, and a P-type semiconductor layer 15 sequentially arranged on the first substrate 11. Specifically, the LED chip of the present invention can be a red, green, yellow, or violet LED chip. Based on the control of the emission wavelength, different types of semiconductor layers, active layers, and contact layers can be selected. For example, in one embodiment, when the LED chip is a blue LED chip or a green LED chip, the N-type semiconductor layer 13 can be an N-type GaN layer, the active layer 14 can be an InGaN-GaN type multi-quantum well layer, and the P-type semiconductor layer 15 can be a P-type GaN layer, but is not limited to this. In another embodiment, when the LED chip is a violet LED chip, the N-type semiconductor layer 13 can be an N-type AlGaN layer, the active layer 14 can be an AlGaN-AlGaN type multi-quantum well layer, and the P-type semiconductor layer 15 can be a P-type AlGaN layer, but is not limited to this. In another embodiment, when the LED chip is a red light LED chip, the N-type contact layer 12 is an N-type GaAs layer, the N-type semiconductor layer 13 is an N-type AlGaInP layer, the active layer 14 is an AlGaInP-AlGaInP type multi-quantum well layer, and the P-type semiconductor layer 15 is a P-type AlGaInP layer.

[0056] Preferably, in one embodiment, the epitaxial wafer 1 includes an N-type GaAs buffer layer 16, an N-type GaInP etching stop layer 17, an N-type contact layer 12, an N-type semiconductor layer 13, an active layer 14, and a P-type semiconductor layer 15, which are sequentially arranged on a first substrate 11. The first substrate 11 is a GaAs substrate. The N-type contact layer 12 is an N-type GaAs layer. The N-type semiconductor layer 13 includes an N-type AlGaAs roughening layer 131 and an N-type AlGaAs confinement layer 132, which are sequentially stacked on the N-type contact layer 12. The active layer 14 is an AlGaInAs-AlGaInAs type multi-quantum well layer. The P-type semiconductor layer 15 includes a P-type AlGaAs confinement layer 151, a P-type AlGaAs current spreading layer 152, and a P-type GaP window layer 153, which are sequentially stacked on the active layer 14.

[0057] More preferably, in some embodiments, the epitaxial wafer 1 further includes an electrode securing layer 18 disposed between the N-type contact layer 12 and the N-type semiconductor layer 13. Specifically, the electrode securing layer 18 is an N-type GaInP layer. Because it does not incorporate Al, it exhibits strong adhesion to the metal N-electrode. Specifically, the thickness of the electrode securing layer 18 is 1 nm to 10 nm.

[0058] S2: forming a dielectric layer, a metal reflective layer and a bonding layer in sequence on the P-type semiconductor layer;

[0059] The dielectric layer 2 has a low refractive index and can be combined with the metal reflective layer 3 to reflect light and improve light extraction efficiency. Specifically, the dielectric layer 2 is one or more of, but not limited to, a SiO2 layer, a MgF2 layer, a TiO2 layer, or a Ti2O5 layer. A SiO2 layer is preferred. The dielectric layer 2 has a thickness of 0.1 μm to 2 μm, preferably 0.1 μm to 1 μm.

[0060] Specifically, the dielectric layer 2 may be formed by PECVD or MOCVD, but is not limited thereto.

[0061] The metal reflective layer 3 can be one or more of, but not limited to, an Au layer, an Ag layer, or an Al layer. Au is preferred, as it has better adhesion and a reflectivity close to that of Ag. Furthermore, the reflectivity of the Au layer decreases minimally after exposure to high temperatures. The thickness of the metal reflective layer 3 is 100 nm to 600 nm, preferably 100 nm to 500 nm.

[0062] Specifically, the metal reflective layer 3 may be formed by processes such as PVD and evaporation, but is not limited thereto.

[0063] Among them, according to the different later bonding processes, bonding layers 4 of different materials can be used. For example, when a eutectic bonding process is adopted, Au layers, Cu layers, In layers, Pb layers or Sn layers can be used, but are not limited thereto. For another example, when a hot pressing bonding process is adopted, Au layers, Cu layers, Ag layers or Al layers can be used as bonding layers 4, but are not limited thereto. Preferably, in one embodiment, a hot pressing bonding process is adopted for bonding, that is, the bonding layer 4 is selected from Au layers or Ag layers. The bonding layer 4 can assist the metal reflective layer 3 to improve the reflectivity of light; or low-temperature hot pressing bonding can be adopted. During hot pressing bonding, the metal reflective layer 3 and the bonding layer 4 have ductility under the combined action of temperature and pressure, so that the metal is squeezed to fill the gaps on the surface of the epitaxial wafer, that is, the resulting chip has no cavity and can withstand higher pressure without breaking during the later solid crystal and wire bonding processes, thereby improving the yield rate.

[0064] Specifically, the thickness of the bonding layer 4 is 300 nm to 800 nm, preferably 300 nm to 500 nm.

[0065] S3: bonding the epitaxial wafer obtained in step S2 to the second substrate;

[0066] Specifically, the epitaxial wafer and the second substrate 5 can be bonded by eutectic bonding, thermocompression bonding, etc., but are not limited thereto. Preferably, thermocompression bonding is used, with a bonding temperature of 200° C. to 360° C. and a bonding pressure of 8000 kgf to 15000 kgf.

[0067] The second substrate 5 is a common conductive substrate in the art, exemplarily a P-type single crystal silicon substrate.

[0068] S4: removing the first substrate to expose the N-type contact layer;

[0069] Specifically, the first substrate 11 may be removed by an alkali polishing process or a laser lift-off process, but is not limited thereto. Preferably, the first substrate 11 is removed by a laser lift-off process.

[0070] During the removal of the first substrate, the buffer layer, intrinsic GaN layer, etc. disposed on the surface thereof are also removed. In one embodiment of the present invention, the first substrate 11 (GaAs substrate), N-type GaAs buffer layer 16 and N-type GaInP etching stop layer 17 are removed.

[0071] S5: removing the N-type contact layer in the area corresponding to the electrode body to form an electrode body hole;

[0072] The electrode body hole 121 can be formed by photolithography, but is not limited thereto. The size of the electrode body hole 121 is slightly larger than the electrode body 61 to accommodate subsequent alignment errors. Specifically, the electrode body hole 121 is 1 μm to 10 μm larger than the electrode body 61.

[0073] Specifically, refer to Figure 2 and Figure 3 After this step, the N-type contact layer outside the electrode main body hole 121 is retained.

[0074] S6: forming an N electrode on the epitaxial wafer obtained in step S5;

[0075] The N-electrode 6 includes an electrode body 61 and an electrode extension strip 62 connected to the electrode body 61. Specifically, the electrode body 61 can be circular, triangular, or rectangular, but is not limited thereto. It is preferably circular, with a diameter of 50 μm to 120 μm. The electrode extension strip 62 is elongated, but is not limited thereto. The width of the elongated electrode extension strip 62 is 3 μm to 10 μm.

[0076] Specifically, in terms of chemical composition, the N electrode 6 can be one or more of Au layer, Ni layer, AuGe layer, AuGeNi layer, Pt layer, Ti layer, Al layer, and AlCu layer commonly used in the art, but is not limited thereto.

[0077] Specifically, the N electrode 6 may be formed by evaporation, sputtering or other processes, but is not limited thereto.

[0078] Preferably, in one embodiment, reference Figure 4 The N-electrode 6 includes an ohmic metal layer 63, a bonding wire metal layer 64 and an etching stopper layer 65 sequentially stacked on the N-type contact layer 12. The etching stopper layer 65 can protect the ohmic metal layer 63 and the bonding wire metal layer 64 from being etched.

[0079] Specifically, the ohmic metal layer 63 is an Au layer, a Ni layer, an AuGe layer or an AuGeNi layer, but is not limited thereto. The thickness of the ohmic metal layer 63 is 0.1 μm to 0.5 μm. The wire bonding metal layer 64 is one or more of an Au layer, a Pt layer, a Ti layer, an Al layer or an AlCu layer, but is not limited thereto. The thickness of the wire bonding metal layer 64 is 0.5 μm to 4 μm, preferably 1 μm to 3 μm. The etch stop layer 65 is one or more of a Ti layer, a TiW layer, a SiO2 layer, and an Al2O3 layer, but is not limited thereto. Preferably, the etch stop layer 65 is a Ti layer, which not only protects the ohmic metal layer 63 and the wire bonding metal layer 64, but is also easy to remove later, reduces its light absorption, and improves the light efficiency of the vertical LED chip. The thickness of the etch stop layer 65 is 0.1 μm to 1 μm, preferably 0.5 μm to 0.8 μm.

[0080] S7: retaining the N-type contact layer below the electrode extension strip and removing the N-type contact layer in other areas;

[0081] Specifically, the N-type contact layer 12 can be removed by a photolithography and etching process, that is, a photoresist layer is first formed on the epitaxial wafer obtained in step S6, then exposed and developed to obtain a photolithography pattern, and then the N-type contact layer 12 is etched away, but the present invention is not limited thereto.

[0082] Preferably, in one embodiment, when the N-electrode 6 includes an etch stop layer 65, the N-type contact layer in other areas can be directly etched away using the N-electrode as a mask. Based on the above process, not only is the manufacturing process simplified, but side etching of the photoresist layer formed in step S8 is also avoided. That is, the photoresist layer is retained intact on the N-electrode, effectively protecting the N-electrode structure during roughening of the N-type semiconductor layer, preventing the electrode extension strip from falling off and failing, and further improving production yield and reliability.

[0083] More preferably, refer to Figure 5 and Figure 6In one embodiment, when the epitaxial wafer 1 includes an electrode fixing layer 18, it can be removed in this step, that is, the N-type contact layer 12 and the electrode fixing layer 18 are etched away using the N-electrode 6 as a mask. Based on this process, the production yield and reliability can be further improved. It should be noted that, when considering removing the electrode fixing layer 18, those skilled in the art generally tend to adopt a photolithography etching process and integrate this process with the subsequent roughening of the N-type semiconductor layer 13, that is, first forming a layer of photoresist, exposing and developing to form a photolithography pattern, using the photolithography pattern as a mask, etching away the electrode fixing layer, and still using the photolithography pattern as a mask, continuing to roughen the N-type semiconductor layer 13. However, in the process of etching the electrode fixing layer, the plasma will also bombard the photolithography pattern, that is, forming side etching on the photolithography pattern, and even exposing part of the N-electrode, which will corrode the N-electrode in the subsequent roughening process, especially causing the electrode extension strip 62 to fall off, making the chip fail. The present invention uses the N electrode as a mask to remove the N-type contact layer 12 and the electrode fixing layer 18 without etching the photoresist layer, which effectively solves the problem and improves the production yield and chip reliability.

[0084] S8: forming a photoresist layer on the epitaxial wafer obtained in step S7, and performing photolithography and development so that the photoresist layer wraps the electrode body and the electrode extension strip;

[0085] Specifically, the photoresist layer 7 can protect the N-electrode 6 when the N-type semiconductor layer 13 is subsequently roughened.

[0086] S9: roughening the N-type semiconductor layer;

[0087] Specifically, the N-type semiconductor layer may be roughened using an etching solution. More preferably, the N-type AlGaAs roughened layer 131 may be roughened.

[0088] S10: removing the residual photoresist layer;

[0089] Specifically, the photoresist layer can be removed by evaporation, sandblasting, chemical solution cleaning, etc., but is not limited thereto. Preferably, in one embodiment, after removing the residual photoresist layer, the etch stop layer 65 is removed by etching.

[0090] S11: forming a P electrode on a side of the second substrate away from the bonding layer.

[0091] The P electrode 8 may be formed by evaporation, sputtering or other processes. The P electrode 8 may be made of one or more of the Cr layer, Al layer, Pt layer, Au layer and the like commonly used in the art, but is not limited thereto.

[0092] Preferably, in one embodiment, the second substrate 5 is first ground and thinned, and then the P electrode 8 is formed.

[0093] Preferably, in one embodiment, the LED wafer obtained in step S11 is subjected to the processes of cutting, back cutting and splitting to cut the LED wafer into separate LED chips, the structure of which is as follows: Figure 8 shown.

[0094] The above is a preferred embodiment of the invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A method for preparing a vertical LED chip, wherein the vertical LED chip includes an N electrode, the N electrode includes an electrode body and an electrode extension bar, and the electrode extension bar is connected to the periphery of the electrode body; characterized in that: The preparation method comprises the following steps: S1. Providing an epitaxial wafer, wherein the epitaxial wafer includes a first substrate and an N-type contact layer, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer sequentially stacked on the first substrate; S2. forming a dielectric layer, a metal reflective layer and a bonding layer in sequence on the P-type semiconductor layer; S3, bonding the epitaxial wafer obtained in step S2 to the second substrate; S4, removing the first substrate to expose the N-type contact layer; S5, removing the N-type contact layer in the area corresponding to the electrode body to form an electrode body hole, wherein the size of the electrode body hole is larger than the size of the electrode body; S6. Forming an N-type electrode on the epitaxial wafer obtained in step S5, wherein the electrode body is formed in the electrode body hole, and the electrode extension strip is at least partially located on the N-type contact layer; S7, retaining the N-type contact layer below the electrode extension strip and removing the N-type contact layer in other areas; S8, forming a photoresist layer on the epitaxial wafer obtained in step S7, and performing photolithography and development so that the photoresist layer wraps the electrode body and the electrode extension strip; S9, performing a roughening process on the N-type semiconductor layer; S10, removing the remaining photoresist layer; S11. Form a P electrode on a side of the second substrate away from the bonding layer.

2. The method for preparing a vertical LED chip according to claim 1, wherein: The N-electrode comprises an ohmic metal layer, a bonding metal layer and an etching stopper layer sequentially stacked on the N-type contact layer; and / or In step S7, the N-type contact layer is removed by etching using the etching stop layer as a mask.

3. The method for preparing a vertical LED chip according to claim 2, wherein: In step S10 , the photoresist layer and the etching stop layer are removed.

4. The method for preparing a vertical LED chip according to claim 2 or 3, wherein: An electrode fixing layer is further provided between the N-type contact layer and the N-type semiconductor layer, which is used to improve the adhesion of the ohmic metal layer; In step S7, the electrode fixing layer and the N-type contact layer below the electrode extension strip and the electrode fixing layer below the electrode body are retained, and the electrode fixing layer and the N-type contact layer in other areas are removed.

5. The method for preparing a vertical LED chip according to claim 2 or 3, wherein: The ohmic metal layer is an Au layer, a Ni layer, an AuGe layer or an AuGeNi layer, and has a thickness of 0.1 μm to 0.5 μm; The bonding wire metal layer is one or more of an Au layer, a Pt layer, a Ti layer, an Al layer or an AlCu layer, and has a thickness of 0.5 μm to 4 μm; and / or The etching stop layer is one or more of a Ti layer, a TiW layer, a SiO2 layer, and an Al2O3 layer, and has a thickness of 0.1 μm to 1 μm; and / or The dielectric layer is one or more of a SiO2 layer, a MgF2 layer, a TiO2 layer, and a Ti2O5 layer; and its thickness is 0.1 μm to 1 μm; and / or The metal reflective layer is one or more of an Au layer, an Ag layer, and an Al layer, and has a thickness of 100 nm to 500 nm; The bonding layer is one or more of an Au layer, an Ag layer, a Cu layer, an In layer, a Pb layer or a Sn layer, and has a thickness of 300 nm to 800 nm.

6. The method for preparing a vertical LED chip according to claim 4, wherein: The electrode fixing layer is an N-type GaInP layer with a thickness of 1 nm to 10 nm.

7. The method for preparing a vertical LED chip according to claim 1, wherein: The N-type contact layer is an N-type GaAs layer; and / or The N-type semiconductor layer includes an N-type AlGaAs roughening layer and an N-type AlGaAs confinement layer sequentially stacked on the N-type contact layer; and / or The P-type semiconductor layer includes a P-type AlGaAs confinement layer, a P-type AlGaAs current spreading layer and a P-type GaP window layer sequentially stacked on the active layer; and / or The first substrate is a GaAs substrate; and / or The second substrate is a P-type silicon wafer; and / or The epitaxial wafer further includes an N-type GaAs buffer layer and an N-type GaInP etching stop layer which are sequentially arranged between the first substrate and the N-type contact layer.

8. The method for preparing a vertical LED chip according to claim 7, wherein: In step S4, the first substrate, the N-type GaAs buffer layer and the N-type GaInP etching dielectric layer are removed to expose the N-type GaAs layer.

9. The method for preparing a vertical LED chip according to claim 1, wherein: The electrode body is circular, with a diameter of 50 μm to 120 μm; and / or The electrode extension strip is in the shape of a long strip, and its width is 3 μm to 10 μm; and / or The cross section of the electrode main body hole is circular, and the diameter thereof is 52 μm to 130 μm.

10. A vertical LED chip, characterized in that: It is prepared by the preparation method of the vertical LED chip according to any one of claims 1 to 9.

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