Valley voltage detection holding circuit and constant on-time control system

Abstract

The invention discloses a valley voltage detection holding circuit and a constant on-time control system, and relates to the field of analog integrated circuit design, and the circuit comprises a sampling circuit which samples an input power supply and sends a sampling signal to a control circuit; the control circuit is used for detecting the valley voltage of the sampling signal and controlling and maintaining the valley voltage; and the filter circuit filters the high-frequency part of the output voltage. Meanwhile, the circuit is adopted and used in a circuit system based on a COT control mode, a traditional ripple compensation technology is optimized by detecting valley voltage holding, the problem that when the capacitor ESR is small, a traditional COT control step-down converter causes phase lag due to output voltage change, and subharmonic oscillation can be generated is solved, and the voltage-reducing effect of the COT control step-down converter is improved. And the problem that the voltage output precision is reduced due to the introduction of bias voltage in the traditional ripple compensation technology is solved.

Description

Technical Field

[0001] The invention relates to the field of analog integrated circuit design, and in particular to a valley voltage detection and holding circuit and a constant on-time control system. Background Art

[0002] With the rapid development of Internet of Things applications, the supply of high-performance power chips has increased dramatically. The DC / DC converter based on ripple constant on-time (COT) has the advantages of simple structure and fast load transient response, which is very suitable for today's high-power electronic products. Therefore, it plays an increasingly important role in the electronics industry. When the COT control technology is adopted, subharmonic oscillations will occur due to the small equivalent series resistance ESR on the output capacitor, making the system unstable. In order to solve the above problems, ripple compensation technology can be used to solve them. The Chinese patent application with publication number CN106253671A discloses an internal ripple compensation circuit suitable for COT control. Through the internal ripple compensation circuit, the problem of phase lag caused by output voltage changes in the traditional COT control buck converter when the capacitor ESR is small will be solved. Subharmonic oscillations will be generated. However, when the ripple compensation technology is introduced, the bias voltage is also introduced, resulting in reduced voltage output accuracy. Summary of the invention

[0003] The technical solution of the present invention is used to solve the problem that in a COT control mode output circuit, a ripple compensation technology is introduced to eliminate subharmonic oscillations, but a bias voltage is also introduced at the same time, resulting in reduced voltage output accuracy.

[0004] The present invention solves the above technical problems through the following technical means: The present invention discloses a valley voltage detection and holding circuit, the circuit comprising: Sampling circuit, control circuit, filtering circuit.

[0005] The sampling circuit samples the input power supply and sends the sampling signal to the control circuit.

[0006] The control circuit detects the valley voltage of the sampling signal and controls to maintain the valley voltage.

[0007] The filter circuit filters the high frequency part of the output voltage.

[0008] Furthermore, the sampling circuit includes: reference current sources IBIAS1 and IBIAS2; NMOS tubes MN1, MN2, MN3, and MN4; capacitor C1; resistors R1 and R2; and the connection method is: The power supply voltage VIN is connected to one end of the reference current source IBIAS1 and one end of IBIAS2 respectively; the reference voltage VBIAS1 is connected to the gate of the NMOS tube MN1 and the gate of the NMOS tube MN3; the sampling voltage Vsm is connected to the other end of the reference current source IBIAS1, one end of the resistor R1, the drain of the NMOS tube MN1 and the gate of the PMOS tube MP1 respectively; the input voltage VX is connected to the other end of the resistor R1; the other end of the reference current source IBIAS1 is connected to the drain of the NMOS tube NM1, and the other end of the reference current source IBIAS2 is connected to the drain of the NMOS tube NM3; the source of the NMOS tube MN1 is connected to the drain of the NMOS tube MN2; the source of the NMOS tube MN3 is connected to the drain of the NMOS tube MN4; the other end of R2, the source of the NMOS tube MN2, and the source of the NMOS tube MN4 are all grounded; The common connection point of the capacitor C1 and the resistors R1 and R2 is used as the output end of the sampling circuit to send the sampling signal Vsm to the control circuit.

[0009] Furthermore, the sampling circuit operates in the following manner: Assume K is the width-to-length ratio of NMOS tubes MN4 and MN2, then:

[0010] Assume that the current flowing through C1 is IC1 and the current flowing through MN4 is I MN4 , the current flowing through MN2 is I MN2 , the total current flowing through Vsm is I vsm , since MN4 and MN2 form a current mirror, we have:

[0011] Therefore, the equivalent capacitance of C1 is C1 equ equal:

[0012] , Where D is the duty cycle, for the equivalent capacitance C1 equ The charging current I charge and the discharge current I discharge They are:

[0013]

[0014] Therefore, the current is accurately sampled and the current is proportional to the equivalent capacitance C1. equ The ripple formed by charging and discharging contains the information of the sampled current. In order to accurately sample the voltage, there is a time constant:

[0015] Among them, the time constant τ is much larger than the switching period T.

[0016] Preferably, the sampling circuit adjusts the width-to-length ratio of the NMOS transistors MN2 and MN4 to adjust the equivalent resistance of the capacitor C1, thereby adjusting the sampling frequency range of the sampling circuit.

[0017] Furthermore, the control circuit includes: PMOS tubes MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, MP9, MP10, PM11; NMOS tubes MN5, MN6, MN7, MN8, MN9, MN10, MN11, MN12; capacitor C2; resistor R3; the connection method is: The power supply voltage VIN is connected to the sources of the PMOS tubes MP2, MP4, MP6, MP8, MP9, MP10, and MP11 respectively; The reference voltage VBIAS2 is connected to the gate of the PMOS tube MP2; the reference voltage VBIAS3 is connected to the gates of the PMOS tubes MP4 and MP6; the reference voltage VBIAS4 is connected to the gates of the PMOS tubes MP5 and MP7; the reference voltage VBIAS5 is connected to the gates of the NMOS tubes MN5 and MN7; the reference voltage VBIAS6 is connected to the gate of the PMOS tube MP11; The drain of the PMOS tube MP2 is connected to the source of the PMOS tubes MP1 and MP3; the drain of the PMOS tube MP1 is connected to the source of the NMOS tube MN7 and the drain of the NMOS tube MN8; the valley voltage Vvy is connected to the gate of the PMOS tube MP3, one end of the resistors R3 and R4, and the drain of the PMOS tube MP11; the drain of the PMOS tube MP3 is connected to the source of the NMOS tube MN5 and the drain of the NMOS tube MN6; the drain of the PMOS tube MP6 is connected to the source of the PMOS tube MP7; the drain of the PMOS tube MP5 is connected to the drain of the NMOS tube MN5, the drain of the NMOS tube MN6, and the drain of the NMOS tube MN7. The gates of the S transistors MN6 and MN8; the drain of the PMOS transistor MP7 is connected to the drain of the NMOS transistor MN7, the gates of the PMOS transistor MP8 and the NMOS transistor MN9; the drain of the PMOS transistor MP8 is connected to the drain of the NMOS transistor MN9, the gates of the PMOS transistor MP9 and the NMOS transistor MN10; the drain of the PMOS transistor MP9 is connected to the drain of the NMOS transistor MN10, the gates of the PMOS transistor MP10 and the NMOS transistors MN11 and MN12; the drain of the PMOS transistor MP10 is connected to the drain of the NMOS transistor MN11 and the source of the NMOS transistor MN12; One end of the resistor R3 is connected to one end of the capacitor C2; The source terminals of the NMOS tubes MN6, MN8, MN9, MN10, and MN11 and the other terminal of the capacitor C2 are all grounded; The gate of the PMOS tube MP1 is connected to the output of the sampling circuit as the input of the control circuit; the common point of the resistor R3, the PMOS tube MP11, and the NMOS tube MN12 is connected to the output of the control circuit as the input of the filter circuit.

[0018] Furthermore, the control circuit operates in the following manner: When the Vvy voltage is higher than Vsm, the NMOS tube MN12 is turned on, the capacitor C2 is discharged, and the Vvy voltage decreases. When Vvy is lower than Vsm, the PMOS tube MP11 slowly charges the capacitor until it is higher than Vsm.

[0019] Furthermore, the filter circuit includes: a capacitor C3; a resistor R4; and the connection method is: One end of the capacitor C3 is connected to the other end of the resistor R4, and the other end is grounded.

[0020] Furthermore, the operation mode of the filter circuit is specifically as follows: The resistor R4 and the capacitor C3 form a parallel RC low-pass filter to filter out the peaks in the output voltage waveform and obtain a smooth output voltage Vvy_out.

[0021] The present invention also discloses a constant on-time control system, the system comprising: The COT control module is used to control the constant conduction time of the power switch.

[0022] Buck rectifier module, used for DC / DC step-down conversion.

[0023] The ripple compensation module is used to generate a ripple signal.

[0024] The valley voltage detection and holding module adopts the valley voltage detection and holding circuit mentioned above, and is used for sampling the valley voltage of the ripple signal, maintaining it and then filtering and outputting it.

[0025] The feedback voltage module is used for outputting feedback voltage.

[0026] The logic operation module is used to feedback the voltage and superimpose the ripple signal.

[0027] The comparator module is used to compare the output voltage after the ripple is superimposed with the reference voltage, and output a level signal to the COT control module.

[0028] Furthermore, the working process of the above system is as follows: VX obtains a sampling signal Vsm which is linearly related to the inductor current through RC sampling, and the Vsm signal is accompanied by a DC signal which is independent of the inductor current. After passing through the valley voltage detection and holding circuit, a DC signal Vvy_out which is independent of the inductor current is obtained, and Vsm minus Vvy_out obtains a ripple signal with only the inductor current model.

[0029] After the logic operation module, the voltage Vcom is equal to the voltage VFB plus the sampling voltage Vsm, minus the valley voltage Vvy_out; the voltage Vcom is compared with the reference voltage Vref through the comparator module; when the voltage Vcom is smaller than the reference voltage Vref, the power tube M1 is turned on, and the on-time is controlled by the constant on-time controller. When it is turned on, VOUT increases, and VFB increases accordingly. After the constant on-time, the power tube M1 is turned off, the rectifier tube M2 is turned on, and VOUT decreases; after multiple cycles of reciprocating, VOUT finally stabilizes near Vref.

[0030] Since the minimum value of Vcom is equal to the minimum value of VFB, the final value of VOUT is only related to VFB and has no DC error, thereby improving the accuracy of the output voltage.

[0031] The advantages of the present invention are: The present invention optimizes the ripple compensation technology, can eliminate the influence of bias voltage, and improve the accuracy of output voltage. The present invention effectively increases the sampling frequency range by changing the equivalent capacitance, can achieve a wider range of applications, and save integrated circuit area. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 This is a schematic diagram of a valley voltage detection and holding circuit according to a first embodiment of the present invention; Figure 2 This is a structural diagram of a constant on-time control system according to a second embodiment of the present invention; Figure 3 is a signal waveform diagram of VX in the second embodiment of the present invention; Figure 4 1 is a signal waveform diagram of the sampling voltage Vsm and the output valley voltage Vvy_out according to the second embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in combination with the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] Embodiment 1 This embodiment discloses a valley voltage detection and holding circuit. Figure 1 As shown, the circuit comprises: Sampling circuit, control circuit, filtering circuit.

[0034] Furthermore, the sampling circuit samples the input power supply and sends the sampling signal to the control circuit.

[0035] Specifically, Figure 1 As shown, the sampling circuit includes: reference current sources IBIAS1 and IBIAS2; NMOS tubes MN1, MN2, MN3, and MN4; capacitor C1; resistors R1 and R2; and the connection method is: The power supply voltage VIN is connected to one end of the reference current source IBIAS1 and one end of IBIAS2 respectively; the reference voltage VBIAS1 is connected to the gate of the NMOS tube MN1 and the gate of the NMOS tube MN3; the sampling voltage Vsm is connected to the other end of the reference current source IBIAS1, one end of the resistor R1, the drain of the NMOS tube MN1 and the gate of the PMOS tube MP1 respectively; the input voltage VX is connected to the other end of the resistor R1; the other end of the reference current source IBIAS1 is connected to the drain of the NMOS tube NM1, and the other end of the reference current source IBIAS2 is connected to the drain of the NMOS tube NM3; the source of the NMOS tube MN1 is connected to the drain of the NMOS tube MN2; the source of the NMOS tube MN3 is connected to the drain of the NMOS tube MN4; the other end of R2, the source of the NMOS tube MN2, and the source of the NMOS tube MN4 are all grounded; The common connection point of the capacitor C1 and the resistors R1 and R2 is used as the output end of the sampling circuit to send the sampling signal Vsm to the control circuit.

[0036] Furthermore, the operation mode of the sampling circuit is specifically as follows: Assume K is the width-to-length ratio of NMOS tubes MN4 and MN2, then

[0037] Assume that the current flowing through C1 is IC1 and the current flowing through MN4 is I MN4 , the current flowing through MN2 is I MN2 , the total current flowing through Vsm is I vsm , since MN4 and MN2 form a current mirror, we have:

[0038] Therefore, the equivalent capacitance of C1 is C1 equ equal:

[0039] , Where D is the duty cycle, for the equivalent capacitance C1 equ The charging current I charge and the discharge current I discharge They are:

[0040]

[0041] Therefore, the current can be accurately sampled, and the current to the equivalent capacitor C1 equ The ripple formed by charging and discharging contains the information of the sampled current. In order to accurately sample the voltage, there is a time constant:

[0042] Among them, the time constant τ is much larger than the switching period T.

[0043] Preferably, the sampling circuit adjusts the width-to-length ratio of the NMOS transistors MN2 and MN4 to adjust the equivalent resistance of the capacitor C1, thereby adjusting the sampling frequency range of the sampling circuit.

[0044] Furthermore, the control circuit detects the valley voltage of the sampling signal and controls to maintain the valley voltage.

[0045] Specifically, Figure 1 As shown, the control circuit includes: PMOS tubes MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, MP9, MP10, PM11; NMOS tubes MN5, MN6, MN7, MN8, MN9, MN10, MN11, MN12; capacitor C2; resistor R3; the connection method is: The power supply voltage VIN is connected to the sources of the PMOS tubes MP2, MP4, MP6, MP8, MP9, MP10, and MP11 respectively; The reference voltage VBIAS2 is connected to the gate of the PMOS tube MP2; the reference voltage VBIAS3 is connected to the gates of the PMOS tubes MP4 and MP6; the reference voltage VBIAS4 is connected to the gates of the PMOS tubes MP5 and MP7; the reference voltage VBIAS5 is connected to the gates of the NMOS tubes MN5 and MN7; the reference voltage VBIAS6 is connected to the gate of the PMOS tube MP11; The drain of the PMOS tube MP2 is connected to the source of the PMOS tubes MP1 and MP3; the drain of the PMOS tube MP1 is connected to the source of the NMOS tube MN7 and the drain of the NMOS tube MN8; the valley voltage Vvy is connected to the gate of the PMOS tube MP3, one end of the resistors R3 and R4, and the drain of the PMOS tube MP11; the drain of the PMOS tube MP3 is connected to the source of the NMOS tube MN5 and the drain of the NMOS tube MN6; the drain of the PMOS tube MP6 is connected to the source of the PMOS tube MP7; the drain of the PMOS tube MP5 is connected to the drain of the NMOS tube MN5, the drain of the NMOS tube MN6, and the drain of the NMOS tube MN7. The gates of the S transistors MN6 and MN8; the drain of the PMOS transistor MP7 is connected to the drain of the NMOS transistor MN7, the gates of the PMOS transistor MP8 and the NMOS transistor MN9; the drain of the PMOS transistor MP8 is connected to the drain of the NMOS transistor MN9, the gates of the PMOS transistor MP9 and the NMOS transistor MN10; the drain of the PMOS transistor MP9 is connected to the drain of the NMOS transistor MN10, the gates of the PMOS transistor MP10 and the NMOS transistors MN11 and MN12; the drain of the PMOS transistor MP10 is connected to the drain of the NMOS transistor MN11 and the source of the NMOS transistor MN12; One end of the resistor R3 is connected to one end of the capacitor C2; The source terminals of the NMOS tubes MN6, MN8, MN9, MN10, and MN11 and the other terminal of the capacitor C2 are all grounded; The gate of the PMOS tube MP1 is connected to the output of the sampling circuit as the input of the control circuit; the common point of the resistor R3, the PMOS tube MP11, and the NMOS tube MN12 is connected to the output of the control circuit as the input of the filter circuit.

[0046] Furthermore, the control circuit operates in the following manner: When the Vvy voltage is higher than Vsm, the NMOS tube MN12 is turned on, the capacitor C2 is discharged, and the Vvy voltage decreases. When Vvy is lower than Vsm, the PMOS tube MP11 slowly charges the capacitor until it is higher than Vsm. In particular, the above process is repeated.

[0047] Furthermore, the filtering circuit filters the high-frequency part of the output voltage.

[0048] Specifically, Figure 1 As shown, the filter circuit includes: capacitor C3; resistor R4; the connection method is: One end of the capacitor C3 is connected to the other end of the resistor R4, and the other end is grounded; Furthermore, the operation mode of the filter circuit is specifically as follows: The resistor R4 and the capacitor C3 form a parallel RC low-pass filter to filter out the peaks in the output voltage waveform to obtain a smoother output voltage Vvy_out.

[0049] Embodiment 2 It should be further explained that, based on the embodiment and an inventive concept, the present invention also provides a constant on-time control system using a valley voltage detection and holding circuit, which is used in a COT control mode output circuit to eliminate output voltage deviation and improve output accuracy. Figure 2 As shown, the system includes the following modules: The COT control module is used to control the constant conduction time of the power switch.

[0050] Buck rectifier module, used for DC / DC step-down conversion.

[0051] The ripple compensation module is used to generate a ripple signal.

[0052] The valley voltage detection and holding circuit module is used to sample the valley voltage of the ripple signal and hold it before filtering and outputting it.

[0053] The feedback voltage module is used for outputting feedback voltage.

[0054] The logic operation module is used to feedback the voltage and superimpose the ripple signal.

[0055] The comparator module is used to compare the output voltage after the ripple is superimposed with the reference voltage, and output a level signal to the COT control module.

[0056] Furthermore, the system operates in the following manner: like Figure 2 As shown, VX obtains a sampling signal Vsm which is linearly related to the inductor current through RC sampling. The Vsm signal is accompanied by a DC signal which is independent of the inductor current. After passing through the valley voltage detection and holding module, a DC signal Vvy_out which is independent of the inductor current is obtained. In particular, Vsm minus Vvy_out can obtain a ripple signal with only the inductor current model. The valley voltage detection and holding module adopts the circuit structure and operation mode of the above-mentioned embodiment 1. The signal waveform diagram of the above-mentioned VX is shown in FIG. Figure 3 As shown, the signal waveforms of Vsm and Vvy_out are as follows Figure 4 shown.

[0057] Furthermore, after the logic operation module, the voltage Vcom is equal to the voltage VFB plus the sampling voltage Vsm, minus the valley voltage Vvy_out. The voltage Vcom is compared with the reference voltage Vref through the comparator module. When the voltage Vcom is smaller than the reference voltage Vref, the power tube M1 is turned on, and the on-time is controlled by the constant on-time controller. When it is turned on, VOUT increases, and VFB increases accordingly. After the constant on-time, the power tube M1 is turned off, the rectifier tube M2 is turned on, and VOUT decreases. After multiple cycles of reciprocating, VOUT finally stabilizes near Vref.

[0058] Since the minimum value of Vcom is equal to the minimum value of VFB, the final value of VOUT is only related to VFB and has no DC error, thereby improving the accuracy of the output voltage.

[0059] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A valley voltage detection and holding circuit, It is characterized in that The circuit comprises: Sampling circuit, control circuit, filtering circuit; The sampling circuit samples the input power supply and sends the sampling signal to the control circuit; The control circuit detects the valley voltage of the sampling signal and controls to maintain the valley voltage; The filter circuit filters the high frequency part of the output voltage.

2. A valley voltage detection and holding circuit according to claim 1, It is characterized in that The sampling circuit includes: reference current sources IBIAS1 and IBIAS2; NMOS tubes MN1, MN2, MN3, and MN4; capacitor C1; resistors R1 and R2; and the connection method is: The power supply voltage VIN is connected to one end of the reference current source IBIAS1 and one end of IBIAS2 respectively; the reference voltage VBIAS1 is connected to the gate of the NMOS tube MN1 and the gate of the NMOS tube MN3; the sampling voltage Vsm is connected to the other end of the reference current source IBIAS1, one end of the resistor R1, the drain of the NMOS tube MN1 and the gate of the PMOS tube MP1 respectively; the input voltage VX is connected to the other end of the resistor R1; the other end of the reference current source IBIAS1 is connected to the drain of the NMOS tube NM1, and the other end of the reference current source IBIAS2 is connected to the drain of the NMOS tube NM3; the source of the NMOS tube MN1 is connected to the drain of the NMOS tube MN2; the source of the NMOS tube MN3 is connected to the drain of the NMOS tube MN4; the other end of R2, the source of the NMOS tube MN2, and the source of the NMOS tube MN4 are all grounded; The common connection point of the capacitor C1 and the resistors R1 and R2 is used as the output end of the sampling circuit to send the sampling signal Vsm to the control circuit.

3. A valley voltage detection and holding circuit according to claim 2, It is characterized in that The operation mode of the sampling circuit is specifically as follows: Assume K is the width-to-length ratio of NMOS tubes MN4 and MN2, then: Assume that the current flowing through C1 is IC1 and the current flowing through MN4 is I MN4 , the current flowing through MN2 is I MN2 , the total current flowing through Vsm is I vsm , since MN4 and MN2 form a current mirror, we have: Therefore, the equivalent capacitance of C1 is C1 equ equal: ， Where D is the duty cycle, for the equivalent capacitance C1 equ The charging current I charge and the discharge current I discharge They are: Therefore, the current is accurately sampled and the current is proportional to the equivalent capacitance C1. equ The ripple formed by charging and discharging contains the information of the sampled current. In order to accurately sample the voltage, there is a time constant: Among them, the time constant τ is much larger than the switching period T.

4. A valley voltage detection and holding circuit according to claim 3, It is characterized in that The sampling circuit adjusts the width-to-length ratio of the NMOS transistors MN2 and MN4 to adjust the equivalent resistance of the capacitor C1, thereby adjusting the sampling frequency range of the sampling circuit.

5. The valley voltage detection and holding circuit according to claim 1, It is characterized in that The control circuit includes: PMOS tubes MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, MP9, MP10, PM11; NMOS tubes MN5, MN6, MN7, MN8, MN9, MN10, MN11, MN12; capacitor C2; resistor R3; the connection method is: The power supply voltage VIN is connected to the sources of the PMOS tubes MP2, MP4, MP6, MP8, MP9, MP10, and MP11 respectively; The reference voltage VBIAS2 is connected to the gate of the PMOS tube MP2; the reference voltage VBIAS3 is connected to the gates of the PMOS tubes MP4 and MP6; the reference voltage VBIAS4 is connected to the gates of the PMOS tubes MP5 and MP7; the reference voltage VBIAS5 is connected to the gates of the NMOS tubes MN5 and MN7; the reference voltage VBIAS6 is connected to the gate of the PMOS tube MP11; The drain of the PMOS tube MP2 is connected to the source of the PMOS tubes MP1 and MP3; the drain of the PMOS tube MP1 is connected to the source of the NMOS tube MN7 and the drain of the NMOS tube MN8; the valley voltage Vvy is connected to the gate of the PMOS tube MP3, one end of the resistors R3 and R4, and the drain of the PMOS tube MP11; the drain of the PMOS tube MP3 is connected to the source of the NMOS tube MN5 and the drain of the NMOS tube MN6; the drain of the PMOS tube MP6 is connected to the source of the PMOS tube MP7; the drain of the PMOS tube MP5 is connected to the drain of the NMOS tube MN5, the drain of the NMOS tube MN6, and the drain of the NMOS tube MN7. The gates of the S transistors MN6 and MN8; the drain of the PMOS transistor MP7 is connected to the drain of the NMOS transistor MN7, the gates of the PMOS transistor MP8 and the NMOS transistor MN9; the drain of the PMOS transistor MP8 is connected to the drain of the NMOS transistor MN9, the gates of the PMOS transistor MP9 and the NMOS transistor MN10; the drain of the PMOS transistor MP9 is connected to the drain of the NMOS transistor MN10, the gates of the PMOS transistor MP10 and the NMOS transistors MN11 and MN12; the drain of the PMOS transistor MP10 is connected to the drain of the NMOS transistor MN11 and the source of the NMOS transistor MN12; One end of the resistor R3 is connected to one end of the capacitor C2; The source terminals of the NMOS tubes MN6, MN8, MN9, MN10, and MN11 and the other terminal of the capacitor C2 are all grounded; The gate of the PMOS tube MP1 is connected to the output of the sampling circuit as the input of the control circuit; the common point of the resistor R3, the PMOS tube MP11, and the NMOS tube MN12 is connected to the output of the control circuit as the input of the filter circuit.

6. A valley voltage detection and holding circuit according to claim 5, It is characterized in that The operation mode of the control circuit is specifically as follows: When the Vvy voltage is higher than Vsm, the NMOS tube MN12 is turned on, the capacitor C2 is discharged, and the Vvy voltage decreases. When Vvy is lower than Vsm, the PMOS tube MP11 slowly charges the capacitor until it is higher than Vsm.

7. The valley voltage detection and holding circuit according to claim 1, It is characterized in that The filter circuit includes: a capacitor C3; a resistor R4; and the connection method is: One end of the capacitor C3 is connected to the other end of the resistor R4, and the other end is grounded.

8. The valley voltage detection and holding circuit according to claim 7, It is characterized in that The operation mode of the filter circuit is specifically as follows: The resistor R4 and the capacitor C3 form a parallel RC low-pass filter to filter out the peaks in the output voltage waveform and obtain a smooth output voltage Vvy_out.

9. A constant on-time control system, It is characterized in that include: COT control module, used to control the constant conduction time of the power switch; Buck rectifier module, used for DC / DC buck conversion; A ripple compensation module, used for generating a ripple signal; A valley voltage detection and holding module, wherein the valley voltage detection and holding module adopts the valley voltage detection and holding circuit according to any one of claims 1 to 9, and is used for sampling the valley voltage of the ripple signal, maintaining it, and then filtering and outputting it; A feedback voltage module, used for outputting a feedback voltage; Logical operation module, used for feedback voltage superimposed ripple signal; The comparator module is used to compare the output voltage after the ripple is superimposed with the reference voltage, and output a level signal to the COT control module.

10. The constant on-time control system according to claim 9, It is characterized in that The system's workflow is as follows: VX obtains a sampling signal Vsm which is linearly related to the inductor current through RC sampling. The Vsm signal is accompanied by a DC signal which is independent of the inductor current. After passing through the valley voltage detection and holding circuit, a DC signal Vvy_out which is independent of the inductor current is obtained. Vsm minus Vvy_out is used to obtain a ripple signal with only the inductor current model. After the logic operation module, the voltage Vcom is equal to the voltage VFB plus the sampling voltage Vsm, minus the valley voltage Vvy_out; the voltage Vcom is compared with the reference voltage Vref through the comparator module; when the voltage Vcom is smaller than the reference voltage Vref, the power tube M1 is turned on, and the on-time is controlled by the constant on-time controller. When it is turned on, VOUT increases, and VFB increases accordingly. After the constant on-time, the power tube M1 is turned off, the rectifier tube M2 is turned on, and VOUT decreases; after multiple cycles of reciprocating, VOUT finally stabilizes near Vref; Since the minimum value of Vcom is equal to the minimum value of VFB, the final value of VOUT is only related to VFB and there is no DC error.

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