A synchronization signal detection method, device, storage device, program product, chip and computing device for wireless communication

Abstract

A synchronization signal detection method, apparatus, storage device, program product, chip and computing device for wireless communication are provided. The synchronization signal detection method for wireless communication includes acquiring a baseband signal; performing a first process on the baseband signal to obtain a first measurement value of the baseband signal, wherein the first process includes detecting the conjugate symmetry of the baseband signal; performing a second process on the baseband signal to obtain a second measurement value of the baseband signal, wherein the second process includes performing a cross-correlation operation on the baseband signal and a local synchronization signal time domain sequence; in response to the first measurement value and the second measurement value being both greater than their respective threshold values, determining that the synchronization signal has been captured. According to an exemplary embodiment, the detection success rate of the synchronization signal under low signal-to-noise ratio is improved through dual determination of symmetry and cross-correlation.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to a synchronization signal detection method, apparatus, storage device, program product, chip and computing device for wireless communication. Background Art

[0002] The communication terminal implements cell access based on the synchronization signal. The communication terminal should be able to accurately capture the synchronization signal sent by the same communication terminal and detect the synchronization signal to achieve timing synchronization.

[0003] In the related art, the success rate of capturing synchronization signals is low in low signal-to-noise ratio scenarios. In addition, before the synchronization signal is captured, the capture module of the communication terminal works in real time. Due to the high sampling rate and high computational complexity of the synchronization signal capture process, the communication terminal consumes a large amount of computing resources and power consumption, affecting the endurance of the communication terminal.

[0004] It should be noted that the statements herein merely provide background information related to the present disclosure and do not necessarily constitute prior art. Summary of the invention

[0005] In view of the above problems, a synchronization signal detection method, apparatus, storage device, program product, chip and computing device for wireless communication are proposed to overcome the above problems or at least partially solve the above problems.

[0006] The embodiments of the present disclosure adopt the following technical solutions:

[0007] In a first aspect, a synchronization signal detection method for wireless communication is provided, the method comprising: acquiring a baseband signal; performing a first processing on the baseband signal to obtain a first measurement value of the baseband signal, the first processing comprising detecting the conjugate symmetry of the baseband signal; performing a second processing on the baseband signal to obtain a second measurement value of the baseband signal, the second processing comprising performing a cross-correlation operation on the baseband signal and a local synchronization signal time domain sequence; in response to both the first measurement value and the second measurement value being greater than their respective threshold values, determining that the synchronization signal has been captured.

[0008] According to a second aspect, a synchronization signal detection device for wireless communication is provided, the device comprising: a first unit for acquiring a baseband signal; a second unit for performing a first processing on the baseband signal to obtain a first measurement value of the baseband signal, the first processing comprising detecting the conjugate symmetry of the baseband signal; a third unit for performing a second processing on the baseband signal to obtain a second measurement value of the baseband signal, the second processing comprising cross-correlating the baseband signal with a local synchronization signal time domain sequence; and a fourth unit for determining that the synchronization signal has been captured in response to the first measurement value and the second measurement value being both greater than their respective threshold values.

[0009] According to a third aspect, a computer storage medium is provided, on which instructions are stored, which, when executed individually or collectively by at least one processor of a computing device, cause the computing device to perform the method of the first aspect.

[0010] According to a fourth aspect, a computer program product is provided, comprising instructions, which, when executed individually or collectively by at least one processor of a computing device, cause the computing device to perform the method of the first aspect.

[0011] According to a fifth aspect, a chip is provided, wherein the chip comprises a circuit system configured to execute the method according to the first aspect.

[0012] According to a sixth aspect, a computing device is provided, comprising the chip according to the fifth aspect.

[0013] At least one of the above technical solutions adopted by the exemplary embodiment can achieve the following beneficial effects:

[0014] The exemplary embodiment of the present disclosure uses the conjugate symmetry characteristics of the synchronization signal to obtain a first metric value for determining the synchronization signal; and performs a cross-correlation operation between the obtained baseband signal and the local synchronization signal time domain sequence to obtain a second metric value for determining the synchronization signal. The synchronization signal is detected through double determination. The detection probability of the synchronization signal under low signal-to-noise ratio is improved, and the detection performance is good. At the same time, the power consumption of the terminal device is reduced.

[0015] It should be understood that the invention summary is not intended to identify the key or essential features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other objects, features and advantages of the present disclosure will become more apparent through a more detailed description of some embodiments of the present disclosure in the accompanying drawings, in which:

[0017] Figure 1This is a schematic diagram of the first process of the synchronization signal detection method in an embodiment of the present disclosure;

[0018] Figure 2 A schematic diagram of a synchronization signal capture process in an embodiment of the present disclosure;

[0019] Figure 3 This is a schematic diagram of the second process of the synchronization signal detection method in an embodiment of the present disclosure;

[0020] Figure 4 This is a schematic diagram of baseband data preprocessing in an embodiment of the present disclosure;

[0021] Figure 5 This is a schematic diagram of the first implementation of the preprocessing operator in the embodiment of the present disclosure;

[0022] Figure 6 This is a schematic diagram of a second implementation of a preprocessing operator in an embodiment of the present disclosure;

[0023] Figure 7 This is a block diagram of the principle of implementing cross-correlation in the embodiment of the present disclosure;

[0024] Figure 8 A block diagram of a cross-correlation operator implementation in an embodiment of the present disclosure;

[0025] Fig. 9 It is a schematic diagram of a synchronization signal detection device in an embodiment of the present disclosure;

[0026] Fig.10 It is a schematic diagram of the structure of a computing device in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] The principle of the present disclosure will now be described with reference to some embodiments. It should be understood that the description of these embodiments is only for illustrative purposes, and helps those skilled in the art to understand and implement the present disclosure, without any limitation to the scope of the present disclosure. The disclosure described herein can be implemented in a manner different from that described below.

[0028] In the following description and claims, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.

[0029] References in this disclosure to "one embodiment," "an embodiment," "an exemplary embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an exemplary embodiment, whether or not explicitly described, those skilled in the art will recognize that such feature, structure, or characteristic affects incorporation into other embodiments.

[0030] It should be understood that although the terms "first" and "second" etc. may be used to describe various elements herein, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the exemplary embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. The term "and / or" as used herein includes any and all combinations of one or more of the listed terms.

[0031] The terms used herein are only for describing specific embodiments, rather than for limiting exemplary embodiments. The singular forms "one", "an", and "the" used herein also include plural forms, unless the context clearly indicates otherwise. "A group of elements" or "element set" used herein is intended to include one or more elements. It should also be understood that the terms "include", "comprise", "have", "have", "include" and / or "include", when used herein, specify the presence of the features, elements and / or parts, etc., but do not exclude the presence or addition of one or more other features, elements, parts and / or combinations thereof.

[0032] As used in this disclosure, the term "circuitry" may refer to one or more or all of the following:

[0033] (a) Hardware circuit implementation only (e.g., implementation only in analog and / or digital circuits)

[0034] (b) a combination of hardware circuitry and software, such as (where applicable):

[0035] (i) a combination of analog and / or digital hardware circuitry and software / firmware; and

[0036] (ii) any part of a hardware processor (including a digital signal processor) with software, software and memory that work together to enable a device such as a mobile phone or server to perform various functions, and

[0037] (c) A hardware circuit and / or processor, such as a microprocessor or portion of a microprocessor, that requires software (eg, firmware) to operate, but where software is not required for operation, the software may not be present.

[0038] This definition of circuitry applies to all uses of this term in this disclosure, including in any claims. As another example, as used in this disclosure, the term circuitry also includes an implementation of merely a hardware circuit or processor (or multiple processors) or a portion of a hardware circuit or processor and its (or their) accompanying software and / or firmware. The term circuitry also includes, for example, if applicable to the particular claim element, a baseband integrated circuit or processor integrated circuit for a mobile device, or a similar integrated circuit in a server, cellular network device, or other computing network device.

[0039] As used herein, the term "communication network" refers to a network that complies with any appropriate communication standard, such as Long Term Evolution (LTE), LTE-Advanced (LTE-A), Wideband Code Division Multiple Access (WCDMA), High Speed ​​Packet Access (HSPA), Narrowband Internet of Things (NB-IOT), New Radio (NR), Non-terrestrial Network (NTN), etc. In addition, the communication between the terminal equipment and the network equipment in the communication network can be performed according to any appropriate generation of communication protocols, including but not limited to the first generation (1G), second generation (2G), 2.5G, 2.75G, third generation (3G), fourth generation (4G), 4.5G, fifth generation (5G), future sixth generation (6G) communication protocols, and / or any other protocols currently known or to be developed in the future. The embodiments of the present disclosure can be applied in communication systems. In view of the rapid development in communication, there will certainly be future types of communication technologies and systems, and the present disclosure can be implemented with these technologies and systems. It should not be considered that the scope of the present disclosure is limited to the aforementioned system.

[0040] The term "satellite network equipment" used in this article refers to a node set on a satellite in a communication network. The terminal device accesses the network through this node and receives services from it. Depending on the terminology and technology applied, the satellite network equipment may refer to a base station (BS) or access point (AP) as a satellite payload, such as a node B (NodeB or NB), an evolved NodeB (eNodeB or eNB), a NR NB (also known as a gNB), a remote radio unit (RRU), a radio head (RH), a remote radio head (RRH), and a relay node. An example of a relay node may be an integrated access and backhaul (IAB) node. The distributed unit (DU) part of the IAB node can perform the functions of a "satellite network equipment" and can therefore operate as a network device. In the following description, the terms "satellite network equipment", "BS" and "node" may be used interchangeably.

[0041] The term "terminal device" refers to any terminal device capable of wireless communication. As an example and not a limitation, a terminal device may also be referred to as a communication device, a user equipment (UE), a user station (SS), a portable user station, a mobile station (MS), or an access terminal (AT). The terminal device may include, but is not limited to, a mobile phone, a cellular phone, a smart phone, a voice over IP (VoIP) phone, a wireless local loop phone, a tablet computer, a wearable terminal device, a personal digital assistant (PDA), a portable computer, a desktop computer, an image capture terminal device such as a digital camera, a game terminal device, a music storage and playback device, a vehicle-mounted wireless terminal device, a wireless endpoint, a mobile station, a notebook embedded device (LEE), a laptop mounted device (LME), a USB dongle, a smart device, a wireless user equipment (CPE), an Internet of Things (IoT) device, a watch or other wearable device, a head mounted display (HMD), a vehicle, a drone, medical equipment and applications (e.g., remote surgery), industrial equipment and applications (e.g., robots and / or other wireless devices operating in the context of an industrial and / or automated processing chain), consumer electronic devices, relay nodes, devices operating on commercial and / or industrial wireless networks, etc. The mobile terminal (MT) part of the IAB node can perform the functions of a "terminal device" and can therefore operate as a terminal device. In the following description, the terms "terminal device", "communication device", "terminal", "user equipment" and "UE" can be used interchangeably.

[0042] Although the functions described herein may be performed in fixed and / or wireless network nodes in various exemplary embodiments, in other exemplary embodiments, the functions may be implemented in a user equipment device (such as a cellular phone, or a tablet computer, or a laptop computer, or a desktop computer, or a mobile Internet of Things device, or a fixed Internet of Things device). For example, the user equipment device may appropriately have the corresponding capabilities described in relation to fixed and / or wireless network nodes. The user equipment device may be a user device and / or a control device, such as a chipset or a processor, which is configured to control the user device when the user device is installed therein. Examples of these functions include boot server functions and / or home user servers, which may be implemented in a user equipment device by providing the user equipment device with software configured to cause the user equipment device to execute from the perspective of these functions / nodes.

[0043] The technical terms involved in this disclosure are as follows:

[0044] PSS, (Primary Synchronization Signal) primary synchronization signal;

[0045] SSB, (Synchronized Shared Channel) synchronization signal block;

[0046] SCS, (sub-carrier space) sub-carrier spacing;

[0047] In an exemplary embodiment, in response to the current situation of low success rate of synchronization signal detection in related technologies, a synchronization signal detection method with strong universality is designed. This method utilizes the conjugate symmetry characteristics of the synchronization signal to obtain the symmetry value, and obtains the correlation value between the baseband signal and the local synchronization signal time domain sequence. Through double judgment, the detection success rate of the synchronization signal under low signal-to-noise ratio is improved, the power consumption of the communication terminal is reduced, and the user perception is improved.

[0048] The technical solutions provided by various embodiments of the present disclosure are described in detail below in conjunction with the accompanying drawings.

[0049] The disclosed embodiments provide a synchronization signal detection method, apparatus, storage device, program product, chip, and computing device for wireless communication. Figure 1 As shown, a first flow chart of a synchronization signal detection method 100 in an embodiment of the present disclosure is provided, and the synchronization signal detection method 100 at least includes the following steps S110 to S140.

[0050] Step S110, acquiring a baseband signal.

[0051] The baseband signal includes a synchronization signal. The first step to obtain the baseband signal is to obtain the information of the synchronization signal in the baseband signal. Figure 2 As shown in the figure, during the downlink synchronization process, the capture of the synchronization signal has two main functions: detection and timing synchronization. Detection is that the receiver (e.g., terminal equipment) distinguishes noise and target signals from the received signal and identifies the type of target signal according to the baseband processing algorithm. Timing synchronization is that the receiver estimates the starting position of the target signal from the received signal according to the baseband processing algorithm, so that the entire target signal can be obtained based on prior information (target signal length).

[0052] The synchronization signal is carried by the synchronization signal block SSB, including the primary synchronization signal PSS, the secondary synchronization signal SSS, etc. Taking the primary synchronization signal PSS of 5GNR as an example, the primary synchronization signal PSS is the first symbol of SSB, so the core task of SSB capture is to detect and synchronize the PSS. The receiver executes the capture algorithm to determine whether the PSS has been received from the baseband signal from the down-conversion module, and obtains the type of PSS (in the example of 5G NR, there are 3 possible sequence numbers) and the starting time to complete the capture of SSB. PSS is composed of M sequences and has correlation characteristics, that is, the cross-correlation function of the specified PSS and the other two sequence numbers of PSS and noise has no obvious peak, and its autocorrelation function is at zero position. The PSS sequence is broadcast periodically in the downlink transmission, and the PSS broadcast period is uncertain, including 5ms, 10ms, 20ms, 40ms, and 80ms. In order to avoid missing the PSS symbol, all received signal data needs to be detected.

[0053] It should be understood that, as used herein, the term "obtain" may refer to "receiving" from an external communication device, or may refer to "reading" from an internal storage device.

[0054] Step S120: performing a first processing on the baseband signal to obtain a first metric value of the baseband signal, wherein the first processing includes detecting a conjugate symmetry of the baseband signal.

[0055] The synchronization signal block in the baseband signal carries the synchronization signal. The primary synchronization signal PSS of 5G NR is used as an example. PSS is a pseudo-random sequence with a length of 127. It uses the frequency domain BPSK M sequence and is a real sequence with a value of ±1. It can be expressed as According to the discrete Fourier transform, the time domain signal The expression is s m ( n ) = IFFT [ S m ( k ) ] = 1 N ∑ k = 0 N − 1 S m ( k ) e j 2 π N k ;in, n ∈ [ 0 , N − 1 ] , N represents the number of IFFT points; m is , m ∈ [ 0 , 2 ] Depending on the value of n, it can be divided into three cases:

[0056] When n=1,…,N / 2-1,

[0057] ;

[0058] ;because is a real sequence, so we have , where the symbol * represents conjugation.

[0059] When n=0, ;

[0060] When n=N / 2, ;

[0061] From the above, we can see that when n=0,1,…,N-1, the PSS time domain signal has the property of conjugate symmetry. The conjugate symmetry characteristic of the received baseband signal is used to perform central symmetry processing on the signal sequence of the received baseband signal. The symmetry processing includes obtaining a signal sequence of the baseband signal to be processed each time, the sequence length is N, N is an even prime greater than 2, and taking N / 2 as the center, performing a complex conjugate operation on the mutually symmetric signal sequences to obtain a symmetry value. It can be understood that the first metric value includes the symmetry value.

[0062] Step S130: performing a second process on the baseband signal to obtain a second metric value of the baseband signal, wherein the second process includes performing a cross-correlation operation on the baseband signal and a local synchronization signal time domain sequence.

[0063] The baseband signal is subjected to a second processing, including the second processing of the synchronization signal in the baseband signal. Based on step S120, it can be known that when the baseband signal is processed, the baseband signal needs to be captured and then processed. Figure 3 As shown, the processing of the baseband signal includes caching the captured baseband signal in the shift register. The shift register depth can be set to the sequence length of the baseband signal processed each time, and the depth value of the storage is set to N, where N is an even number greater than 2. The shift register is continuously shifted right under the drive of the sampling clock, and the new sampling data enters the shift register from the leftmost side. Each right shift is used to process the baseband signal sequence.

[0064] The baseband signal sequence in the register performs correlation capture with the locally stored local synchronization signal time domain signal. Taking the primary synchronization signal PSS in the synchronization signal as an example, this process is expressed as: the above baseband signal sequence is cross-correlated with multiple locally stored PSS time domain signals to obtain the correlation peak. Taking 5G NR as an example, PSS has three different sequences, so the above baseband signal sequence needs to be cross-correlated with three locally stored PSS time domain signals.

[0065] Step S140: In response to the first metric value and the second metric value both being greater than respective threshold values, it is determined that the synchronization signal has been captured.

[0066] In the case where it is determined that the above-mentioned cross-correlation peak value and the above-mentioned symmetry value are both greater than the corresponding threshold values, it is determined that the synchronization signal has been successfully captured. If the synchronization signal is captured, the sequence and position information of the synchronization signal are obtained. If the synchronization signal is not captured, a sampling point is moved and the capture is continued.

[0067] It should be understood that according to the conjugate symmetry of the synchronization signal, the symmetry value is obtained through the conjugate operation, and the correlation peak is obtained by performing a cross-correlation operation between the baseband signal and the local synchronization signal time domain sequence. The symmetry value and the correlation peak are compared with their respective threshold values ​​to determine the captured synchronization signal. The detection success rate of the synchronization signal under low signal-to-noise ratio is improved through double judgment.

[0068] In some embodiments, the first processing of the baseband signal to obtain a first measurement value of the baseband signal includes: reading a signal sampling sequence of the baseband signal with a length of N, where N is an even number greater than 2; taking the center point of the signal sampling sequence as a reference, performing complex conjugate multiplication and summing the sampling data whose positions are symmetrical to each other to obtain the first measurement value indicating the conjugate symmetry of the baseband signal.

[0069] like Figure 4 As shown, the acquired baseband signal is stored in a shift register, the depth of the shift register is the sequence length of the baseband signal processed each time, and the depth of the shift register is at least an integer N greater than 2. When the baseband signal is subjected to symmetry processing, the baseband signal sequence N in the shift register is read. In the example where N is an even number, the sampled data with mutually symmetrical positions are complex conjugate multiplied and summed with the N / 2th sampled data in the baseband signal sequence as the center to obtain the symmetry value indicating the conjugate symmetry of the baseband signal. The shift register is continuously shifted right under the driving of the sampling clock, and the symmetry processing of the baseband signal sequence is performed once for each right shift.

[0070] It should be noted that the first processed baseband signal includes a synchronization signal obtained by performing multiple decimation on the baseband signal.

[0071] Continue to refer Figure 3 , down-convert or low-pass filter the sampled air interface data to obtain baseband signal data; perform multiple decimation on the baseband signal data after down-conversion or low-pass filtering. Taking the subcarrier spacing SCS=120kHz of the 5G NR working frequency band FR2 as an example, the channel bandwidth is 100MHz and the system sampling rate is 122.88MHz. The current SSB bandwidth is fixed at 240*120kHz=28.8MHz, so the baseband signal sampling rate only needs to be 30.72MHz, which can be decimated four times.

[0072] Let the baseband signal (signal sampling sequence) after four times extraction be ,in and They represent the I and Q paths of the received signal respectively.

[0073] The received baseband signal is folded in half with N / 2 as the center, and then complex conjugate multiplication is performed one by one, that is, each data after N / 2 in the received vector (that is, from N / 2+1 to N-1) is complex conjugate multiplied with the corresponding data in the symmetrical position (from N / 2-1 to 1), and the result can be used as a symmetry value to measure the symmetry. This operation can be expressed as:

[0074] in, is the normalized frequency deviation.

[0075] In the above manner, the symmetry value of the baseband signal can be obtained.

[0076] It can be understood that by symmetry processing of the baseband signal, a signal sequence with symmetry in the baseband signal can be screened out, so as to preliminarily determine whether there is a synchronization signal in the baseband signal, such as the main synchronization signal PSS, and reduce the false alarm probability of PSS detection through the symmetry value.

[0077] In some implementations, the local synchronization signal time domain sequence includes multiple time domain signal sequences, and the multiple time domain signal sequences all have conjugate symmetry. The second processing of the baseband signal to obtain the second measurement value of the baseband signal includes: reading a signal sampling sequence of the baseband signal with a length of N, where N is an even number greater than 2; based on the conjugate symmetry of the multiple time domain signal sequences, preprocessing the signal sampling sequence, the preprocessing including horizontal flipping, translation and linear combination of the I-path component and the Q-path component of the signal sampling sequence; cross-correlating the preprocessed signal sampling sequence with the multiple time domain signal sequences to obtain multiple second measurement values ​​indicating the cross-correlations between the baseband signal and the multiple time domain signal sequences. The signal sampling sequence is represented as ,in and are the I-path component and the Q-path component of the signal sampling sequence respectively, and the multiple time domain signal sequences are expressed as , m∈[0, M-1], where and are the I-path component and the Q-path component of the time domain signal sequence, respectively, M is the number of the multiple time domain signal sequences, and the preprocessing of the signal sampling sequence includes: based on Calculate intermediate sequence , , , :

[0078] , τ is the function independent variable. In one example, in order to use the fast Fourier algorithm for calculation, N is a power of 2.

[0079] The performing cross-correlation operations on the pre-processed signal sampling sequence and the multiple time domain signal sequences respectively comprises: based on the intermediate sequence , , , Calculate multiple cross-correlation peaks , as the plurality of second metric values:

[0080] The second metric value of the baseband signal includes a cross-correlation peak, and the synchronization signal includes a 5G NR primary synchronization signal PSS. Figure 3 Taking the primary synchronization signal PSS as an example, obtaining the cross-correlation peak mainly includes the following steps:

[0081] Step 1: Let the baseband signal (signal sampling sequence) after quadruple decimation be ,in and They represent the I and Q paths of the received signal respectively.

[0082] Step 2: Perform cross-correlation operation between the signal sampling sequence and the local PSS time domain signal:

[0083] The signal sampling sequence is respectively related to the three local PSS time domain signals Perform cross-correlation operation. Among them, the PSS time domain signal sequence is expressed as , m∈[0, M-1], and are the I-path component and the Q-path component of the PSS time domain signal sequence, respectively, and M is the number of the multiple time domain signal sequences (in the example of 5G NR described above, M=3). The cross-correlation calculation formula is:

[0084] P corr , m ( τ ) = | ∑ n = 0 N − 1 s m * ( n ) r ( n + τ ) | 2 = | s m * ( 0 ) r ( τ ) + s m * ( N / 2 ) r ( n + N / 2 ) + ∑ n = 1 N / 2 − 1 [ s m * ( n ) r ( n + τ ) + s m * ( N − n ) r ( N − n + τ ) ] | 2

[0085] according to The conjugate symmetry characteristics of can be obtained:

[0086] P corr , m ( τ ) = | s m * ( 0 ) r ( τ ) + s m * ( N / 2 ) r ( n + N / 2 + τ ) + ∑ n = 1 N / 2 − 1 [ s m * ( n ) r ( n + τ ) + s m ( n ) r ( N − n + τ ) ] | 2

[0087] Will and Substitution Available

[0088] P corr , m ( τ ) = | [ s m , i ( 0 ) − js m , q ( 0 ) ] [ r i ( τ ) + jr q ( τ ) ] + [ s m , i ( N / 2 ) − js m , q ( N / 2 ) ] [ r i ( N / 2 + τ ) + jr q ( N / 2 + τ ) ] + ∑ n = 1 N / 2 − 1 { s m , i ( n ) [ r i ( n + τ ) + r i ( N − n + τ ) ] + s m , q ( n ) [ r q ( n + τ ) − r q ( N − n + τ ) ] } − j ∑ n = 1 N / 2 − 1 { s m , q ( n ) [ r i ( n + τ ) − r i ( N − n + τ ) ] − s m , i ( n ) [ r q ( n + τ ) + r q ( N − n + τ ) ] } | 2 The cross-correlation peak of the baseband signal can be obtained in the above manner. In one example, the cross-correlation operation can be divided into two sub-steps:

[0089] Step 2-1, preprocess the extracted baseband signal data:

[0090]

[0091] Preprocessing is to simplify Calculation of. In the formula, τ is the function variable, To be separated from , , , A total of 4 numbers are multiplied. To be separated from , , , A total of 4 numbers are multiplied, and a total of 8 multiplication operations are required. After preprocessing, the number of multiplication operations can be reduced to 4. It should be noted that the subscript r consists of 3 letters. The first letter p represents preprocessing, the second letter represents the real part or imaginary part (i represents the real part, q represents the imaginary part), and the third letter represents addition and subtraction operations (a represents addition, s represents subtraction). For example, the subscript pia represents preprocessing addition of the real part, and pqs represents preprocessing subtraction of the imaginary part.

[0092] Step 2-2, cross-correlation with the local PSS time domain sequence:

[0093] P corr , m ( τ ) = | [ s m , i ( 0 ) − js m , q ( 0 ) ] [ r i ( τ ) + jr q ( τ ) ] + [ s m , i ( N / 2 ) − js m , q ( N / 2 ) ] [ r i ( N / 2 + τ ) + jr q ( N / 2 + τ ) ] + ∑ n = 1 N / 2 − 1 { s m , i ( n ) r pia + s m , q ( n ) r pq } − j ∑ n = 1 N / 2 − 1 { s m , q ( n ) r pis − s m , i ( n ) r pq } | 2

[0094] It can be understood that when performing the cross-correlation operation, this solution uses the 127 PSS sequences in the received signal to correlate with the local 127 PSS sequences, thereby improving the detection probability of the synchronization signal under a low signal-to-noise ratio.

[0095] In some embodiments, the signal sampling sequence is buffered in a shift register, and the preprocessing is implemented by a preprocessing circuit, which includes 4 parallel adders ( Figure 5 ) or 1 serial adder ( Figure 6 In some embodiments, the cross-correlation operation between the pre-processed signal sampling sequence and the multiple time-domain signal sequences is implemented by M cross-correlation circuits, each cross-correlation circuit includes N / 2-1 cross-correlation circuit units, each cross-correlation circuit unit includes 4 real multipliers and 2 adders, or 1 real multiplier, 1 delay and 1 adder ( Figure 8 ).

[0096] In such an example, the cross-correlation operation is implemented in hardware, see Figure 4The preprocessing circuit includes a preprocessing unit. The preprocessing unit is composed of N / 2-1 preprocessing operators, and the sampled data is sent to the corresponding preprocessing operator as shown in FIG4. Figure 5 As shown, the function of each preprocessing operator is to implement the centrally symmetric vector element values ​​through adders, and a total of 4 adders are required. In one example, considering that the system clock is 4 times the sampling clock, in order to save resources, when implementing the preprocessing operator, 4 parallel adders are implemented using 1 serial adder, as shown in Figure 6 shown.

[0097] It can be understood that there are two possible implementation schemes to achieve cross-correlation with a local PSS time domain sequence of length N. Both schemes require a shift register depth of N, and the second scheme requires the addition of N / 2 adders.

[0098] The cross-correlation circuit implements its function by the cross-correlation module. The baseband data after receiving data preprocessing is cross-correlated with the local PSS time domain sequence. Since 5G NR has three different PSS sequences, the receiving end does not know which PSS sequence is in the current sampled data. In order to achieve the purpose of real-time processing, three parallel cross-correlation modules are required. The principle block diagram of each cross-correlation module is as follows: 7, the symbol " " represents complex multiplication, each of which corresponds to a cross-correlation operator (such as 7), it can be seen that each cross-correlation module is composed of N / 2 cross-correlation operators. The cross-correlation module performs N / 2-1 point cross-correlation on the pre-processed sampled data and a local PSS time domain sequence.

[0099] according to From the calculation formula, it can be seen that each preprocessed sample data multiplied by the corresponding PSS time domain sequence requires 4 real number multipliers and 2 adders. That is,

[0100] , which is calculated by Figure 7 In one example, , , and It is calculated serially under the drive of the system clock. The system clock frequency is more than 4 times greater than the sampling clock frequency. By multiplexing a multiplier, one multiplier can complete 4 parallel multiplier operations. Figure 8 The method shown in the figure only requires one real number multiplier and one adder to realize the function of the cross-correlation operator. In the figure, z-1 represents a delay of one system clock cycle, and "×" represents real number multiplication.

[0101] It can be understood that there are two implementation schemes to implement the cross-correlation operation with the local PSS time domain sequence (real part + imaginary part) of length N. The first scheme requires a storage space depth of N×3 to store the local PSS sequence, N×4×3 real multipliers required for the cross-correlation operation, and N×2×3 adders required for the cross-correlation operation. The second scheme will have a storage space depth of N×3 / 2, N / 2×3 real multipliers required for the cross-correlation operation, and N / 2×3 adders required for the cross-correlation operation. Of the two schemes, the second scheme reduces the amount of hardware and computational complexity.

[0102] Continue to refer Figure 3 After obtaining the maximum correlation peak and symmetry value, the cross-correlation test results Cross-correlation threshold Compare and compare the symmetry test results Symmetry Threshold Compare, if both exceed the corresponding threshold, it is considered that the PSS signal is captured, and the detected PSS sequence number, start time and success indication are output; complete the timing operation and exit the capture; if at least one of the maximum peak value and symmetry value of the cross-correlation is less than the corresponding threshold, then output the PSS capture failure flag. When the sampling pulse arrives, update the shift register and continue to capture the PSS.

[0103] In order to better illustrate the technical effect of the present disclosure, the complexity of the time domain PSS detection method proposed in the present disclosure and the conventional method are compared. The comparison results are as follows: shown.

[0104] Real number multiplication times Number of additions Storage Space Conventional solution N×12 N×6 N×4 This public scheme N×3 / 2 N×2 N×5 / 2

[0105] It can be understood that the exemplary embodiment proposes a synchronization signal detection method that reduces the computational complexity in synchronization signal capture, performs central symmetry preprocessing on the acquired baseband signal by utilizing the conjugate symmetry characteristics of the synchronization signal in the time domain, and adopts downsampling technology using the synchronization signal to achieve a significant reduction in multiplier and adder resources, thereby reducing the consumption of multiplication and addition resources, and also reducing the power consumption of the receiver and improving the battery life.

[0106] The embodiment of the present disclosure also provides a synchronization signal detection device 900 for wireless communication, such as Fig. 9 As shown, the synchronization signal detection device 900 at least includes: a first unit 910, a second unit 920, a third unit 930, and a fourth unit 940, wherein:

[0107] The first unit 910 is specifically configured to obtain a baseband signal by down-converting or low-pass filtering the air interface signal to obtain the baseband signal.

[0108] The second unit 920 is specifically configured to: perform a first processing on the baseband signal to obtain a first measurement value of the baseband signal, wherein the first processing includes detecting a conjugate symmetry of the baseband signal.

[0109] The third unit 930 is specifically used to: perform a second processing on the baseband signal to obtain a second metric value of the baseband signal, wherein the second processing includes performing a cross-correlation operation on the baseband signal and a local synchronization signal time domain sequence.

[0110] The fourth unit 940 is specifically configured to: in response to the first metric value and the second metric value both being greater than respective threshold values, determine that the synchronization signal has been captured.

[0111] The above-mentioned synchronization signal detection device can implement each step of the synchronization signal detection method provided in the aforementioned embodiment. The relevant explanations about the synchronization signal detection method are applicable to the PSS signal detection device and will not be repeated here.

[0112] Although specific functions are discussed above with reference to specific units, it should be noted that the functions of the various units discussed herein can be divided into multiple units, and / or at least some functions of multiple units can be combined into a single unit. The specific unit discussed herein performs an action including the specific unit itself performing the action, or alternatively the specific unit calls or otherwise accesses another component or unit that performs the action (or performs the action in conjunction with the specific unit). Therefore, the specific unit that performs an action can include the specific unit itself that performs the action and / or another unit that the specific unit calls or otherwise accesses and performs the action.

[0113] It should also be understood that various techniques may be described herein in the general context of software hardware elements or program units. Fig. 9 The various units described may be implemented in hardware or in hardware in combination with software and / or firmware. For example, these units may be implemented as computer program code / instructions configured to be executed in one or more processors and stored in a computer-readable storage medium. Alternatively, these units may be implemented as hardware logic / circuits.

[0114] The embodiment of the present disclosure also provides a computer storage medium on which instructions are stored. When the instructions are executed individually or collectively by at least one processor of a computing device, the computing device is caused to execute the method of the first aspect.

[0115] The embodiment of the present disclosure also provides a computer program product, including instructions, which, when executed individually or collectively by at least one processor of a computing device, enable the computing device to execute the above-mentioned synchronization signal detection method.

[0116] The embodiment of the present disclosure further provides a chip, the chip comprising a circuit system, the circuit system being configured to execute the above synchronization signal detection method. It should be noted that the circuit system may be a dedicated integrated circuit, a general-purpose processor, or a combination thereof.

[0117] An embodiment of the present disclosure also provides a computing device, comprising the above-mentioned chip.

[0118] Fig.10 1 is a simplified block diagram of a computing device 1000 suitable for implementing embodiments of the present disclosure. As shown, the computing device 1000 includes one or more processors 1010, one or more memories 1020 coupled to the processors 1010, and one or more communication modules 1040 coupled to the processors 1010.

[0119] The communication module 1040 is used for two-way communication. The communication module 1040 has at least one antenna to facilitate communication. The communication interface may represent any interface necessary for communicating with other network elements.

[0120] Processor 1010 may be of any type suitable for the local technology network, and may include, as non-limiting examples, one or more of: a general purpose computer, a special purpose computer, a microprocessor, a digital signal processor (DSP), and a processor based on a multi-core processor architecture. Computing device 1000 may have multiple processors, such as application specific integrated circuit chips, which are driven in time to a clock that synchronizes a main processor.

[0121] The memory 1020 may include one or more non-volatile memories and one or more volatile memories. Examples of non-volatile memories include, but are not limited to, read-only memory (ROM) 1024, electrically programmable read-only memory (EPROM), flash memory, hard disk, compact disk (CD), digital video disk (DVD), and other magnetic and / or optical memories. Examples of volatile memories include, but are not limited to, random access memory (RAM) 1022 and other volatile memories that do not persist during the duration of a power outage.

[0122] Computer program 1030 includes computer executable instructions executed by associated processor 1010. Program 1030 may be stored in ROM 1024. Processor 1010 may perform any appropriate actions and processes by loading program 1030 into RAM 1022.

[0123] The embodiments of the present disclosure may be implemented by the program 1030 so that the computing device 1000 may execute the reference Figure 1 Any process of the disclosure discussed. The embodiments of the present disclosure may also be implemented by hardware or by a combination of software and hardware.

[0124] In some embodiments, the program 1030 may be tangibly embodied in a computer-readable medium, which may be contained in the computing device 1000 (e.g., memory 1020) or other storage device accessible to the computing device 1000. The computing device 1000 may load the program 1030 from the computer-readable medium to the RAM 1022 for execution. The computer-readable medium may include any type of tangible non-volatile memory, such as ROM, EPROM, flash memory, hard disk, CD, DVD, etc. The computer-readable medium has the program 1030 stored thereon.

[0125] It should be noted that computing devices include but are not limited to terminal devices, base station devices (for example, ground base stations or satellite network devices), and devices that can implement the above-mentioned synchronization signal detection method all fall within the scope of protection of the present disclosure.

[0126] Generally, various embodiments of the present disclosure may be implemented in hardware or dedicated circuits, software, logic, or any combination thereof. Certain aspects may be implemented in hardware, while other aspects may be implemented in firmware or software, which may be executed by a controller, microprocessor, or other computing device. Although various aspects of the embodiments of the present disclosure are shown and described as block diagrams, flow charts, or using some other graphical representations, it should be understood that, as non-limiting examples, the blocks, devices, systems, techniques, or methods described herein may be implemented in hardware, software, firmware, dedicated circuits or logic, general hardware or controllers or other computing devices, or some combination thereof.

[0127] The present disclosure also provides at least one computer program product tangibly stored on a non-transient computer-readable storage medium. The computer program product includes computer executable instructions, such as instructions included in program modules, which are executed in a device on a target real or virtual processor. Typically, program modules include routines, programs, libraries, objects, classes, components, data structures, etc. that perform specific tasks or implement specific abstract data types. In various embodiments, the functions of program modules can be combined or separated between program modules as needed. Machine executable instructions for program modules can be executed in local or distributed devices. In distributed devices, program modules can be located in local and remote storage media.

[0128] The program code for executing the disclosed method can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer or other programmable data processing equipment so that when the program code is executed by the processor or controller, the function / operation specified in the flow chart and / or block diagram is realized. The program code can be executed completely on the machine as an independent software package, partially on the machine, partially on the machine, partially on a remote machine, partially on a remote machine, or all on a remote machine or server.

[0129] In the context of the present disclosure, computer program codes or related data may be carried by any appropriate carrier to enable a device, apparatus or processor to perform various processes and operations as described above. Examples of carriers include signals, computer readable media, etc.

[0130] The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared or semiconductor systems, devices or apparatuses, or any suitable combination of the foregoing. More specific examples of computer readable storage media include an electrical connection having one or more conductors, a portable computer floppy disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0131] In addition, although the operations are described in a specific order, this should not be understood as requiring the specific order or sequence shown to be performed, or performing all the operations shown, to obtain the desired result. In some cases, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the above discussion, these details should not be interpreted as limitations on the scope of the present disclosure, but can be interpreted as descriptions of features specific to a particular embodiment. Certain features described in the context of a separate embodiment may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination.

[0132] Although the disclosure has been described in language specific to structural features and / or methodological acts, it should be understood that the disclosure defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

[0133] It should be fully understood that the use of personally identifiable information should comply with industry standards generally considered to meet or exceed standards for maintaining user privacy. In particular, personally identifiable information data should be managed and processed to minimize the risk of inadvertent or unauthorized access or use, and the nature of authorized use should be clearly indicated to users.

Claims

1. A synchronization signal detection method for wireless communication, characterized in that: The method comprises: Acquire baseband signal; Performing a first processing on the baseband signal to obtain a first measurement value of the baseband signal, wherein the first processing includes detecting the conjugate symmetry of the baseband signal, wherein the performing the first processing on the baseband signal to obtain the first measurement value of the baseband signal includes: reading a signal sampling sequence of the baseband signal having a length of N, where N is an even number greater than 2; taking a center point of the signal sampling sequence as a reference, performing complex conjugate multiplication and summing sampling data whose positions are mutually symmetrical, to obtain the first measurement value indicating the conjugate symmetry of the baseband signal; The baseband signal is subjected to a second processing to obtain a second measurement value of the baseband signal, wherein the second processing includes performing a cross-correlation operation on the baseband signal and a local synchronization signal time domain sequence, wherein the local synchronization signal time domain sequence includes multiple time domain signal sequences, and the multiple time domain signal sequences all have conjugate symmetry. The second processing on the baseband signal to obtain the second measurement value of the baseband signal includes: reading a signal sampling sequence of the baseband signal with a length of N, where N is an even number greater than 2; based on the conjugate symmetry of the multiple time domain signal sequences, preprocessing the signal sampling sequence, wherein the preprocessing includes horizontal flipping, translation and linear combination of the I-path component and the Q-path component of the signal sampling sequence; performing cross-correlation operations on the preprocessed signal sampling sequence and the multiple time domain signal sequences, respectively, to obtain multiple second measurement values ​​indicating the cross-correlations between the baseband signal and the multiple time domain signal sequences; the signal sampling sequence is represented by r(n)=r i (n)+jr q (n), where r i (n) and r q (n) are the I-path component and the Q-path component of the signal sampling sequence respectively, and the multiple time domain signal sequences are represented as s m (n) = s m,i (n)+js m,q (n), m∈[0,M-1], where s m,i (n) and s m,q (n) are the I-path component and the Q-path component of the time domain signal sequence, M is the number of the multiple time domain signal sequences, and the preprocessing of the signal sampling sequence includes: based on r(n)=r i (n)+jr q (n) Calculate the intermediate sequence r pia (n),r pqs (n),r pis (n),r pqa (n): Among them, τ is the independent variable of the function; In response to the first metric value and the second metric value both being greater than respective threshold values, it is determined that the synchronization signal has been captured.

2. The method according to claim 1, characterized in that: The performing cross-correlation operations on the pre-processed signal sampling sequence and the multiple time domain signal sequences respectively comprises: based on the intermediate sequence r pia (n),r pqs (n),r pis (n),r pqa (n) Calculate multiple cross-correlation peaks P corr,m (τ), as the plurality of second metric values:

3. The method according to any one of claims 1 to 2, characterized in that: The signal sampling sequence is buffered in a shift register, and the preprocessing is implemented by a preprocessing circuit, which includes four parallel adders or one serial adder.

4. The method according to any one of claims 1 to 2, characterized in that: The cross-correlation operation of the preprocessed signal sampling sequence and the multiple time domain signal sequences is implemented through M cross-correlation circuits, each cross-correlation circuit includes N / 2-1 cross-correlation circuit units, and each cross-correlation circuit unit includes 4 real number multipliers and 2 adders, or 1 real number multiplier, 1 delay device and 1 adder.

5. A synchronization signal detection device for wireless communication, characterized in that: include: The first unit is used to obtain a baseband signal; A second unit is configured to perform a first processing on the baseband signal to obtain a first measurement value of the baseband signal, wherein the first processing includes detecting the conjugate symmetry of the baseband signal, wherein the first processing on the baseband signal to obtain the first measurement value of the baseband signal includes: reading a signal sampling sequence of the baseband signal having a length of N, where N is an even number greater than 2; taking a center point of the signal sampling sequence as a reference, performing complex conjugate multiplication and summing sampling data whose positions are mutually symmetrical, to obtain the first measurement value indicating the conjugate symmetry of the baseband signal; The third unit is used to perform a second processing on the baseband signal to obtain a second metric value of the baseband signal, wherein the second processing includes performing a cross-correlation operation on the baseband signal and a local synchronization signal time domain sequence, wherein the local synchronization signal time domain sequence includes multiple time domain signal sequences, and the multiple time domain signal sequences all have conjugate symmetry. The second processing on the baseband signal to obtain the second metric value of the baseband signal includes: reading a signal sampling sequence of the baseband signal with a length of N, where N is an even number greater than 2; preprocessing the signal sampling sequence based on the conjugate symmetry of the multiple time domain signal sequences, wherein the preprocessing includes horizontal flipping, translation and linear combination of the I-path component and the Q-path component of the signal sampling sequence; performing cross-correlation operations on the preprocessed signal sampling sequence and the multiple time domain signal sequences, respectively, to obtain multiple second metric values ​​indicating the cross-correlations between the baseband signal and the multiple time domain signal sequences; the signal sampling sequence is represented by r(n)=r i (n)+jr q (n), where r i (n) and r q (n) are the I-path component and the Q-path component of the signal sampling sequence respectively, and the multiple time domain signal sequences are represented as s m (n) = s m,i (n)+js m,q (n), m∈[0,M-1], where s m,i (n) and s m,q (n) are the I-path component and the Q-path component of the time domain signal sequence, M is the number of the multiple time domain signal sequences, and the preprocessing of the signal sampling sequence includes: based on r(n)=r i (n)+jr q (n) Calculate the intermediate sequence r pia (n),r pqs (n),r pis (n),r pqa (n): Among them, τ is the independent variable of the function; The fourth unit is configured to determine that the synchronization signal has been captured in response to the first metric value and the second metric value being both greater than respective threshold values.

6. A computer storage medium storing instructions, characterized in that: When the instructions are executed individually or collectively by at least one processor of a computing device, the computing device is caused to perform the method according to any one of claims 1 to 2.

7. A computer program product comprising instructions, characterized in that When the instructions are executed individually or collectively by at least one processor of a computing device, the computing device is caused to perform the method according to any one of claims 1 to 2.

8. A chip, characterized in that: The chip comprises a circuit system configured to perform the method according to any one of claims 1 to 4.

9. A computing device, characterized in that Comprising the chip according to claim 8.

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