Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate, the substrate comprising sequentially adjacent storage areas and boundary areas; forming an initial conductive layer on the substrate; patterning the initial conductive layer to form a plurality of initial bit line structures and an initial bit line contact layer, the plurality of initial bit line structures extending along a first direction and arranged at intervals along a second direction; forming an etching mask having a plurality of first openings; patterning the initial bit line structures and the initial bit line contact layer using the etching mask as a mask to form a plurality of bit line structures and a plurality of bit line contact pads; forming a bit line isolation structure, the bit line isolation structure comprising a first isolation portion between the bit line structures and a second isolation portion between the bit line contact pads, the first width of the first isolation portion being greater than the second width of the second isolation portion. The method for forming the semiconductor structure can improve the reliability of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] With the development of the electronics industry and the needs of users, electronic devices have been designed to have small size and high performance. Therefore, the memory used in the electronic devices is also required to be highly integrated and have high performance.

[0003] In order to improve the integration of memory, the pattern line width of semiconductor structure is gradually reduced. However, the increase in the integration density of semiconductor structure may lead to the deterioration of the reliability of semiconductor structure. In addition, with the high development of electronic industry, the demand for highly reliable semiconductor structure is growing. Therefore, many studies are being conducted to realize highly reliable semiconductor structure. Summary of the invention

[0004] According to a first aspect of an embodiment of the present disclosure, a method for forming a semiconductor structure is provided, comprising: providing a substrate, the substrate comprising a storage area and a boundary area adjacent to each other in sequence, the storage area comprising an array area and a dummy area; forming an initial conductive layer on the substrate; patterning the initial conductive layer of the storage area to form a plurality of initial bit line structures, retaining the initial conductive layer of the boundary area to form an initial bit line contact layer, the plurality of initial bit line structures extending along a first direction and arranged at intervals along a second direction; forming an etching mask having a plurality of first openings, the plurality of first openings exposing a portion of the initial bit line structures of the dummy area and a portion of the initial bit line contact layer of the boundary area; patterning the initial bit line structures and the initial bit line contact layer using the etching mask as a mask to form a plurality of bit line structures and a plurality of bit line contact pads; forming a bit line isolation structure, the bit line isolation structure comprising a first isolation portion located between the bit line structures and a second isolation portion between the bit line contact pads, the first width of the first isolation portion being greater than the second width of the second isolation portion.

[0005] In some embodiments, the substrate also includes a peripheral region, and when the initial conductive layer of the storage region is patterned to form multiple initial bit line structures, it also includes: patterning the initial conductive layer of the peripheral region to form a peripheral gate; after patterning the initial conductive layer of the storage region to form multiple initial bit line structures, it also includes: forming a peripheral gate protection layer on the side wall of the peripheral gate, and forming a bit line protection layer on the side wall of the initial bit line structure.

[0006] In some embodiments, the etching mask is further provided with a second opening, and the second opening exposes a portion of the peripheral gate in the peripheral area. When the initial bit line structure and the initial bit line contact layer are patterned using the etching mask as a mask, it also includes: patterning the peripheral gate using the etching mask as a mask to form two relative peripheral sub-gates, and the arrangement direction of the two relative peripheral sub-gates is the extension direction of the peripheral gate.

[0007] In some embodiments, after patterning the initial conductive layer of the storage area to form multiple initial bit line structures, it also includes: forming a peripheral mask, the peripheral mask covers the dummy area, the boundary area and the peripheral area; using the peripheral mask as a mask, removing the bit line protection layer on the substrate in the array area to expose the substrate in the array area; removing the peripheral mask and filling the initial contact layer between the multiple initial bit line structures.

[0008] In some embodiments, the method further includes: patterning the initial contact layer to form node contact layers spaced apart along the first direction, with node spacing grooves between adjacent node contact layers; and filling the node isolation structures in the node spacing grooves.

[0009] In some embodiments, it also includes: removing part of the node contact layer to form a node contact structure; forming plug grooves in the boundary area and the peripheral area; and simultaneously forming a contact pad structure located above the node contact structure, a bit line pad contact structure located in the plug groove in the boundary area, and a peripheral contact structure located in the plug groove in the peripheral area.

[0010] In some embodiments, the multiple initial bit line structures include a first initial bit line structure and a second initial bit line structure alternately arranged along the second direction; the dummy area includes a first dummy area and a second dummy area respectively located on both sides of the array area along the first direction; the first opening exposes a portion of the first initial bit line structure located in the first dummy area, and the first opening also exposes a portion of the second initial bit line structure located in the second dummy area; the multiple bit line structures extend along the first direction and are arranged at intervals along the second direction, the multiple bit line structures include a first bit line and a second bit line alternately arranged along the second direction, the first bit line is formed by the portion of the first initial bit line structure located in the array area and the second dummy area, and the second bit line is formed by the portion of the second initial bit line structure located in the array area and the first dummy area.

[0011] According to a second aspect of an embodiment of the present disclosure, a semiconductor structure is provided, comprising: a substrate, the substrate comprising a storage area and a boundary area adjacent to each other in sequence, the storage area comprising an array area and a dummy area; a plurality of bit line structures located in the storage area, the plurality of bit line structures extending along a first direction and arranged at intervals along a second direction, the plurality of bit line structures comprising first bit lines and second bit lines alternately arranged along the second direction; a plurality of bit line contact pads located in the boundary area, the plurality of bit line contact pads arranged at intervals along the second direction, the second bit lines extending to the dummy area and connected to the bit line contact pads in a one-to-one correspondence; a bit line isolation structure located in the dummy area and the boundary area, the bit line isolation structure comprising a first isolation portion located between the second bit lines and a second isolation portion between the bit line contact pads, the first width of the first isolation portion being greater than the second width of the second isolation portion.

[0012] In some embodiments, the dummy area includes a first dummy area and a second dummy area respectively located on both sides of the array area along the first direction, and the boundary area includes a first boundary area and a second boundary area respectively located on both sides of the storage area along the first direction; the first bit line extends to the second dummy area and is connected one-to-one with the bit line contact pad located in the second boundary area; the second bit line extends to the first dummy area and is connected one-to-one with the bit line contact pad located in the first boundary area.

[0013] In some embodiments, the substrate also includes a peripheral region, and the semiconductor structure also includes: two relative peripheral sub-gates located in the peripheral region; a gate isolation structure located between relative first side walls of the two relative peripheral sub-gates, the gate isolation structure being made of the same material as the bit line isolation structure; and a peripheral gate protection layer located on the second side walls of the two relative peripheral sub-gates, the second side wall being adjacent to the first side wall, the peripheral gate protection layer being made of a different material from the gate isolation structure.

[0014] In some embodiments, a first width of the first isolation portion is equal to a spacing between adjacent second bit lines.

[0015] In some embodiments, the second width of the second isolation portion is equal to a bit line width of the bit line structure.

[0016] In some embodiments, the semiconductor structure further includes: a plurality of node contact structures located in the array region, and the plurality of node contact structures are arranged in an array along the first direction and the second direction.

[0017] In some embodiments, the node contact structure located in the array region is embedded in the substrate and contacts the array active region in the substrate; the second isolation portion located in the dummy region is located on the substrate and is flush with the top surface of the substrate.

[0018] In the disclosed embodiment, an etching mask patterning process is used to obtain a bitline structure and a bitline contact pad to form a bitline isolation structure located in the dummy area and the boundary area, and the bitline isolation structure has a first isolation portion located between the bitline structures and a second isolation portion located between the bitline contact pads, and a first width of the first isolation portion is greater than a second width of the second isolation portion, thereby increasing the effective area of ​​the bitline contact pad, thereby improving the alignment of the bitline contact pad and the bitline pad contact structure, and avoiding line short circuits between the bitline pad contact structure and non-corresponding structures in the dummy area caused by alignment deviations, thereby improving the reliability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 is a flow chart showing a method for forming a semiconductor structure according to an exemplary embodiment;

[0021] FIG. 2A to FIG. 11C is a schematic top view and a schematic cross-sectional view showing a formation process of a semiconductor structure according to an embodiment of the present disclosure, wherein: Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , FIG. 10A to FIG. 11A It is a top view schematic diagram of the semiconductor structure. Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , FIG. 10B to FIG. 11B and Figure 2C , Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Fig. 9C , FIG. 10C to FIG. 11C It is a cross-sectional schematic diagram of a semiconductor structure;

[0022] Fig.12 It is a schematic top view of another semiconductor structure shown according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] The technical solution of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0024] The present disclosure is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0025] It will be understood that the meaning of “on,” “over,” and “over” of the present disclosure should be interpreted in the broadest manner, such that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning that it is “on” something with intervening features or layers.

[0026] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0027] In the disclosed embodiments, the term "layer" refers to a material portion including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0028] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0029] Take dynamic random access memory (DRAM) as an example. DRAM is a volatile memory. DRAM usually includes a storage area composed of memory cells and a peripheral area composed of logic control circuits. A typical memory cell includes a switch structure (such as a transistor) and a storage structure (such as a capacitor). The logic control circuit in the peripheral area can address each memory cell in the storage area through multiple columns of word lines and multiple rows of bit lines passing through the storage area, and open the switch structure to electrically connect the storage structure to perform data reading, writing or access. In advanced semiconductor manufacturing, the chip size of DRAM can be greatly reduced by adopting a buried word line architecture, through which the active area of ​​the memory cell can be arranged at a dense pitch to obtain a higher cell density.

[0030] As semiconductor structures including logic control circuits and memory cells are shrunk to smaller sizes, the technical barriers faced by patterning processes are becoming increasingly significant. For example, in today's DRAM, due to the reduction in the size of the memory cell, it is difficult to form a good electrical contact between the bit line and the logic control circuit. For example, in order to form an electrical connection between the bit line and the sense amplifier, it is necessary to form a structure such as a bit line pad contact structure that electrically connects the bit line. Due to the close arrangement of the bit lines, the bit line pad contact structure may not be able to effectively contact the corresponding bit line, causing a line break. Alternatively, due to alignment deviation, the bit line pad contact structure may come into contact with a non-corresponding structure (such as a node contact structure, a non-corresponding bit line, etc.), causing a line short circuit. Both line breakage and line short circuit will cause data read errors to occur, reducing the reliability of the memory.

[0031] Based on this, in order to solve the above problems, an embodiment of the present disclosure provides a method for forming a semiconductor structure.

[0032] Figure 1 is a flow chart of a method for forming a semiconductor structure according to an embodiment of the present disclosure; FIG. 2A to FIG. 11C is a schematic top view and a schematic cross-sectional view showing a formation process of a semiconductor structure according to an embodiment of the present disclosure, wherein: Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , FIG. 10A to FIG. 11A It is a top view schematic diagram of the semiconductor structure. Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B and 11B is a cross-sectional schematic diagram of the semiconductor structure along the A-A' and BB' cross sections in the top view schematic diagram, Figure 2C , Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Fig. 9C , Fig. 10C and 11C is a cross-sectional schematic diagram of the semiconductor structure along the C-C' section in the top view schematic diagram; Fig.12 FIG. 1 is a schematic top view of another semiconductor structure according to an embodiment of the present disclosure. Figure 1-12The method for forming the semiconductor structure provided by the embodiment of the present disclosure is described in detail. It can be understood that, FIG. 2A to FIG. 11A and Fig.12 In the embodiment, the first direction D1, the second direction D2 and the third direction D3 are horizontal directions parallel to the plane where the substrate 110 is located, and the first direction D1 intersects with the second direction D2. For example, the first direction D1 may be perpendicular to the second direction D2, and the third direction D3 is a direction intersecting with both the first direction D1 and the second direction D2.

[0033] Reference Figure 1 As shown, the method for forming a semiconductor structure includes at least the following steps:

[0034] S101: providing a substrate, the substrate comprising sequentially adjacent storage areas and boundary areas, the storage area comprising an array area and a dummy area;

[0035] S102: forming an initial conductive layer on the substrate;

[0036] S103: patterning the initial conductive layer in the storage area to form a plurality of initial bit line structures, retaining the initial conductive layer in the boundary area to form an initial bit line contact layer, wherein the plurality of initial bit line structures extend along the first direction and are arranged at intervals along the second direction;

[0037] S104: forming an etching mask having a plurality of first openings, wherein the plurality of first openings expose a portion of the initial bit line structure in the dummy region and a portion of the initial bit line contact layer in the boundary region;

[0038] S105: patterning the initial bit line structure and the initial bit line contact layer using the etching mask as a mask to form a plurality of bit line structures and a plurality of bit line contact pads;

[0039] S106: forming a bit line isolation structure, the bit line isolation structure comprising a first isolation portion between the bit line structures and a second isolation portion between the bit line contact pads, wherein a first width of the first isolation portion is greater than a second width of the second isolation portion.

[0040] It should be understood that Figure 1 The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Figure 1 The steps shown in the figure can be adjusted in sequence according to actual needs.

[0041] In the method for forming a semiconductor structure provided by the present disclosure, in the first aspect, by setting a dummy area and a boundary area to form a bit line contact pad located in the boundary area and a bit line structure partially extending to the dummy area, the arrangement density of the bit line contact pad can be reduced, and the effective contact area of ​​the bit line contact pad can be increased, and the alignment between the bit line contact pad and the subsequently formed bit line pad contact structure can be improved. In the second aspect, the initial bit line structure and the initial bit line contact layer are etched in one step through an etching mask provided with a first opening, which effectively improves the manufacturing process efficiency of the semiconductor structure and ensures the electrical connection between the bit line structure and the corresponding bit line contact pad. In the third aspect, by forming a "convex"-shaped bit line isolation structure, the first isolation portion located between the bit line structures has a larger second width, which can effectively avoid the short circuit between the bit line pad contact structure and the non-corresponding structure, and the second isolation portion located between the bit line contact pads has a smaller first width, which can increase the occupied space of the bit line contact pad in the boundary area and improve the process window of the bit line pad contact structure.

[0042] Reference Figure 2A , Figure 2B and Figure 2C As shown, Figure 2B Included Figure 2A The schematic cross-sectional view of the semiconductor structure taken along the cross sections AA' and BB' in the top view shown, Figure 2C for Figure 2A The schematic cross-sectional view of the semiconductor structure taken along the CC' section in the top view shown. The substrate 110 can be divided into a storage region MR, a boundary region BR and a peripheral region PR which are adjacent to each other in sequence, wherein the boundary region BR is located at least one outer side of the storage region MR, and the peripheral region PR is located at least one outer side of the boundary region BR. For example, the boundary region BR surrounds the storage region MR, and the peripheral region PR surrounds the boundary region BR. The storage region MR can be divided into an array region AR and a dummy region DR located at least one outer side of the array region AR.

[0043] Reference Figure 2A and Figure 2BAs shown, an array active region 111 and a shallow trench isolation structure 112 separating the array active region 111 are provided in the storage region MR of the substrate 110. The array active region 111 is arranged in an array along the first direction D1 and the second direction D2, and each array active region 111 extends along the third direction D3 in the top view schematic diagram. The shallow trench isolation structure 112 is an integrated structure located in the storage region MR, the boundary region BR and the peripheral region PR. The shallow trench isolation structures 112 located in different regions may have different depths. For example, the bottom surface of the shallow trench isolation structure 112 located in the peripheral region PR and the boundary region BR may be lower than the bottom surface of the shallow trench isolation structure 112 located in the storage region MR. A peripheral active region 113 separated by the shallow trench isolation structure 112 is also provided in the peripheral region PR in the substrate 110. The array active region 111 may be located in the array region AR and the dummy region DR of the storage region MR, or the array active region 111 may be located only in the array region AR of the storage region MR. The array region AR is a region for forming effective memory cells, and the dummy region DR is a region for forming dummy memory cells. The dummy memory cells refer to memory cells that are not used for actual work and are used to reduce the impact of actual manufacturing process deviations.

[0044] The material of the substrate 110 includes semiconductor materials, for example, single-element semiconductor materials (for example, silicon (Si) or germanium (Ge), etc.), III-V compound semiconductor materials (for example, gallium nitride (GaN), gallium arsenide (GaAs) or indium phosphide (InP), etc.), II-VI compound semiconductor materials (for example, zinc sulfide (ZnS), cadmium sulfide (CdS) or cadmium telluride (CdTe), etc.), organic semiconductor materials or other semiconductor materials known in the art. The material of the shallow trench isolation structure 112 includes one or more insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc. The shallow trench isolation structure 112 can be a single-layer structure or a multi-layer structure. For example, the shallow trench isolation structure 112 can be a multi-layer structure composed of silicon nitride-silicon oxide-silicon nitride (NON).

[0045] In some embodiments, the substrate 110 further includes a substrate protection layer located on the top surfaces of the array active region 111 and the shallow trench isolation structure 112. The substrate protection layer and the shallow trench isolation structure 112 are made of the same material.

[0046] Reference Figure 2A and Figure 2CAs shown, buried word lines 120 are also formed in the substrate 110. The buried word lines 120 are formed in the storage region MR. The buried word lines 120 extend along the second direction D2 and are arranged at intervals along the first direction D1, and intersect with the array active areas 111. Each array active area 111 intersects with two buried word lines 120. The buried word lines 120 are formed by forming word line trenches 120T in the substrate 110, and sequentially forming a gate dielectric layer 121, a gate conductive layer, and a gate cap layer 124 in the word line trenches 120T. The gate conductive layer may be a single-layer structure or a multi-layer structure. For example, the gate conductive layer may include a first gate conductive layer 122 and a second gate conductive layer 123, wherein the work function of the second gate conductive layer 123 is lower than the work function of the first gate conductive layer 122, and gate-induced drain leakage (GIDL) can be reduced. The material of the gate conductive layer may be a conductive material including semiconductor materials (e.g., doped polysilicon), metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.) and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). In one example, the material of the first gate conductive layer 122 is metal, and the material of the second gate conductive layer 123 is doped polysilicon. The material of the gate dielectric layer 121 may be silicon oxide, silicon nitride, silicon oxynitride, etc., and the gate dielectric layer 121 may be formed at the bottom and sidewall of the word line trench 120T by an in-situ steam generation process (ISSG), or may be formed by an atomic layer deposition process, a plasma vapor deposition process, or a rapid thermal oxidation process (RTO). The material of the gate cap layer 124 includes insulating materials such as silicon nitride and silicon oxynitride.

[0047] A bit line contact plug 130 is also formed in the substrate 110. The bit line contact plug 130 can be arranged in one-to-one contact with the array active area 111. The bit line contact plug 130 is located in the middle of the array active area 111, and the bottom surface of the bit line contact plug 130 is lower than the top surface of the array active area 111. The top surface of the bit line contact plug 130 can be flush with the top surface of the array active area 111. The material of the bit line contact plug 130 may include conductive materials such as doped polysilicon.

[0048] Reference Figure 2A and Figure 2CAs shown, an initial first conductive layer 212L may be formed on the peripheral region PR of the substrate 110, and the initial first conductive layer 212L may be formed simultaneously with the bit line contact plug 130. Before forming the initial first conductive layer 212L and the bit line contact plug 130, a peripheral dielectric layer 211 may be formed on the substrate 110. The material of the peripheral dielectric layer 211 may include a high dielectric constant material and silicon oxide, etc. The high dielectric constant material is one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, etc.

[0049] Reference Figure 3A , Figure 3B and Figure 3C As shown, Figure 3B Included Figure 3A The schematic cross-sectional view of the semiconductor structure taken along the cross sections AA' and BB' in the top view shown, Figure 3C for Figure 3A The schematic cross-sectional view of the semiconductor structure taken along the CC' section in the top view schematic diagram shown. An initial conductive layer 141L is formed on the storage region MR, the boundary region BR and the peripheral region PR of the substrate 110. The material of the initial conductive layer 141L can be a conductive material such as a semiconductor material, a metal, a conductive metal nitride and a metal semiconductor compound. The initial conductive layer 141L can be a single-layer structure or a multi-layer structure. For example, the initial conductive layer 141L can be a multi-layer structure composed of a metal semiconductor compound and a metal. The metal semiconductor compound (for example, tungsten silicide, cobalt silicide, titanium silicide, etc.) can reduce the contact resistance between the metal and the bit line contact plug 130. An initial cap layer 142L can also be formed on the initial conductive layer 141L. The material of the initial cap layer 142L is an insulating material such as silicon nitride.

[0050] Reference Figure 4A , Figure 4B and Figure 4C As shown, Figure 4B Included Figure 4A The schematic cross-sectional view of the semiconductor structure taken along the cross sections AA' and BB' in the top view shown, Figure 4C for Figure 4AThe schematic cross-sectional view of the semiconductor structure taken along the C-C' section in the top view schematic diagram shown. The initial conductive layer 141L of the storage region MR is patterned to form a plurality of initial bit line structures 140a, and the initial bit line structure 140a may include a stacked initial bit line conductive layer 141a and an initial bit line capping layer 142a, wherein the initial bit line conductive layer 141a is patterned by the initial conductive layer 141L, and the initial bit line capping layer 142a is patterned by the initial capping layer 142L. The initial conductive layer 141L and the initial capping layer 142L of the boundary region BR are retained to form an initial bit line contact layer 151a and an initial contact capping layer 152a, and the plurality of initial bit line structures 140a extend along the first direction D1 and are arranged at intervals along the second direction D2, and the initial bit line contact layer 151a is connected to the end of the initial bit line conductive layer 141a of each initial bit line structure 140a. A plurality of initial bit line structures 140 a may be formed by using a self-aligned double patterning process (SADP).

[0051] Reference Figure 4A and Figure 4C As shown, when the initial conductive layer 141L of the memory region MR is patterned to form a plurality of initial bit line structures 140a, it further includes: patterning the initial conductive layer 141L of the peripheral region PR to form a peripheral gate 210a, and the initial bit line contact layer 151a is spaced apart from the peripheral gate 210a. The peripheral gate 210a may include a stacked first peripheral gate conductive layer 212, a second peripheral gate conductive layer 213, and a peripheral gate capping layer 214, wherein the first peripheral gate conductive layer 212 is patterned by the initial first conductive layer 212L, the second peripheral gate conductive layer 213 is patterned by the initial conductive layer 141L, and the peripheral gate capping layer 214 is patterned by the initial capping layer 142L.

[0052] In some embodiments, one peripheral gate 210a may correspond to at least two peripheral active regions 113, that is, a projection of one peripheral gate 210a on the substrate 110 may intersect with projections of at least two peripheral active regions 113 on the substrate 110, and one peripheral gate 210a is used to form at least two peripheral transistors.

[0053] Reference Figure 5A , Figure 5B and Figure 5C As shown, Figure 5B Included Figure 5A The schematic cross-sectional view of the semiconductor structure taken along the cross sections AA' and BB' in the top view shown, Figure 5C for Figure 5AThe schematic cross-sectional view of the semiconductor structure taken along the CC' section in the top view shown. After the initial conductive layer 141L of the memory region MR is patterned to form a plurality of initial bit line structures 140a and a peripheral gate 210a, the method further includes: forming a peripheral gate protection layer 210p on the sidewall of the peripheral gate 210a, and forming a bit line protection layer 140p on the sidewall of the initial bit line structure 140a. The peripheral gate protection layer 210p and the bit line protection layer 140p are integrally formed and also cover a portion of the surface of the substrate 110.

[0054] In some embodiments, reference Figure 5A , Figure 5B and Figure 5C As shown, after forming the peripheral gate protection layer 210p and the bit line protection layer 140p, it also includes: forming a peripheral mask M1, the peripheral mask M1 covers the dummy region DR, the boundary region BR and the peripheral region PR; Fig. 6A , Figure 6B and Figure 6C As shown, Figure 6B Included Fig. 6A The schematic cross-sectional view of the semiconductor structure taken along the cross sections AA' and BB' in the top view shown, Figure 6C for Fig. 6AIn the cross-sectional schematic diagram of the semiconductor structure taken along the CC' section in the top view schematic diagram shown, the bit line protection layer 140p on the substrate 110 in the array region AR is removed by using the peripheral mask M1 as a mask to expose the substrate 110 in the array region AR, and then the peripheral mask M1 is removed. The material of the peripheral mask M1 may be a photoresist, which is used to protect the substrate 110 in other regions outside the array region AR. Since the peripheral mask M1 does not cover the array region AR, an etching process may be used to remove part of the bit line protection layer 140p and part of the substrate 110 between the initial bit line structures 140a on the array region AR to form a recess R, and the recess R exposes the end of the array active region 111 in the substrate 110. The etching process includes a dry etching process or a wet etching process, and the dry etching includes at least any one of reactive ion etching (RIE), inductively coupled plasma etching (ICP) or high-density plasma etching (HDP). The dry etching process can be used to remove the bit line protection layer 140p located on the substrate 110 between the initial bit line structures 140a in the array region AR to expose the substrate 110, and the bit line protection layer 140p located on the top of the initial bit line structure 140a in the array region AR is removed simultaneously, and then a wet etching process is used to form a recess R on the surface of the substrate 110. The bit line protection layer 140p is retained only on the sidewall of the initial bit line structure 140a located in the array region AR, and the bit line protection layer 140p is retained on the sidewall and the top of the initial bit line structure 140a located in the dummy region DR.

[0055] Reference Fig. 7A , Figure 7B and Figure 7C As shown, Figure 7B Included Fig. 7A The schematic cross-sectional view of the semiconductor structure taken along the cross sections AA' and BB' in the top view shown, Figure 7C for Fig. 7AThe cross-sectional schematic diagram of the semiconductor structure taken along the CC' section in the top view schematic diagram shown. After removing the peripheral mask M1, the peripheral isolation layer 220 is filled in the gap between the peripheral gates 210a in the peripheral region PR, and the initial contact layer 160a is filled between the multiple initial bit line structures 140a. The top surface of the initial contact layer 160a can be controlled to be flush with the initial bit line structure 140a through a planarization process. The material of the initial contact layer 160a includes conductive materials such as semiconductor materials (for example, doped polysilicon) and metal semiconductor compounds (for example, tungsten silicide, cobalt silicide, titanium silicide, etc.). In the array region AR, the initial contact layer 160a is in direct contact with the array active area 111 in the substrate 110 exposed by the recess R, and the initial contact layer 160a in the array region AR is used to form a node contact structure electrically connecting the array active area 111 and the storage structure. In the dummy region DR, the initial contact layer 160a contacts the bit line protection layer 140p retained on the surface of the substrate 110 but is not electrically connected to the substrate 110. The initial contact layer 160a in the dummy region DR is used to form a dummy node contact structure. No storage structure may be formed on the dummy region DR, or a storage structure that is not electrically connected to the substrate 110 may be formed. Usually, due to manufacturing process errors of structures such as the array active region 111, poor performance memory cells are easily formed in the dummy region DR. By providing a dummy node contact structure in the dummy region DR, the poor performance memory cells can be prevented from affecting the semiconductor structure.

[0056] Reference Fig. 8A , Figure 8B and Figure 8C As shown, Figure 8B Included Fig. 8A The schematic cross-sectional view of the semiconductor structure taken along the cross sections AA' and BB' in the top view shown, Figure 8C for Fig. 8A The cross-sectional schematic diagram of the semiconductor structure taken along the CC' section in the top view schematic diagram shown. An etching mask M2 having a plurality of first openings K1 is formed, and the plurality of first openings K1 expose a portion of the initial bit line structure 140a in the dummy region DR and a portion of the initial bit line contact layer 151a and the initial contact cap layer 152a in the boundary region BR. The first width w1 of the first opening K1 in the dummy region DR is greater than the second width w2 of the first opening K1 in the boundary region BR.

[0057] In some embodiments, the first opening K1 is a "convex"-shaped opening from the dummy region DR toward the boundary region BR, and may be composed of a first rectangular opening located in the dummy region DR and a second rectangular opening located in the boundary region BR, and the length of the first rectangular opening along the first direction D1 is greater than or equal to the length of the second rectangular opening along the first direction D1, and the first width w1 of the first rectangular opening along the second direction D2 is greater than the second width w2 of the second rectangular opening along the second direction D2. In some examples, the first width w1 of the portion of the first opening K1 located in the dummy region DR is equal to the spacing between the initial bit line structures 140a, that is, equal to the width of one initial bit line structure 140a plus two adjacent initial contact layers 160a. The portion of the first opening K1 located in the dummy region DR exposes the initial contact layer 160a located in the dummy region DR. The second width w2 of the portion of the first opening K1 located in the boundary region BR is substantially equal to the width of one initial bit line structure 140a, for example, the ratio of the second width w2 to the width of one initial bit line structure 140a is in the range of 0.8-1.5.

[0058] Reference Fig.9A , Fig. 9B and Fig. 9C As shown, Fig. 9B Included Fig.9A The schematic cross-sectional view of the semiconductor structure taken along the cross sections AA' and BB' in the top view shown, Fig. 9C for Fig.9A The cross-sectional schematic diagram of the semiconductor structure taken along the CC' section in the top view schematic diagram shown. The two end surfaces of the first opening K1 along the first direction D1 are adjacent to the interface between the peripheral region PR and the boundary region BR and the interface between the dummy region DR and the array region AR respectively. Using the etching mask M2 as a mask to pattern the initial bit line structure 140a and the initial bit line contact layer 151a includes: etching the initial bit line structure 140a along the first opening K1 to form a plurality of bit line structures 140, and the plurality of bit line structures 140 alternately extend to the dummy region DR; etching the initial bit line contact layer 151a along the first opening K1 to cut off the initial bit line contact layer 151a along the first direction D1 to form a plurality of bit line contact pads 150 arranged at intervals along the second direction D2; and also includes: etching the initial contact layer 160a along the first opening K1 to remove the initial contact layer 160a in the dummy region DR. By removing the initial contact layer 160a in the dummy region DR, the short circuit between the bit line and the storage structure caused by the position deviation of the subsequently formed bit line pad contact structure can be avoided. By not forming a dummy node contact structure, the abnormal electrical connection between the dummy node contact structure and the substrate caused by process errors can be avoided, further improving the process window of the bit line pad contact structure.

[0059] In some embodiments, the second opening K2 exposes part of the peripheral gate 210a of the peripheral region PR, and when the initial bit line structure 140a and the initial bit line contact layer 151a are patterned using the etching mask M2 as a mask, the method further includes: patterning the peripheral gate 210a using the etching mask M2 as a mask to form two opposite peripheral sub-gates 210, and the arrangement direction of the two opposite peripheral sub-gates 210 is the extension direction of the peripheral gate 210a. The extension direction of the peripheral gate 210a can be the first direction D1 or the second direction D2, Fig.9A In the example, the extension direction of the peripheral gate 210a is the first direction D1. The second opening K2 can be used to pattern a plurality of peripheral gates 210a arranged in parallel, and the extension direction of the second opening K2 is perpendicular to the extension direction of the peripheral gate 210a. For example, the peripheral gate 210a extends along the first direction D1, and the plurality of peripheral gates 210a are etched through the second opening K2 extending along the second direction D2, so that each peripheral gate 210a is patterned into two peripheral sub-gates 210 opposite to each other along the first direction D1, and the width of the second opening K2 along the first direction D1 is less than the spacing between the two peripheral active regions 113 intersecting with the peripheral gate 210a, for example, the width of the second opening K2 along the first direction D1 is less than one third of the spacing between the two peripheral active regions 113 intersecting with the peripheral gate 210a. By using an etching mask M2 with a second opening K2 to perform patterning on the peripheral gate 210a, the end morphology of the peripheral sub-gate 210 can be optimized without increasing the mask cost, avoiding the end rounding problem caused by one-step etching, thereby greatly reducing the distance between the relative ends of the peripheral sub-gates 210, thereby significantly improving the peripheral device integration of the peripheral region PR.

[0060] Reference Fig. 10A , Fig. 10B and Fig. 10C As shown, Fig. 10B Included Fig. 10A The schematic cross-sectional view of the semiconductor structure taken along the cross sections AA' and BB' in the top view shown, Fig. 10C for Fig. 10AThe schematic cross-sectional view of the semiconductor structure taken along the CC' section in the top view schematic diagram shown. The space where a portion of the initial bit line structure 140a, the initial bit line contact layer 151a and the initial contact layer 160a are removed is filled with a bit line isolation structure 170, and the bit line isolation structure 170 includes a first isolation portion 171 located between the bit line structures 140 and a second isolation portion 172 between the bit line contact pads 150, and the first width w1 of the first isolation portion 171 along the second direction D2 is greater than the second width w2 of the second isolation portion 172 along the second direction D2. The size and position of the bit line isolation structure 170 correspond to the size and position of the first opening K1 in the etching mask M2, and the first isolation portion 171 fills the space corresponding to the first rectangular opening of the first opening K1, and the second isolation portion 172 fills the space corresponding to the second rectangular opening of the first opening K1. The first isolation portion 171 is used to isolate adjacent bit line structures 140 in the dummy region DR and contacts the bit line protection layer 140 p on the sidewall of the bit line structure 140 . The second isolation portion 172 is used to isolate adjacent bit line contact pads 150 in the boundary region BR and contacts the sidewall of the bit line contact pad 150 .

[0061] In some embodiments, a gate isolation structure 230 is filled in the space where a portion of the peripheral gate 210a and the peripheral isolation layer 220 are removed. The size and position of the gate isolation structure 230 correspond to the size and position of the second opening K2 in the etching mask M2. The gate isolation structure 230 is used to isolate the opposite ends of two opposite peripheral sub-gates 210 in the peripheral region PR. The gate isolation structure 230 is located between the opposite first side walls s1 of the two opposite peripheral sub-gates 210. The gate isolation structure 230 and the bit line isolation structure 170 are formed synchronously and are made of the same material. The first side wall s1 refers to the side walls of the two opposite peripheral sub-gates 210 facing each other. The peripheral gate protection layer 210p is located on the second side walls s2 of the two opposite peripheral sub-gates 210, and the second side wall s2 is adjacent to the first side wall s1. The peripheral gate protection layer 210p can also be located on the opposite side walls of the two opposite peripheral sub-gates 210. The peripheral gate protection layer 210p and the gate isolation structure 230 are made of different materials. In one example, the peripheral gate protection layer 210p can be a multi-layer structure, such as a multi-layer structure composed of NON, which is used to protect the side wall morphology of the peripheral sub-gate 210; the gate isolation structure 230 is a single-layer structure, such as a single-layer structure composed of low dielectric constant materials such as silicon oxide, silicon nitride, silicon carbide, silicon carbide or silicon oxynitride, which is used to reduce mutual interference and parasitic capacitance between relative peripheral sub-gates 210.

[0062] Reference Fig.11A , Fig. 11B and Fig. 11C As shown, Fig. 11B Included Fig.11AThe schematic cross-sectional view of the semiconductor structure taken along the cross sections AA' and BB' in the top view shown, Fig. 11C for Fig.11A The cross-sectional schematic diagram of the semiconductor structure taken along the CC' section in the top view schematic diagram shown. The method for forming the semiconductor structure also includes: patterning the initial contact layer 160a to form node contact layers arranged in intervals along the first direction D1, with node spacing grooves 180T between adjacent node contact layers; filling the node isolation structure 180 in the node spacing grooves 180T. Removing part of the node contact layer to form a node contact structure 160; forming plug grooves 311T and 312T in the boundary region BR and the peripheral region PR; and simultaneously forming a contact pad structure 190 located above the node contact structure 160, a bit line pad contact structure 311 located in the plug groove 311T in the boundary region BR, and a peripheral contact structure 312 located in the plug groove 312T in the peripheral region PR.

[0063] In some embodiments, the node contact structures 160 are arranged in an array along the first direction D1 and the second direction D2 and are in a quadrilateral layout, that is, the node contact structures 160 arranged along the first direction D1 are substantially aligned in the first direction D1, and the node contact structures 160 arranged along the second direction D2 are substantially aligned in the second direction D2. The contact pad structures 190 are arranged in an array along the first direction D1 and the second direction D2 and are in a hexagonal layout, that is, each contact pad structure 190 has a substantially consistent distance with its five adjacent contact pad structures 190, and the five adjacent contact pad structures 190 form a regular hexagon. The contact pad structure 190 is used to connect the storage structure formed subsequently and to achieve the densest stacking of the storage structure. The material of the contact pad structure 190 includes conductive materials such as metals (for example, tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.), conductive metal nitrides (for example, titanium nitride, tantalum nitride, etc.) and metal semiconductor compounds (for example, tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0064] In some embodiments, the plug trenches 311T and 312T are respectively formed in the boundary region BR and the peripheral region PR simultaneously by using an etching process. The plug trench 311T located in the boundary region BR may expose a portion of the surface of the bit line contact pad 150, and the plug trench 312T located in the peripheral region PR may expose a portion of the surface of the peripheral active region 113. The projection of the plug trench 311T located in the boundary region BR on the substrate is located at the center position of the projection of the bit line contact pad 150 on the substrate, and the projection of the plug trench 312T located in the peripheral region PR on the substrate is located at the center position and both ends of the projection of the peripheral active region 113 on the substrate.

[0065] In other examples, the plug trench 311T may be formed in the boundary region BR and the plug trench 312T may be formed in the peripheral region PR respectively through different steps. For example, after the plug trench 312T is formed in the peripheral region PR, a sacrificial layer is filled in the plug trench 312T in the peripheral region PR, and then the plug trench 311T is formed in the boundary region BR, and the sacrificial layer filled in the plug trench 312T in the peripheral region PR is removed.

[0066] In some instances, after removing a portion of the node contact layer to form the node contact structure 160 and forming plug grooves 311T and 312T in the boundary region BR and the peripheral region PR, respectively, the contact pad structure 190, the bit line pad contact structure 311 and the peripheral contact structure 312 can be simultaneously formed by a one-step deposition, thereby improving the manufacturing process efficiency and reducing the manufacturing cost.

[0067] Reference Figure 5A , 6A , 7A, 8A and Fig.12 As shown, the plurality of initial bit line structures 140a include a first initial bit line structure BL1a and a second initial bit line structure BL2a alternately arranged along the second direction D2; the dummy region DR includes a first dummy region DR1 and a second dummy region DR2 respectively located on both sides of the array region AR along the first direction D1; Fig. 8A and Fig.12 As shown, the first opening K1 exposes a portion of the first initial bit line structure BL1a located in the first dummy region DR1, and the first opening K1 also exposes a portion of the second initial bit line structure BL1a located in the second dummy region DR2; Fig.9A and Fig.12 As shown, after the plurality of initial bit line structures 140a are patterned based on the etching mask M2, the plurality of bit line structures 140 are obtained. The plurality of bit line structures 140 extend along the first direction D1 and are arranged at intervals along the second direction D2. The plurality of bit line structures 140 include first bit lines BL1 and second bit lines BL2 arranged alternately along the second direction D2. The first bit line BL1 is formed by the portion of the first initial bit line structure BL1a located in the array region AR and the second dummy region DR2, and the second bit line BL2 is formed by the portion of the second initial bit line structure BL2a located in the array region AR and the first dummy region DR1. The first bit line BL1 and the second bit line BL2 extend alternately to the second dummy region DR2 or the first dummy region DR1, respectively, so that the layout density of the bit line structure 140 in the dummy region DR can be reduced.

[0068] In some embodiments, reference Fig.12As shown, the boundary region BR includes a first boundary region BR1 adjacent to the first dummy region DR1 and a second boundary region BR2 adjacent to the second dummy region DR2, and the first boundary region BR1 and the second boundary region BR2 are respectively located on both sides of the storage region MR along the first direction D1. The first bit line BL1 extends to the second dummy region DR2 and is connected to the bit line contact pad 150 located in the second boundary region BR2 in a one-to-one correspondence; the second bit line BL2 extends to the first dummy region DR1 and is connected to the bit line contact pad 150 located in the first boundary region BR1 in a one-to-one correspondence. The peripheral region PR may include a first peripheral region PR1 adjacent to the first boundary region BR1 and a second peripheral region PR2 adjacent to the second boundary region BR2. The bit line isolation structure 170 located in the first boundary region BR1 and the first dummy region DR1 is sandwiched between adjacent second bit lines BL2, and the bit line isolation structure 170 located in the second boundary region BR2 and the second dummy region DR2 is sandwiched between adjacent first bit lines BL1.

[0069] Based on the above-mentioned method for forming a semiconductor structure, an embodiment of the present disclosure further provides a semiconductor structure. Fig.11A , Fig. 11B and Fig. 11C Shown is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure.

[0070] Reference Fig.11A , Fig. 11B and Fig. 11C As shown, the semiconductor structure includes: a substrate 110, the substrate 110 includes a storage region MR and a boundary region BR adjacent to each other in sequence, the storage region MR includes an array region AR and a dummy region DR; a plurality of bit line structures 140 located in the storage region MR, the plurality of bit line structures 140 extend along a first direction D1 and are arranged at intervals along a second direction D2, the plurality of bit line structures 140 include first bit lines BL1 and second bit lines BL2 alternately arranged along the second direction D2; a plurality of bit line contact pads 150 located in the boundary region BR, the plurality of bit line contact pads 150 are arranged at intervals along the second direction D2, the second bit lines D2 extend to the dummy region DR and are connected to the bit line contact pads 150 in a one-to-one correspondence; a bit line isolation structure 170 located in the dummy region DR and the boundary region BR, the bit line isolation structure 170 includes a first isolation portion 171 located between the second bit lines BL2 and a second isolation portion 172 between the bit line contact pads 150, and a first width w1 of the first isolation portion 171 is greater than a second width w2 of the second isolation portion 172. The first isolation portion 171 contacts the sidewall of the second bit line BL2 perpendicular to the second direction D2 and the end surface of the second bit line BL2 perpendicular to the first direction D1 between the portions of the second bit line BL2 located in the dummy region DR.

[0071] In some embodiments, the ratio of the width of the bit line contact pad 150 along the second direction D2 to the bit line width of the bit line structure 140 is in the range of 3 to 5. That is, the width of the bit line contact pad 150 is at least three times the bit line width to increase the effective contact area of ​​the bit line contact pad 150 .

[0072] In some embodiments, the first width w1 of the first isolation portion 171 is substantially equal to the spacing between adjacent second bit lines BL2 , or the first width w1 of the first isolation portion 171 is equal to the spacing between adjacent first bit lines BL1 and the line structures formed by the bit line protection layers 140 p on both sides.

[0073] In some embodiments, the second width w2 of the second isolation portion 172 is substantially equal to the bit line width of the bit line structure 140, or the second width w2 of the second isolation portion 172 is substantially equal to the width of the line structure formed by the bit line structure 140 and the bit line protection layers 140p on both sides. For example, the ratio of the second width w2 to the width of an initial bit line structure 140a is in the range of 0.8-1.5.

[0074] The substrate 110 also includes a peripheral region PR adjacent to the boundary region BR. An array active region 111 and a shallow trench isolation structure 112 separating the array active regions 111 are provided in the storage region MR of the substrate 110. The array active regions 111 are arranged in an array along the first direction D1 and the second direction D2, and each array active region 111 extends along the third direction D3. A buried word line 120 is also formed in the substrate 110. The buried word line 120 is formed in the storage region MR. The buried word line 120 extends along the second direction D2 and is arranged at intervals along the first direction D1, and intersects with the array active region 111. Each array active region 111 intersects with two buried word lines 120.

[0075] In some embodiments, reference Fig.12 As shown, the dummy region DR includes a first dummy region DR1 and a second dummy region DR2 respectively located on both sides of the array region AR along the first direction, and the boundary region BR includes a first boundary region BR1 and a second boundary region BR2 respectively located on both sides of the storage region MR along the first direction D1; the first bit line BL1 extends to the second dummy region DR2 and is connected to the bit line contact pad 150 located in the second boundary region BR2 in a one-to-one correspondence; the second bit line BL2 extends to the first dummy region DR1 and is connected to the bit line contact pad 150 located in the first boundary region BR1 in a one-to-one correspondence.

[0076] In some embodiments, reference Fig.12As shown, the substrate 110 also includes a peripheral region PR, and the semiconductor structure also includes: two relative peripheral sub-gates 210 located in the peripheral region PR; a gate isolation structure 230 located between the relative first side walls s1 of the two relative peripheral sub-gates 210, the gate isolation structure 230 is made of the same material as the bit line isolation structure 140p; a peripheral gate protection layer 210p located on the second side walls s2 of the two relative peripheral sub-gates 230, the second side wall s2 is adjacent to the first side wall s1, and the peripheral gate protection layer 210p is made of a different material from the gate isolation structure 230.

[0077] In some embodiments, reference Fig. 11B and Fig. 11C As shown, the semiconductor structure further includes: a plurality of node contact structures 160 located in the array region AR, and the plurality of node contact structures 160 are arranged in an array along the first direction D1 and the second direction D2. A contact pad structure 190 is also formed above the node contact structure 160, and the contact pad structure 190 is used to connect a storage structure, such as a capacitor.

[0078] In some embodiments, reference Fig. 11B and Fig. 11C As shown, the node contact structure 160 located in the array region AR is embedded in the substrate 110 and contacts the array active region 111 in the substrate 110 ; the second isolation portion 172 located in the dummy region DR is located on the substrate 110 , and the bottom surface of the second isolation portion 172 is flush with the top surface of the substrate 110 .

[0079] In some embodiments, the substrate 110 further includes a substrate protection layer located on the top surfaces of the array active region 111 and the shallow trench isolation structure 112. The second isolation portion 172 located in the dummy region DR may be in contact with the substrate protection layer and isolated from the array active region 111. The top surface of the array active region 111 of the substrate 110 in the dummy region DR is flat, while the top surface of the array active region 111 of the substrate 110 in the array region AR is formed with a recess R, and the recess R is used to accommodate the node contact structure 160.

[0080] In some embodiments, the semiconductor structure includes: a memory, which may be a dynamic random access memory, or a memory known in the art, such as a phase change memory or a ferroelectric memory.

[0081] The various semiconductor structures shown in this specific embodiment can be used for electronic devices with storage functions. The electronic device can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc. The storage function in the electronic device can be realized by the following memories: dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), magnetic random access memory (MRAM) or resistive random access memory (RRAM).

[0082] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a storage area and a boundary area adjacent to each other in sequence, the storage area comprising an array area and a dummy area; forming an initial conductive layer on the substrate; Patterning the initial conductive layer in the storage area to form a plurality of initial bit line structures, retaining the initial conductive layer in the boundary area to form an initial bit line contact layer, wherein the plurality of initial bit line structures extend along the first direction and are arranged at intervals along the second direction; forming an etching mask having a plurality of first openings, wherein the plurality of first openings expose a portion of the initial bit line structure in the dummy region and a portion of the initial bit line contact layer in the boundary region; Using the etching mask as a mask, patterning the initial bit line structure and the initial bit line contact layer to form a plurality of bit line structures and a plurality of bit line contact pads; A bit line isolation structure is formed, wherein the bit line isolation structure includes a first isolation portion between the bit line structures and a second isolation portion between the bit line contact pads, wherein a first width of the first isolation portion is greater than a second width of the second isolation portion.

2. The method for forming a semiconductor structure according to claim 1, wherein: The substrate further includes a peripheral region, and when the initial conductive layer of the storage region is patterned to form a plurality of initial bit line structures, it further includes: patterning the initial conductive layer of the peripheral region to form a peripheral gate; After patterning the initial conductive layer of the storage region to form a plurality of initial bit line structures, the method further includes: A peripheral gate protection layer is formed on the sidewall of the peripheral gate, and a bit line protection layer is formed on the sidewall of the initial bit line structure.

3. The method for forming a semiconductor structure according to claim 2, wherein: The etching mask is further provided with a second opening, the second opening exposing a portion of the peripheral gate of the peripheral region, and when the initial bit line structure and the initial bit line contact layer are patterned using the etching mask as a mask, the method further includes: The peripheral gate is patterned using the etching mask as a mask to form two opposite peripheral sub-gates, and the arrangement direction of the two opposite peripheral sub-gates is the extension direction of the peripheral gate.

4. The method for forming a semiconductor structure according to claim 2, wherein: After patterning the initial conductive layer of the storage region to form a plurality of initial bit line structures, the method further includes: forming a peripheral mask, wherein the peripheral mask covers the dummy area, the boundary area and the peripheral area; Using the peripheral mask as a mask, removing the bit line protection layer on the substrate in the array area to expose the substrate in the array area; The peripheral mask is removed, and an initial contact layer is filled between the plurality of initial bit line structures.

5. The method for forming a semiconductor structure according to claim 4, characterized in that: Also includes: Patterning the initial contact layer to form node contact layers spaced apart along the first direction, with node spacing grooves between adjacent node contact layers; A node isolation structure is filled in the node spacing groove.

6. The method for forming a semiconductor structure according to claim 5, characterized in that: Also includes: removing a portion of the node contact layer to form a node contact structure; forming plug grooves in the boundary region and the peripheral region; A contact pad structure located above the node contact structure, a bit line pad contact structure located in the plug groove in the boundary area, and a peripheral contact structure located in the plug groove in the peripheral area are simultaneously formed.

7. The method for forming a semiconductor structure according to claim 1, wherein: The multiple initial bit line structures include a first initial bit line structure and a second initial bit line structure alternately arranged along the second direction; the dummy region includes a first dummy region and a second dummy region respectively located at two sides of the array region along the first direction; The first opening exposes a portion of the first initial bit line structure located in the first dummy region, and the first opening also exposes a portion of the second initial bit line structure located in the second dummy region; The multiple bit line structures extend along a first direction and are arranged at intervals along a second direction. The multiple bit line structures include first bit lines and second bit lines alternately arranged along the second direction. The first bit line is formed by a portion of the first initial bit line structure located in the array area and the second dummy area, and the second bit line is formed by a portion of the second initial bit line structure located in the array area and the first dummy area.

8. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a storage area and a boundary area adjacent to each other in sequence, the storage area comprising an array area and a dummy area; A plurality of bit line structures located in the storage area, the plurality of bit line structures extending along a first direction and arranged at intervals along a second direction, the plurality of bit line structures comprising first bit lines and second bit lines alternately arranged along the second direction; a plurality of bit line contact pads located in the boundary region, the plurality of bit line contact pads being arranged at intervals along the second direction, the second bit lines extending to the dummy region and being connected to the bit line contact pads in a one-to-one correspondence; A bit line isolation structure located in the dummy area and the boundary area includes a first isolation portion located between the second bit lines and a second isolation portion between the bit line contact pads, wherein a first width of the first isolation portion is greater than a second width of the second isolation portion.

9. The semiconductor structure according to claim 8, characterized in that: The dummy area includes a first dummy area and a second dummy area respectively located at two sides of the array area along the first direction, and the boundary area includes a first boundary area and a second boundary area respectively located at two sides of the storage area along the first direction; The first bit lines extend to the second dummy area and are connected to the bit line contact pads located in the second boundary area in a one-to-one correspondence; The second bit lines extend to the first dummy region and are connected to the bit line contact pads located in the first boundary region in a one-to-one correspondence.

10. The semiconductor structure according to claim 8, characterized in that The substrate further includes a peripheral region, and the semiconductor structure further includes: two opposite peripheral sub-gates located in the peripheral region; A gate isolation structure located between the opposite first side walls of the two opposite peripheral sub-gates, the gate isolation structure being made of the same material as the bit line isolation structure; A peripheral gate protection layer is located on the second sidewalls of the two opposite peripheral sub-gates, the second sidewalls are adjacent to the first sidewalls, and the peripheral gate protection layer is made of a different material from the gate isolation structure.

11. The semiconductor structure according to claim 8, characterized in that: A first width of the first isolation portion is equal to a distance between adjacent second bit lines.

12. The semiconductor structure according to claim 8, characterized in that A second width of the second isolation portion is equal to a bit line width of the bit line structure.

13. The semiconductor structure according to claim 8, characterized in that The semiconductor structure further comprises: A plurality of node contact structures are located in the array region, and the plurality of node contact structures are arranged in an array along the first direction and the second direction.

14. The semiconductor structure according to claim 13, characterized in that: A node contact structure located in the array region is embedded in the substrate and contacts the array active region in the substrate; The second isolation portion located in the dummy area is located on the substrate and is flush with the top surface of the substrate.

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