semiconductor devices

Abstract

The semiconductor device (1) includes: a semiconductor layer (40); a first vertical MOS transistor (10) and a second vertical MOS transistor (20) formed on the semiconductor layer (40); a metal layer (30) in full contact with the back side of the semiconductor layer (40); and a support (42) bonded to the back side of the metal layer (30) via a conductive adhesive (41); in planar view, the support (42) is larger in area than the semiconductor layer (40) and includes the semiconductor layer (40); the thickness of the support (42) is greater than the thickness of the semiconductor layer (40); in a cross-section of the semiconductor device (1) including the center and the outer periphery of the semiconductor layer (40) in planar view, the semiconductor chip (2) obtained by removing the support (42) and the conductive adhesive (41) from the semiconductor device (1) is a curved shape that convexes away from the support (42).

Description

Technical Field

[0001] This disclosure relates to semiconductor devices. Background Technology

[0002] To protect lithium-ion batteries from overcharging and / or over-discharging, a vertically oriented MOS transistor with a dual structure is used, which can control bidirectional conduction with a single chip.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: US Patent No. 4,616,413 Summary of the Invention

[0006] The problem that the invention aims to solve

[0007] To reduce the on-resistance of a dual-structure vertical MOS transistor (hereinafter, also referred to as a "semiconductor chip"), a dual-structure vertical MOS transistor is preferably constructed with a large area in planar view and a thin semiconductor substrate. However, with such a construction, the warpage of the semiconductor chip increases, and the strength of the semiconductor chip decreases. Patent Document 1 discloses a construction in which a printed circuit board is bonded to a rigid metal plate via a conductive adhesive.

[0008] Therefore, the purpose of this disclosure is to provide a semiconductor device having a vertically oriented MOS transistor with a dual structure that improves the density of the contact, in a construction where a rigid metal plate is bonded by a conductive adhesive.

[0009] Methods used to solve problems

[0010] To address the aforementioned issues, the semiconductor device disclosed herein is a chip-scale packaged semiconductor device capable of being mounted face-down, characterized by comprising: a semiconductor substrate; a low-concentration impurity layer formed on the surface side of the semiconductor substrate; a first vertical MOS transistor formed in a first region of the semiconductor layer, wherein the semiconductor substrate and the low-concentration impurity layer are together used as the semiconductor layer; a second vertical MOS transistor formed in a second region adjacent to the first region in planar view of the semiconductor layer; a first source electrode of the first vertical MOS transistor formed on the surface side of the semiconductor layer; and the second vertical MOS transistor... The second source electrode of the tube is formed on the surface side of the semiconductor layer; and the support is formed on the back side of the semiconductor substrate via a conductive adhesive; in the planar view, the support has a larger area than the semiconductor layer and includes the semiconductor layer; the thickness of the support is greater than the thickness of the semiconductor layer; in the cross-section of the semiconductor device including the center and the outer periphery of the semiconductor layer in the planar view, when observing the semiconductor chip in the semiconductor device other than the support and the conductive adhesive, the semiconductor chip has a curved shape that convexes away from the support.

[0011] Based on the above structure, in the dual-structure vertical MOS transistor, the warpage of the semiconductor chip can be reduced while decreasing the on-resistance, and the strength of the semiconductor chip can be improved.

[0012] Invention Effects

[0013] The purpose of this disclosure is to provide a semiconductor device having a vertically oriented MOS transistor with a dual structure that reduces the on-resistance of a semiconductor chip while mitigating warpage of the semiconductor chip, thereby improving the strength of the semiconductor chip. Attached Figure Description

[0014] Figure 1 This is a cross-sectional schematic diagram illustrating an example of the structure of the semiconductor device according to Embodiment 1.

[0015] Figure 2A This is a plan view illustrating an example of the structure of the semiconductor device according to Embodiment 1.

[0016] Figure 2B This is a cross-sectional schematic diagram showing the main current flowing in the semiconductor device of Embodiment 1.

[0017] Figure 3A This is a plan view illustrating an example of the structure of the semiconductor device according to Embodiment 1.

[0018] Figure 3BThis is a three-dimensional schematic diagram illustrating an example of the structure of the semiconductor device according to Embodiment 1.

[0019] Figure 4A This is a flowchart illustrating a part of the manufacturing process of the semiconductor device in Embodiment 1.

[0020] Figure 4B This is a cross-sectional schematic diagram showing the process of mounting the semiconductor device of Embodiment 1 face down.

[0021] Figure 5 This is a cross-sectional schematic diagram showing an example of the structure of a semiconductor device according to a variation of Embodiment 1.

[0022] Figure 6 This is a drawing showing the size range of a semiconductor chip that can achieve the effect of the semiconductor device of Embodiment 1.

[0023] Figure 7A This is a cross-sectional SEM image illustrating an example of the structure of the semiconductor device in Embodiment 1.

[0024] Figure 7B This is a cross-sectional SEM image illustrating an example of the structure of the semiconductor device in Embodiment 1.

[0025] Figure 7C This is a cross-sectional SEM image illustrating an example of the structure of the semiconductor device in Embodiment 1.

[0026] Figure 8A This is a cross-sectional schematic diagram showing an example of the structure of a semiconductor device in a variation 2 of Embodiment 1.

[0027] Figure 8B This is a cross-sectional schematic diagram showing an example of the structure of a semiconductor device of Modification 3 of Embodiment 1.

[0028] Figure 9 This is a cross-sectional schematic diagram illustrating an example of the structure of the semiconductor device according to Embodiment 2.

[0029] Figure 10 This is a flowchart illustrating a part of the manufacturing process of the semiconductor device in Embodiment 2.

[0030] Figure 11A This is a cross-sectional schematic diagram illustrating an example of the structure of the semiconductor device according to Embodiment 3.

[0031] Figure 11B This is a plan view illustrating an example of the structure of the processing support in the semiconductor device according to Embodiment 3.

[0032] Figure 11C This is a plan view illustrating an example of the structure of the semiconductor device according to Embodiment 3. Detailed Implementation

[0033] Hereinafter, specific examples of a semiconductor device according to a technical solution of the present disclosure will be described with reference to the accompanying drawings. The embodiments shown herein are all specific examples of the present disclosure. Therefore, the values, shapes, constituent elements, arrangements of constituent elements, and connection patterns shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, the figures are schematic diagrams and are not necessarily strictly illustrated. In the figures, substantially identical structures are given the same reference numerals, and repeated descriptions are omitted or simplified.

[0034] (Implementation 1)

[0035] [1. Structure of a Semiconductor Device]

[0036] Figure 1 This is a cross-sectional view illustrating an example of the construction of a semiconductor device. Figure 2A This is a planar diagram; besides being rectangular (square or oblong), the size and shape of a semiconductor device are examples. Furthermore, the size, shape, and arrangement of the solder pads are also examples. Figure 2B It is a schematic cross-sectional view showing the main current flowing in a semiconductor device. Figure 1 and Figure 2B It is along Figure 2A The cut surface when cutting I-I.

[0037] In this disclosure, the semiconductor device 1 is described assuming that it has a metal layer 30, but the semiconductor device 1 is not limited to having a structure that necessarily has a metal layer 30.

[0038] like Figure 1 and Figure 2B As shown, the semiconductor device 1 has a semiconductor substrate 32, a metal layer 30, and a low-concentration impurity layer 33 formed on the semiconductor substrate 32. In this disclosure, the semiconductor substrate 32 and the low-concentration impurity layer 33 are collectively referred to as the semiconductor layer 40.

[0039] A semiconductor substrate 32 is disposed on the back side of the semiconductor layer 40 and is made of silicon of the first conductivity type, containing impurities of the first conductivity type. A low-concentration impurity layer 33 is disposed on the surface side of the semiconductor layer 40, formed in contact with the semiconductor substrate 32, and contains impurities of the first conductivity type at a lower concentration than those of the first conductivity type impurities in the semiconductor substrate 32, and is of the first conductivity type. The low-concentration impurity layer 33 can be formed on the semiconductor substrate 32, for example, by epitaxial growth.

[0040] like Figure 1 and Figure 2AAs shown, the semiconductor device 1 has a first vertical MOS transistor 10 (hereinafter also referred to as "transistor 10") formed in a first region A1 within the semiconductor layer 40 and a second vertical MOS transistor 20 (hereinafter also referred to as "transistor 20") formed in a second region A2 within the semiconductor layer 40.

[0041] Here, as Figure 2A As shown, region A1 and region A2 are adjacent to each other in planar view of semiconductor layer 40, dividing semiconductor layer 40 into two equal parts in area. Figure 2A In the diagram, the imaginary boundary line 90 between region A1 and region A2 is represented by a dashed line (for ease of understanding, the dashed line representing the boundary line 90 extends to the outside of semiconductor layer 40 and semiconductor device 1). Additionally, in... Figure 2A In the diagram, the dashed lines representing regions A1 and A2 are not strictly aligned with the semiconductor layer 40 and boundary line 90 for ease of understanding. Instead, they are slightly left blank and represent the inner side. However, in reality, the outer perimeter of region A1 and the outer perimeter of region A2 are aligned with the outer perimeter of semiconductor layer 40 and boundary line 90.

[0042] The metal layer 30 is formed by contacting the back side of the semiconductor layer 40 (semiconductor substrate 32), and is made of, for example, silver (Ag) or copper (Cu). Additionally, the metal layer 30 may contain trace amounts of elements other than the metal that were introduced as impurities during the manufacturing process of the metal material. Furthermore, the metal layer 30 may be formed on the entire back side of the semiconductor layer 40 (semiconductor substrate 32). The thickness of the metal layer 30 is preferably 10 μm or less, more preferably 5 μm or less. For example, the thickness of the metal layer 30 is 3 μm.

[0043] The support 42 is formed by indirect contact with the back side of the metal layer 30 via a conductive adhesive 41. Typically, the support 42 is more than twice the thickness of the semiconductor layer 40, for example, a flat metal plate with a uniform in-plane thickness of 200 μm. Hereinafter, the support 42 may also be referred to as a thick-film metal plate. The thick-film metal plate is, for example, made of a metal material primarily composed of copper (Cu). Furthermore, the conductive adhesive 41 is typically silver paste.

[0044] like Figure 1 As shown, in this disclosure, the structure of the semiconductor device 1 after removing the support 42 and the conductive adhesive 41 is referred to as the semiconductor chip 2. The semiconductor chip 2 is as follows... Figure 1As shown, it exhibits a curved shape that convexes away from the support 42. This curved shape is, for example, a shape resulting from warping. The amount of warping in the semiconductor chip 2 is the difference between the highest and lowest positions in the Z direction of the upper or lower surface of the semiconductor layer 40, or the lower surface of the metal layer 30, when the semiconductor chip 2 is viewed in cross-section. In the case where the warping in the semiconductor chip 2 is a convex warping away from the support 42, the highest position is the center of the semiconductor layer 40 in planar view, and the lowest position is the outer periphery of the semiconductor layer 40 in planar view, particularly the corners at the outer periphery.

[0045] Furthermore, the center of semiconductor layer 40 in planar view refers to the intersection of the diagonals of semiconductor layer 40 in planar view. Additionally, the cross-sectional view of semiconductor device 1 as described in this disclosure refers to the view of a cross-section of semiconductor device 1 taken from a plane that simultaneously includes the center of semiconductor layer 40 in planar view and the outer periphery of semiconductor layer 40 in semiconductor chip 2. In this case, the outer periphery of semiconductor layer 40 can be any position on the outer periphery of semiconductor layer 40.

[0046] like Figure 1 and Figure 2A As shown, in the first region A1 of the semiconductor layer 40 (low-concentration impurity layer 33), a first body region 18 containing impurities of a second conductivity type different from the first conductivity type is formed. In the first body region 18, a first source region 14 containing impurities of the first conductivity type, a first gate conductor 15, and a first gate insulating film 16 are formed.

[0047] A first gate insulating film 16 is formed inside a plurality of first gate trenches 17, which extend from the upper surface of the semiconductor layer 40 through the first source region 14 and the first body region 18 to a depth reaching a portion of the low-concentration impurity layer 33. A first gate conductor 15 is formed inside the first gate trenches 17 on the first gate insulating film 16. The first gate conductor 15 is a buried gate electrode embedded in the semiconductor layer 40 and electrically connected to the first gate pad 119.

[0048] The first source electrode 11 is composed of a portion 12 and a portion 13, with portion 12 connected to the first source region 14 and the first body region 18 via portion 13. The portion 12 of the first source electrode 11 is a layer that bonds with solder during reflow in a face-down mounting configuration. As a non-limiting example, it may be made of one or more metallic materials including nickel, titanium, tungsten, and palladium. A plating layer such as gold may be applied to the surface of portion 12.

[0049] The portion 13 of the first source electrode 11 is a layer that connects the portion 12 to the semiconductor layer 40. As an example that is not limited, it may be made of one or more metallic materials including aluminum, copper, gold, and silver.

[0050] The thickness of the first source electrode 11 is, for example, 2 μm or more and 13 μm or less when the portions 12 and 13 are combined.

[0051] In the second region A2 of the low-concentration impurity layer 33, a second body region 28 containing impurities of a second conductivity type is formed. In the second body region 28, a second source region 24 containing impurities of a first conductivity type, a second gate conductor 25, and a second gate insulating film 26 are formed.

[0052] A second gate insulating film 26 is formed inside a plurality of second gate trenches 27. The second gate trenches 27 extend from the upper surface of the semiconductor layer 40 through the second source region 24 and the second body region 28 to a depth reaching a portion of the low-concentration impurity layer 33. A second gate conductor 25 is formed on the second gate insulating film 26 inside the second gate trenches 27. The second gate conductor 25 is a buried gate electrode embedded in the semiconductor layer 40 and electrically connected to the second gate pad 129.

[0053] The second source electrode 21 is composed of a portion 22 and a portion 23, with portion 22 connected to the second source region 24 and the second body region 28 via portion 23. Portion 22 of the second source electrode 21 is a layer that bonds with solder during reflow in a face-down mounting configuration. As a non-limiting example, it may be made of one or more metallic materials including nickel, titanium, tungsten, and palladium. A plating layer such as gold may be applied to the surface of portion 22.

[0054] The portion 23 of the second source electrode 21 is a layer that connects portion 22 to the semiconductor layer 40. As an example that is not limited, it may be made of one or more metallic materials including aluminum, copper, gold, and silver.

[0055] The thickness of the second source electrode 21 is, for example, 2 μm or more and 13 μm or less when the portions 22 and 23 are combined.

[0056] With the aforementioned structures of transistors 10 and 20, the semiconductor substrate 32 functions as a common drain region that combines the first drain region of transistor 10 and the second drain region of transistor 20. A portion of the side of the semiconductor substrate 32 with the low-concentration impurity layer 33 also functions as a common drain region. Furthermore, the low-concentration impurity layer 33 is also a drift layer common to both transistors 10 and 20, and is sometimes referred to as a drift layer in this specification.

[0057] Furthermore, the metal layer 30 functions as a common drain electrode that makes the drain electrodes of transistor 10 and transistor 20 common. When the support 42 is a thick-film metal plate, not only the metal layer 30, but also the conductive adhesive 41 and the thick-film metal plate function as common drain electrodes.

[0058] like Figure 1 As shown, the first body region 18 is covered by an interlayer insulating layer 34 with an opening, and is connected to a portion 13 of the first source electrode 11 connected to the first source region 14 through the opening of the interlayer insulating layer 34. The interlayer insulating layer 34 and the portion 13 of the first source electrode 11 are covered by a passivation layer 35 with an opening, and are connected to a portion 12 connected to the portion 13 of the first source electrode 11 through the opening of the passivation layer 35.

[0059] The second body region 28 is covered by an interlayer insulating layer 34 with an opening, and is connected to a portion 23 of the second source electrode 21 connected to the second source region 24 through the opening of the interlayer insulating layer 34. The interlayer insulating layer 34 and the portion 23 of the second source electrode 21 are covered by a passivation layer 35 with an opening, and are connected to a portion 22 connected to the portion 23 of the second source electrode 21 through the opening of the passivation layer 35.

[0060] Therefore, the plurality of first source pads 111 and the plurality of second source pads 121 refer to the areas where the first source electrode 11 and the second source electrode 21 are partially exposed on the surface of the semiconductor device 1, the so-called terminal portions. Similarly, one or more first gate pads 119 and one or more second gate pads 129 refer to the areas where the first gate electrode 19 (in) is partially exposed on the surface of the semiconductor device 1, the so-called terminal portions. Figure 1 , Figure 2A , Figure 2B (not shown in the diagram) and the second gate electrode 29 (in Figure 1 , Figure 2A , Figure 2B (Not shown in the figure) The area partially exposed on the surface of semiconductor device 1, the so-called terminal portion.

[0061] Furthermore, in this disclosure, it is assumed that, in planar view, only the structure constituting the first vertical MOS transistor 10 is present in the first region A1, and only the structure constituting the second vertical MOS transistor 20 is present in the second region A2. Additionally, the boundary line 90 can also be understood as an imaginary line along the central position of the interval between the portion 13 of the first source electrode 11 and the portion 23 of the second source electrode 21. Furthermore, although it has a finite width, it can also be understood as the interval itself (even in the case of this interval, it can be identified as a line to the naked eye or at low magnification).

[0062] In semiconductor device 1, for example, the first conductivity type can be set as N-type, the second conductivity type can be set as P-type, the first source region 14, the second source region 24, the semiconductor substrate 32 and the low concentration impurity layer 33 are N-type semiconductors, and the first body region 18 and the second body region 28 are P-type semiconductors.

[0063] Furthermore, in the semiconductor device 1, for example, the first conductivity type may be set to P-type, the second conductivity type may be set to N-type, the first source region 14, the second source region 24, the semiconductor substrate 32 and the low-concentration impurity layer 33 are P-type semiconductors, and the first body region 18 and the second body region 28 are N-type semiconductors.

[0064] [2. Operation of a vertically oriented MOS transistor with a dual structure]

[0065] In the following description, it is assumed that transistors 10 and 20 are so-called N-channel transistors with the first conductivity type set to N-type and the second conductivity type set to P-type, and the conduction operation of semiconductor device 1 will be described.

[0066] Figure 3A and Figure 3B These are planar and three-dimensional views, respectively, of the approximate unit structure of transistors 10 (or 20) repeatedly formed in the X and Y directions of semiconductor device 1. Figure 3A and Figure 3B For ease of understanding, the semiconductor substrate 32 and metal layer 30, conductive adhesive 41, thick film metal plate, passivation layer 35 and first source electrode 11 (or second source electrode 21), and interlayer insulating layer 34 are not illustrated.

[0067] The construction of transistor 10 is the same as that of transistor 20. Therefore, the following description uses the designation of transistor 10 to illustrate the approximate unit structure.

[0068] The Y direction is parallel to the upper surface of the semiconductor layer 40 and extends along the first gate trench 17. Furthermore, the X direction is parallel to the upper surface of the semiconductor layer 40 and orthogonal to the Y direction. The Z direction is orthogonal to both the X and Y directions and represents the height direction of the semiconductor device 1. In this disclosure, there are also cases where the Y direction is referred to as the first direction, the X direction as the second direction, and the Z direction as the third direction.

[0069] like Figure 3A and Figure 3BAs shown, transistor 10 includes a first connection portion 18a that electrically connects a first body region 18 to a first source electrode 11. The first connection portion 18a is a region in the first body region 18 where the first source region 14 is not formed, and contains impurities of the same second conductivity type as the first body region 18. The first source region 14 and the first connection portion 18a are alternately and periodically arranged along the Y direction. Transistor 20 is similar.

[0070] In semiconductor device 1, if a high voltage is applied to the first source electrode 11 and a low voltage is applied to the second source electrode 21, and a voltage above a threshold is applied to the second gate electrode 29 (second gate conductor 25) with reference to the second source electrode 21, a conductive channel is formed near the second gate insulating film 26 in the second body region 28. As a result, a main current flows through the path of first source electrode 11 – first connection portion 18a – first body region 18 – low concentration impurity layer 33 – semiconductor substrate 32 – metal layer 30 – conductive adhesive 41 – thick film metal plate – conductive adhesive 41 – metal layer 30 – semiconductor substrate 32 – low concentration impurity layer 33 – conductive channel formed in the second body region 28 – second source region 24 – second source electrode 21, and semiconductor device 1 becomes conductive. A PN junction exists at the contact surface between the second body region 28 and the low concentration impurity layer 33 in this conductive path, which functions as a body diode.

[0071] Similarly, in semiconductor device 1, if a high voltage is applied to the second source electrode 21 and a low voltage is applied to the first source electrode 11, and a voltage above a threshold is applied to the first gate electrode 19 (first gate conductor 15) with reference to the first source electrode 11, a conductive channel is formed near the first gate insulating film 16 in the first body region 18. As a result, a main current flows through the path of second source electrode 21 – second connection portion 28a – second body region 28 – low concentration impurity layer 33 – semiconductor substrate 32 – metal layer 30 – conductive adhesive 41 – thick film metal plate – conductive adhesive 41 – metal layer 30 – semiconductor substrate 32 – low concentration impurity layer 33 – conductive channel formed in the first body region 18 – first source region 14 – first source electrode 11, and semiconductor device 1 becomes conductive. A PN junction exists at the contact surface between the first body region 18 and the low concentration impurity layer 33 in this conductive path, functioning as a body diode.

[0072] exist Figure 2BThe bidirectional flow of the main current is schematically indicated by arrows. Horizontal (X-direction) main current flows in each of the layers: metal layer 30, conductive adhesive 41, thick-film metal plate, and semiconductor substrate 32. Since the resistivity of metal layer 30 and the thick-film metal plate is lower than that of the other layers, by making metal layer 30 or the thick-film metal plate thicker, the cross-sectional area of ​​the main current path can be increased, thereby reducing the on-resistance of the semiconductor device 1.

[0073] [3. Manufacturing method of semiconductor device]

[0074] The manufacturing method of semiconductor device 1 will be described.

[0075] Figure 4A This diagram simply illustrates a portion of the manufacturing process of the semiconductor device 1 according to Embodiment 1. The construction of each dual-structure vertical MOS transistor, which is subsequently monolithized, is formed in a grid pattern on a silicon wafer up to step 501.

[0076] Next, in step 502, the back side of the silicon wafer (which corresponds to the semiconductor substrate 32 in view of the various dual-structure vertical MOS transistors that will be monolithically assembled later) is thinned. In the thinning process of step 502, it is preferable to control the thickness of the semiconductor layer 40 to be 15 μm or more and 100 μm or less, and more preferably to be 15 μm or more and 75 μm or less.

[0077] Next, in step 503, a metal layer 30 is formed on the back side of the thinned silicon wafer. The metal layer 30 may be, for example, a multilayer structure comprising multiple metal layers. The multiple metal layers may be formed individually by one of the following methods: vapor deposition, sputtering, or plating.

[0078] Next, in process 504, the silicon wafer is sliced ​​to monolithize each dual-structure vertical MOS transistor. Since the monolithized dual-structure vertical MOS transistor is not yet bonded to the thick-film metal plate, it is in the state described above, which can be called semiconductor chip 2.

[0079] Next, in step 505, a thick-film metal plate coated with a conductive adhesive 41 such as silver paste is prepared in advance, and the back side of the metal layer 30 of the semiconductor chip 2 is bonded. Typically, the amount of conductive adhesive 41 pushed in is set to, for example, between 5 [μm] and 10 [μm], and the thickness of the bonded conductive adhesive 41 after curing is calculated to a target value (for example, 20 [μm] to 60 [μm]), and the conductive adhesive 41 is coated on the surface of the thick-film metal plate.

[0080] The conductive adhesive 41 is used to bond the back side of the metal layer 30 to the thick film metal plate. Preferably, when viewed in the state after the conductive adhesive 41 has been cured and bonded to the thick film metal plate, the entire back side of the metal layer 30 is completely covered by the conductive adhesive 41.

[0081] For thick-film metal plates, a structure is chosen whose area exceeds that of the semiconductor substrate 32 in planar view. During bonding, alignment is performed so that a gap of approximately equal width exists from the outer periphery of the metal layer 30 to the outer periphery of the nearest thick-film metal plate in planar view. As an example, such as... Figure 2A As shown, the thick-film metal plate has a similar shape to the semiconductor layer 40. The statement that the semiconductor layer 40 and the thick-film metal plate have similar shapes means that, when viewed in a planar view, the semiconductor layer 40 and the thick-film metal plate have the same shape, differing only in area.

[0082] Furthermore, regarding the thick-film metal plate, it is preferable for bonding the semiconductor layer 40 to have a thickness that is uniform in plane from a macroscopic perspective, and to be a so-called flat plate without any steps or unevenness. In this embodiment 1, it is assumed that the thick-film metal plate is a flat plate for explanation.

[0083] During bonding, typically, a relatively large, thick-film metal plate is used as the receiving side, and the relatively small semiconductor chip 2 is aligned. This also allows the conductive adhesive 41 to be exposed from the back side of the metal layer 30 in planar view. Whether the amount of exposed conductive adhesive 41 is uniform along the outer periphery of the semiconductor layer 40 in planar view is acceptable. Figure 2A In the example shown, the exposure of the conductive adhesive 41 is uniform.

[0084] In step 505, to harden the conductive adhesive 41 such as silver paste, a heat treatment is performed on the thick-film metal plate at a high temperature of approximately 170°C while the semiconductor chip 2 is aligned. The conductive adhesive 41 begins to harden from around 170°C, and the metal layer 30 is bonded to the thick-film metal plate to form the semiconductor device 1.

[0085] Furthermore, during the heat treatment of the thick-film metal plate at a high temperature of 170°C, the semiconductor chip 2 warps. As described above, the thickness of the semiconductor layer 40 is preferably 15 μm or more and 75 μm or less, and the thicknesses of the first source electrode 11 and the second source electrode 21 are 2 μm or more and 13 μm or less. The thickness of the metal layer 30 is preferably 5 μm or less. By appropriately selecting the respective film thicknesses, the warping orientation of the semiconductor chip 2 at 170°C can be controlled.

[0086] For example, if the thickness of the semiconductor layer 40 is 53 μm, the thickness of the first source electrode 11 and the second source electrode 21 is 5 μm, and the thickness of the metal layer 30 is 3 μm, then at 170 °C, the semiconductor chip 2 will generate a direction away from the thick-film metal plate (in... Figure 1 The warping is convex in the +Z direction (see cross-section in the middle).

[0087] Figure 4B This is a schematic diagram of the semiconductor device 1 installed facing downwards.

[0088] [4. Investigation]

[0089] The effects of the semiconductor device 1 in Embodiment 1 will be explained below.

[0090] In a vertically oriented MOS transistor with a dual structure, to reduce the on-resistance during conduction, the semiconductor substrate 32 (semiconductor layer 40) needs to be relatively thin and the metal layer 30 relatively thick. Such a semiconductor chip 2 is prone to warping in the -Z direction at high temperatures. The thinner the semiconductor layer 40 and the thicker the metal layer 30, the greater the warping at high temperatures.

[0091] In particular, in the case of a vertically oriented MOS transistor with a dual structure requiring low on-resistance, increasing the area of ​​the semiconductor chip 2 in planar view is effective in order to increase the total gate width of the channel. However, if the area is large, the warpage occurring on the semiconductor chip 2 increases significantly.

[0092] When mounting semiconductor chip 2 face down onto the mounting substrate, a reflow process at a high temperature of approximately 240°C is required using soldering materials. It is known that if the warpage of semiconductor chip 2 at 240°C exceeds 40 μm, mounting defects are likely to occur regardless of the warpage orientation. Therefore, it is necessary to suppress the warpage of semiconductor chip 2 to below 40 μm.

[0093] The structure of the semiconductor device 1 in this embodiment 1 is particularly effective for semiconductor chips 2 where the semiconductor layer 40 is thin and has a large area, as described above. In the semiconductor device 1, the support 42 is made into a thick-film metal plate, and it is also connected to the metal layer 30 with a conductive adhesive 41. Therefore, even if the metal layer 30 is thin, as long as the thick-film metal plate is sufficiently thick, the thick-film metal plate becomes a horizontal conductive path, thereby reducing the on-resistance of the semiconductor device 1. Furthermore, in the semiconductor chip 2, by making the metal layer 30 thinner, warping can be reduced.

[0094] Furthermore, since the bonding of the semiconductor chip 2 to the thick-film metal plate occurs at a temperature around 170°C, which is lower than 240°C, the warpage of the semiconductor chip 2 can be suppressed to a level that occurs around 170°C. As for the conductive adhesive 41, if a material that does not remelt, such as silver paste, is chosen, the semiconductor chip 2, already bonded to the thick-film metal plate, will not experience increased warpage during the reflow process (240°C) when mounting the semiconductor device 1 face down onto the mounting substrate.

[0095] Furthermore, if the thick-film metal plate is sufficiently thick, it acts as a support for the semiconductor chip 2, thus compensating for the decrease in strength of the semiconductor chip 2 caused by making the semiconductor layer 40 thinner.

[0096] Therefore, the thick-film metal plate of the semiconductor device 1 in this embodiment 1 has the effect of physically compensating for the thinning of the semiconductor layer 40 and electrically compensating for the thinning of the metal layer 30. In an extreme case, the metal layer 30 may not even exist. In this case, such as... Figure 5 As shown in Modification 1 of Embodiment 1, the conductive adhesive 41 is directly bonded to the entire back surface of the semiconductor substrate 32 (semiconductor layer 40).

[0097] The larger the area of ​​the semiconductor layer 40 in the semiconductor chip 2 when viewed from a plane, and the thinner the semiconductor layer 40, the more useful the structure of the semiconductor device 1 with a thick-film metal plate in Embodiment 1. Conversely, for semiconductor chips 2 with a small area of ​​the semiconductor layer 40 when viewed from a plane and a thick semiconductor layer 40, bonding the thick-film metal plate is of little significance. Therefore, the dimensions (area and thickness) of the semiconductor chip 2 that are useful for the structure of the semiconductor device 1 with a thick-film metal plate in Embodiment 1 were investigated.

[0098] exist Figure 6 The diagram shows a plot of the area and thickness of the semiconductor layer 40 (from the upper surface of the low-concentration impurity layer 33 to the lower surface of the semiconductor substrate 32) as required in a planar view to achieve an on-resistance of less than 1 [mΩ] for the semiconductor chip 2, and the resulting warpage of the semiconductor chip 2. Here, 1 [mΩ] is a rough standard; for battery protection circuits, a low on-resistance of, for example, less than 1 [mΩ] is required when handling high currents, which has become increasingly demanding in recent years.

[0099] The horizontal axis represents the area S [mm] of the semiconductor layer 40 as viewed from the plane of semiconductor chip 2. 2 The left vertical axis represents the thickness h [mm] of the semiconductor layer 40 of semiconductor chip 2. The semiconductor layer 40 is square in shape. For example, 2.5 × 2.5 [mm] corresponds to an area of ​​6.2 [mm²]. 2 ], 3.4 × 3.4 [mm] is equivalent to an area of ​​11.5 [mm²]2 The symbol 〇 indicates the thickness of semiconductor layer 40 when the on-resistance of semiconductor chip 2 is exactly 1.00 [mΩ]. The symbol △ indicates the thickness of semiconductor layer 40 when the on-resistance of semiconductor chip 2 is exactly 0.75 [mΩ]. In calculating the thickness of semiconductor layer 40 in semiconductor chip 2, the metal layer 30 is made of silver (Ag) and has a thickness of 50 [μm].

[0100] To achieve a low on-resistance of less than 1.00 mΩ, the semiconductor chip 2 needs to be configured to include a region below and within the curve connecting the zero-marked plots. If the area of ​​the semiconductor layer 40 in the semiconductor chip 2 as viewed from the planar perspective is small, the thickness of the semiconductor layer 40 must be thin, while if the area of ​​the semiconductor layer 40 in the semiconductor chip 2 as viewed from the planar perspective is large, the thickness of the semiconductor layer 40 can be increased to a certain extent.

[0101] The line connecting the 0 marks is approximately in the relationship h = 0.016 × S - 0.042. Figure 6 The dashed line in the figure has good accuracy when 6.2≤S≤11.5. Therefore, in order to make the on-resistance below 1.00[mΩ], the semiconductor layer 40 of the semiconductor chip 2 is required to be in the relationship of h≤0.016×S-0.042.

[0102] The line connecting the △ markers is approximately in the relationship h = 0.014 × S - 0.074. Figure 6 The dashed line in the figure has good accuracy when 6.2≤S≤11.5. Therefore, in order to make the on-resistance below 0.75[mΩ], the semiconductor layer 40 of the semiconductor chip 2 is required to be in the relationship of h≤0.014×S-0.074.

[0103] Figure 6 The right vertical axis represents the warpage [μm] of the semiconductor chip 2 at a high temperature of 240 [°C]. The figure marked with □ represents the warpage that occurs when the semiconductor layer 40 of each semiconductor chip 2, represented by 〇, has a metal layer 30 with a thickness of 50 [μm] and Ag is formed therein. The thickness of Ag is set to 50 [μm] for the metal layer 30 of the semiconductor chip 2 to allow for comparison with the structure of the semiconductor device 1 of this embodiment 1, which has a thick-film metal plate. The material constituting the metal layer 30 is Ag, which has good resistivity, and the thickness of 50 [μm] was chosen to ensure that the contribution to reducing the on-resistance is approximately saturated.

[0104] Furthermore, the semiconductor layer 40 is designed as a square in planar view because, even with the same structure (area S and thickness h), a square shape best reduces warpage. Therefore, Figure 5 The □ mark indicates the minimum amount of warpage in the state of the semiconductor chip 2, which can be compared with the semiconductor device 1 of Embodiment 1 in terms of electrical aspects.

[0105] according to Figure 6 It can be seen that, when the on-resistance is required to be below 1.00 mΩ, and the area is 6.2 mm², 2 At temperatures above 240°C, the warpage exceeds 40 μm. Therefore, in an area of ​​6.2 mm²... 2 When the above conditions are met, it is difficult to install the semiconductor chip 2 in its original state, and countermeasures to reduce the amount of warpage are required.

[0106] Even with an on-resistance of 1.00 mΩ, the area of ​​semiconductor chip 2, when viewed from a planar surface, is less than 6.2 mm². 2 In the case of [missing information], since the warpage is less than 40 [μm], it is possible to mount the semiconductor chip 2 in its original state. Furthermore, even if the area of ​​the semiconductor chip 2 is the same at 6.2 [mm²] when viewed from a planar perspective... 2 As long as the on-resistance can also be higher than 1.00 [mΩ], there is no need to make the thickness of the semiconductor layer 40 excessively thin, so the warpage is less than 40 [μm], and the semiconductor chip 2 can be installed in its original state.

[0107] Therefore, for a square shape viewed in a plane with a diameter of 6.2 mm, 2 When a semiconductor chip 2 with an area of ​​2.5 × 2.5 mm or more is required to have an on-resistance of 1.00 mΩ or less, that is, when the relationship h ≤ 0.016 × S - 0.042 holds for the semiconductor layer 40 of the semiconductor chip 2, it is preferable to bond a thick film metal plate as in the semiconductor device 1 of this embodiment 1.

[0108] Furthermore, for example, when it is required that the on-resistance be below 0.75 [mΩ], it is necessary to make the thickness of the semiconductor layer 40 in the semiconductor chip 2 thinner. That is, regarding the semiconductor layer 40 of the semiconductor chip 2, when the relationship h ≤ 0.014 × S - 0.074 holds, it is more preferable to bond a thick film metal plate as in the semiconductor device 1 of this embodiment 1.

[0109] Furthermore, in this embodiment 1, by appropriately selecting the thicknesses of the semiconductor layer 40 (semiconductor substrate 32), the first source electrode 11 and the second source electrode 21, and the metal layer 30, the warpage of the 170°C semiconductor chip 2 can be controlled to bulge in a direction away from the support 42 (+Z direction).

[0110] like Figure 1 As shown, if warping occurs from the perspective of the thick-film metal plate, causing it to bulge in a direction away from the back side of the metal layer 30 (+Z direction), then the conductive adhesive 41 is squeezed between the metal layer 30 and the thick-film metal plate. Specifically, the end of the metal layer 30 approaches the thick-film metal plate relatively (-Z direction) due to the bending of the semiconductor chip 2, pushing the conductive adhesive 41 towards the thick-film metal plate side. If the semiconductor chip 2 has such a bent shape, an improved bonding tightness between the semiconductor chip 2 and the thick-film metal plate can be achieved.

[0111] Therefore, for the semiconductor device 1, in a cross-sectional view of the semiconductor device 1, when observing the semiconductor chip 2 in the semiconductor device 1 excluding the thick-film metal plate and the conductive adhesive 41, the semiconductor chip 2 preferably has a curved shape that convexes away from the thick-film metal plate. In other words, it is preferable that the thickness of the conductive adhesive 41 directly below the semiconductor layer 40 at the outer periphery of the semiconductor layer 40 in planar view is thinner than the thickness of the conductive adhesive 41 directly below the semiconductor layer 40 at the center of the semiconductor layer 40 in planar view.

[0112] exist Figure 7A , Figure 7B , Figure 7C The image shown is a cross-sectional SEM image of the semiconductor device 1 of this embodiment 1 mounted face down on the mounting substrate. Figure 7B yes Figure 7A A magnified cross-sectional SEM image of the portion enclosed by the dashed line. Figure 7C yes Figure 7B A magnified cross-sectional SEM image of the portion enclosed by the dashed line. Figures 7A to 7C In the semiconductor device 1 shown, the thickness of the semiconductor layer 40 is 53 [μm], the thickness of the first source electrode 11 and the second source electrode 21 is 4 [μm], the thickness of the metal layer 30 is 3 [μm], and the thickness of the thick film metal plate is 200 [μm].

[0113] Figure 7B and Figure 7C The horizontal line A in the diagram is represented by extending the interface between the semiconductor layer 40 and the metal layer 30 at the center of the semiconductor layer 40 in planar view to the outer periphery of the semiconductor layer 40 in planar view. Furthermore, Figure 7CThe horizontal line B in the diagram indicates the interface location between the semiconductor layer 40 and the metal layer 30 at the outer periphery of the semiconductor layer 40. Figure 7C In the middle, horizontal line B is on the side closer to the thick film metal plate (in the -Z direction) than horizontal line A, and the Z-direction interval between horizontal line A and horizontal line B is 2 [μm].

[0114] Therefore, the semiconductor chip 2 has a convex and warped shape in the direction away from the thick-film metal plate (+Z direction), and the warping amount is 2 [μm]. The conductive adhesive 41 that bonds the semiconductor chip 2 to the thick-film metal plate is extruded between the two and hardened, covering the entire back side of the semiconductor chip 2. With the conductive adhesive 41, the areas where pores occur and the areas to be peeled off are not visible, and the good adhesion can be confirmed.

[0115] The inventors' research shows that if the warpage of the semiconductor chip 2 at 170°C is 2 μm or more, a stable effect of improved adhesion can be achieved. When the warpage is less than 2 μm, or when the warpage is convex in the opposite direction, the conductive adhesive 41 cannot be reliably squeezed between the semiconductor chip 2 and the thick-film metal plate, and traces of the conductive adhesive 41 peeling off at the end of the semiconductor device 1 can be observed.

[0116] The semiconductor chip 2 warps at high temperatures because the first source electrode 11 and the second source electrode 21 are formed on the surface side of the semiconductor layer 40. Furthermore, the formation of the metal layer 30, which is present on the back side of the semiconductor layer 40, also has an impact. The warping direction (also called the bending direction) and warping amount (also called bending amount) of the semiconductor chip 2 are determined by the relationship between the linear expansion coefficient, Young's modulus, and other physical properties of the semiconductor layer 40, the first source electrode 11, the second source electrode 21, and the metal layer 30 and their respective thicknesses.

[0117] In the case where semiconductor chip 2 does not have metal layer 30 (in the case of Figure 5 In the variation 1 of this embodiment 1 shown, the warpage of the semiconductor chip 2 is determined solely by the relationship between the semiconductor layer 40 and the first source electrode 11 and the second source electrode 21. Since the coefficient of linear expansion is generally larger in the case of metals, the warpage occurring at high temperatures is convex in the +Z direction. The amount of warpage is determined by the relative thicknesses of the semiconductor layer 40 and the first source electrode 11 and the second source electrode 21; the thinner the semiconductor layer 40 and the thicker the first source electrode 11 and the second source electrode 21, the greater the warpage.

[0118] When the semiconductor chip 2 has a metal layer 30, the warpage is mainly determined by the relationship between the metal layer 30 and the first source electrode 11 and the second source electrode 21. Furthermore, since the coefficients of linear expansion of the metals constituting the first source electrode 11 and the second source electrode 21 and the metal constituting the metal layer 30 are mostly close, the direction and amount of warpage are mostly determined by their respective thicknesses. When it is required to control the warpage to convex in the +Z direction, the thickness of the metal layer 30 is preferably thinner than the thicknesses of the first source electrode 11 and the second source electrode 21. This is because, at high temperatures, a thicker film increases the stress caused by expansion, resulting in a curved shape convex in those directions.

[0119] As described above, in order to improve the bonding tightness between the metal layer 30 and the thick-film metal plate, the semiconductor chip 2 is required to warp in a direction away from the thick-film metal plate (+Z direction). However, if the warping is too large, pores are likely to occur in the conductive adhesive 41 near the center of the semiconductor layer 40 in planar view. According to the inventors' research, if the warping of the semiconductor chip 2 at 170°C is adjusted to 20 μm or less, the occurrence of pores can be stably prevented. Therefore, the warping of the semiconductor chip 2 at 170°C is preferably 2 μm or more and 20 μm or less.

[0120] To make the semiconductor chip 2 a curved shape convex away from the thick-film metal plate (+Z direction), the thickness of the semiconductor layer 40 in the semiconductor chip 2 is preferably 100 μm or less, more preferably 75 μm or less. This is because it is difficult to fabricate films with extremely thick first source electrode 11 and second source electrode 21, and a thinner semiconductor layer 40 makes it easier for the semiconductor chip 2 to bend. Furthermore, the decrease in strength of the semiconductor chip 2 caused by the thinning of the semiconductor layer 40 can be compensated by bonding the thick-film metal plate, so the side effects caused by thinning the semiconductor layer 40 can be mitigated in this disclosure.

[0121] However, if the thickness of the semiconductor layer 40 is extremely thin, for example, less than 15 μm, cracks are easily generated in the semiconductor layer 40 (semiconductor substrate 32) during monolithization. Therefore, the thickness of the semiconductor layer 40 is preferably 15 μm or more and 100 μm or less, more preferably 15 μm or more and 75 μm or less.

[0122] The thicknesses of the first source electrode 11 and the second source electrode 21 are preferably, for example, 2 μm or more and 13 μm or less. When the semiconductor chip 2 does not have a metal layer 30, if the semiconductor layer 40 is thin, even if the thicknesses of the first source electrode 11 and the second source electrode 21 are 2 μm to 5 μm, the warpage at 170°C can be 2 μm or more. However, when the semiconductor layer 40 is thicker, it is preferable that the thicknesses of the first source electrode 11 and the second source electrode 21 also vary in the thicker direction, correspondingly to 10 μm to 13 μm.

[0123] If the film thickness structure is as described above, the warping direction of the semiconductor chip 2 at high temperature can be controlled to be the direction in which the semiconductor chip 2 bulges away from the thick film metal plate (+Z direction), thereby controlling the warping amount to be more than 2 [μm] and less than 20 [μm].

[0124] In addition, such as in Figure 1 As schematically illustrated, in the semiconductor device 1 of this embodiment 1, the conductive adhesive 41 often forms a roughly triangular chamfer, such that a portion of it is raised on the sidewall of the semiconductor chip 2. In the semiconductor device 1 of this embodiment 1, because the semiconductor chip 2 has a curved shape that convexes away from the thick-film metal plate, the chamfer of the conductive adhesive 41 is as follows: Figures 7A to 7C As shown, it reaches a position relatively close to the upper surface of the semiconductor layer 40.

[0125] like Figure 7C As shown, if the chamfer angle is defined with the upper surface of the thick-film metal plate as a reference, the minimum angle in the semiconductor device 1 of this embodiment is 20 degrees. Therefore, the conductive adhesive 41 may be exposed from the outer periphery of the semiconductor layer 40 by a maximum of (h+hp) / tan(20 degrees) mm in planar view. Here, in planar view, the total thickness of the metal layer 30 directly below the corner of the semiconductor layer 40 and the conductive adhesive 41 is set as hp mm. The corner of the semiconductor layer 40 is specified because it is the location where the conductive adhesive 41 is pushed in the most by the warping of the semiconductor chip 2. Furthermore, tan is the tangent function.

[0126] If the area of ​​the thick-film metal plate in planar observation is not sufficiently large compared to the area of ​​the semiconductor layer 40, it is possible that the exposed conductive adhesive 41 may not be contained within the thick-film metal plate. Therefore, the area of ​​the thick-film metal plate in planar observation must be prepared in consideration of the possibility that the exposed conductive adhesive 41 exists in proportion to the length of the bottom edge of the chamfer of the conductive adhesive 41.

[0127] If we define the minimum length of the closest distance from the outer periphery of the semiconductor layer 40 to the outer periphery of the thick-film metal plate in planar observation as L [mm], and the thickness of the semiconductor layer 40 as h [mm], and the total thickness of the metal layer 30 directly below the semiconductor layer 40 and the conductive adhesive 41 at the corner of the semiconductor layer 40 in planar observation as hp [mm], then since the minimum chamfer of the conductive adhesive 41 is 20 [deg], it is preferable that the relationship L ≥ (h + hp) / tan(20 [deg]) holds. If this relationship holds, then in planar observation, the exposed conductive adhesive 41 will not exceed the outer periphery of the thick-film metal plate along the entire circumference of the semiconductor layer 40.

[0128] Hereinafter, a modified example of the semiconductor device 1 of this embodiment 1 will be described.

[0129] exist Figure 8A The diagram shows a cross-sectional view of a modified example 2 of the semiconductor device 1 according to Embodiment 1. In the modified example 2, the support 42 has a curved shape that convexes toward the semiconductor chip 2. The curved shape of the support 42 refers to, for example, the shape caused by warping of the support 42 during heat treatment when the metal layer 30 is bonded to the support 42 via a conductive adhesive 41. The amount of warping of the support 42 is the difference between the highest and lowest positions in the Z direction on the upper or lower surface of the support 42 when viewed in cross-section. When the warping of the support 42 is a convex warping toward the semiconductor chip 2, the highest position is the center of the support 42 in plan view, and the lowest position is the outer periphery of the support 42 in plan view, particularly at the corners of the outer periphery.

[0130] The direction and amount of warpage of the support 42 can be controlled by adjusting the amount of warpage of the semiconductor chip 2 occurring at 170°C, the thickness and / or material of the support 42, the thickness and / or material of the conductive adhesive 41, or the bonding conditions. The easiest way to adjust this is to make the support 42 thinner. If the support 42 is thinner, the amount of warpage of the support 42 at the point of completion of the semiconductor device 1 can be increased, but the rigidity of the semiconductor device 1 decreases. Therefore, as a reference, it is preferable to design the thickness of the support 42 such that the amount of warpage of the support 42 is smaller than the amount of warpage of the semiconductor chip 2.

[0131] like Figure 8AAs shown, in the semiconductor device 1, when the bending amount of the support 42 is smaller than that of the semiconductor chip 2 and the support 42 has a bent shape that convexes toward the semiconductor chip 2, the pushing force of the conductive adhesive 41 is reduced compared to the case where the support 42 is not bent. Therefore, the length of the conductive adhesive 41 exposed from the semiconductor layer 40 in planar view can be suppressed.

[0132] exist Figure 8B The diagram shows a cross-sectional view of a modified example 3 of the semiconductor device 1 according to Embodiment 1. In the modified example 3, the support 42 has a curved shape that convexes away from the semiconductor chip 2. Figure 8B As shown, in the semiconductor device 1, when the bending amount of the support 42 is smaller than the bending amount of the semiconductor chip 2, and the support 42 has a bent shape that convexes away from the semiconductor chip 2, compared with the case where the support 42 is not bent, it is possible to prevent the formation of pores between the semiconductor chip 2 and the conductive adhesive 41 near the center of the semiconductor layer 40 in planar view.

[0133] (Implementation Method 2)

[0134] Hereinafter, the semiconductor device 100 of Embodiment 2, which is derived from the semiconductor device 1 of Embodiment 1 by modifying a portion of its structure, will be described.

[0135] The semiconductor device 100 of Embodiment 2 is an example of a structure in which the thick film metal plate, i.e., the support 42, of Embodiment 1 is replaced with an insulating support 420, and a support metal layer 300 is formed on the surface side of the insulating support 420, i.e. the side that is bonded to the semiconductor chip 2.

[0136] Here, regarding the semiconductor device 100 of Embodiment 2, the same reference numerals are assigned to the same constituent elements as those of the semiconductor device 1 of Embodiment 1, and detailed descriptions are omitted, with the focus on the differences from the semiconductor device 1.

[0137] [1. Structure of a semiconductor device]

[0138] exist Figure 9 The diagram shows a cross-sectional view of the semiconductor device 100 according to Embodiment 2. The difference from the semiconductor device 1 of Embodiment 1 is that the support 42 is replaced with an insulating support 420, and a support metal layer 300 is formed on the surface side of the insulating support 420. Alternatively, the support metal layer 300 may cover the entire surface side of the insulating support 420 in the same manner as the insulating support 420. Furthermore, it may be as follows... Figure 9 As shown, only a portion of the surface side of the insulating support 420 is covered.

[0139] [2. Manufacturing method of semiconductor device]

[0140] exist Figure 10 This diagram simply illustrates a portion of the manufacturing process of the semiconductor device 100 in Embodiment 2. Steps 501 to 504 are the same as the manufacturing process of the semiconductor device 1 in Embodiment 1. Step 506 is the same as step 505 in Embodiment 1.

[0141] In this embodiment 2, the semiconductor chip 2 is bonded to the insulating support 420 in step 506. In step 506, a support metal layer 300 is formed on the surface side of the insulating support 420 beforehand, and a conductive adhesive 41 is applied to the upper surface of the support metal layer 300. The conductive adhesive 41 is, for example, silver paste, which is cured by heating to a high temperature of 170°C to bond the semiconductor chip 2 to the insulating support 420 or the support metal layer 300.

[0142] [3. Site Visit]

[0143] In the semiconductor device 100 of this embodiment, the rigidity is improved compared to the thick-film metal plate of Embodiment 1 because an insulating support 420 is used. A silicon substrate is a good example of a rigid material. When a silicon substrate is used as the insulating support 420, the same effect as when a thick-film metal plate is used in the semiconductor device 1 of Embodiment 1 can be achieved with a thinner profile.

[0144] On the other hand, in the semiconductor device 100 of this embodiment 2, since a support metal layer 300 is provided on the surface of the insulating support 420, a sufficiently low on-resistance can be achieved using it as a conduction path. In particular, the semiconductor device 100 of this embodiment 2 is practical when the thickness of the support metal layer 300 is greater than the thickness of the first source electrode 11 and the thickness of the second source electrode 21 in the semiconductor chip 2.

[0145] In the semiconductor device 1 of Embodiment 1, if the thickness of the metal layer 30 in the semiconductor chip 2 is greater than the thickness of the first source electrode 11 and the second source electrode 21, it is impossible for the warping occurring in the semiconductor chip 2 at 170°C to bulge away from the support 42. In contrast, in the semiconductor device 100 of Embodiment 2, as long as the thickness of the metal layer 30 in the semiconductor chip 2 is smaller than the thickness of the first source electrode 11 and the second source electrode 21, it is possible for the warping occurring in the semiconductor chip 2 at 170°C to bulge away from the support 42.

[0146] The support metal layer 300 preferably covers the entire area bonded to the back side of the semiconductor chip 2. Therefore, on the surface side of the insulating support 420, there is a support metal layer 300 formed in a region larger than the area of ​​the semiconductor layer 40 in planar view, and the thickness of the support metal layer 300 is preferably greater than the thickness of the first source electrode 11 and the thickness of the second source electrode 21.

[0147] (Implementation 3)

[0148] Hereinafter, we will describe the semiconductor device 200 of embodiment 3, which is a partial structural modification of the semiconductor device 1 of embodiment 1.

[0149] In the semiconductor device 200 of Embodiment 3, an example of the structure is as follows: the plate support 42, which is a thick film metal plate with uniform in-plane thickness in Embodiment 1, is changed to a processing support 430, which is a thick film metal plate with surface processing performed on the surface.

[0150] Here, regarding the semiconductor device 200 of Embodiment 3, the same components as those of the semiconductor device 1 of Embodiment 1 are considered to have been described and are given the same reference numerals, and their detailed descriptions are omitted. The description will focus on the differences from the semiconductor device 1.

[0151] [1. Structure of a semiconductor device]

[0152] exist Figure 11A The diagram shows a cross-sectional view of the semiconductor device 200 according to Embodiment 3. Figure 11B The diagram shows a plan view of the machining support 430 according to Embodiment 3. Figure 11C The diagram shows a plan view of a semiconductor device 200 after the semiconductor chip 2 has been mounted onto the processing support 430. The difference is that the support 42 in the semiconductor device 1 of Embodiment 1 is replaced by the processing support 430.

[0153] When only the processing support 430 is observed, the surface of the processing support 430 (the surface that is bonded to the semiconductor chip 2) is as follows: Figure 11B As shown, in planar view, it is divided into a first region that includes the center of the machining support 430 but does not include the outer periphery of the machining support 430, and a second region that surrounds the first region and constitutes the remaining region of the surface of the machining support 430. Figure 11A and Figure 11B In the diagram, the imaginary boundary lines of the first and second ranges are represented by dashed lines.

[0154] In the first range, the thickness of the machining support 430 is constant. However, in the second range, a portion of the surface of the machining support 430 is grooved, resulting in a portion where the thickness of the machining support 430 is thinner than in the first range. In this embodiment 3, an example is shown where the thickness of the machining support 430 in the second range is equal to that in the first range near its outer periphery. However, the thickness of the machining support 430 in the second range may also be constant, or it may be a shape that gradually thins compared to the thickness of the machining support 430 in the first range.

[0155] In the semiconductor device 200, the semiconductor chip 2 is bonded to the surface side of the processing support 430 via a conductive adhesive 41, such as... Figure 11A and Figure 11C As shown, in planar view, the outer periphery of the semiconductor layer 40 of the semiconductor chip 2 is included within the width of the groove formed in the second region of the processing support 430. Additionally, in Figure 11C The conductive adhesive 41, which should be visible from the semiconductor chip 2 in a planar view, is omitted from the illustration.

[0156] Therefore, in planar view, the area of ​​the first region on the surface of the support 430 of the semiconductor device 200 in this embodiment 3 is smaller than the area of ​​the semiconductor layer 40 of the semiconductor chip 2, and in planar view, the semiconductor layer 40 is bonded in a manner that completely covers the first region.

[0157] [2. Investigation]

[0158] By creating the structure described above, the length of the conductive adhesive 41 exposed in the horizontal direction from the semiconductor layer 40 can be suppressed when viewed in a planar manner. Since a groove-shaped process is performed in the second region of the processing support 430, the extruded conductive adhesive 41 flows into the groove. Because the extruded conductive adhesive 41 can be accumulated to a certain extent in the groove, by appropriately changing the width and depth of the groove, the horizontal exposure length and the height of elevation towards the side of the semiconductor chip 2 can be suppressed.

[0159] The semiconductor device of the present disclosure has been described above based on embodiments 1 to 3 and variations 1 to 3, but the present disclosure is not limited to these embodiments and variations. As long as it does not depart from the spirit of the present disclosure, various modifications to these embodiments that can be conceived by those skilled in the art, or forms constructed by combining the constituent elements of different embodiments and variations, may also be included within the scope of one or more technical solutions of the present disclosure.

[0160] Industrial applicability

[0161] Semiconductor devices incorporating the vertical MOS transistor of this application can be widely used as devices for controlling the conduction state of current paths.

[0162] Label Explanation

[0163] 1, 100, 200 semiconductor devices

[0164] 2 Semiconductor chips

[0165] 10 transistors (first vertical MOS transistor)

[0166] 11 First source electrode

[0167] Parts 12 and 13

[0168] 14. First source region

[0169] 15 First gate conductor

[0170] 16 First gate insulating film

[0171] 17 Gate Trench No. 1

[0172] 18th body region

[0173] 18a First Connecting Region

[0174] 19 First gate electrode

[0175] 20 transistors (second vertical MOS transistor)

[0176] 21 Second source electrode

[0177] Parts 22 and 23

[0178] 24 Second source region

[0179] 25 Second gate conductor

[0180] 26. Second gate insulating film

[0181] 27 Second gate trench

[0182] 28. Second body region

[0183] 28a Second Connection Region

[0184] 29 Second gate electrode

[0185] 30 metal layers

[0186] 32 Semiconductor Substrate

[0187] 33 Low-concentration impurity layer (drift layer)

[0188] 34 interlayer insulation

[0189] 35 Passivation layer

[0190] 40 semiconductor layers

[0191] 41 Conductive adhesives

[0192] 42 Support body

[0193] 300 Support Metal Layer

[0194] 420 Insulating Support

[0195] 430 Machining Support

[0196] 90 boundary line

[0197] 111 Source Pad 1

[0198] 119 Gate Pad 1

[0199] 121 Second source pad

[0200] 129 Gate Pad 2

[0201] Area A1, Section 1

[0202] Area A2, Zone 2

Claims

1. A semiconductor device, a chip-scale packaged semiconductor device capable of being mounted face-down, characterized in that, have: Semiconductor substrate; A low-concentration impurity layer is formed on the surface side of the aforementioned semiconductor substrate; The first vertical MOS transistor is formed in the first region of the semiconductor layer when the semiconductor substrate and the low concentration impurity layer are used together as the semiconductor layer. The second vertical MOS transistor is formed in the second region adjacent to the first region when viewed in planar view of the semiconductor layer described above. The first source electrode of the first vertical MOS transistor is formed on the surface side of the semiconductor layer. The second source electrode of the aforementioned second vertical MOS transistor is formed on the surface side of the aforementioned semiconductor layer; as well as A support is formed on the back side of the semiconductor substrate via a conductive adhesive; In the planar view described above, the support body has a larger area than the semiconductor layer and includes the semiconductor layer. The thickness of the aforementioned support is greater than the thickness of the aforementioned semiconductor layer; In a cross-sectional view of the semiconductor device, including the center of the semiconductor layer and the outer periphery of the semiconductor layer in the planar view, when observing the semiconductor chip in the semiconductor device other than the support and the conductive adhesive, the semiconductor chip has a curved shape that convexes away from the support. In the planar view described above, the semiconductor layer appears to be square. The thickness of the conductive adhesive located directly beneath the semiconductor layer at the outer periphery of the semiconductor layer in the planar view is less than the thickness of the conductive adhesive located directly beneath the semiconductor layer at the center of the semiconductor layer in the planar view.

2. The semiconductor device as claimed in claim 1, characterized in that, In the planar view described above, the semiconductor layer has an area of ​​6.2 or more, in mm². 2 ; Let the area of ​​the semiconductor layer described above be S, in mm. 2 Let the thickness of the aforementioned semiconductor layer be h, in mm, then The relationship h≤0.016×S-0.042 holds true.

3. The semiconductor device as claimed in claim 1, characterized in that, In the planar view described above, the semiconductor layer is 11.5 mm thick. 2 The following area; The relationship h≤0.014×S-0.074 holds true.

4. The semiconductor device as claimed in claim 1, characterized in that, In the planar view described above, the semiconductor layer appears to be square. On the back side of the aforementioned semiconductor substrate, a metal layer is provided that is in contact with the entire back side of the aforementioned semiconductor substrate; In the above planar observation, let the shortest length of the closest distance from the outer periphery of the semiconductor layer to the outer periphery of the support be L in mm. In the aforementioned planar view, at the corner of the semiconductor layer, let the total thickness of the metal layer directly below the semiconductor layer and the conductive adhesive be expressed as hp (in mm). The relationship L≥(h+hp) / tan(20deg) holds true.

5. The semiconductor device as claimed in claim 1, characterized in that, The aforementioned support is made of metal.

6. The semiconductor device as claimed in claim 1, characterized in that, On the back side of the aforementioned semiconductor substrate, a metal layer is provided that is in contact with the entire back side of the aforementioned semiconductor substrate; The thickness of the first source electrode and the thickness of the second source electrode are greater than the thickness of the metal layer.

7. The semiconductor device as claimed in claim 1, characterized in that, The aforementioned conductive adhesive is directly bonded to the entire back side of the aforementioned semiconductor substrate.

8. The semiconductor device as claimed in claim 1, characterized in that, On the surface side of the support, there is a support metal layer connected to an area that is larger than the semiconductor substrate in the planar view. The thickness of the aforementioned support metal layer is greater than the thickness of the aforementioned first source electrode and the thickness of the aforementioned second source electrode; The aforementioned support is made of insulating material.

9. The semiconductor device as claimed in claim 1, characterized in that, In the above planar view, the surface side of the support body has a first range and a second range, the first range includes the center of the support body but does not include the outer periphery of the support body, and the second range surrounds the first range; In the above cross-sectional view, the height of the first range is constant, and the second range includes a portion with a height lower than that of the first range. In the above planar view, the area of ​​the first region is smaller than the area of ​​the semiconductor substrate. In the planar view described above, the semiconductor substrate is arranged such that it completely covers the first region of the support.

10. The semiconductor device as claimed in claim 9, characterized in that, The second range also includes a portion whose height is the same as that of the first range.

11. The semiconductor device as claimed in claim 1, characterized in that, In the above cross-sectional view, the support body has a curved shape that convexes toward the semiconductor chip; The bending amount of the aforementioned support is smaller than that of the aforementioned semiconductor chip.

12. The semiconductor device as claimed in claim 1, characterized in that, In the above cross-sectional view, the support body has a curved shape that convexes away from the semiconductor chip. The bending amount of the aforementioned support is smaller than that of the aforementioned semiconductor chip.

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