A method for extracting parasitic capacitance of IGBT modules based on external inductor resonance

Abstract

The present invention discloses a method for extracting parasitic capacitance of an IGBT module based on external inductor resonance, comprising: using symmetrical ports for measurement, utilizing an improved calculation method to extract parasitic capacitance parameters, and verifying the accuracy of the method through experiments with multiple sets of external inductors. Compared to existing extraction methods, the present invention's method for extracting parasitic capacitance of an IGBT module uses symmetrical ports with similar impedances for measurement, resulting in a much smaller error than existing extraction methods. This method can significantly eliminate the influence of the nonlinear characteristics of junction capacitance, and the extraction results are unaffected by the value of the external inductor. This method can be used to accurately extract the parasitic capacitance of IGBT modules, especially high-power IGBT modules, with good precision.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronic simulation, and in particular relates to a method for extracting parasitic capacitance of an IGBT module based on external inductor resonance. Background Art

[0002] Insulated-Gate Bipolar Transistors (IGBTs) combine the advantages of power MOSFETs and bipolar transistors. They are widely used in power electronic devices and systems due to their high input impedance, high withstand voltage, high output current, low on-state resistance, and fast switching speed. With increasing switching frequencies and power densities, the rate of change of voltage across the IGBT module (dv / dt) and the rate of change of current through the IGBT module (di / dt) during switching become extremely large. Due to the presence of circuit parasitics, this generates significant electromagnetic interference (EMI).

[0003] The positive, negative, and midpoint terminals of a classic half-bridge IGBT module are connected through the direct bonding copper (DBC) and structural components, with the bottom portion secured to the copper layer of the backplane (BP). The parasitic common-mode capacitance formed between the DBC and BP through the substrate is a key factor in determining the common-mode EMI performance of power electronics. Common-mode EMI generated by motor drive inverters propagates through these parasitic common-mode capacitances to the heat sink and motor. Therefore, accurately extracting parasitic common-mode capacitance is crucial for modeling and evaluating EMI in power electronics.

[0004] There are many studies on the parasitic parameters in IGBT modules. For example, the literature [Q. Yang, L Wang, Z Qi et al., “Analysis and Optimization of High-Frequency Switching Oscillation Conducted CM Current Considering Parasitic Parameters Based on a Half-Bridge Power Module,” IEEE Trans. Power Electron., vol. 38, no. 10, pp. 12659–12674, Oct. 2023] uses finite element simulation to extract the parasitic inductance of the DBC inside the module and establishes an inductance distribution network; the literature [BT De Boi, ANLemmon, BW Nelson, CD New, and DMH Dudson, “Improved Methodology for Parasitic Characterization of High-Performance Power Modules,” IEEE Trans. Power Electron., vol. 35, no. 12, pp. 13400–13408, Dec. 2020] measures the impedance of the IGBT module to obtain its parasitic inductance and capacitance parameters. However, there are few literatures on the parasitic common-mode capacitance of IGBT modules. Only one literature [A. Cataliotti, D.Cara, G. Marsala, A. Pecoraro, A. Ragusa, and G. Tine, “High-Frequency Experimental Characterization and Modeling of Six Pack IGBTs Power Modules,” IEEE Trans. Ind. Electron., vol. 63, no. 11, pp. 6664–6673, Nov. 2016] proposes an original method for extracting parasitic common-mode capacitance based on external inductor resonance. This method extracts the value of parasitic common-mode capacitance by fitting the parasitic parameters measured from different terminals.

[0005] However, the original method uses asymmetric terminals for measurement, resulting in significantly different voltages applied to the junction capacitance when measuring at different terminals. Due to the nonlinear characteristics of the freewheeling diode (FWD) junction capacitance, the junction capacitance value also varies during measurement, leading to significant calculation errors. This ultimately leads to significant deviations in the parasitic common-mode capacitance values ​​extracted by the original method. Summary of the Invention

[0006] In view of the above, the present invention provides a method for extracting parasitic capacitance of an IGBT module based on external inductor resonance, which can greatly eliminate the influence of the nonlinear characteristics of the junction capacitance and accurately extract the parasitic capacitance value of the IGBT module.

[0007] A method for extracting parasitic capacitance of an IGBT module based on external inductor resonance. The IGBT module is composed of two connected IGBT tubes T1 and T2. The collector of T1 is the terminal P of the IGBT module. The emitter of T1 is connected to the collector of T2 as the terminal O of the IGBT module. The emitter of T2 is the terminal N of the IGBT module. The method for extracting parasitic capacitance of the IGBT module includes the following steps:

[0008] (1) Measure the total parasitic capacitance C between the IGBT module copper layer and the backplane copper layer T ;

[0009] (2) Connect a parallel resonant inductor between terminals P and O to achieve parallel resonance. Measure the port impedance Z between terminal P and the backplane copper layer. PB , measure the port impedance Z from terminal O and the backplane copper layer OB(PB) ;

[0010] (3) According to the port impedance Z at the resonant frequency PB and Z OB(PB) , calculate the parasitic common mode capacitance C formed by the copper layer of the connection terminal P on the backplane copper layer based on the measured value P ;

[0011] (4) Reconnect the resonant inductor and connect it in parallel at both ends of terminal N and terminal O. Measure the port impedance Z between terminal N and the backplane copper layer. NB , measure the port impedance Z from terminal O and the backplane copper layer OB(NB) ;

[0012] (5) According to the port impedance Z at the resonant frequency NB and Z OB(NB) , calculate the parasitic common mode capacitance C formed by the copper layer of the connection terminal N on the backplane copper layer based on the measured value N ;

[0013] (6) According to the total value of parasitic capacitance C T And the parasitic common mode capacitance C calculated above P and C N , calculate the parasitic common mode capacitance C formed by the copper layer of the connection terminal O on the backplane copper layer O .

[0014] Furthermore, in step (1), since the junction capacitance of the freewheeling diodes T1 and T2 is much larger than the parasitic common mode capacitance, the junction capacitance is regarded as a short circuit at high frequency. Therefore, any one terminal among the terminals P, O, and N of the IGBT module is selected, and the total parasitic capacitance C is measured between the terminal and the backplane copper layer. T , the measurement results are the same.

[0015] Furthermore, in step (2), a vector network analyzer is used to measure the port impedance Z at different frequencies from the terminal P and the backplane copper layer. PB , measure the port impedance Z at different frequencies from both ends of terminal O and the backplane copper layer OB(PB) , record the data and draw a graph; in step (4), a vector network analyzer is used to measure the port impedance Z at different frequencies from the terminal N and the backplane copper layer. NB , measure the port impedance Z at different frequencies from both ends of terminal O and the backplane copper layer OB(NB) , record the data and draw a graph.

[0016] Furthermore, in step (3), the parasitic common-mode capacitance C is calculated by the following expression: P :

[0017]

[0018] Where: Z PB (jω r1 ) represents the frequency jω r1 Lower port impedance Z PB The measured value, Z OB(PB) (jω r1 ) represents the frequency jω r1 Lower port impedance Z OB(PB) The measured value, ω r1 is the resonant angular frequency, j is the imaginary unit, and Re[] represents the real part.

[0019] Furthermore, in step (5), the parasitic common-mode capacitance C is calculated by the following expression: N :

[0020]

[0021] Where: Z NB (jω r2 ) represents the frequency jωr2 Lower port impedance Z NB The measured value, Z OB(NB) (jω r2 ) represents the frequency jω r2 Lower port impedance Z OB(NB) The measured value, ω r2 is the resonant angular frequency.

[0022] Furthermore, the resonant angular frequency ω r1 and ω r2 The expression is as follows:

[0023]

[0024] Where: C D1 and C D2 are the capacitance values ​​of the freewheeling diode junction capacitances of T1 and T2, L r is the inductance value of the resonant inductor.

[0025] Furthermore, in step (6), the parasitic common-mode capacitance C is calculated by the following expression: O :

[0026] C O =C T -C P -C N

[0027] Furthermore, the resonant inductance is changed, and five groups of inductance values ​​are selected from 3.3 to 100 uH as the resonant inductance value to repeat steps (2) to (6), thereby verifying the accuracy and stability of the IGBT module parasitic capacitance extraction method.

[0028] A computer device includes a memory and a processor, wherein the memory stores a computer program, and the processor is used to execute the computer program to implement the above-mentioned IGBT module parasitic capacitance extraction method.

[0029] A computer-readable storage medium stores a computer program, wherein the computer program is executed by a processor to implement the above-mentioned IGBT module parasitic capacitance extraction method.

[0030] Compared with the existing extraction methods, the IGBT module parasitic capacitance extraction method of the present invention selects symmetrical ports with close impedance for measurement, and the error is much smaller than the existing extraction method. It can greatly eliminate the influence of the nonlinear characteristics of the junction capacitance, and the extraction result is not affected by the external inductance value. It can be used to accurately extract the parasitic capacitance value of IGBT modules, especially high-power IGBT modules, with good precision. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1The figure is a flow chart of the method for extracting parasitic capacitance of an IGBT module based on external inductor resonance according to the present invention.

[0032] Figure 2 This is a schematic diagram of the topology of an actual half-bridge IGBT module power electronic system.

[0033] Figure 3 The parallel resonant inductor L is connected across terminals P and O. r Then measure the port impedance Z from terminals P and BP PB Schematic diagram of the test circuit.

[0034] Figure 4 The parallel resonant inductor L is connected across terminals P and O. r Then measure the port impedance Z from terminals O and BP OB(PB) Schematic diagram of the test circuit.

[0035] Figure 5 is the port impedance Z PB and Z OB(PB) Schematic diagram of the comparison spectrum.

[0036] Figure 6 is the resonant frequency f under five sets of external inductors rPB and f ROB(PB) Schematic diagram of the experimental results.

[0037] Figure 7 Schematic diagram of parasitic capacitance curves extracted using the method of the present invention under five groups of external inductors. DETAILED DESCRIPTION

[0038] In order to describe the present invention more specifically, the technical solution of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0039] like Figure 1 As shown, the method for extracting parasitic capacitance of an IGBT module based on external inductor resonance of the present invention includes the following specific steps:

[0040] (1) Measure the total parasitic capacitance C between DBC and BP from both ends of the IGBT module terminals P and BP. T , C T According to the positive electrode P, negative electrode N and midpoint O, it is divided into C P 、C N and C O .

[0041] The IGBT module used in this embodiment is 2MB600XNG170-50, and the power level of the module is 1700V and 600A. Figure 2As shown in the figure, a typical half-bridge IGBT module has terminals P, N and O. The DBCs connected to these three terminals are separated by the two IGBTs T1 and T2, and form three parasitic common-mode capacitors C in the BP copper layer. P 、C N and C O . FWD junction capacitance C D1 and C D2 Connect to the parasitic common mode capacitor C P 、C N and C O , due to the junction capacitance C D1 and C D2 Very large, reaching tens of nF, much larger than the parasitic common-mode capacitance of hundreds of pF. At high frequencies, C D1 and C D2 The value of can be regarded as a short circuit. Therefore, the measurement result from the terminal P, N or O to the BP copper layer is the same, that is, the sum of all three parasitic capacitances. The method of this embodiment measures the total parasitic capacitance C between DBC and BP from both ends of the terminals P and BP. T , while C T Satisfaction relationship: C T =C P +C O +C N .

[0042] (2) Connect a parallel resonant inductor L across terminals P and O r To achieve parallel resonance, measure the port impedance Z from terminals P and BP. PB , measure the port impedance Z from terminals O and BP OB(PB) .

[0043] Connect a parallel resonant inductor L across terminals P and O. r Then, measure the port impedance Z from terminals P and BP. PB The test circuit is as follows Figure 3 As shown, the port impedance Z is measured from terminals O and BP. OB(PB) The test circuit is as follows Figure 4 As shown. Definition C ON is the equivalent capacitance from terminals O and N to BP. Due to the high frequency junction capacitance C D1 and C D2 can be ignored, then C ON It can be expressed as:

[0044] C ON =C O +C N / / C D2 ≈C O +C N

[0045] Use a vector network analyzer to measure the port impedance Z at different frequencies from both ends of terminals P and BP PB And measure the port impedance Z at different frequencies from terminals O and BP OB(PB) , record the data and plot it as Figure 5 As shown, the real part of the impedance Re[Z PB ] and Re[Z OB(PB) ].

[0046] (3) Derivation of Z at resonant frequency PB , Z OB(PB) The parasitic capacitance C is calculated by combining the measured value with the expression of P The value of .

[0047] In this embodiment, considering the junction capacitance C D1 and parasitic capacitance C P 、C ON The value of the port impedance Z at terminals P and BP PB It can be derived as:

[0048]

[0049] When the external inductor L r and junction capacitance C D1 When resonance occurs between rPB The relationship should be satisfied:

[0050] s=jω rPB =j2πf rPB

[0051] s 2 L r C D1(PB) +1=0

[0052] Therefore, when resonance occurs, Z PB (jω rPB ) can be expressed as:

[0053]

[0054] Similarly, the port impedance Z at terminals O and BP is OB(PB) It can be expressed as:

[0055]

[0056] Comparing Equation (2) and Equation (3), we can find that the real part difference only exists in C ON and C P Since this test uses symmetrical ports with similar impedance for measurement, the value of D1 The voltage across the terminals remains essentially unchanged, which means that CD1(PB) =C D1(OB) , while ω rPB =ω rOB =ω r Therefore, according to equations (2) and (3), the parasitic capacitance C can be obtained P and the total value C T The relationship between them is as follows:

[0057]

[0058] Arranging the above formula, we can get the parasitic capacitance C P The values ​​are:

[0059]

[0060] (4) Reconnect the resonant inductor L r , the resonant inductor L r Connect in parallel across terminals N and O, and measure the port impedance Z from terminals N and BP. NB , measure the port impedance Z from terminals O and BP OB(NB) .

[0061] Definition C OP is the equivalent capacitance from terminals O and P to BP. Due to the high frequency junction capacitance C D1 and C D2 Can be ignored, similarly C OP It can be expressed as:

[0062] C OP =C O +C P / / C D1 ≈C O +C P

[0063] Use a vector network analyzer to measure the port impedance Z at different frequencies from both ends of terminals N and BP NB And measure the port impedance Z at different frequencies from terminals O and BP OB(NB) , we can get the real part of the impedance Re[Z NB ] and Re[Z OB(NB) ].

[0064] (5) Derivation of Z at resonant frequency NB , Z OB(NB) The parasitic capacitance C is calculated by combining the measured value with the expression of N The value of .

[0065] Z NB The expression is as follows:

[0066]

[0067] Z OB(NB) The expression is:

[0068]

[0069] Similarly, according to equations (6) and (7), the parasitic capacitance C can be obtained N and the total value C T The relationship between them is as follows:

[0070]

[0071] Arranging the above formula, we can get the parasitic capacitance C N The values ​​are:

[0072]

[0073] (6) According to the total value C T and the resulting C P 、C N Calculate the value of parasitic capacitance C O value.

[0074] According to C O =C T -C P -C N Get the parasitic capacitance C O Based on this, all parasitic capacitance values ​​are extracted.

[0075] (7) Change the external resonant inductor value and repeat the experiment to verify the accuracy of the proposed method

[0076] To further verify the accuracy of the method of the present invention, five groups of inductance values ​​from 3.3 to 100uH were selected as external resonant inductance values ​​and the experiment was repeated; Figure 6 Shows the resonant frequency f under five sets of external inductors rPB and f ROB(PB) The comparison results, Figure 7 The parasitic capacitance values ​​extracted using the method of the present invention under five groups of external inductors are shown.

[0077] The above description of the embodiments is intended to facilitate understanding and application of the present invention by those skilled in the art. It is apparent that those skilled in the art can readily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without requiring creative effort. Therefore, the present invention is not limited to the above embodiments. Any improvements or modifications made by those skilled in the art based on the disclosure of the present invention should fall within the scope of protection of the present invention.

Claims

1. A method for extracting parasitic capacitance of an IGBT module based on external inductor resonance, wherein the IGBT module is composed of two IGBT tubes T1 and T2 connected together, the collector of T1 is the terminal P of the IGBT module, the emitter of T1 is connected to the collector of T2 as the terminal O of the IGBT module, and the emitter of T2 is the terminal N of the IGBT module, characterized in that: The IGBT module parasitic capacitance extraction method comprises the following steps: (1) Measure the total parasitic capacitance C between the IGBT module copper layer and the backplane copper layer T ; (2) Connect a parallel resonant inductor between terminals P and O to achieve parallel resonance. Measure the port impedance Z between terminal P and the backplane copper layer. PB , measure the port impedance Z from terminal O and the backplane copper layer OB(PB) ; (3) According to the port impedance Z at the resonant frequency PB and Z OB(PB) , calculate the parasitic common mode capacitance C formed by the copper layer of the connection terminal P on the backplane copper layer based on the measured value P ; (4) Reconnect the resonant inductor and connect it in parallel at both ends of terminal N and terminal O. Measure the port impedance Z between terminal N and the backplane copper layer. NB , measure the port impedance Z from terminal O and the backplane copper layer OB(NB) ; (5) According to the port impedance Z at the resonant frequency NB and Z OB(NB) , calculate the parasitic common mode capacitance C formed by the copper layer of the connection terminal N on the backplane copper layer based on the measured value N ; (6) According to the total value of parasitic capacitance C T And the parasitic common mode capacitance C calculated above P and C N , calculate the parasitic common mode capacitance C formed by the copper layer of the connection terminal O on the backplane copper layer O .

2. The method for extracting parasitic capacitance of an IGBT module according to claim 1, wherein: In step (1), since the junction capacitance of the freewheeling diodes T1 and T2 is much larger than the parasitic common mode capacitance, the junction capacitance is regarded as a short circuit at high frequencies. Therefore, one terminal is selected from the terminals P, O, and N of the IGBT module, and the total parasitic capacitance C is measured between the terminal and the backplane copper layer. T , the measurement results are the same.

3. The method for extracting parasitic capacitance of an IGBT module according to claim 1, wherein: In step (2), a vector network analyzer is used to measure the port impedance Z at different frequencies from the terminal P and the backplane copper layer. PB , measure the port impedance Z at different frequencies from both ends of terminal O and the backplane copper layer OB(PB) , record the data and draw a graph; in step (4), a vector network analyzer is used to measure the port impedance Z at different frequencies from the terminal N and the backplane copper layer. NB , measure the port impedance Z at different frequencies from both ends of terminal O and the backplane copper layer OB(NB) , record the data and draw a graph.

4. The method for extracting parasitic capacitance of an IGBT module according to claim 1, wherein: In step (3), the parasitic common-mode capacitance C is calculated by the following expression: P : Where: Z PB (jω r1 ) represents the frequency jω r1 Lower port impedance Z PB The measured value, Z OB(PB) (jω r1 ) represents the frequency jω r1 Lower port impedance Z OB(PB) The measured value, ω r1 is the resonant angular frequency, j is the imaginary unit, and Re[] represents the real part.

5. The method for extracting parasitic capacitance of an IGBT module according to claim 4, wherein: In step (5), the parasitic common-mode capacitance C is calculated by the following expression: N : Where: Z NB (jω r2 ) represents the frequency jω r2 Lower port impedance Z NB The measured value, Z OB(NB) (jω r2 ) represents the frequency jω r2 Lower port impedance Z OB(NB) The measured value, ω r2 is the resonant angular frequency.

6. The method for extracting parasitic capacitance of an IGBT module according to claim 5, wherein: The resonant angular frequency ω r1 and ω r2 The expression is as follows: Where: C D1 and C D2 are the capacitance values ​​of the freewheeling diode junction capacitances of T1 and T2, L r is the inductance value of the resonant inductor.

7. The method for extracting parasitic capacitance of an IGBT module according to claim 1, wherein: In step (6), the parasitic common-mode capacitance C is calculated by the following expression: O : C O =C T -C P -C N 。 8. The method for extracting parasitic capacitance of an IGBT module according to claim 1, wherein: The resonant inductance is changed, and five groups of inductance values ​​are selected from 3.3 to 100 uH as the resonant inductance value, and steps (2) to (6) are repeated to verify the accuracy and stability of the IGBT module parasitic capacitance extraction method.

9. A computer device comprising a memory and a processor, characterized in that: The memory stores a computer program, and the processor is configured to execute the computer program to implement the method for extracting parasitic capacitance of an IGBT module according to any one of claims 1 to 8.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method for extracting parasitic capacitance of an IGBT module according to any one of claims 1 to 8 is implemented.

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