A true random number sequence generator, chip and electronic device

Abstract

The application provides a true random number sequence generator, a chip and an electronic device, and belongs to the technical field of electronics. The true random number sequence generator comprises: a processing circuit and M entropy source acquisition circuits; each entropy source acquisition circuit is configured to output a random sequence, and the random sequences output by different entropy source acquisition circuits are different, and M is an integer not less than 2; the processing circuit is connected with each entropy source acquisition circuit, and the processing circuit is configured to perform XOR processing on the random sequences output by each entropy source acquisition circuit to obtain a random number. The application can obtain a random number with better quality by performing XOR processing on the random sequences output by the M entropy source acquisition circuits.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of electronics, and particularly relates to a true random number sequence generator, a chip and an electronic device. BACKGROUND

[0002] A true random number sequence generator (TRNG) has a wide range of applications in the fields of statistics and information security. In chip or system design, it is often used for statistical, encryption, information entropy related algorithm implementation, etc. In these fields, not only is it required that the data sequence generated by the TRNG is uniformly distributed and independent of each other, but also it is required that it has unpredictability and can resist attacks on randomness. When evaluating the quality of the random numbers generated by the TRNG, the national standard for information security of China, GM / T 0005-2021 "Randomness Detection Specification", points out that: 1000000 random numbers of 1048576 bits (or 1000000 bits) generated by the TRNG should be detected 100 times (i.e. 1000 random numbers of 1048576 bits generated each time) to obtain the minimum passing rate of each detection and the number of detections with a passing rate of no less than 98.1% each time.

[0003] The structure of the most commonly used TRNG in a digital chip at present is as shown in the following formula Figure 1 This TRNG adopts the principle of clock acquisition circuit, two clock sources exist as entropy sources, a DFF (Data Flip Flop) is used as an acquisition circuit, and the outputs of the high-frequency clock source and the low-frequency clock source are respectively input to the D end and the CLK end of the DFF. The high-frequency clock source and the low-frequency clock source are both ring oscillators composed of digital standard cells (buffers and inverters), and the frequencies of the two clock sources generally satisfy a fixed ratio, which is usually (2M+1) / 2, where M is a positive integer.

[0004] Figure 1 The TRNG in the manner shown in the formula is prone to cause the DFF output sequence to have a periodic "101010" sequence and lack randomness, so that the randomness quality of the generated random numbers is limited. For example, for the aforementioned "Randomness Detection Specification", the passing rate of 1000 random outputs of 1048576 bits each time is often less than 95%, and the number of detections with a passing rate of no less than 98.1% each time is often less than 50 times. SUMMARY

[0005] In view of this, the purpose of the present application is to provide a true random number sequence generator, a chip and an electronic device to improve the output efficiency and quality of the random number sequence output by the true random number sequence generator.

[0006] Embodiments of the present application are implemented as follows:

[0007] In a first aspect, an embodiment of the present application provides a true random number sequence generator, comprising: a processing circuit and M entropy source acquisition circuits, each of the entropy source acquisition circuits is configured to output a random sequence, and the random sequences output by different entropy source acquisition circuits are different, M is an integer not less than 2; the processing circuit is connected with each of the entropy source acquisition circuits, and the processing circuit is configured to perform XOR processing on the random sequences output by each of the entropy source acquisition circuits to obtain a random number.

[0008] In the above embodiment, by designing M entropy source acquisition circuits and the random sequences output by different entropy source acquisition circuits are different, and then using the processing circuit to perform XOR processing on the random sequences output by each of the entropy source acquisition circuits, the output efficiency and quality of the random number sequence output by the true random number sequence generator can be further improved.

[0009] In combination with a possible implementation manner of the first aspect, the M entropy source acquisition circuits include N entropy source acquisition circuits of different types, N is an integer not less than 2.

[0010] In the above embodiment, by designing multiple entropy source acquisition circuits of different types, the randomness quality of the finally formed random sequence is better.

[0011] In combination with a possible implementation manner of the first aspect, the M entropy source acquisition circuits include: a first entropy source acquisition circuit, a second entropy source acquisition circuit, and a third entropy source acquisition circuit; the first entropy source acquisition circuit is configured to generate a random sequence based on a ring oscillator; the second entropy source acquisition circuit is configured to generate a random sequence based on a relaxation oscillator; and the third entropy source acquisition circuit is configured to generate a random sequence based on a chaotic circuit.

[0012] In the above embodiment, by designing three entropy source acquisition circuits of different principles, the randomness quality of the finally formed random sequence is better.

[0013] In combination with a possible implementation manner of the first aspect, the first entropy source acquisition circuit includes: a first entropy source, a second entropy source, and a first acquisition circuit; the first entropy source is configured to generate a first clock source based on two ring oscillators with different frequencies; the second entropy source is configured to generate a second clock source based on two ring oscillators with different frequencies, wherein the frequency of the first clock source is less than the frequency of the second clock source; and the first acquisition circuit is connected with the first entropy source and the second entropy source respectively, and the first acquisition circuit is configured to sample the second clock source based on the first clock source to output a random sequence.

[0014] In the above embodiment, the first entropy source acquisition circuit with the above structure is used, so that the clock source output by the first entropy source and the second entropy source is a clock source in which clock jitter of the clock signal generated by the other ring oscillator is superimposed on the basis of the clock signal generated by one of the ring oscillators, and then a random sequence is obtained on the basis of the clock source, so that the randomness of the obtained random sequence is better and the random sequence is less likely to have periodic characteristics.

[0015] In a possible implementation of the first aspect, the first entropy source includes: a first ring oscillator, a second ring oscillator, and a flip-flop; the first ring oscillator is configured to generate a first initial clock source; the second ring oscillator is configured to generate a second initial clock source, the frequency of the second initial clock source is greater than the frequency of the first initial clock source, and the frequency of the second initial clock source is not an integer ratio of the frequency of the first initial clock source; the flip-flop is connected to the first ring oscillator and the second ring oscillator respectively, and the flip-flop is configured to sample the first initial clock source based on the second initial clock source to obtain the first clock source.

[0016] In the above embodiment, because the frequency of the second initial clock source is greater than the frequency of the first initial clock source, and the frequency of the second initial clock source is not an integer ratio of the frequency of the first initial clock source, when the first initial clock source is sampled based on the second initial clock source, clock jitter of the second initial clock source is superimposed on the first initial clock source, thereby generating a random first clock source.

[0017] In a possible implementation of the first aspect, the first entropy source further includes: a selector, a first input end of the selector is connected to the first ring oscillator, a second input end of the selector is connected to an output end of the flip-flop, and an output end of the selector is connected to the first acquisition circuit.

[0018] In the above embodiment, the selector is provided, so that different signal outputs can be selected through the selector, and flexibility and applicability of the scheme can be improved.

[0019] In a possible implementation of the first aspect, the first entropy source acquisition circuit further includes: a third entropy source, a second acquisition circuit, and a first selection circuit; the third entropy source is configured to generate a third clock source based on two ring oscillators with different frequencies, and the frequency of the first clock source is less than the frequency of the third clock source; the second acquisition circuit is connected to the first entropy source and the third entropy source respectively, and the second acquisition circuit is configured to sample the third clock source based on the first clock source to output a random sequence; and the first selection circuit is connected to the first acquisition circuit and the second acquisition circuit respectively, and the first selection circuit is configured to select the random sequence output by the first acquisition circuit or the second acquisition circuit.

[0020] In the above embodiment, by further providing the third entropy source, the second acquisition circuit and the first selection circuit, the random sequence output by the first acquisition circuit or the second acquisition circuit can be selected by the first selection circuit, so as to improve the flexibility and applicability of the scheme.

[0021] With reference to a possible implementation of the first aspect, the first entropy source acquisition circuit further comprises a third acquisition circuit connected with the first entropy source, the second entropy source, the third entropy source and the first selection circuit respectively, and configured to sample the XOR result of the second clock source and the third clock source based on the first clock source and output a random sequence.

[0022] In the above embodiment, by further providing the third acquisition circuit, the XOR result of the second clock source and the third clock source is sampled, so that the random sequence output by the first acquisition circuit, the second acquisition circuit or the third acquisition circuit can be selected.

[0023] With reference to a possible implementation of the first aspect, the first selection circuit comprises a first selector, a second selector and a third selector, the first input end of the first selector is connected with the first acquisition circuit, and the second input end of the first selector is connected with the second acquisition circuit, the first input end of the second selector is configured to receive the XOR result of the random sequence output by the first acquisition circuit and the random sequence output by the second acquisition circuit, the second input end of the second selector is connected with the third acquisition circuit, and the first input end of the third selector is connected with the output end of the first selector, and the second input end of the third selector is connected with the output end of the second selector.

[0024] In the above embodiment, the selection circuit comprising the first selector, the second selector and the third selector can flexibly select the required output signal, and the configurability of the first entropy source acquisition circuit is improved to meet the requirements of various use scenarios.

[0025] In a possible implementation of the first aspect, the second entropy source acquisition circuit includes a relaxation oscillator configured to generate a third clock source, wherein the third clock source is related to a random sequence generated by the second entropy source acquisition circuit, and the relaxation oscillator includes a current mirror, a load capacitor, an inverting amplification circuit, and a feedback circuit; the current mirror is connected to a power supply and a digital ground respectively; the load capacitor is connected to the current mirror and the digital ground respectively; the inverting amplification circuit is connected to the power supply, the digital ground, and the load capacitor respectively; and the feedback circuit is connected to an output terminal of the inverting amplification circuit, the current mirror, and the digital ground respectively, and a target position of the feedback circuit is configured to output the third clock source; when the load capacitor is discharged through the current mirror, an end voltage of the load capacitor gradually decreases, and a first driving signal gradually increases after passing through the inverting amplification circuit; when the first driving signal is greater than a flip threshold of the feedback circuit, the feedback circuit controls the current mirror to charge the load capacitor; when the current mirror charges the load capacitor, the end voltage of the load capacitor gradually increases, and a second driving signal gradually decreases after passing through the inverting amplification circuit; and when the second driving signal is less than the flip threshold of the feedback circuit, the feedback circuit controls the current mirror to discharge the load capacitor.

[0026] In the above embodiment, the relaxation oscillator with the above structure can simplify the circuit structure and reduce the area and implementation difficulty of the circuit compared with other relaxation oscillators while achieving the inventive purpose.

[0027] In a possible implementation of the first aspect, the third entropy source acquisition circuit includes a first oscillator, a second oscillator, a chaotic circuit, and a full-swing circuit; the first oscillator is configured to generate a first signal; the second oscillator is configured to generate a second signal; the chaotic circuit is connected to the first oscillator and the second oscillator respectively, and is configured to generate a third signal with uncertain state based on the first signal and the second signal; and the full-swing circuit is connected to the chaotic circuit, and is configured to generate a fourth clock source with certain state based on the third signal, wherein the fourth clock source is related to a random sequence generated by the third entropy source acquisition circuit.

[0028] In the above embodiment, the chaotic circuit is used to generate a third signal with uncertain state (e.g., not a state-determined signal with only 1 or 0, but also an intermediate state between 0 and 1) based on the first signal and the second signal, to improve randomness, and then the full-swing circuit is used to generate a fourth clock source with a determined state (only a state-determined signal with 1 or 0) based on the third signal, so that the randomness of the final generated random sequence is better and the quality is higher. In combination with a possible implementation manner of the first aspect embodiment, the true random number sequence generator further includes a second selection circuit connected with the M entropy source acquisition circuits and the processing circuit respectively, and the second selection circuit is configured to select the number of the entropy source acquisition circuits accessing the processing circuit.

[0029] In the above embodiment, the second selection circuit is used to select the number of the entropy source acquisition circuits accessing the processing circuit, so that the M entropy source acquisition circuits can work independently or cooperatively, and better random number output effect can be obtained by combining different types of entropy source acquisition circuits.

[0030] In the second aspect, the embodiments of the present application further provide a chip including the true random number sequence generator provided in the above first aspect embodiment and / or any possible implementation manner in combination with the first aspect embodiment.

[0031] In the third aspect, the embodiments of the present application further provide an electronic device including the chip provided in the above second aspect embodiment.

[0032] Other features and advantages of the present application will be described in the following description and other parts of the specification. The purposes and other advantages of the present application can be achieved and obtained by the structures particularly pointed out in the written description and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor. Through the drawings shown, the above and other purposes, features and advantages of the present application will be clearer.

[0034] Figure 1 FIG. 1 is a structural schematic diagram of a true random number sequence generator in the related art.

[0035] Figure 2 FIG. 2 is a structural schematic diagram of a true random number sequence generator provided by an embodiment of the present application.

[0036] Figure 3A structural schematic diagram of the first entropy source acquisition circuit is shown.

[0037] Figure 3a A structural schematic diagram of the first entropy source acquisition circuit is shown.

[0038] Figure 3b A structural schematic diagram of the first entropy source acquisition circuit is shown.

[0039] Figure 4 A structural schematic diagram of the first entropy source acquisition circuit is shown.

[0040] Figure 4a A structural schematic diagram of the first entropy source acquisition circuit is shown.

[0041] Figure 5 A structural schematic diagram of the first entropy source acquisition circuit is shown.

[0042] Figure 5a A structural schematic diagram of the first entropy source acquisition circuit is shown.

[0043] Figure 5b A structural schematic diagram of the first entropy source acquisition circuit is shown.

[0044] Figure 6 A structural schematic diagram of the first entropy source acquisition circuit is shown.

[0045] Figure 6a A structural schematic diagram of the first entropy source acquisition circuit is shown.

[0046] Figure 6b A structural schematic diagram of the first entropy source acquisition circuit is shown.

[0047] Figure 7 A structural schematic diagram of the first entropy source acquisition circuit is shown.

[0048] Figure 7a A structural schematic diagram of the first entropy source acquisition circuit is shown.

[0049] Figure 8 A structural schematic diagram of the first entropy source acquisition circuit is shown. DETAILED DESCRIPTION

[0050] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. The following embodiments are provided as examples to more clearly illustrate the technical solutions of this application, and should not be used to limit the scope of protection of this application. Those skilled in the art will understand that, without conflict, the following embodiments and features can be combined with each other.

[0051] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0052] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0053] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical term "connection" can be a direct connection or an indirect connection through an intermediate medium.

[0054] Given Figure 1 The output sequence (random numbers) generated by the True Random Number Generator (TRNG) shown has limited random number quality, resulting in a low pass rate for randomness detection according to national cryptographic standards. Based on this, this application provides a configurable True Random Number Generator composed of multiple entropy sources to further improve the output efficiency and quality of random number sequences and enhance the flexibility of use.

[0055] The following is combined with Figure 2 The principle of the true random number sequence generator provided in this application embodiment is explained. The true random number sequence generator includes a processing circuit and M entropy source acquisition circuits, all of which are connected to the processing circuit. In one possible implementation, the M entropy source acquisition circuits may include N different types of entropy source acquisition circuits. It is understood that... Figure 2Only the case of N=3 is shown, N is not limited to 3, for example, N can also be 1, at this time, the M entropy source acquisition circuits are all the same type of entropy source acquisition circuit.

[0056] In a possible implementation, the M entropy source acquisition circuits include N types of entropy source acquisition circuits, each of which is configured to output a random sequence, wherein the random sequences output by each of the entropy source acquisition circuits are different, and M and N are integers not less than 2. The processing circuit is connected to each of the entropy source acquisition circuits, and the processing circuit is configured to perform XOR processing on the random sequences output by each of the entropy source acquisition circuits to obtain a random number. Through the combination of the M N types of entropy source acquisition circuits, a better random number output effect can be achieved.

[0057] The processing circuit can include an XOR hardware circuit for performing XOR processing on the random sequences output by each of the entropy source acquisition circuits. In a possible implementation, the processing circuit can include a programmable device, and the XOR logic can be implemented through firmware burned in the programmable device.

[0058] Each of the above-described entropy source acquisition circuits can be an analog circuit, a digital circuit, or a combination of an analog circuit and a digital circuit.

[0059] When M=N=2, the true random number sequence generator includes two types of entropy source acquisition circuits, and the number of each type of entropy source acquisition circuit is one. When M is greater than 2 and N=2, the true random number sequence generator includes two types of entropy source acquisition circuits, and the number of each type of entropy source acquisition circuit is one or more. Generally, M is greater than or equal to N, that is, the number of entropy source acquisition circuits is greater than or equal to the number of types of entropy source acquisition circuits, in other words, the number of at least one type of entropy source acquisition circuit is greater than one. When the number of a certain type of entropy source acquisition circuit is multiple, the multiple entropy source acquisition circuits, although based on the same principle to generate random sequences, generate different random sequences.

[0060] In a possible implementation, the above-described M entropy source acquisition circuits include a first entropy source acquisition circuit, a second entropy source acquisition circuit, and a third entropy source acquisition circuit. In some possible implementations, the true random number sequence generator includes eight entropy source acquisition circuits, which are composed of three types of entropy source acquisition circuits, for example, including two first entropy source acquisition circuits, four second entropy source acquisition circuits, and two third entropy source acquisition circuits, wherein the random sequences generated by the two first entropy source acquisition circuits are different, the random sequences generated by the four second entropy source acquisition circuits are different, and the random sequences generated by the two third entropy source acquisition circuits are different. The eight entropy source acquisition circuits can work independently or cooperatively, and through the combination of different types of entropy source acquisition circuits, a better random number output effect can be achieved.

[0061] The first entropy source acquisition circuit is configured to generate a random sequence based on a ring oscillator. The second entropy source acquisition circuit is configured to generate a random sequence based on a relaxation oscillator. The third entropy source acquisition circuit is configured to generate a random sequence based on a chaotic circuit. The embodiments of the present application combine the random sequences generated by the three different principles to output random numbers with better quality.

[0062] In one possible manner, the schematic diagram of the first entropy source acquisition circuit can be as shown in Figure 3 , and includes a first entropy source, a second entropy source, and a first acquisition circuit. The first acquisition circuit is connected with the first entropy source and the second entropy source respectively, and is configured to sample a second clock source generated by the second entropy source based on a first clock source generated by the first entropy source, and output a random sequence.

[0063] The first acquisition circuit can include a D flip-flop (Data Flip-Flop). In some possible embodiments, the first entropy source and the second entropy source correspond to a low-frequency clock source and a high-frequency clock source respectively, as shown in Figure 1 , at this time, the circuit diagram of the first entropy source acquisition circuit is equivalent to the circuit diagram shown in Figure 1 . In the circuit diagram shown in Figure 1 , the low-frequency clock source and the high-frequency clock source are relative. For example, for the high-frequency clock source, as long as the frequency of the high-frequency clock source is greater than or equal to the frequency of the low-frequency clock source multiplied by a specified multiple (such as 3.5), the high-frequency clock source is not necessarily greater than a certain frequency. For the low-frequency clock source, the frequency is usually not lower than MHz.

[0064] In some possible embodiments, the first entropy source is configured to generate the first clock source based on two ring oscillators with different frequencies. The second entropy source is configured to generate the second clock source based on two ring oscillators with different frequencies, and the frequency of the first clock source is less than the frequency of the second clock source. The present application generates the clock source based on two ring oscillators with different frequencies, so that the clock jitter can be superimposed, which is beneficial to improve the uncertainty of the random number.

[0065] In some possible embodiments, the first entropy source includes a first ring oscillator (indicated by ring 1A), a second ring oscillator (indicated by ring 2B), and a flip-flop (DFF1), as shown in Figure 3a . In the circuit diagram shown in Figure 3a , ring 1A in the first entropy source indicates the first ring oscillator in the first entropy source, ring 1B indicates the second ring oscillator in the first entropy source, ring 2A indicates the first ring oscillator in the second entropy source, and ring 2B indicates the second ring oscillator in the second entropy source. Figure 3a In the circuit diagram shown in , DDF4 is the flip-flop included in the first acquisition circuit.

[0066] A first ring oscillator is configured to generate a first initial clock source (may be referred to as clock signal A). A second ring oscillator is configured to generate a second initial clock source (may be referred to as clock signal B). The frequency f B of the second initial clock source is greater than the frequency f A of the first initial clock source, and is not an integer ratio of the frequency of the first initial clock source, for example, f B > 2f A , and f B and f A are not an integer ratio. In one possible implementation, the frequency of f B is about 4-5 times the frequency of f A , and the more irregular the ratio is, the better.

[0067] A flip-flop is connected to the first ring oscillator and the second ring oscillator, respectively. The flip-flop is configured to sample the first initial clock source based on the second initial clock source to obtain a first clock source. Since the frequency of the sampling clock of the flip-flop is higher than the frequency of the first initial clock source as data, the clock jitter of the second initial clock source can be superimposed into the first initial clock source. With a clock signal A having a frequency of f A as the D input of the flip-flop, and another non-identical clock B having a frequency of f B as the CLK input of the flip-flop, the maximum delay of the new clock after sampling compared to the edge of the clock signal A is 1 / f B , and the minimum delay is 0. If a clock having a frequency of f B is used, and the clock having a frequency of f A is sampled by the flip-flop, the jitter of the flip-flop output signal is about 1 / f B .

[0068] In some possible implementations, the first entropy source further includes a selector (denoted as X1). A first input of the selector is connected to the first ring oscillator, a second input of the selector is connected to the output of the flip-flop, and an output of the selector is connected to the first acquisition circuit. The schematic diagram is shown in Figure 3b . That is, the signal of the first input of the selector is the first initial clock source, and the signal of the second input of the selector is the first clock source. In this way, it can be determined by the selector whether the signal input to the D terminal of the first acquisition circuit is the first initial clock source or the first clock source. The selector can be controlled by CONF[0], for example, when CONF[0] = 1, the selector selects the first clock source as the output, and when CONF[0] = 0, the selector selects the first initial clock source as the output.

[0069] The structure of the second entropy source is similar to that of the first entropy source. For example, in some possible embodiments, the second entropy source comprises a first ring oscillator (denoted as ring oscillator 2A), a second ring oscillator (denoted as ring oscillator 2B), and a flip-flop (DFF2), the schematic diagram of which is shown in FIG. 2B. In yet some possible embodiments, the second entropy source further comprises a selector (denoted as X2), the schematic diagram of which is shown in FIG. 2C, and the specific principle can refer to the description of the first entropy source. Figure 3a Figure 3b

[0070] In one possible embodiment, the first entropy source acquisition circuit further comprises a third entropy source, a second acquisition circuit, and a first selection circuit, the schematic diagram of which is shown in FIG. 3A. Figure 4

[0071] The third entropy source is configured to generate a third clock source based on two ring oscillators with different frequencies, wherein the frequency of the first clock source is less than the frequency of the third clock source. The frequency of the first clock source, the frequency of the second clock source, and the frequency of the third clock source are different from each other.

[0072] The structure of the third entropy source is similar to that of the first entropy source and the second entropy source. For example, in some possible embodiments, the third entropy source comprises a first ring oscillator (denoted as ring oscillator 3A), a second ring oscillator (denoted as ring oscillator 3B), and a flip-flop (DFF3). In yet some possible embodiments, the third entropy source further comprises a selector (denoted as X3), and the specific principle can refer to the description of the first entropy source.

[0073] The second acquisition circuit is connected with the first entropy source and the third entropy source respectively, and the second acquisition circuit is configured to sample the third clock source based on the first clock source and output a random sequence. The structure of the second acquisition circuit can be similar to that of the first acquisition circuit, for example, can comprise a flip-flop (DFF5).

[0074] The first selection circuit is connected with the first acquisition circuit and the second acquisition circuit respectively, and the first selection circuit is configured to select the random sequence output by the first acquisition circuit or the second acquisition circuit.

[0075] In one embodiment, the first selection circuit can comprise a selector (denoted as X4), which can be a two-way selector, and the random sequence output by the first acquisition circuit or the second acquisition circuit is selected through the selector.

[0076] In yet another embodiment, the first selection circuit can comprise a first selector (denoted as X4) and a second selector (denoted as X5), the schematic diagram of which is shown in FIG. 3C, and the specific principle can refer to the description of the first entropy source. Figure 4a ​​​As shown. The first input terminal of the first selector is connected to the first acquisition circuit (DFF4), and the second input terminal of the first selector is connected to the second acquisition circuit (DFF5). The first input terminal of the second selector is used to receive the XOR result of the random sequence output by the first acquisition circuit and the random sequence output by the second acquisition circuit, and the second input terminal of the second selector is connected to the output terminal of the first selector.

[0077] In some possible implementations, the first entropy source acquisition circuit further includes a third acquisition circuit, which is connected to the first entropy source, the second entropy source, the third entropy source, and the first selection circuit, respectively, as shown in the schematic diagram below. Figure 5 As shown. The third acquisition circuit is configured to sample the XOR result of the second and third clock sources based on the first clock source and output a random sequence. The structure of the third acquisition circuit can be similar to that of the first acquisition circuit, for example, it can include flip-flops (such as DFF6).

[0078] exist Figure 5 In the illustrated implementation, the first selection circuit may include a selector (3-to-1), which selects the output random sequence from the first acquisition circuit, the second acquisition circuit, or the third acquisition circuit. Its schematic diagram is shown below. Figure 5a , Figure 5a X4 in the diagram represents the first selection circuit.

[0079] In another implementation, the first selection circuit can consist of a first selector (e.g., represented by X4), a second selector (e.g., represented by X5), and a third selector (e.g., represented by X6), as shown in the schematic diagram below. Figure 5b As shown. The first input terminal of the first selector is connected to the first acquisition circuit, and the second input terminal of the first selector is connected to the second acquisition circuit. The first input terminal of the second selector is used to receive the XOR result of the random sequence output by the first acquisition circuit and the random sequence output by the second acquisition circuit, and the second input terminal of the second selector is connected to the third acquisition circuit. The first input terminal of the third selector is connected to the output terminal of the first selector, and the second input terminal of the third selector is connected to the output terminal of the second selector.

[0080] by Figure 5b Taking the first entropy source acquisition circuit shown as an example, the first entropy source acquisition circuit can be configured using CONF[0]~CONF[4], so that its output random sequence is configurable, thereby obtaining a better random number output effect. In practical applications, the values ​​of CONF[0]~CONF[4] can be continuously switched in a certain way by software or algorithm to achieve the optimal random number output effect.

[0081] CONF[0]=0, the output of ring oscillator 1A is used as the output of the first entropy source; CONF[0]=1, the output of ring oscillator 1B is used for sampling the output of ring oscillator 1A, so that the output jitter of ring oscillator 1B is superimposed on the output of ring oscillator 1A as the output of the first entropy source.

[0082] CONF[1]=0, the output of ring oscillator 2A is used as the output of the second entropy source; CONF[1]=1, the output of ring oscillator 2B is used for sampling the output of ring oscillator 1A, so that the output jitter of ring oscillator 2B is superimposed on the output of ring oscillator 2A as the output of the second entropy source.

[0083] CONF[2]=0, the output of ring oscillator 3A is used as the output of the third entropy source; CONF[2]=1, the output of ring oscillator 3B is used for sampling the output of ring oscillator 3A, so that the output jitter of ring oscillator 3B is superimposed on the output of ring oscillator 3A as the output of the third entropy source.

[0084] CONF[4:3]=00, the output of the first entropy source acquisition circuit is the sampling result of DFF5; CONF[4:3]=01, the output of the first entropy source acquisition circuit is the sampling result of DFF4; CONF[4:3]=10, the output of the first entropy source acquisition circuit is the exclusive-OR result of the sampling result of DFF4 and the sampling result of DFF5; CONF[4:3]=11, the output of the first entropy source acquisition circuit is the sampling result of DFF6.

[0085] In combination with the above, it can be seen that the six ring oscillators can be connected to the circuit in different ways through different configurations, which can increase the clock jitter or improve the unpredictability of DFF sampling through exclusive-OR operation. By controlling CONF[4:0] and constantly switching in a certain way, the optimal random number output effect can be achieved.

[0086] The overall structure of the above-mentioned second entropy source acquisition circuit is similar to the structure shown in Figure 1 , for example, both of them contain two clock sources with different frequencies and acquisition circuits, and the difference lies in the different implementation principles of the clock sources. For example, the second entropy source acquisition circuit includes a relaxation oscillator for generating a third clock source, and the third clock source is related to the random sequence generated by the second entropy source acquisition circuit. The original low-frequency clock source in Figure 1 may be replaced by the relaxation oscillator, and the random sequence can be obtained by sampling the high-frequency clock source with the third clock source generated by the relaxation oscillator. Since the relaxation oscillator is an analog circuit, its clock jitter and PVT (Process, Voltage, and Temperature) variation in the circuit are larger, so the DFF can also exhibit more irregular sampling characteristics. In some possible implementations, the original high-frequency clock source in may also be replaced by the relaxation oscillator.Figure 1 The high frequency clock source in the prior art.

[0087] In some possible embodiments, the relaxation oscillator comprises a current mirror, a load capacitor, an inverting amplification circuit and a feedback circuit, the schematic diagram of which is shown in Figure 6 The current mirror is connected with the power supply and the digital ground respectively. The load capacitor is connected with the current mirror and the digital ground respectively. The inverting amplification circuit is connected with the power supply, the digital ground and the load capacitor respectively. The feedback circuit is connected with the output terminal of the inverting amplification circuit, the current mirror and the digital ground respectively, and the target position of the feedback circuit is used for outputting the third clock source.

[0088] Wherein, when the load capacitor is discharged by the current mirror, the terminal voltage of the load capacitor gradually decreases, and after passing through the inverting amplification circuit, a first driving signal gradually increasing is outputted, when the first driving signal increases to be greater than the flip threshold of the feedback circuit, the feedback circuit controls the current mirror to charge the load capacitor; when the current mirror charges the load capacitor, the terminal voltage of the load capacitor gradually increases, and after passing through the inverting amplification circuit, a second driving signal gradually decreasing is outputted, when the second driving signal decreases to be less than the flip threshold of the feedback circuit, the feedback circuit controls the current mirror to discharge the load capacitor; thus, the load capacitor repeatedly charges and discharges, and oscillation is formed.

[0089] In one embodiment, the current mirror comprises four transistors, which include two P-type transistors and two N-type transistors, wherein one P-type transistor and one N-type transistor are connected in series, two P-type transistors are connected in parallel, the two P-type transistors are connected at the gate and are driven by a bias voltage VBB, and the two N-type transistors are connected at the gate and are connected with the drain of the N-type transistor, the source of the N-type transistor is grounded, and the source of the P-type transistor is connected with the power supply. The drain of one of the N-type transistors is connected with the feedback circuit, and the drain of the other N-type transistor is connected with the load capacitor.

[0090] In one embodiment, the inverting amplification circuit can be a single-tube single-stage inverting amplifier, which comprises two transistors, including one P-type transistor and one N-type transistor, the P-type transistor and the N-type transistor are connected in series, the source of the P-type transistor is connected with the power supply, the source of the N-type transistor is grounded, the gate of the P-type transistor is driven by a bias voltage VBB, the gate of the N-type transistor is connected with the load capacitor, and the drain of the N-type transistor (the drain of the P-type transistor) is connected with the feedback circuit. In addition, the inverting amplification circuit can also be a double-tube double-stage inverting amplifier.

[0091] In one implementation, the feedback circuit includes multiple stages of inverters and feedback transistors in series, for example, including even stages of inverters and N-type transistors (or including odd stages of inverters and P-type transistors). The first stage of inverters is connected to the inverting amplifier circuit, and the output of the last stage of inverters is connected to the gate of the N-type transistor, the source of the N-type transistor is connected to ground, and the drain of the N-type transistor is connected to the current mirror, specifically, the drain of the current mirror N-type transistor. In some possible implementations, the feedback circuit can further include a buffer, for example, the buffer can be located between the inverters and the inverting amplifier circuit to enhance the driving capability of the circuit.

[0092] In one possible implementation, the main structure of the relaxation oscillator described above can be as shown in FIG. 1, Figure 6a Figure 6a The ellipsis in the feedback circuit in FIG. 1 can be a buffer. Figure 6a The M3 transistor and the M4 transistor in FIG. 1 respectively serve as active loads of the current mirror M1 transistor and the current mirror M2 transistor, and the M5 transistor and the M6 transistor form a single-transistor single-stage inverting amplifier. The advantage of using a single-transistor single-stage amplifier is that no additional reference voltage circuit needs to be designed, thereby simplifying the circuit structure. Generally, the output of the I4 or the I2 serves as the output signal of the entire relaxation oscillator. The C is a variable capacitor, which can be used to adjust the frequency of the relaxation oscillator, so that the frequency ratio of the high-frequency clock source and the low-frequency clock source is not easy to satisfy the integer ratio, and thus the output sequence is not easy to appear periodicity.

[0093] The bias voltage described above can be provided by a bias circuit. In addition, in order to facilitate the start and stop of the relaxation oscillator, the relaxation oscillator can further include an enable circuit, a start-up circuit, and a bias circuit. The start-up circuit, the enable circuit, and the bias circuit can all be start-up circuits, enable circuits, and bias circuits commonly used in related technologies.

[0094] In one possible implementation, the circuit structure of the relaxation oscillator can be as shown in FIG. 2. The start-up circuit includes Figure 6b Figure 6b The resistors R2 and R3, the MB transistor, and the MC transistor in FIG. 2 are responsible for starting up the entire circuit and establishing the static operating point of the current mirror. The bias circuit includes Figure 6b The resistor R1, the M transistor, and the MA transistor in FIG. 2 are responsible for providing a bias voltage VBB for the M3 transistor, the M4 transistor, and the M5 transistor. The enable circuit includes the M0 transistor, the M01 transistor, and the M02 transistor. The position of the M0 transistor is not limited to FIG. 2. Figure 6b ​​In the positions shown, transistors M0 and M02 are controlled by the enable signal EN, and transistor M01 is controlled by the inverted enable signal ENB. When EN = 0, transistor M0 is turned on, the gates of transistors M3 to M5 are short-circuited to VDD, all are in a high-impedance state, and the relaxation oscillator is turned off; when EN = 1, transistor M0 is turned off, and the gates of transistors M3 to M5 are biased by VBB. EN can be configured by registers or software. When EN is 0, transistor M02 pulls C high to VDD, and transistor M01 acts as an enable switch. It is understood that the structure of the relaxation oscillator is not limited to the above structure; in one implementation, a relaxation oscillator from related technologies can also be used instead.

[0095] When the oscillator starts working, i.e., EN=1, and the MS transistor is off (i.e., the gate of the MS transistor is low), the M2 transistor provides a discharge path for capacitor C. C discharges at a certain rate through the internal resistance of the M2 transistor. The voltage at the top of capacitor C decreases, and through the amplification effect of the M6 ​​transistor, a gradually increasing signal is formed at the drain of the M6 ​​transistor. When this signal increases to a level greater than the threshold of inverter I1, the output of inverter I1 flips from high level to low level, and then the output of I4 flips to high level, turning on the MS transistor.

[0096] After the MS transistor is turned on, the gate terminals of M1 and M2 are short-circuited to ground, and M2 is turned off, exhibiting a high-impedance state. M4 acts as a current source to charge capacitor C, and the potential at the top of C gradually increases. Through the amplification effect of M6, a gradually decreasing signal is formed at the drain terminal of M6. When this signal decreases to less than the threshold of inverter I1, the output of inverter I1 flips from low to high, and then the output of I4 flips to low, turning off the MS transistor. This cycle repeats continuously, resulting in relaxation oscillation.

[0097] The overall structure of the third entropy source acquisition circuit described above is similar to... Figure 1 The structures shown are similar, for example, both containing two clock sources with different frequencies and acquisition circuits. The difference lies in the implementation principle of the clock sources. For example, the third entropy source acquisition circuit includes an entropy source circuit that generates a fourth clock source based on a chaotic circuit. The fourth clock source is related to the random sequence generated by the three entropy source acquisition circuits. For example, the fourth clock source generated by this entropy source circuit can be used to sample a high-frequency clock source to obtain a random sequence. In some possible implementations, this entropy source circuit can also be used to replace... Figure 1 The original high-frequency clock source in the Central Plains.

[0098] In one possible implementation, the third entropy source acquisition circuit includes: a first oscillator, a second oscillator, a chaotic circuit, and a full-swing circuit, with the following structure: Figure 7 As shown. Both the first and second oscillators are connected to a chaotic circuit, which in turn is connected to a full-swing circuit. This can be achieved using... Figure 7 Replace the circuit shownFigure 1 The low frequency clock source in the prior art.

[0099] The first oscillator is configured to generate a first signal. The second oscillator is configured to generate a second signal. The chaotic circuit is connected with the first oscillator and the second oscillator respectively, and the chaotic circuit is configured to generate a third signal with uncertain state based on the first signal and the second signal (such as a signal with uncertain state of 1, 0, but also containing intermediate state between 0 and 1). The full swing circuit is connected with the chaotic circuit, and the full swing circuit is configured to generate a fourth clock source with certain state based on the third signal, that is, the fourth clock source only contains the determined state of 1 and 0.

[0100] In an embodiment, the frequency ratio of the first signal and the second signal is within 2, that is, the frequency ratio of the two is not more than 2, which can be that the frequency of the first signal is greater than the frequency of the second signal, or the frequency of the first signal is less than the frequency of the second signal.

[0101] The first oscillator and the second oscillator described above can be relaxation oscillators and the like, for example, in an embodiment, the first oscillator and the second oscillator can be the relaxation oscillators shown in Figure 6b The outputs of the two relaxation oscillators are connected together through the chaotic circuit to form competition and adventure, thereby generating the third signal with uncertain state, and then the full swing circuit is connected to generate the clock source signal with the determined signal of 1 and 0.

[0102] In an embodiment, the chaotic circuit can be implemented using an adjustable nonlinear resistance-capacitance network, and the schematic diagram is as shown in Figure 7a The full swing circuit can be implemented using the full swing circuit in the related art, which is not introduced here. The variable resistance and the variable capacitance can be the variable resistance and the variable capacitance in the related art, which is not introduced here. The first signal and the second signal will form competition and adventure at the nonlinear resistance-capacitance network, if the resistance of R11 and the capacitive reactance of C11 are greater than the resistance of R12 and the capacitive reactance of C12 respectively, then the third signal is closer to the second signal; if the resistance of R11 and the capacitive reactance of C11 are less than the resistance of R12 and the capacitive reactance of C12 respectively, then the third signal is closer to the first signal.

[0103] Each entropy source acquisition circuit described above can be directly connected with the processing circuit, and in a possible embodiment, the M entropy source acquisition circuits can also be connected with the processing circuit through the second selection circuit, and the number of the entropy source acquisition circuits connected with the processing circuit through the second selection circuit is selected, that is, in Figure 2The second selection circuit is added between the M entropy source acquisition circuits and the processing circuit in the circuit shown. The second selection circuit can include selectors, the number of which can be multiple, one entropy source acquisition circuit can be connected to the processing circuit through one selector, or multiple entropy source acquisition circuits can be connected to the processing circuit through the same selector. In a possible implementation, the number of selectors is N, and the same type of entropy source acquisition circuit can be connected to the processing circuit through one selector. The outputs of all the entropy source acquisition circuits are connected to the subsequent circuit through an exclusive OR operation, and these entropy source acquisition circuits can be flexibly turned on or turned off according to requirements, at least one is turned on, and at most M are turned on.

[0104] The true random number sequence generator shown in the present application is subjected to a standard test process, and the detection pass rate of the randomness of 1000 random numbers of 1048576 bits generated is more than 97%, and the test is continuously performed 100 times, and the average pass rate of 60% is more than 98.1%. However, the true random number sequence generator of a traditional structure (such as Figure 1 ), the detection pass rate of 100 times of detection is not less than 98.1% is often less than 50 times.

[0105] The present application also provides a chip, which includes the true random number sequence generator described above. The chip can be various chips that need to use random numbers, for example, can be an encryption chip, a communication chip, a processing chip, and the like. In one implementation, the chip can be a processor.

[0106] The chip provided in the embodiments of the present application has the same implementation principle and technical effects as the true random number sequence generator described above. For brevity, the part of the chip embodiments not mentioned can be referred to the corresponding content in the true random number sequence generator embodiments.

[0107] The present application also provides an electronic device, which includes the chip described above. In one implementation, the structural block diagram of the electronic device is as shown in Figure 8 The electronic device includes a transceiver, a memory, a communication bus, and a processor. The processor can be the chip including the true random number sequence generator described above.

[0108] The transceiver, the memory, the processor are electrically connected with each other directly or indirectly to realize the transmission or interaction of data. For example, these elements can be electrically connected with each other through one or more communication buses or signal lines. Among them, the transceiver is used for transceiving data. The memory is used for storing a computer program, wherein the computer program 100 includes at least one software function module which can be stored in the memory in the form of software or firmware (Firmware) or solidified in the operating system (Operating System, OS) of the electronic device. The processor is used for executing the software function module or the computer program stored in the memory.

[0109] Among them, the memory can be, but is not limited to, a random access memory (Random Access Memory, RAM), a read-only memory (Read Only Memory, ROM), a programmable read-only memory (Programmable Read-Only Memory, PROM), an erasable read-only memory (Erasable Programmable Read-Only Memory, EPROM), an electrically erasable read-only memory (Electric Erasable Programmable Read-Only Memory, EEPROM) and the like.

[0110] The processor can be an integrated circuit chip with a processing capability of signals. The above-mentioned processor can be a general processor including a central processing unit (Central Processing Unit, CPU), a network processor (Network Processor, NP), a microprocessor and the like; can also be a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. Or the processor can also be any conventional processor and the like.

[0111] The electronic device includes, but is not limited to, a mobile device, a computing device, a security device, a network and communication device, a vehicle, and the like. The mobile device includes, but is not limited to, a smartphone, a tablet, a wearable device. The computing device includes, but is not limited to, a personal computer, a server, a computing card, and the like. The security device includes, but is not limited to, a camera, a smart lock, an access control system, and the like. The network and communication device includes, but is not limited to, a router, a switch, a firewall, and the like. The vehicle includes, but is not limited to, various vehicles including an electronic control unit.

[0112] It should be noted that each of the embodiments in the present specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts of each embodiment can be mutually referred to.

[0113] In addition, each functional module in each of the embodiments of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0114] The above is merely specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A true random number sequence generator, characterized in that, include: There are M entropy source acquisition circuits, each of which is configured to output a random sequence, and the random sequences output by different entropy source acquisition circuits are different, where M is an integer not less than 2. A processing circuit, connected to each entropy source acquisition circuit, is configured to perform an XOR operation on the random sequence output by each entropy source acquisition circuit to obtain a random number. Among them, the M entropy source acquisition circuits include N types of entropy source acquisition circuits of different types, where N is an integer not less than 2 and M is greater than or equal to N, such that the number of at least one type of entropy source acquisition circuit is greater than 1. Each entropy source acquisition circuit consists of two clock sources and acquisition circuits with different frequencies. The output of one clock source is connected to the data input terminal of the acquisition circuit, and the other clock source is connected to the clock input terminal of the acquisition circuit. Different entropy source acquisition circuits have different clock sources.

2. The true random number sequence generator according to claim 1, characterized in that, The M entropy source acquisition circuits include: The first entropy source acquisition circuit is configured to generate random sequences based on a ring oscillator; The second entropy source acquisition circuit is configured to generate random sequences based on a relaxation oscillator. The third entropy source acquisition circuit is configured to generate random sequences based on chaotic circuits.

3. The true random number sequence generator according to claim 2, characterized in that, The first entropy source acquisition circuit includes: The first entropy source is configured to generate a first clock source based on two ring oscillators with different frequencies; The second entropy source is configured to generate a second clock source based on two ring oscillators with different frequencies, wherein the frequency of the first clock source is less than the frequency of the second clock source. A first acquisition circuit is connected to the first entropy source and the second entropy source respectively. The first acquisition circuit is configured to sample the second clock source based on the first clock source and output a random sequence.

4. The true random number sequence generator according to claim 3, characterized in that, The first entropy source includes: A first ring oscillator is configured to generate a first initial clock source; A second ring oscillator is configured to generate a second initial clock source, the frequency of which is greater than the frequency of the first initial clock source and is not an integer ratio to the frequency of the first initial clock source. A trigger is connected to the first ring oscillator and the second ring oscillator respectively. The trigger is configured to sample the first initial clock source based on the second initial clock source to obtain the first clock source.

5. The true random number sequence generator according to claim 4, characterized in that, The first entropy source also includes: The selector has a first input terminal connected to the first ring oscillator, a second input terminal connected to the output terminal of the trigger, and an output terminal connected to the first acquisition circuit.

6. The true random number sequence generator according to claim 3, characterized in that, The first entropy source acquisition circuit also includes: The third entropy source is configured to generate a third clock source based on two ring oscillators with different frequencies, wherein the frequency of the first clock source is less than the frequency of the third clock source. The second acquisition circuit is connected to the first entropy source and the third entropy source respectively. The second acquisition circuit is configured to sample the third clock source based on the first clock source and output a random sequence. A first selection circuit is connected to both the first acquisition circuit and the second acquisition circuit. The first selection circuit is configured to select and output a random sequence from either the first acquisition circuit or the second acquisition circuit.

7. The true random number sequence generator according to claim 6, characterized in that, The first entropy source acquisition circuit also includes: The third acquisition circuit is connected to the first entropy source, the second entropy source, the third entropy source and the first selection circuit respectively. The third acquisition circuit is configured to sample the XOR result of the second clock source and the third clock source based on the first clock source and output a random sequence.

8. The true random number sequence generator according to claim 7, characterized in that, The first selection circuit includes: A first selector, wherein the first input terminal of the first selector is connected to the first acquisition circuit, and the second input terminal of the first selector is connected to the second acquisition circuit; The second selector has a first input terminal for receiving the XOR result of the random sequence output by the first acquisition circuit and the random sequence output by the second acquisition circuit, and the second input terminal of the second selector is connected to the third acquisition circuit. A third selector, wherein the first input terminal of the third selector is connected to the output terminal of the first selector, and the second input terminal of the third selector is connected to the output terminal of the second selector.

9. The true random number sequence generator according to claim 2, characterized in that, The second entropy source acquisition circuit includes: a relaxation oscillator for generating a third clock source, wherein the third clock source is related to a random sequence generated by the second entropy source acquisition circuit, and the relaxation oscillator includes: A current mirror is connected to both the power supply and digital ground. The load capacitor is connected to the current mirror and digital ground, respectively. The inverting amplifier circuit is connected to the power supply, digital ground, and the load capacitor, respectively. The feedback circuit is connected to the output terminal of the inverting amplifier circuit, the current mirror, and the digital ground, respectively. The target position of the feedback circuit is used to output the third clock source. When the load capacitor discharges through the current mirror, the terminal voltage of the load capacitor gradually decreases. After passing through the inverting amplifier circuit, a first driving signal that gradually increases is output. When the first driving signal is greater than the switching threshold of the feedback circuit, the feedback circuit controls the current mirror to charge the load capacitor. When the current mirror charges the load capacitor, the terminal voltage of the load capacitor gradually increases. After passing through the inverting amplifier circuit, a gradually decreasing second drive signal is output. When the second drive signal is less than the switching threshold of the feedback circuit, the feedback circuit controls the current mirror to discharge the load capacitor.

10. The true random number sequence generator according to claim 2, characterized in that, The third entropy source acquisition circuit includes: The first oscillator is configured to generate the first signal; The second oscillator is configured to generate the second signal; A chaotic circuit is connected to the first oscillator and the second oscillator respectively. The chaotic circuit is configured to generate a third signal with an uncertain state based on the first signal and the second signal. A full-swing circuit is connected to the chaotic circuit. The full-swing circuit is configured as a fourth clock source determined based on the third signal generation state, wherein the fourth clock source is related to the random sequence generated by the three-entropy source acquisition circuit.

11. The true random number sequence generator according to any one of claims 1-10, characterized in that, The true random number sequence generator further includes a second selection circuit, which is connected to the M entropy source acquisition circuits and the processing circuit respectively. The second selection circuit is configured to select the number of entropy source acquisition circuits connected to the processing circuit.

12. A chip, characterized in that, Includes the true random number sequence generator as described in any one of claims 1-11.

13. An electronic device, characterized in that, include: The chip as described in claim 12.

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