Construction method of check matrix, storage medium, computer program product and related apparatus

Abstract

Embodiments of the present application provide a parity check matrix construction method, a storage medium, a computer program product and related devices. The parity check matrix construction method comprises: generating a base matrix, wherein the difference between the offsets of adjacent blocks in the same row of the base matrix is equal; selecting a plurality of effective blocks from each column of the base matrix by a progressive edge growth algorithm; setting the blocks other than the effective blocks in the base matrix as invalid blocks to obtain a parity check matrix for checking a low-density parity-check code. The present scheme can simplify the hardware structure for decoding the low-density parity-check code based on the parity check matrix and reduce the hardware shift overhead in the decoding process of the low-density parity-check code.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of computer technology, and in particular, to a parity check matrix construction method, a storage medium, a computer program product, and related devices. BACKGROUND

[0002] A solid state disk (SSD) includes a storage controller and a plurality of NAND flash memories. A host can read data from the NAND flash memories through the storage controller. When storing data into the SSD, the storage controller processes the data to be stored based on a generator matrix to obtain a low density parity check (LDPC) code, and stores the LDPC code into the NAND flash memories. When reading data from the SSD, the storage controller reads the corresponding LDPC code from the NAND flash memories, and decodes the LDPC code based on a parity check matrix to perform error checking and correction.

[0003] At present, the parity check matrix is randomly constructed based on a graph or an algebraic structure.

[0004] However, in the process of decoding the LDPC code based on the randomly constructed parity check matrix, the shift is unpredictable, resulting in a large hardware overhead. SUMMARY

[0005] Therefore, embodiments of the present application provide a parity check matrix construction method, a storage medium, a computer program product, and related devices to at least solve or alleviate the above problems.

[0006] According to a first aspect of embodiments of the present application, a parity check matrix construction method is provided, including: generating a base matrix, wherein a difference between offset amounts of adjacent blocks in a same row in the base matrix is equal; selecting a plurality of effective blocks from each column of the base matrix by using a progressive edge growth algorithm; and setting blocks other than the effective blocks in the base matrix as invalid blocks to obtain a parity check matrix used for checking a low density parity check code.

[0007] According to a second aspect of embodiments of the present application, a parity check matrix construction device is provided, including: a generating unit configured to generate a base matrix, wherein a difference between offset amounts of adjacent blocks in a same row in the base matrix is equal; a selecting unit configured to select a plurality of effective blocks from each column of the base matrix by using a progressive edge growth algorithm; and an invalidating unit configured to set blocks other than the effective blocks in the base matrix as invalid blocks to obtain a parity check matrix used for checking a low density parity check code.

[0008] According to a third aspect of the embodiments of the present application, a solid state disk is provided, comprising: a storage control chip and a solid state electronic storage chip; the storage control chip is configured to read data from the solid state electronic storage chip, and perform error checking and correction on the read data based on a check matrix constructed by the method of the first aspect.

[0009] According to a fourth aspect of the embodiments of the present application, an electronic device is provided, comprising: a processor, a memory, a communication interface and a communication bus, the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is configured to store at least one executable instruction, and the executable instruction causes the processor to perform operations corresponding to the method of the first aspect.

[0010] According to a fifth aspect of the embodiments of the present application, a computer storage medium is provided, and the computer storage medium stores a computer program, and the program is executed by a processor to implement the method of the first aspect.

[0011] According to a sixth aspect of the embodiments of the present application, a computer program product is provided, comprising computer instructions, and the computer instructions instruct a computing device to execute the method of the first aspect.

[0012] According to the construction scheme of the check matrix provided by the embodiments of the present application, the difference between the offsets of the adjacent blocks in the same row in the base matrix is equal, after selecting the effective blocks from each column of the base matrix by the progressive edge growth algorithm and setting the blocks other than the effective blocks in the base matrix as invalid blocks, the check matrix for checking the low-density parity-check code is obtained. Since the difference between the offsets of the blocks in the same row in the base matrix is equal, when switching the adjacent columns in the check matrix for processing when checking the low-density parity-check code based on the base matrix with the specific structure, the shift number of each row remains unchanged, which can simplify the hardware structure for decoding the low-density parity-check code based on the check matrix and reduce the hardware shift overhead in the decoding process of the low-density parity-check code. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments described in the embodiments of the present application, and other drawings can also be obtained by those skilled in the art based on these drawings.

[0014] Figure 1 is a schematic block diagram of a solid state disk according to an embodiment of the present application;

[0015] Figure 2 is a flowchart of a construction method of a check matrix according to an embodiment of the present application;

[0016] Figure 3 is a schematic diagram of a base matrix of an embodiment of the present application;

[0017] Figure 4 is a schematic diagram of a base matrix of an embodiment of the present application;

[0018] Figure 5 is a schematic diagram of a check matrix of an embodiment of the present application;

[0019] Figure 6 is a schematic diagram of an invalidation base matrix of an embodiment of the present application;

[0020] Figure 7 is a flow chart of an effective check node selection method of an embodiment of the present application;

[0021] Figure 8 is a schematic diagram of a construction device of a check matrix of an embodiment of the present application;

[0022] Figure 9 is a schematic diagram of a single-sub device of an embodiment of the present application. DETAILED DESCRIPTION

[0023] The present application is described in the following based on embodiments, but the present application is not limited to these embodiments only. In the following detailed description of the present application, some specific details are described in detail. The present application can be understood without these details by those skilled in the art. In order to avoid obscuring the essence of the present application, well-known methods, processes, procedures are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0024] First, some of the nouns or terms appearing in the description of the embodiments of the present application are explained as follows.

[0025] NAND type flash memory: NAND type flash memory (NAND flash memory) is also known as NAND flash, which is a non-volatile flash memory. NAND flash uses tunnel injection writing and tunnel release erasing, and address lines and data lines are multiplexed.

[0026] Solid state disk: Solid state disk (Solid State Disk or Solid State Drive, SSD) is also known as solid state drive, which is a hard disk made of solid state electronic storage chip array. The solid state disk in the embodiments of the present application refers to a solid state disk composed of NAND flash memory chips.

[0027] Storage control chip: the storage control chip is an SDD controller, also known as a master control chip or master control, which is one of the key components of a solid state disk, composed of an embedded processor executing code and several hardware acceleration modules.

[0028] Low-density parity-check code: Low-Density Parity-Check (LDPC) code is a kind of linear block code, which is widely used in channel coding field such as Wi-Fi, 5G, SSD, etc. due to its flexible construction method, low encoding and decoding complexity, and error correction characteristics approaching Shannon limit.

[0029] Check matrix: the check matrix of LDPC code is also called H matrix. The check matrix is a sparse matrix, that is, most elements are 0 and only a few elements are 1. Each row of the check matrix represents a check equation, and each column corresponds to a bit of the encoded code word. The design principle of LDPC code is to ensure that the check matrix has good cyclic characteristics, so that it can converge effectively during decoding.

[0030] Generator matrix: the generator matrix of LDPC is also called G matrix. The generator matrix is a matrix used to map information bits to code words. The generator matrix and the check matrix satisfy GH T = 0, and the information can be encoded into LDPC code through the generator matrix.

[0031] Progressive edge growth algorithm: the Progressive Edge Growth (PEG) algorithm is a classical random construction method. Its core idea is to use a greedy algorithm to select the check node that satisfies the maximum cycle length, that is, the check node with the smallest degree, to connect it to the variable node when adding a variable node. In this way, the edges between variable nodes and check nodes are added continuously. In the process of constructing the check matrix, the density evolution algorithm is used to obtain the degree distribution suitable for itself, and LDPC codes with different code lengths and code rates are constructed.

[0032] Application environment of the present application

[0033] Embodiments of the present application provide a construction scheme for the check matrix of an LDPC code. The entire scheme is relatively general and can be used in various hardware devices including solid state disks, such as data centers, servers, personal computers, Internet of Things (IoT) devices, embedded devices, etc. The check matrix construction scheme provided by the embodiments of the present application is independent of the hardware deployed by the computing device that executes the scheme.

[0034] Solid state disk

[0035] Figure 1A schematic block diagram of a solid state disk 100 is shown. The solid state disk (SSD) is also called solid state drive, which is made of solid state electronic storage chip array. According to the difference of storage medium, the solid state disk can be divided into flash-based solid state disk and dynamic random access memory (DRAM)-based solid state disk. The solid state disk 100 in the embodiment of the present application can be a NAND flash-based solid state disk or a DRAM-based solid state disk.

[0036] The solid state disk has many advantages over the traditional mechanical hard disk, such as stronger security for storing data. For example, there is no need to worry about damaging the stored data when the solid state disk is shaken during use, and sudden power failure during use will not cause data loss in the solid state disk. Based on this, the solid state disk is widely used in various complex working environments, such as high-availability servers, and the solid state disk is also an ideal storage device for personal users.

[0037] As shown in Figure 1 , the solid state disk 100 includes a storage control chip 10 and a plurality of solid state electronic storage chips 20. As an example, as shown in Figure 1 , the solid state disk 100 includes 3 solid state electronic storage chips 20, but it should be understood that the number of solid state electronic storage chips 20 should not be limited to this. The solid state electronic storage chip 20 can be a NAND flash memory, and the data of the NAND flash memory is stored in the form of bits in a memory cell. A memory cell can store one bit, and a plurality of memory cells constitute a bit line, and the bit line is the bit width of the NAND flash memory. A plurality of bit lines can form a flash page, and a plurality of flash pages form a flash block. The NAND flash memory reads and writes data in units of flash pages, and erases data in units of flash blocks.

[0038] In addition to including the solid state electronic storage chip 20 for storing data, the solid state disk 100 can also include a storage control chip 10 for controlling the read and write operations of the solid state disk. When storing data in the solid state electronic storage chip 20, the storage control chip 10 encodes the data to be stored by generating a matrix to obtain an LDPC code, and then stores the LDPC code in the solid state electronic storage chip 20. When reading data from the solid state electronic storage chip 20, the storage control chip 10 reads the LDPC code from the solid state electronic storage chip 20, and decodes the LDPC code by using a check matrix. The decoding process can check and correct errors of the LDPC code, and the corresponding valid data is obtained after decoding.

[0039] One or more application programs 201 are deployed on the host 200, as an example, such as Figure 1 As shown, application program 1, application program 2 and application program 3 are deployed on the host 200, but it should be understood that the number of application programs 201 should not be limited thereto.

[0040] The application programs 201 can send a write instruction or a read instruction to the storage control chip 10, the write instruction carrying address information of a storage unit for storing data, and the read instruction carrying address information of a storage unit storing data to be read. After receiving the write instruction, the storage control chip 10 writes the LDPC code obtained by encoding into the corresponding one or more storage units according to the address information carried by the write instruction, and sends indication information indicating that the data storage is successful to the application program 201. After receiving the read instruction, the storage control chip 10 reads the LDPC code from the corresponding one or more storage units according to the address information carried by the read instruction, obtains the data required by the application program 201 after decoding the LDPC code, and sends the data obtained by decoding to the corresponding application program 201.

[0041] The host 200 can be a personal computer (PC) or a server, etc. having read and write operation functions, and the type of the host 200 is not limited in the present application. The solid state disk 100 can be connected with the host 200 through a peripheral component interconnect express (PCIE) interface, and the host 200 and the storage control chip 10 transmit data through the PCIE interface.

[0042] After the storage control chip 10 reads the LDPC code from the solid state electronic storage chip 20, the LDPC code is decoded based on the check matrix, and error checking and correction are performed on the LDPC code in the decoding process, so that the required valid data is obtained. The check matrix can be constructed by the storage control chip 10, or generated by a central processing unit (CPU), a graphics processing unit (GPU) or other processors with corresponding capabilities, and the generated check matrix is sent to the storage control chip 10. The check matrix can be stored in a double data rate synchronous dynamic random access memory (DDR) of the solid state disk 10, and the storage control chip 10 reads the check matrix from the DDR of the solid state disk 10 when decoding the LDPC code.

[0043] The check matrix can be obtained by invalidating part of the blocks of the base matrix. In order to reduce the hardware overhead when the storage control chip 10 decodes the LDPC code according to the check matrix, the base matrix can have a special format, such as the difference between adjacent blocks in the same row of the base matrix being the same. When decoding the LDPC code by using the check matrix generated based on the base matrix having the special format, the shift for the adjacent blocks in the same row of the check matrix in the decoding process is the same, so that the check matrix is more friendly to hardware, and the hardware overhead in the decoding process of the LDPC code is reduced.

[0044] The embodiment of the present application mainly focuses on the construction process of the check matrix, which will be described in detail in the following.

[0045] Construction method of check matrix

[0046] Figure 2 is a flowchart of a construction method of a check matrix according to an embodiment of the present application. As shown in Figure 2 , the construction method of the check matrix comprises the following steps:

[0047] Step 201, generating a base matrix.

[0048] The base matrix is used to construct the check matrix, and the check matrix can be obtained by selecting part of the valid blocks in the base matrix, that is, invalidating part of the blocks in the base matrix. The base matrix comprises sparse cyclic matrices, and the offset of a block is the cyclic shift number of the block relative to the unit matrix, so the base matrix can be represented by the offsets of the blocks relative to the unit matrix.

[0049] In an example, the base matrix can be represented as a base matrix BG and a promotion value Z as follows:

[0050]

[0051] Each element in the base matrix BG represents a block in the base matrix, Z=3, element 0 represents a 3x3 unit matrix, element 1 represents a cyclic shift matrix obtained by cyclically shifting the unit matrix by 1 bit, and element 2 represents a cyclic shift matrix obtained by cyclically shifting the unit matrix by 2 bits. The base matrix H base as shown in Figure 3 .

[0052] Referring to Figure 3 , element 0 in the base matrix BG represents the unit matrix base in the base matrix H Element 1 in the base matrix BG represents the cyclic shift matrix base in the base matrix H Element 2 in the base matrix BG represents the cyclic shift matrix baseCyclic shift matrix in the base matrix

[0053] The base matrix can be randomly generated or generated based on algebraic structure, and the number of short loops (6-element loop, 8-element loop, 10-element loop) in the base matrix is small.

[0054] The difference between the offsets of adjacent blocks in the same row in the base matrix is equal, that is, the offsets of blocks in the same row in the base matrix form an arithmetic sequence. The check matrix constructed based on the base matrix with such a structure can simplify the hardware structure for decoding the LDPC code based on the check matrix and reduce the hardware shift overhead.

[0055] Figure 4 A schematic diagram of the base matrix of one embodiment of the present application is shown. As shown in Figure 4 The base matrix BG is a 10x20 matrix, and each element in the base matrix BG represents a 128x128 unit matrix or a cyclic shift matrix. The element 0 in the base matrix BG represents a 128x128 unit matrix, and the element X (X is greater than or equal to 0 and less than 128) in the base matrix BG represents a 128x128 cyclic shift matrix obtained by cyclically shifting a 128x128 unit matrix by X positions. It should be understood that the base matrix BG shown in Figure 4 The base matrix BG represents a base matrix H base which is a 1280x2560 matrix.

[0056] Referring to Figure 4 , the difference between the offsets of adjacent blocks in the first row of the base matrix H base is equal to 0, the difference between the offsets of adjacent blocks in the second row of the base matrix H base is equal to 126, the difference between the offsets of adjacent blocks in the third row of the base matrix H base is equal to 1, the difference between the offsets of adjacent blocks in the fourth row of the base matrix H base is equal to 125, the difference between the offsets of adjacent blocks in the fifth row of the base matrix H base is equal to 4, the difference between the offsets of adjacent blocks in the sixth row of the base matrix H base is equal to 1, the difference between the offsets of adjacent blocks in the seventh row of the base matrix H base is equal to 124, the difference between the offsets of adjacent blocks in the eighth row of the base matrix H base is equal to 4, the difference between the offsets of adjacent blocks in the ninth row of the base matrix H base is equal to 2, and the difference between the offsets of adjacent blocks in the tenth row of the base matrix H base is equal to 3.

[0057] It should be noted that the base matrix H baseThe difference between the offsets of the adjacent blocks in the same row is the result of the addition operation in the finite field GF(128), thus 127+125=125, 127+124=123, and 8+125=5.

[0058] In one example, when generating the base matrix, the blocks in the first column of the base matrix can be randomly generated based on the identity matrix, and the difference between the offsets of the adjacent blocks in each row of the base matrix can be randomly determined. Then, according to the first block in each row of the base matrix and the difference between the offsets of the adjacent blocks in the row, the other blocks in the row of the base matrix can be determined, and thus all the blocks in the base matrix can be determined.

[0059] It should be noted that the difference between the offsets of the adjacent blocks in different rows of the base matrix can be the same or different, which is not limited in the embodiments of the present application.

[0060] In step 202, a plurality of effective blocks are selected from each column of the base matrix by using the progressive edge growth (PEG) algorithm.

[0061] After the base matrix is generated, the PEG algorithm can be used to select a plurality of effective blocks from each column of the base matrix. The effective blocks selected from the base matrix will be used as the effective blocks of the check matrix, and the blocks in the base matrix that are not selected as the effective blocks will be used as the ineffective blocks of the check matrix. It should be noted that the effective block refers to a non-full zero matrix, and the ineffective block refers to a full zero matrix.

[0062] It should be noted that in the subsequent embodiments, unless otherwise specified, the column of the base matrix refers to the block column, that is, the column composed of the blocks in the base matrix.

[0063] A column weight target value is set for each block column of the base matrix. The column weight is used to indicate the number of effective blocks included in the corresponding block column, and the column weight target value corresponding to a block column refers to the number of effective blocks required by the block column. When selecting the effective blocks from the base matrix, the same or different column weight target values can be set for different block columns. For example, the column weight target value of each block column in the base matrix can be set as 4, or the column weight target value of the odd block column in the base matrix can be set as 4, and the column weight target value of the even block column in the base matrix can be set as 5.

[0064] When selecting the effective blocks from each block column of the base matrix by using the PEG algorithm, the effective blocks are selected from each block column one by one. When the number of the effective blocks selected from the current block column reaches the column weight target value of the current block column, the effective blocks are selected from the next block column one by one, until the number of the effective blocks selected from each block column reaches the corresponding column weight target value.

[0065] In step 203, the blocks in the base matrix except the effective blocks are set as ineffective blocks, and a check matrix used for checking the low-density parity-check code is obtained.

[0066] After determining the valid blocks from the basis matrix, all other blocks in the basis matrix are set as invalid blocks to obtain the parity check matrix. The parity check matrix includes valid blocks and invalid blocks; valid blocks are non-all-zero matrices, and invalid blocks are all-zero matrices. In one example, because the parity check matrix is ​​a sparse matrix, the number of valid blocks in the parity check matrix is ​​less than the number of invalid blocks.

[0067] When setting blocks other than valid blocks in a base matrix as invalid blocks, you can set all elements of the blocks in the base matrix other than valid blocks to 0, making the block an invalid block (an all-zero matrix).

[0068] In one example, the fundamental matrix represents the basis matrix. The basis matrix H is obtained through the PEG algorithm. base The first and second blocks of the first column are selected as valid blocks, the second and third blocks of the second column are selected as valid blocks, the first and third blocks of the third column are selected as valid blocks, and the first and third blocks of the fourth column are selected as valid blocks, thus making the base matrix H... base The third block in the first column is set to invalid, the first block in the second column is set to invalid, the second block in the third column is set to invalid, and the second block in the fourth column is set to invalid. This results in an invalidation base matrix. In the invalidated basis matrix BG′, the element -1 represents a matrix of all zeros.

[0069] The parity-check matrix H, represented by the aforementioned invalidation basis matrix BG′, is as follows: Figure 5 As shown. See also Figure 5 The matrix in the verification matrix H corresponding to the element -1 in the invalidation basis matrix BG′ is a matrix of all zeros. The matrix in the verification matrix H corresponding to the element 0 in the invalidation basis matrix BG′ is the identity matrix. The matrix in the verification matrix H corresponding to element 1 in the invalidation basis matrix BG′ is a cyclic shift matrix. The matrix in the verification matrix H corresponding to element 2 in the invalidation basis matrix BG′ is a cyclic shift matrix.

[0070] In another example, from the PEG algorithm Figure 4 After selecting valid blocks from each column of the base matrix shown, and setting the blocks not selected as valid blocks as invalid blocks, we obtain... Figure 6 The invalidated fundamental matrix BG′ is shown. Figure 4 and Figure 6As shown, the base matrix BG and the invalidation base matrix BG' have the same number of rows and the same number of columns, each element in the invalidation base matrix BG' represents a 128 x 128 unit matrix, a cyclic shift matrix, or a full zero matrix, the element 0 in the invalidation base matrix BG' represents a 128 x 128 unit matrix, the element X (X is greater than or equal to 0 and less than 128) in the invalidation base matrix BG' represents a 128 x 128 cyclic shift matrix obtained by cyclically shifting a 128 x 128 unit matrix by X positions, and the element -1 in the invalidation base matrix BG' represents a 128 x 128 full zero matrix.

[0071] Referring to Figure 4 and Figure 6 , the 3rd, 5th, 6th, and 8th blocks in the 1st column of the base matrix BG are selected as valid blocks, the 1st, 2nd, 7th, and 9th blocks in the 2nd column of the base matrix BG are selected as valid blocks, the 3rd, 5th, 7th, and 9th blocks in the 3rd column of the base matrix BG are selected as valid blocks, the 2nd, 4th, 6th, and 7th blocks in the 4th column of the base matrix BG are selected as valid blocks, the 3rd, 5th, 6th, and 8th blocks in the 5th column of the base matrix BG are selected as valid blocks, the 3rd, 5th, 7th, and 10th blocks in the 6th column of the base matrix BG are selected as valid blocks, the 1st, 5th, 6th, and 8th blocks in the 7th column of the base matrix BG are selected as valid blocks, the 5th, 7th, 8th, and 9th blocks in the 8th column of the base matrix BG are selected as valid blocks, the 3rd, 5th, 8th, and 10th blocks in the 9th column of the base matrix BG are selected as valid blocks, the 1st, 3rd, 4th, and 8th blocks in the 10th column of the base matrix BG are selected as valid blocks, the 1st, 2nd, 5th, and 9th blocks in the 11th column of the base matrix BG are selected as valid blocks, the 2nd, 3rd, 4th, and 5th blocks in the 12th column of the base matrix BG are selected as valid blocks, the 1st, 2nd, 6th, and 8th blocks in the 13th column of the base matrix BG are selected as valid blocks, the 2nd, 3rd, 7th, and 8th blocks in the 14th column of the base matrix BG are selected as valid blocks, the 2nd, 4th, 5th, and 8th blocks in the 15th column of the base matrix BG are selected as valid blocks, the 1st, 2nd, 3rd, and 8th blocks in the 16th column of the base matrix BG are selected as valid blocks, the 2nd, 4th, 7th, and 9th blocks in the 17th column of the base matrix BG are selected as valid blocks, the 4th, 6th, 7th, and 9th blocks in the 18th column of the base matrix BG are selected as valid blocks, the 5th, 6th, 8th, and 10th blocks in the 19th column of the base matrix BG are selected as valid blocks, and the 2nd, 4th, 6th, and 7th blocks in the 20th column of the base matrix BG are selected as valid blocks.

[0072] In the embodiments of the present application, the difference between the offsets of the adjacent blocks in the same row of the base matrix is equal, and after the effective blocks are selected from each column of the base matrix by the progressive edge growth algorithm and the blocks other than the effective blocks in the base matrix are set as invalid blocks, a check matrix used for checking the low-density parity-check code is obtained. Since the difference between the offsets of the blocks in the same row of the base matrix is equal, when the check matrix generated based on the base matrix with the specific structure is used for checking the LDPC code and the adjacent columns of the check matrix are switched for processing, the shift number of each row remains unchanged, which can simplify the hardware structure for decoding the LDPC code based on the check matrix and reduce the hardware shift overhead in the process of decoding the LDPC code.

[0073] In a possible implementation, when the effective blocks are selected from the base matrix by the PEG algorithm, the effective check nodes can be determined from a plurality of nodes according to the girth corresponding to the check nodes, the Approximate Cycle Extrinsic Message Degree (ACE), the Extrinsic Message Degree (EMD), the cycle number and the row degree, and then the blocks in the base matrix corresponding to the same number of rows and the same number of block columns of the effective check nodes are determined as the effective blocks.

[0074] The girth is used to indicate the number of edges included in a cycle, and the edge is used to connect a variable node and a check node.

[0075] The ACE is used to approximately evaluate the proportion of the information not included in any cycle (especially a cycle with a shorter length) in the messages received by a variable node from the check nodes in the iterative decoding process. The ACE attempts to quantify how much of the message is “new” information that is not repeated in the cycle during the propagation of the message in the graph.

[0076] The EMD is an index for measuring the quality of the information carried by the messages during the transmission between the internal nodes of the decoder in the iterative decoding process of the LDPC code. The EMD is defined as the proportion of the “new” information amount of the message after a plurality of iterations in the iterative decoding process relative to the original information amount. The “new” information herein refers to the information obtained through the interaction between the check nodes and the variable nodes in the decoding process.

[0077] The cycle number refers to the number of cycles that can be formed based on a check node if the check node is selected as an effective check node. When a check node is selected as an effective check node, at least one cycle can be formed based on the check node.

[0078] The row degree is used to indicate the number of effective blocks selected in the corresponding row of the base matrix.

[0079] When selecting valid blocks using the PEG algorithm, the PEG algorithm constructs a ring that includes variable nodes and check nodes. Variable nodes correspond to block columns in the basis matrix, and check nodes correspond to blocks in the basis matrix. In most cases, when different check nodes are selected as valid check nodes, at least some of the ring length, ACE, EMD, number of rings, and row weight of the formed ring will change. Therefore, based on the ring length, ACE, EMD, number of rings, and row weight of the ring formed when check nodes are selected as valid check nodes, valid check nodes can be selected from the check nodes corresponding to each block column in the basis matrix, and the block in the block column of the basis matrix corresponding to the valid check node is determined as a valid block.

[0080] In this embodiment, due to the specific structure of the base matrix, a more refined strategy is needed to select valid blocks from the base matrix to ensure the accuracy of the constructed parity check matrix in verifying the LDPC code. Valid blocks are selected from each column of the base matrix based on the ring length, ACE, EMD, number of rings, and row weight corresponding to the parity check node. Then, a parity check matrix is ​​constructed based on the selected valid blocks. This ensures that the constructed parity check matrix can reduce hardware shifting overhead while also ensuring the accuracy of the LDPC code verification through the parity check matrix.

[0081] In one possible implementation, when selecting valid check nodes from check nodes using the PEG algorithm based on ring length, ACE, EMD, number of rings, and row weight, the priority of ring length, ACE, EMD, number of rings, and row weight is from high to low. Then, valid check nodes are selected in order of priority from high to low based on ring length, ACE, EMD, number of rings, and row weight.

[0082] Figure 7 This is a flowchart of an effective verification node selection method according to an embodiment of this application. Figure 7 As shown, the effective verification node selection method includes the following steps:

[0083] Step 701: Perform a breadth-first expansion with the variable node corresponding to the i-th block column in the base matrix as the root node.

[0084] `i` is a positive integer less than or equal to the number of columns in the block of the base matrix. For example, if the base matrix comprises 10 rows × 20 blocks, then `i` is an integer in the interval [1, 20]. Valid check nodes are determined starting from the first block column of the base matrix. After determining the valid check node corresponding to the first block column, the valid check node corresponding to the second block column is determined, and so on, until the valid check node corresponding to the 20th block column is determined. It should be noted that the `i`th block column refers to the `i`th column of the base matrix when the elements are blocks; see [link to documentation]. Figure 3 Basis matrix H base It includes 3 block columns, and each block column includes 3 blocks.

[0085] Each block column of the base matrix corresponds to a variable node, and different block columns correspond to different variable nodes.

[0086] It should be noted that the manner of determining the effective check node corresponding to each block column in the base matrix is the same, and the embodiment only takes the determination of the effective check node corresponding to the i-th block column as an example for description.

[0087] In step 702, based on the girth and the score value determined by the ACE, the first check node is determined from the multiple check nodes corresponding to the i-th block column and which can be selected as the effective check node.

[0088] Each block in the base matrix corresponds to a check node, and different blocks correspond to different check nodes. When the effective check node corresponding to the i-th block column in the base matrix is determined, the effective check node is selected from the check nodes corresponding to the blocks in the i-th block column in the base matrix. The check node which is not selected as the effective check node can be selected as the effective check node. In one example, referring to Figure 4 , each block column of the base matrix includes 10 blocks, and after the check node corresponding to the block located at the first block row in the first block column in the base matrix is determined as the effective check node, when the effective check node corresponding to the first block column is determined again, the check node is selected from the check nodes corresponding to the remaining 9 blocks in the first block column.

[0089] It should be noted that, for the convenience of description, in the embodiments of the present application, the check nodes described subsequently, if not specifically stated, are the check nodes corresponding to the i-th block column and which can be selected as the effective check node. The effective check nodes described subsequently in the embodiments of the present application, if not specifically stated, are the effective check nodes corresponding to the i-th block column.

[0090] For each check node, the girth and the ACE of the loop formed if the check node is taken as the effective check node can be determined, and then the effective check node can be selected from the multiple check nodes according to the girth and the ACE corresponding to each check node. When each check node is taken as the effective check node, the check node can form at least one loop with the variable node, each loop has a corresponding girth and ACE, so each check node corresponds to at least one girth and at least one ACE.

[0091] In one example, the score value based on the girth and the ACE can be equal to the sum of the reciprocal of the girth and the ACE. After determining the girth and the ACE corresponding to the check nodes, the score value of the loop corresponding to the same loop can be calculated according to the girth and the ACE. After calculating the score value of the loop based on the girth and the ACE of the loop formed by each check node, the check node corresponding to the loop with the minimum score value is determined as the first check node. The first score value is calculated according to the girth and the ACE, and the check nodes are not screened based on the girth and the ACE respectively, which can improve the construction efficiency of the check matrix.

[0092] In another example, the score value includes a first score value and a second score value, the first score value is the girth, and the second score value is the ACE. When the first check node is determined according to the score value, the check node corresponding to the maximum first score value is screened from the plurality of check nodes first. If the number of the check nodes corresponding to the maximum first score value is 1, the check node corresponding to the maximum first score value is determined as the first check node. If the number of the check nodes corresponding to the maximum first score value is greater than 1, the check node corresponding to the minimum second score value is determined as the first check node from the plurality of check nodes corresponding to the maximum first score value.

[0093] Step 703, it is judged whether the number of the first check nodes is equal to 1. If yes, step 704 is executed, otherwise step 705 is executed.

[0094] After the first check node is determined, it is judged whether the number of the first check nodes is equal to 1. If the number of the first check nodes is equal to 1, the first check node can be determined as the effective check node, and step 704 is executed accordingly. If the number of the first check nodes is greater than 1, a step of screening the effective check node from the first check nodes is needed, and step 705 is executed accordingly.

[0095] Step 704, the first check node is determined as the effective check node corresponding to the i-th block column, and step 719 is executed.

[0096] Step 705, the EMD of the loop formed by each variable node corresponding to the i-th block column and each first check node is determined.

[0097] If the number of the first check nodes is multiple, the EMD of the loop formed by each variable node corresponding to the i-th block column and each first check node is determined respectively.

[0098] Each first check node can form at least one loop with the variable node corresponding to the i-th block column, and each loop has a corresponding EMD, so the EMD of each loop based on each first check node can be determined.

[0099] Step 706, determining the second check node corresponding to the minimum EMD from the plurality of first check nodes according to the EMD corresponding to the first check node.

[0100] Each first check node corresponds to a plurality of EMDs, the minimum EMD is determined from the EMDs corresponding to the first check nodes, and the first check node corresponding to the minimum EMD is determined as the second check node.

[0101] In one example, the number of first check nodes is 3, the first check node 1 corresponds to EMD1, EMD2 and EMD3, the first check node 2 corresponds to EMD1, EMD4 and EMD5, and the first check node 3 corresponds to EMD2 and EMD4. If EMD1 is the minimum among EMD1, EMD2, EMD3, EMD4 and EMD5, the first check node 1 is determined as the second check node. If EMD2 is the minimum among EMD1, EMD2, EMD3, EMD4 and EMD5, the first check node 1 and the first check node 3 are both determined as the second check node.

[0102] Step 707, determining whether the number of second check nodes is equal to 1, if yes, executing step 708, otherwise executing step 709.

[0103] After the second check node is determined, it is determined whether the number of second check nodes is equal to 1. If the number of second check nodes is equal to 1, the second check node can be determined as the effective check node, and step 708 is executed accordingly. If the number of second check nodes is greater than 1, the effective check node needs to be further screened from the second check nodes, and step 709 is executed accordingly.

[0104] In the embodiment of the present application, since the ACE is an approximation of the EMD, the EMD needs to be retrieved from the formed ring, while the ACE can be determined in the process of forming the ring, so the time consumption of obtaining the EMD is greater than that of the ACE. Therefore, when the number of first check nodes corresponding to the same ring length and ACE is multiple, the second check node is screened from the first check nodes based on the EMD, which can ensure the accuracy of the check matrix formed by the check matrix to check the LDPC code, and can ensure the efficiency of the check matrix construction.

[0105] Step 708, determining the second check node as the effective check node corresponding to the i-th block column, and executing step 718.

[0106] Step 709, determining the number of rings formed by the variable nodes corresponding to the i-th block column and each second check node.

[0107] Each second check node can form at least one loop with the variable nodes corresponding to the i-th block column, and the PEG algorithm can be used to determine how many loops each second check node can form with the variable nodes corresponding to the i-th block column, i.e., the number of loops formed by the second check node and the variable nodes corresponding to the i-th block column.

[0108] Step 710: determining a third check node corresponding to the minimum number of loops from the plurality of second check nodes.

[0109] Each second check node corresponds to a number of loops, i.e., the number of loops formed by the second check node and the variable nodes corresponding to the i-th block column, and the second check node corresponding to the minimum number of loops is determined as the third check node.

[0110] Step 711: determining whether the number of third check nodes is equal to 1, if yes, executing step 712, otherwise executing step 713.

[0111] After determining the third check nodes, it is determined whether the number of third check nodes is equal to 1. If the number of third check nodes is equal to 1, the third check node can be determined as an effective check node, and step 712 is executed accordingly. If the number of third check nodes is greater than 1, the effective check node needs to be further screened from the third check nodes, and step 713 is executed accordingly.

[0112] Step 712: determining the third check node as the effective check node corresponding to the i-th block column, and executing step 718.

[0113] Step 713: determining the row weight of the block row corresponding to the third check node in the base matrix.

[0114] The check node corresponds to a block in the base matrix, and the block row corresponding to the check node is the block row in the base matrix where the block corresponding to the check node is located, and the block column corresponding to the check node is the block column in the base matrix where the block corresponding to the check node is located.

[0115] When the number of third check nodes is multiple, the row weight of the block row corresponding to each third check node in the base matrix can be determined, and the row weight is used to indicate the number of blocks determined as effective blocks in the corresponding block row in the base matrix.

[0116] Step 714: determining a fourth check node corresponding to the minimum row weight from the plurality of third check nodes.

[0117] Each third check node corresponds to a row weight, i.e., the number of blocks determined as effective blocks in the block row corresponding to the third check node in the base matrix, and the third check node corresponding to the minimum row weight is determined as the fourth check node.

[0118] Step 715, judging whether the number of the fourth check nodes is equal to 1, if yes, executing step 716, otherwise executing step 718.

[0119] After the fourth check nodes are determined, it is judged whether the number of the fourth check nodes is equal to 1. If the number of the fourth check nodes is equal to 1, the fourth check node can be determined as the valid check node, and step 716 is executed accordingly. If the number of the fourth check nodes is greater than 1, the valid check node needs to be further screened from the fourth check nodes, and step 717 is executed accordingly.

[0120] Step 716, determining the fourth check node as the valid check node corresponding to the i-th block column, and executing step 718.

[0121] Step 717, randomly selecting one fourth check node from the plurality of fourth check nodes as the valid check node corresponding to the i-th block column, and executing step 718.

[0122] Step 718, judging whether the number of the valid check nodes corresponding to the i-th block column is equal to the number of the valid blocks required by the i-th block column of the base matrix, if yes, ending the current flow, otherwise executing step 701.

[0123] The valid block required by each block column of the base matrix is the column repetition target value in the foregoing embodiments. For example, if the number of the valid blocks required by the i-th block column of the base matrix is N, the column repetition target value of the i-th block column of the base matrix is N. The valid check nodes corresponding to the i-th block column are determined one by one. When the number of the valid check nodes corresponding to the i-th block column is less than the column repetition target value, one valid check node corresponding to the i-th block column can be determined by executing steps 701 to 718 once, until the number of the valid check nodes corresponding to the i-th block column is equal to the column repetition target value.

[0124] After the number of the valid check nodes corresponding to the i-th block column is determined to be equal to the column repetition target value of the i-th block column, the valid check nodes corresponding to the i+1-th block column are determined, until the number of the valid check nodes corresponding to the last block column in the base matrix is equal to the column repetition target value of the last block column in the base matrix.

[0125] In the embodiments of the present application, in the process of determining the effective check nodes by the PEG algorithm, the effective check nodes are filtered from the check nodes based on the cycle length, ACE, EMD, cycle number and row weight in turn. The effective check nodes are determined by the multiple indexes of cycle length, ACE, EMD, cycle number and row weight, which can make the constructed check matrix more refined, reduce the hardware shift overhead, and ensure the accuracy of checking the LDPC code by the check matrix. Since it takes longer time to obtain EMD than to obtain ACE, after the effective check nodes cannot be determined based on ACE, the effective check nodes are determined by EMD, and if the effective check nodes can be determined based on ACE, there is no need to obtain EMD, thereby reducing the number of times of obtaining EMD and ensuring the efficiency of constructing the check matrix.

[0126] In a possible implementation, after obtaining the check matrix, at least one type of elementary trapping set (ETS) of the check matrix can be determined.

[0127] The ETS is a key structure that causes the error floor phenomenon in the low LDPC code. The ETS generally refers to a subgraph composed of variable nodes and check nodes in the Tanner graph of the LDPC code, and the degrees of the check nodes in the subgraph are only 1 or 2. In the iterative decoding process, if the check nodes in the ETS cannot be satisfied (i.e., the degree is odd), the decoder can be trapped in a stable state of error, which leads to incorrect decoding.

[0128] The ETS includes multiple types, such as (8, 6) ETS, (10, 7) ETS, (11, 8) ETS, and the like. The (a, b) ETS refers to a subgraph formed by a number of variable nodes, in which all check nodes have a degree not greater than 2, and b check nodes have a degree of 1, and a and b are positive integers. The number of ETSs in the check matrix is negatively related to the decoding performance of the check matrix. There are corresponding number thresholds for different types of ETSs, and the number thresholds corresponding to different types of ETSs can be different.

[0129] After the ETS of the check matrix is determined, it can be judged whether the number of each type of ETS is greater than the corresponding number threshold, and if the number of at least one type of ETS is greater than the corresponding number threshold, the check matrix can be reconstructed according to the base matrix.

[0130] In one example, the check matrix is ​​determined to have (8,6)ETS, (10,7)ETS, and (11,8)ETS. The threshold for (8,6)ETS is threshold 1, the threshold for (10,7)ETS is threshold 2, and the threshold for (11,8)ETS is threshold 3. The check matrix is ​​reconstructed based on the base matrix when at least one of the following three conditions is detected:

[0131] (1)(8,6) The number of ETS is greater than the number threshold 1;

[0132] (2)(10,7) The number of ETS is greater than the number threshold 2;

[0133] (3)(11,8) The number of ETS is greater than the number threshold 3.

[0134] It should be noted that the basic trap set of the verification matrix can be obtained in various suitable ways, and the embodiments of this application do not limit the way of obtaining the basic trap set.

[0135] In this embodiment of the application, after constructing the parity check matrix, at least one type of basic trap set of the parity check matrix is ​​obtained. If the number of basic trap sets of a certain type is greater than the corresponding number threshold, the parity check matrix is ​​reconstructed based on the base matrix to ensure the error correction capability of the constructed parity check matrix.

[0136] Construction device of check matrix

[0137] Figure 8 A schematic diagram of a check matrix construction apparatus 800 according to an embodiment of this application is shown. Figure 8 As shown, the apparatus 800 for constructing the parity check matrix includes:

[0138] Generation unit 801 is used to generate a base matrix in which the offset difference between adjacent blocks in the same row is equal.

[0139] Selection unit 802 is used to select multiple valid blocks from each column of the base matrix using an asymptotic edge growth algorithm;

[0140] Invalid unit 803 is used to set blocks other than valid blocks in the base matrix as invalid blocks, so as to obtain a parity check matrix for verifying low-density parity check codes.

[0141] In the embodiment of the present application, the generating unit 801 generates a base matrix in which the difference between the offsets of adjacent blocks in the same row is equal, the selecting unit 802 selects valid blocks from each column of the base matrix by using the progressive edge growth algorithm, the invalidating unit 803 sets the blocks other than the valid blocks in the base matrix as invalid blocks, and thus a check matrix used for checking the low-density parity-check code is obtained. Since the difference between the offsets of the blocks in the same row in the base matrix is equal, when the check matrix generated based on the base matrix with the specific structure is used to check the LDPC code and the adjacent columns in the check matrix are switched for processing, the shift number of each row remains unchanged, which can simplify the hardware structure for decoding the LDPC code based on the check matrix and reduce the hardware shift overhead in the process of decoding the LDPC code.

[0142] It should be noted that the check matrix construction apparatus of the embodiment is used to implement the check matrix construction method in the foregoing method embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be described here.

[0143] Electronic device

[0144] Figure 9 is a schematic block diagram of an electronic device provided by an embodiment of the present application. Embodiments of the present application do not limit the specific implementation of the electronic device. As shown in Figure 9 the electronic device can include a processor 902, a communications interface 904, a memory 906, and a communications bus 908. Among them:

[0145] The processor 902, the communications interface 904, and the memory 906 complete mutual communication through the communications bus 908.

[0146] The communications interface 904 is configured to communicate with other electronic devices or servers.

[0147] The processor 902 is configured to execute the program 910, and specifically can execute the related steps in any of the foregoing check matrix construction method embodiments.

[0148] Specifically, the program 910 can include program code including computer operation instructions.

[0149] The processor 902 can be a CPU, or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement one or more embodiments of the present application. The one or more processors included in the smart device can be the same type of processor, such as one or more CPUs; or different types of processors, such as one or more CPUs and one or more ASICs.

[0150] RISC-V is an open-source instruction set architecture based on the principle of reduced instruction set (RISC), which can be applied to various aspects such as single-chip microcomputers and FPGA chips. Specifically, it can be applied in the fields of Internet of Things security, industrial control, mobile phones, personal computers, etc. Due to its consideration of small size, speed, and low power consumption in design, it is particularly suitable for modern computing devices such as warehouse-scale computers, high-end mobile phones, and small embedded systems. With the rise of artificial intelligence Internet of Things (AIoT), the RISC-V instruction set architecture has received more and more attention and support, and is expected to become the next generation of widely used CPU architecture.

[0151] The computer operation instructions in the embodiments of the present application can be computer operation instructions based on the RISC-V instruction set architecture, and correspondingly, the processor 902 can be designed based on the RISC-V instruction set. Specifically, the chip of the processor in the electronic device provided by the embodiments of the present application can be a chip designed based on the RISC-V instruction set, which can execute executable code based on the configured instructions, and thus implement the construction method of the check matrix in the above embodiments.

[0152] The memory 906 is used to store the program 910. The memory 906 can include a high-speed RAM memory, and can also include a non-volatile memory such as at least one disk memory.

[0153] The program 910 can be specifically used to make the processor 902 execute the construction method of the check matrix in any of the preceding embodiments.

[0154] The specific implementation of each step in the program 910 can refer to the corresponding description in the corresponding steps and units of any of the preceding construction methods of the check matrix embodiments, which will not be described here. Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the devices and modules described above can refer to the corresponding process description in the preceding method embodiments, which will not be described here.

[0155] By the electronic device of the embodiment of the present application, the difference between the offsets of the adjacent blocks in the same row in the base matrix is equal, and after the effective blocks are selected from each column of the base matrix by the progressive edge growth algorithm and the blocks other than the effective blocks in the base matrix are set as invalid blocks, a check matrix for checking the low-density parity-check code is obtained. Since the difference between the offsets of the blocks in the same row in the base matrix is equal, when the check matrix generated based on the base matrix with the specific structure is used to check the LDPC code, the shift number of each row remains unchanged when the adjacent columns in the check matrix are switched for processing, which can simplify the hardware structure for decoding the LDPC code based on the check matrix and reduce the hardware shift overhead in the process of decoding the LDPC code.

[0156] Computer storage medium

[0157] The present application also provides a computer-readable storage medium storing instructions for causing a machine to perform the method of constructing a check matrix as described herein. Specifically, a system or apparatus equipped with a storage medium on which a software program code for realizing the functions of any of the above embodiments is stored, and causing the computer (or CPU or MPU) of the system or apparatus to read and execute the program code stored in the storage medium can be provided.

[0158] In this case, the program code read from the storage medium itself can realize the functions of any of the above embodiments, and thus the program code and the storage medium storing the program code constitute a part of the present application.

[0159] The storage medium for providing the program code includes a floppy disk, a hard disk, a magneto-optical disk, an optical disk (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), a magnetic tape, a non-volatile memory card, and a ROM. Alternatively, the program code can be downloaded from a server computer via a communication network.

[0160] Computer program product

[0161] The embodiment of the present application also provides a computer program product comprising computer instructions instructing a computing device to perform any corresponding operation in the above method embodiments.

[0162] It should be noted that the information related to the user (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to sample data for training the model, data for analysis, stored data, displayed data, etc.) involved in the embodiments of the present application are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of the related data need to comply with the relevant laws, regulations and standards of the relevant countries and regions, and there are corresponding operation entrances for the user to choose authorization or refusal.

[0163] It should be noted that according to the needs of implementation, each component / step described in the embodiments of the present application can be split into more components / steps, or two or more components / steps or part of the operation of the components / steps can be combined into a new component / step to achieve the purpose of the embodiments of the present application.

[0164] The above method according to the embodiments of the present application can be implemented in hardware, firmware, or as software or computer code that can be stored in a recording medium such as a CD ROM, RAM, floppy disk, hard disk or magneto-optical disk, or downloaded through a network and originally stored in a remote recording medium or non-transitory machine readable medium and then stored in a local recording medium, so that the method described herein can be processed by such software on a recording medium using a general purpose computer, a special purpose processor or programmable or special purpose hardware (such as ASIC or FPGA). It can be understood that the computer, processor, microprocessor controller or programmable hardware includes a storage component (for example, RAM, ROM, flash memory, etc.) that can store or receive software or computer code, when the software or computer code is accessed and executed by the computer, processor or hardware, the method described herein is implemented. In addition, when the general purpose computer accesses the code for implementing the method shown herein, the execution of the code will convert the general purpose computer into a special purpose computer for executing the method shown herein.

[0165] It should be noted that the information related to the user (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to sample data for training the model, data for analysis, stored data, displayed data, etc.) involved in the embodiments of the present application are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of the related data need to comply with the relevant laws, regulations and standards of the relevant countries and regions, and there are corresponding operation entrances for the user to choose authorization or refusal.

[0166] Those skilled in the art can understand that the units and method steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software manner depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for a specific application, but such implementation should not be considered beyond the scope of the embodiments of the present application.

[0167] The above embodiments are only used to illustrate but not to limit the embodiments of the present application. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present application, and all equivalent technical solutions belong to the scope of the embodiments of the present application. The patent protection scope of the embodiments of the present application should be defined by the claims.

Claims

1. A method for constructing a check matrix, comprising: generating a base matrix, wherein a difference between offsets of adjacent blocks in a same row of the base matrix is equal; selecting, by a progressive edge growth algorithm, a plurality of active blocks from each column of the base matrix; setting blocks other than the active blocks in the base matrix as inactive blocks to obtain a check matrix for checking a low-density parity-check code; the selecting, by the progressive edge growth algorithm, the plurality of active blocks from each column of the base matrix, comprising: determining, by the progressive edge growth algorithm, active check nodes from a plurality of check nodes according to a cycle length, an approximate extrinsic information degree, an extrinsic information degree, a cycle number and a row weight corresponding to the check nodes; determining, as the active blocks, blocks in the base matrix corresponding to the active check nodes in a same row and a same column; the determining, by the progressive edge growth algorithm, the active check nodes from the plurality of check nodes according to the cycle length, the approximate extrinsic information degree, the extrinsic information degree, the cycle number and the row weight corresponding to the check nodes, comprising: performing a breadth-first expansion with a variable node corresponding to an i th block column in the base matrix as a root node, i being a positive integer less than or equal to a column number of blocks in the base matrix; determining, from a plurality of check nodes corresponding to the i th block column and selectable as the active check nodes, a first check node based on a score value determined according to the cycle length and the approximate extrinsic information degree; if a number of the first check nodes is 1, determining the first check node as the active check node corresponding to the i th block column; if the number of the first check nodes is greater than 1, determining an extrinsic information degree of each cycle formed by each of the first check nodes and a variable node corresponding to the i th block column; determining, from a plurality of the first check nodes, a second check node corresponding to a minimum extrinsic information degree according to the extrinsic information degree corresponding to the first check node; if a number of the second check nodes is 1, determining the second check node as the active check node corresponding to the i th block column.

2. The method of claim 1, wherein, the score value is equal to a sum of a reciprocal of the cycle length and the approximate extrinsic information degree. 3.The method of claim 1, further comprising: if the number of the second check nodes is greater than 1, determining a cycle number of a cycle formed by each of the second check nodes and a variable node corresponding to the i th block column; determining, from a plurality of the second check nodes, a third check node corresponding to a minimum cycle number; if a number of the third check nodes is 1, determining the third check node as the active check node corresponding to the i th block column. 4.The method of claim 3, further comprising: if the number of the third check nodes is greater than 1, determining a row weight of a block row corresponding to the third check node in the base matrix, the row weight being used to indicate a number of blocks determined as the active blocks in a corresponding block row in the base matrix; determining, from a plurality of the third check nodes, a fourth check node corresponding to a minimum row weight; if a number of the fourth check nodes is 1, determining the fourth check node as the active check node corresponding to the i th block column. If the number of the fourth check nodes is greater than 1, randomly select one of the fourth check nodes as an effective check node corresponding to the i-th block column.

5. The method of any one of claims 1-4, further comprising: After the effective check nodes corresponding to the i-th block column are determined, determine the effective check nodes corresponding to the (i+1)-th block column of the base matrix, where N is the number of effective blocks required by the i-th block column of the base matrix, and i+1 is less than or equal to the number of block columns of the base matrix.

6. The method of any one of claims 1-4, further comprising: After the check matrix is obtained, determine at least one type of basic trap set of the check matrix; If the number of any basic trap set is greater than the corresponding number threshold, reconstruct the check matrix based on the base matrix.

7. An apparatus for constructing a check matrix, comprising: a generating unit configured to generate a base matrix, wherein a difference between offsets of adjacent blocks in a same row of the base matrix is equal; a selecting unit configured to select a plurality of effective blocks from each column of the base matrix by using a progressive edge growth algorithm; an invalidating unit configured to set blocks of the base matrix other than the effective blocks as invalid blocks, and obtain a check matrix for checking a low-density parity-check code; the selecting a plurality of effective blocks from each column of the base matrix by using a progressive edge growth algorithm comprises: determining, by using the progressive edge growth algorithm, effective check nodes from a plurality of check nodes according to a cycle length, an approximate extrinsic information degree, an extrinsic information degree, a cycle number, and a row weight of the check nodes; determining, as the effective blocks, blocks of the base matrix corresponding to the same row number and the same column number of the effective check nodes; the determining, by using the progressive edge growth algorithm, effective check nodes from a plurality of check nodes according to a cycle length, an approximate extrinsic information degree, an extrinsic information degree, a cycle number, and a row weight of the check nodes comprises: performing a breadth-first expansion with a variable node corresponding to an i-th block column of the base matrix as a root node, where i is a positive integer less than or equal to a column number of blocks of the base matrix; determining, as first check nodes, a plurality of check nodes corresponding to the i-th block column and selectable as effective check nodes based on score values determined according to the cycle length and the approximate extrinsic information degree; if the number of the first check nodes is 1, determining the first check node as an effective check node corresponding to the i-th block column; if the number of the first check nodes is greater than 1, determining an extrinsic information degree of each cycle formed by each of the first check nodes and a variable node corresponding to the i-th block column; determining, as second check nodes, a plurality of the first check nodes corresponding to a minimum extrinsic information degree based on the extrinsic information degrees of the first check nodes; if the number of the second check nodes is 1, determining the second check node as an effective check node corresponding to the i-th block column.

8. A solid state drive, comprising: a memory control chip and a solid-state electronic memory chip; The storage control chip is configured to read data from the solid-state electronic storage chip and perform error checking and correction on the read data based on the check matrix constructed by the method of any one of claims 1-6.

9. An electronic device comprising: The processor, the memory, the communication interface and the communication bus are in communication with each other through the communication bus; The memory is configured to store at least one executable instruction, and the executable instruction causes the processor to perform operations corresponding to the method of any one of claims 1-6. 10.A computer storage medium having stored thereon a computer program, which, when executed by a processor, implements the method of any one of claims 1-6. 11.A computer program product comprising computer instructions that direct a computing device to perform the method of any one of claims 1-6.

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