Shared memory parallel access method and device and electronic equipment

Abstract

The invention provides a shared memory parallel access method and device and electronic device.The method comprises the steps that based on a preset write operation list, corresponding write operation items are determined for multiple write tasks through lock-free operation, and based on the write operation items, storage space is distributed for each write task in a shared memory pool, and writing the target data of each writing task into the storage space in parallel, taking the writing information of the target data of each writing task as the field information of the corresponding writing operation item, and updating the writing operation item to a reading operation list by adopting lockless operation to serve as the reading operation item, the read operation items are used for reading the data in the shared memory pool in parallel, the technical effect that the multiple write-in tasks and the multiple read tasks access the shared memory in parallel can be achieved through lock-free operation, and the requirements of high-concurrency and high-real-time-performance scenes are met.

Description

Technical Field

[0001] The present disclosure relates to the technical field of shared memory, and in particular to a method, device and electronic device for parallel access to a shared memory. Background Art

[0002] Shared memory is a mechanism for inter-process communication. Shared memory allows two or more tasks (processes or threads) to share the same memory pool. The memory blocks in the memory pool are mapped to the virtual address space of each task, and the tasks can directly access them, avoiding the data copying process.

[0003] However, the design of the shared memory database (shared memory pool) in the prior art usually requires locking the entire database or the table. Due to the locking operation, only a single write task or read task can perform write or read operations in the shared memory pool at the same time. When multiple tasks operate the shared memory at the same time, multiple tasks need to operate in sequence and cannot achieve concurrency. Therefore, when the current task operates the shared memory, other tasks need to wait. However, in some high-concurrency and high-real-time application scenarios, for example, in the autonomous driving scenario, there will be multiple high-real-time tasks that need to operate the shared memory at the same time. Since the shared memory pool locking access method in the prior art does not support concurrency, multiple tasks in scenarios such as autonomous driving need to wait, which cannot meet the needs of high-concurrency and high-real-time scenarios. Summary of the invention

[0004] The present disclosure proposes a shared memory parallel access method, device and electronic device, aiming to solve one of the technical problems in the related art at least to a certain extent.

[0005] An embodiment of the first aspect of the present disclosure proposes a shared memory parallel access method, including: based on a preset write operation list, using lock-free operations to respectively determine corresponding write operation items for multiple write tasks; based on the write operation items, allocating storage space for each write task in a shared memory pool, and writing target data of each write task in parallel to the storage space; using write information of the target data of each write task as field information of the corresponding write operation item; and using lock-free operations to update the write operation item to a read operation list as a read operation item, wherein the read operation item is used to read data in the shared memory pool in parallel.

[0006] An embodiment of the second aspect of the present disclosure proposes a shared memory parallel access device, including: a first determination module, used to determine corresponding write operation items for multiple write tasks based on a preset write operation list by adopting lock-free operations; a write module, used to allocate storage space for each write task in a shared memory pool based on the write operation items, and write the target data of each write task into the storage space in parallel; a second determination module, used to use the write information of the target data of each write task as the field information of the corresponding write operation item; and an update module, used to update the write operation item to the read operation list by adopting lock-free operations as a read operation item, wherein the read operation item is used to read data in the shared memory pool in parallel.

[0007] An embodiment of the third aspect of the present disclosure proposes an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the shared memory parallel access method of the embodiment of the present disclosure.

[0008] The fourth aspect embodiment of the present disclosure proposes a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable the computer to execute the shared memory parallel access method disclosed in the embodiment of the present disclosure.

[0009] A fifth aspect of the present disclosure provides a vehicle, wherein the vehicle includes an electronic device according to the first aspect.

[0010] In this embodiment, based on a preset write operation list, corresponding write operation items are determined for multiple write tasks respectively using lock-free operations, and based on the write operation items, storage space is allocated to each write task in the shared memory pool, and the target data of each write task is written into the storage space in parallel, and the write information of the target data of each write task is used as the field information of the corresponding write operation item, and the write operation item is updated to the read operation list as a read operation item using lock-free operations, wherein the read operation item is used to read data in the shared memory pool in parallel, and the technical effect of multiple write tasks and multiple read tasks accessing the shared memory in parallel can be achieved using lock-free operations, meeting the requirements of high concurrency and high real-time scenarios.

[0011] Additional aspects and advantages of the present disclosure will be given in part in the following description and in part will be obvious from the following description or learned through practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and / or additional aspects and advantages of the present disclosure will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0013] Figure 1 It is a flowchart of a shared memory parallel access method provided according to an embodiment of the present disclosure;

[0014] Figure 2 A schematic diagram of a shared memory parallel access system architecture is provided according to an embodiment of the present disclosure;

[0015] Figure 3 is a flow chart of a shared memory parallel access method provided according to another embodiment of the present disclosure;

[0016] Figure 4 It is a schematic diagram of the overall process of multi-round multi-person shared memory parallel access provided according to an embodiment of the present disclosure;

[0017] Figure 5 is a schematic diagram of a shared memory parallel access device provided according to another embodiment of the present disclosure;

[0018] Figure 6 A block diagram of an exemplary electronic device suitable for implementing embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0019] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0020] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0021] It should be noted that the executor of the shared memory parallel access method of this embodiment may be a shared memory parallel access device, which may be implemented by software and / or hardware, and which may be configured in an electronic device, which may include but is not limited to a terminal, a server, etc.

[0022] Figure 1 is a flow chart of a shared memory parallel access method provided according to an embodiment of the present disclosure, such as Figure 1 As shown, the method includes:

[0023] S101: Based on a preset write operation list, corresponding write operation items are respectively determined for a plurality of write tasks using a lock-free operation.

[0024] Among them, the task for writing data into the shared memory pool can be called a write task, and the write task can be a task in any application scenario, and the write task can be executed by a process, a thread, and any other possible executable body, without limitation.

[0025] The write operation list is an operable list (also called a view window) provided for multiple write tasks to concurrently access the shared memory pool. Each entry in the write operation list can be used as an operation item, and the operation item applied for the write task can be called a write operation item, which is used to allocate storage space for the write task in the shared memory pool. The number of write operation items can be flexibly set according to the actual application scenario, and there is no limit to this.

[0026] The lock-free operation may be any type of lock-free operation, for example, a compare-and-swap (CAS) atomic operation, and there is no restriction on this.

[0027] According to the disclosed embodiment, when multiple write tasks need to write data to a shared memory pool, firstly, based on a preset write operation list, corresponding write operation items can be determined for the multiple write tasks using lock-free operations. That is, a corresponding write operation item is applied for each write task in the write operation list.

[0028] In a specific example, Figure 2 A schematic diagram of a shared memory parallel access system architecture is provided according to an embodiment of the present disclosure, such as Figure 2 As shown, there are multiple write tasks such as task A, task B, task C, etc. Each row of entries in the write operation list can be used as an operation item. Each operation item can have multiple fields, such as identification, timestamp, load, etc., and there is no restriction on this.

[0029] In some embodiments, each operation item in the write operation list can be used as a write operation item. When task A, task B, and task C need to access the shared memory pool in parallel, this embodiment can use a lock-free operation (such as a CAS atomic operation) based on the write operation list to randomly apply for an operation item as a write operation item for task A, task B, and task C respectively.

[0030] In some other embodiments, the identification field of the operation item is divided into identifications such as "empty", "write", and "available", that is, there are multiple types of operation items. Among them, the operation item identified as "empty" indicates that the write operation can be performed, that is, the operation of allocating storage space for the write task can be provided, the operation item identified as "write" indicates that the operation item is performing a write operation, and the operation item identified as "available" indicates that the write operation has been completed. Among them, this embodiment can use the "empty" identifier as the first identifier and the "write" identifier as the second identifier. When task A, task B, and task C need to access the shared memory pool in parallel, this embodiment can use the compare-and-exchange atomic operation (i.e., CAS atomic operation) for each write task to traverse the operation items marked with the first identifier ("empty") in the write operation list as write operation items, and replace the first identifier of the write operation item with the second identifier ("write"). That is to say, this embodiment uses CAS atomic operations to traverse the operation items in the write operation list that can perform write operations as write operation items for multiple write tasks, and modifies the identifier of the write operation item to "write", wherein the CAS atomic operation is expressed as: CAS (operation item, empty identifier, write identifier).

[0031] S102: Based on the write operation item, allocate storage space for each write task in the shared memory pool, and write target data of each write task into the storage space in parallel.

[0032] Among them, the data that needs to be written by the write task can be called target data, and this embodiment can allocate storage space (i.e., physical memory slice cache) for storing target data to each write task in a shared memory pool in parallel based on the write operation items corresponding to multiple write tasks, and write the target data of each write task in parallel into the corresponding storage space.

[0033] In some embodiments, the target data may be in the form of a key-value pair, that is, the target data includes key data (key) and value data (value). In this embodiment, storage space may be allocated for the key data and value data of each write task in a shared memory pool, respectively, and the storage spaces are respectively referred to as a first storage space (key buf) and a second storage space (valuebuf); further, the key data (key) of each write task is written to the first storage space, and the value data (value) is written to the second storage space in parallel.

[0034] Some embodiments, such as Figure 2As shown, the shared memory pool can be divided into multiple groups of physical memory slice groups according to the storage byte length, for example, 1T-byte physical memory slice group, 2T-byte physical memory slice group, 4T-byte physical memory slice group, etc., each group includes multiple memory slice caches of the same byte length. In the process of allocating the first storage space and the second storage space, this embodiment can allocate a memory block that matches the length of the key data as the first storage space for each write task in the shared memory pool, that is, allocate the first storage space according to the length of the key data, for example, if the length of the key data is 1T, then an empty memory slice can be allocated in the 1T-byte physical memory slice group as the first storage space; similarly, this embodiment can allocate a memory block that matches the length of the value data as the second storage space for each write task in the shared memory pool. Therefore, this embodiment can reasonably allocate storage space according to the length of the target data.

[0035] Some embodiments, such as Figure 2 As shown, a shared memory register for managing a shared memory pool can also be provided. After the storage space (the first storage space and the second storage space) of each write task is determined in this embodiment, the mapping relationship between the storage space number (i.e., the memory block number) and the offset address of the storage space can be recorded in the shared memory register, so that each write task and read task (i.e., process or thread) can access the shared memory through the storage space number, wherein the storage space number can be expressed as shm_register_get(64Byte). Thus, when a write task or a read task accesses the shared memory, it cannot see the offset address of the memory, thus avoiding abnormal access of the task and improving access security.

[0036] It can be understood that, in this embodiment, before writing the target data into the storage space, it is necessary to map the shared memory pool and the write operation list and the read operation list to the virtual address space of each task.

[0037] S103: Using the write information of the target data of each write task as the field information of the corresponding write operation item.

[0038] The write information is used to describe any information in the process of writing the target data of each write task into the storage space. For example, in the process of writing the target data into the storage space, it is necessary to determine the write time, calculate the value data check code, the value data length, the key data length, etc., and determine the key data storage space number and the value data storage space number. In other words, the write information of this embodiment includes, for example, the write time, the value data check code, the value data length, the key data length, the key data storage space number, the value data storage space number, etc.

[0039] Each write operation item in the write operation list corresponds to one or more fields, and the fields are used to record the information of the write operation item. The fields include, for example, value data check code, key data storage space number, key data length, value data storage space number, value data length, and timestamp fields, wherein the timestamp belongs to the timestamp field, and the value data check code, key data storage space number, key data length, value data storage space number, and value data length belong to the load field, and there is no restriction on this.

[0040] In the embodiment of the present disclosure, after writing the target data (e.g., key data and value data) of each write task into the storage space, further, the field information of the field corresponding to each write operation item in the write operation list is determined. The write information of each target data can be used as one or more field information of the corresponding write operation item, for example, the write time, value data check code, value data length, key data length, key data storage space number, value data storage space number and other write information are used as the field information of the timestamp field, value data length field, key data length field, key data storage space number field, and value data storage space number field, respectively.

[0041] S104: Using a lock-free operation to update the write operation item to the read operation list as a read operation item.

[0042] like Figure 2 As shown, this embodiment can also provide an operable list (also referred to as a view window) for multiple read tasks (task D, task E, task F) to concurrently access the shared memory pool, and the operation list can be referred to as a read operation list. Each entry in the read operation list can be used as a read operation item, and the read operation item is used to read data in the shared memory pool in parallel, and the number of read operation items in the read operation list can be flexibly set according to the actual application scenario, and there is no restriction on this.

[0043] After the target data of the write task is written into the shared memory pool through the write operation item in this embodiment, the write operation item can be updated to the read operation list as a read operation item by a lock-free operation, and the write operation item can be removed from the write operation list, wherein the update process is not specifically limited here.

[0044] In actual applications, when multiple read tasks need to read target data concurrently, a read operation item can be applied for each read task based on the read operation list, and the data in the shared memory pool can be read through the read operation item. Specifically, the read operation uses an O(1) algorithm, for example, value = hash(key) to find the corresponding value, and the read operation can be performed concurrently through the configured concurrent readers without locking or atomic operations.

[0045] In this embodiment, based on a preset write operation list, corresponding write operation items are determined for multiple write tasks respectively using lock-free operations, and based on the write operation items, storage space is allocated to each write task in the shared memory pool, and the target data of each write task is written into the storage space in parallel, and the write information of the target data of each write task is used as the field information of the corresponding write operation item, and the write operation item is updated to the read operation list as a read operation item using lock-free operations, wherein the read operation item is used to read data in the shared memory pool in parallel, and the technical effect of multiple write tasks and multiple read tasks accessing the shared memory in parallel can be achieved using lock-free operations, meeting the requirements of high concurrency and high real-time scenarios.

[0046] Figure 3 is a flow chart of a shared memory parallel access method provided according to another embodiment of the present disclosure, such as Figure 3 As shown, the method includes:

[0047] S301: Based on a preset write operation list, corresponding write operation items are determined for multiple write tasks respectively by adopting a lock-free operation.

[0048] S302: Based on the write operation item, allocate storage space for each write task in the shared memory pool, and write target data of each write task into the storage space in parallel.

[0049] S303: Use the write information of the target data of each write task as the field information of the corresponding write operation item.

[0050] The specific description of S301 - S303 refers to the above embodiment and will not be repeated here.

[0051] S304: Use a compare-and-exchange atomic operation to insert the write operation item marked with the second identifier in the write operation list into the read operation list as a read operation item, and replace the identifier with the third identifier.

[0052] In the disclosed embodiment, a lock-free operation may be used to update the write operation item to the read operation list in different update modes as a read operation item, wherein the update mode is, for example, divided into an append mode and an overwrite mode.

[0053] Specifically, in the append mode, this embodiment can use a compare-and-exchange (CAS) atomic operation to insert the write operation item marked as the second identifier in the write operation list into the target slot of the read operation list as a read operation item, and replace the mark of the write operation item inserted in the read operation list with a third identifier, wherein the second identifier is "write", and the third identifier indicates that the operation item can perform a read operation, and the third identifier can be configured as "read", for example, that is, the write operation item marked as "write" in the write operation list is inserted into the target slot of the read operation list using the CAS atomic operation, and then the mark is modified to "read", indicating that the operation item can perform a read operation but not a write operation. Among them, the CAS atomic operation can be expressed as: CAS (update cursor register, old update cursor, new update cursor), wherein the update cursor register points to the write operation item inserted in the target slot, the old update cursor corresponds to the second identifier, and the new update cursor corresponds to the third identifier.

[0054] S305: Determine whether there is a target operation item corresponding to the target data in the read operation list.

[0055] In some other embodiments, in the overwrite mode, this embodiment first determines whether there is a target operation item corresponding to the target data in the read operation list.

[0056] The read operation item corresponding to the target data may be referred to as a target operation item (also referred to as an old operation item), that is, the target operation item is used to read the old target data.

[0057] In some embodiments, for example, the key data key corresponding to each read operation item in the read operation list can be calculated by an O(1) hash algorithm, and it can be further determined whether there is a target operation item in the read operation item that is the same as the key data key of the write task, that is, the key data key corresponding to the target operation item is the same as the key data key of the write task.

[0058] S306: When there is a target operation item, a compare-and-exchange atomic operation is used to replace the field information corresponding to the target operation item with the field information of the write operation item corresponding to the target data.

[0059] Further, the present embodiment adopts a compare-and-exchange (CAS) atomic operation to replace the field information of the target operation item with the field information of the write operation item, wherein the field information includes a timestamp and a load (value data check code, key data storage space number, key data length, value data storage space number, value data length), that is, the timestamp and load information of the new write operation item are used to replace the timestamp and load information of the old target operation item, and the timestamp and load information can be replaced synchronously. In the replacement process, the mark of the target operation item can first be replaced with a first identifier (i.e., "empty"), and further a compare-and-exchange atomic operation is adopted to update the field information corresponding to the target operation item to the field information corresponding to the write operation item, and the first identifier ("empty") is replaced with a third identifier ("read"), wherein the CAS atomic operation can be expressed as: CAS (read flag register address, read flag old timestamp and load, empty flag new timestamp and load). It should be noted that if the target operation item does not exist, the present embodiment can also adopt an append mode to update the write operation item to the read operation list.

[0060] In some embodiments, in overlay mode, in order to ensure data consistency, when the number of read threads of the target operation item is zero, this embodiment can release the target operation item from the read operation list and update it to the write operation list, and modify the mark of the target operation item to "available".

[0061] Therefore, this embodiment can use different updating methods to update the write operation items to the read operation list, ensuring that the read task can accurately read the target data in the shared memory pool.

[0062] In this embodiment, based on a preset write operation list, a lock-free operation is used to determine corresponding write operation items for multiple write tasks respectively, and based on the write operation items, a storage space is allocated to each write task in a shared memory pool, and the target data of each write task is written to the storage space in parallel, and the write information of the target data of each write task is used as the field information of the corresponding write operation item, and the write operation item is updated to the read operation list as a read operation item using a lock-free operation, wherein the read operation item is used to read data in the shared memory pool in parallel, and the lock-free operation can be used to achieve the technical effect of multiple write tasks and multiple read tasks accessing the shared memory in parallel, meeting the needs of high concurrency and high real-time scenarios. In addition, this embodiment can use different update methods to update the write operation item to the read operation list to ensure that the read task can accurately read the target data in the shared memory pool.

[0063] In one specific example, Figure 4 is a schematic diagram of the overall process of multi-round multi-person shared memory parallel access provided according to an embodiment of the present disclosure, such as Figure 4As shown, in actual applications, the write task maps the shared memory pool to its own virtual address space and maps the inserted view window (i.e., the write operation list) to its own virtual address space; further, the task randomly selects an entry (i.e., the write operation entry) from the empty management bitmap of the inserted view window and sets the write flag CAS (entry address, empty flag, write flag) for the found entry through CAS; further, a cache (the first storage space) matching the key length is fetched from the memory pool, such as T<key, length 2T>, then an empty key buf is fetched from the 2T cache and put into the shared memory register, and a memory block number (storage space number) is allocated, and a cache (the second storage space) matching the value length is fetched from the memory pool, such as T<value, length 2T>, then an empty value buf is fetched from the 2T cache and put into the shared memory register, and a memory block number is allocated; further, the key is written into the key buf (the first storage space) fetched by the write task, and the value is written into the value buf (the second storage space) fetched by the write task; further, the value checksum is calculated, and the checksum, key memory block number, key length, value memory block number, and value length are inserted into the payload field of the corresponding entry in the inserted view window, and the current timestamp is calculated and written into the timestamp field of the corresponding entry in the inserted view window; further, the write operation entry is updated to the read operation list (read view window) in the overwrite mode or the append mode. In the append mode, the entry marked as written is inserted into the read view window using the CAS atomic operation, CAS (update cursor register, old update cursor, new update cursor), the entry with the write flag is inserted into the entry slot pointed to by the update cursor, and the entry flag is atomically updated to read; in the overwrite mode, when the key is found, the old entry flag and timestamp are updated using the CAS atomic operation, CAS (read flag register address, old read flag timestamp, empty flag new timestamp), and when the number of read tasks for the memory block pointed to by the read entry is 0, the old entry is released from the read view window and appended to the inserted view window. If the key is not found, the append mode is adopted.

[0064] To implement the above embodiments, the present disclosure also proposes a shared memory parallel access device.

[0065] Figure 5 It is a schematic diagram of a shared memory parallel access device according to another embodiment of the present disclosure.

[0066] As Figure 5 shown, the shared memory parallel access device 50 includes:

[0067] A first determination module 501 is used to determine corresponding write operation items for multiple write tasks respectively by using a lock-free operation based on a preset write operation list;

[0068] A writing module 502, configured to allocate storage space for each writing task in a shared memory pool based on the writing operation item, and write target data of each writing task into the storage space in parallel;

[0069] A second determining module 503 is configured to use the write information of the target data of each write task as the field information of the corresponding write operation item; and

[0070] The updating module 504 is used to update the write operation item to the read operation list as a read operation item by adopting a lock-free operation, wherein the read operation item is used to read data in the shared memory pool in parallel.

[0071] In some embodiments, the first determination module 501 is specifically used to: for each write task, use a comparison and exchange atomic operation to traverse the operation items marked with the first identifier in the write operation list as write operation items, and replace the identifier of the write operation item with the second identifier, wherein the first identifier indicates that the corresponding operation item can perform a write operation, and the second identifier indicates that the corresponding operation item is performing a write operation.

[0072] In some embodiments, the update module 504 is specifically used to: use a compare-and-exchange atomic operation to insert the write operation item marked with the second identifier in the write operation list into the read operation list as a read operation item, and replace the mark with a third identifier, wherein the third identifier indicates that the corresponding operation item can perform a read operation.

[0073] In some embodiments, the update module 504 is specifically used to: determine whether there is a target operation item corresponding to the target data in the read operation list; and if there is a target operation item, use a compare-and-exchange atomic operation to replace the field information corresponding to the target operation item with the field information of the write operation item corresponding to the target data.

[0074] In some embodiments, the update module 504 is specifically configured to: when the number of read threads of the target operation item is zero, release the target operation item from the read operation list and update it to the write operation list.

[0075] In some embodiments, the update module 504 is specifically used to determine whether there is a target operation item in the read operation list that has the same key data as the write task.

[0076] In some embodiments, the write module 502 is specifically used to: allocate a first storage space and a second storage space for the key data and value data of each write task in a shared memory pool, respectively; and write the key data and value data of each write task into the first storage space and the second storage space in parallel.

[0077] In some embodiments, the write module 502 is specifically used to: allocate a memory block matching the length of the key data as a first storage space for each write task in the shared memory pool; and allocate a memory block matching the length of the value data as a second storage space for each write task in the shared memory pool.

[0078] In some embodiments, the field information corresponding to the write operation item includes at least one of the following: a value data check code, a key data storage space number, a key data length, a value data storage space number, a value data length, and a timestamp.

[0079] In some embodiments, the apparatus 50 further includes: a recording module, configured to record a mapping relationship between a storage space number and an offset address of the storage space in a shared memory register.

[0080] In this embodiment, based on a preset write operation list, corresponding write operation items are determined for multiple write tasks respectively using lock-free operations, and based on the write operation items, storage space is allocated to each write task in the shared memory pool, and the target data of each write task is written into the storage space in parallel, and the write information of the target data of each write task is used as the field information of the corresponding write operation item, and the write operation item is updated to the read operation list as a read operation item using lock-free operations, wherein the read operation item is used to read data in the shared memory pool in parallel, and the technical effect of multiple write tasks and multiple read tasks accessing the shared memory in parallel can be achieved using lock-free operations, meeting the requirements of high concurrency and high real-time scenarios.

[0081] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

[0082] In order to implement the above embodiments, the present disclosure further proposes a computer program product. When an instruction processor in the computer program product executes, the shared memory parallel access method proposed in the above embodiments of the present disclosure is executed.

[0083] Figure 6 A block diagram of an exemplary electronic device suitable for implementing embodiments of the present disclosure is shown. Figure 6 The electronic device 12 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0084] like Figure 6 As shown, the electronic device 12 is in the form of a general purpose computing device. The components of the electronic device 12 may include, but are not limited to: one or more processors or processing units 16, a system memory 28, and a bus 18 that connects various system components (including the system memory 28 and the processing unit 16).

[0085] The bus 18 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a processor or a local bus using any of a variety of bus structures. For example, these architectures include but are not limited to Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MAC) bus, Enhanced ISA bus, Video Electronics Standards Association (VESA) local bus and Peripheral Component Interconnection (PCI) bus.

[0086] The electronic device 12 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by the electronic device 12, including volatile and non-volatile media, removable and non-removable media.

[0087] The memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. The electronic device 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, the storage system 34 may be used to read and write non-removable, non-volatile magnetic media ( Figure 6 Not shown, often called a "hard drive").

[0088] although Figure 6 Not shown in the figure, a disk drive for reading and writing a removable non-volatile disk (e.g., a "floppy disk"), and an optical disk drive for reading and writing a removable non-volatile optical disk (e.g., a compact disc read only memory (CD-ROM), a digital versatile disc read only memory (DVD-ROM), or other optical media) may be provided. In these cases, each drive may be connected to the bus 18 via one or more data medium interfaces. The memory 28 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the various embodiments of the present disclosure.

[0089] A program / utility 40 having a set (at least one) of program modules 42 may be stored, for example, in the memory 28, such program modules 42 including but not limited to an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment. The program modules 42 generally perform the functions and / or methods of the embodiments described in the present disclosure.

[0090] The electronic device 12 may also communicate with one or more external devices 14 (e.g., keyboards, pointing devices, displays 24, etc.), may also communicate with one or more devices that enable a user to interact with the electronic device 12, and / or may communicate with any device that enables the electronic device 12 to communicate with one or more other computing devices (e.g., network cards, modems, etc.). Such communication may be performed via an input / output (I / O) interface 22. Furthermore, the electronic device 12 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 20. As shown, the network adapter 20 communicates with other modules of the electronic device 12 via a bus 18. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 12, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0091] The processing unit 16 executes various functional applications by running programs stored in the system memory 28, such as implementing the shared memory parallel access method mentioned in the above embodiment.

[0092] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0093] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

[0094] It should be noted that, in the description of the present disclosure, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present disclosure, unless otherwise specified, the meaning of "plurality" is two or more.

[0095] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present disclosure includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present disclosure belong.

[0096] It should be understood that the various parts of the present disclosure can be implemented in hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0097] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0098] In addition, each functional unit in each embodiment of the present disclosure may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0099] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0100] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0101] Although the embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present disclosure. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present disclosure.

Claims

1. A shared memory parallel access method, It is characterized in that The method comprises: Based on the preset write operation list, a lock-free operation is used to determine corresponding write operation items for multiple write tasks respectively; Based on the write operation item, allocating storage space for each of the write tasks in a shared memory pool, and writing target data of each of the write tasks into the storage space in parallel; Using the write information of the target data of each write task as the field information of the corresponding write operation item; and The write operation item is updated to the read operation list as a read operation item by adopting a lock-free operation, wherein the read operation item is used to read data in the shared memory pool in parallel.

2. The method according to claim 1, It is characterized in that The method of using a lock-free operation based on a preset write operation list to respectively determine corresponding write operation items for a plurality of write tasks includes: For each of the write tasks, a compare-and-exchange atomic operation is used to traverse the operation items marked with the first identifier in the write operation list as the write operation items, and the identifier of the write operation item is replaced with the second identifier, wherein the first identifier indicates that the corresponding operation item can perform a write operation, and the second identifier indicates that the corresponding operation item is performing a write operation.

3. The method according to claim 2, It is characterized in that The adopting a lock-free operation to update the write operation item to the read operation list as a read operation item includes: A compare-and-exchange atomic operation is used to insert the write operation item marked as the second identifier in the write operation list into the read operation list as the read operation item, and the second identifier is replaced with a third identifier, wherein the third identifier indicates that the corresponding operation item can perform a read operation.

4. The method according to claim 1, It is characterized in that The adopting a lock-free operation to update the write operation item to the read operation list as a read operation item includes: Determine whether there is a target operation item corresponding to the target data in the read operation list; In the case where the target operation item exists, a compare-and-exchange atomic operation is used to replace the field information corresponding to the target operation item with the field information of the write operation item corresponding to the target data.

5. The method according to claim 4, It is characterized in that After the comparison and exchange atomic operation is used to replace the field information corresponding to the target operation item with the field information of the write operation item corresponding to the target data, the method further includes: When the number of read threads of the target operation item is zero, the target operation item is released from the read operation list and inserted into the write operation list.

6. The method according to claim 4, It is characterized in that The determining whether there is a target operation item corresponding to the target data in the read operation list includes: It is determined whether there is a target operation item in the read operation list that has the same key data as the write task.

7. The method according to claim 1, It is characterized in that The allocating storage space in the shared memory pool for each of the write tasks, and writing the target data of each of the write tasks into the storage space in parallel, comprises: Allocating a first storage space and a second storage space in the shared memory pool for the key data and the value data of each of the write tasks respectively; and The key data and the value data of each of the write tasks are written into the first storage space and the second storage space in parallel.

8. The method according to claim 7, It is characterized in that The allocating a first storage space and a second storage space respectively for the key data and the value data of each write task in the shared memory pool comprises: Allocating a memory block matching the length of the key data as the first storage space to each of the write tasks in the shared memory pool; and A memory block matching the length of the value data is allocated in the shared memory pool for each of the write tasks as the second storage space.

9. The method according to claim 1, It is characterized in that in, The field information corresponding to the write operation item includes at least one of the following: a value data check code, a key data storage space number, a key data length, a value data storage space number, a value data length, and a timestamp.

10. The method according to claim 1, It is characterized in that After allocating storage space in the shared memory pool for each of the write tasks, the method further includes: A mapping relationship between the storage space number and the offset address of the storage space is recorded in the shared memory register.

11. A shared memory parallel access device, It is characterized in that include: A first determination module is used to determine corresponding write operation items for multiple write tasks respectively by using a lock-free operation based on a preset write operation list; A writing module, configured to allocate storage space for each of the writing tasks in a shared memory pool based on the writing operation item, and write target data of each of the writing tasks into the storage space in parallel; A second determining module, configured to use the writing information of the target data of each writing task as the field information of the corresponding writing operation item; as well as An update module is used to update the write operation item to the read operation list as a read operation item by adopting a lock-free operation, wherein the read operation item is used to read data in the shared memory pool in parallel.

12. An electronic device, include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 10.

13. A non-transitory computer-readable storage medium storing computer instructions, in, The computer instructions are used to cause the computer to execute the method according to any one of claims 1-10.

14. A vehicle, It is characterized in that The vehicle includes the electronic device as claimed in claim 12.

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