Multi-thread transmission device and method

Abstract

The invention relates to the field of data transmission, in particular to a multi-thread transmission device and method. Comprising a serializer, a deserializer, an interface controller, a logic manager and a direct memory access controller, deserializing the received physical layer message into a transaction layer message, inputting the transaction layer message into the interface controller, serializing the transaction layer message generated by the interface controller into a physical layer code stream, and outputting the physical layer code stream to the CPU; the interface controller processes a transaction layer message input by the serializer / deserializer or the logic manager; the logic manager generates a chip access message in a specified format from the transaction layer message, and outputs the chip access message to a direct memory access controller in a pipeline form; and the direct memory access controller receives the chip access message. The method can be suitable for a super-large-scale chip and a scene with a complex address space, and can realize rapid and efficient register and table item access.

Description

Technical Field

[0001] The present invention relates to the field of data transmission, and in particular to a device and method for multi-threaded transmission. Background Art

[0002] With the rapid development of ultra-large-scale chips, there are more and more registers in the chip, the address space scenarios are becoming more and more complex, and the access requirements for registers and table entries are becoming more and more abundant. The register access function is a very important part of chip design. In the work and design process of ultra-large-scale chips, each functional subsystem and submodule has a large number of registers that need to be accessed or debugged by the system. This requires the chip to provide a unified register access interface and a complete register access mechanism, and ensure low latency, fast and efficient, accurate and complete access efficiency.

[0003] Traditional switching chips and network processors mostly access registers of various hardware modules on the chip in bus form, and each module shares the same bus in time-sharing. When the chip is large in scale, the number of registers is large, the address space is complex, or the access frequency is high, the existing shared bus access method will increase access latency and even cause congestion, reduce efficiency, and affect the central processing unit (CPU) used to manage the chip and the processing performance of the chip itself.

[0004] On the other hand, most traditional chip bottom-level events or errors are reported to the CPU in a polling manner. The cumbersome polling mechanism takes up CPU processing time and is inefficient. Even if it is later changed to a CPU interrupt mode, if frequent interrupts occur, the CPU needs to read related registers to obtain detailed abnormal information, which will seriously affect the processing efficiency of the CPU and chip.

[0005] In view of this, how to overcome the defects of the prior art and solve the problem that the use of a shared bus in the prior art affects the register access performance is a problem to be solved in the field of this technology. Summary of the invention

[0006] In view of the above defects or improvement requirements of the prior art, the present invention solves the problem in the prior art that the use of a shared bus affects the register access performance.

[0007] The embodiment of the present invention adopts the following technical solution:

[0008] In a first aspect, the present invention provides a multi-thread transmission device, specifically: a serial deserializer, an interface controller, a logic manager and a direct memory access controller, specifically including: a PCIe interface is connected to a CPU through a serial deserializer, deserializes a received physical layer message into a transaction layer message and inputs it into the interface controller, and serializes the transaction layer message generated by the interface controller into a physical layer code stream and outputs it to the CPU; the interface controller processes the transaction layer message input by the serial deserializer or the logic manager, and / or generates a transaction layer message that needs to be output by the serial deserializer or the logic manager; the logic manager and the interface controller interact through transaction layer messages, the logic manager generates a chip access message in a specified format from the transaction layer message, and outputs the chip access message to the direct memory access controller in a pipeline form, and / or receives the chip access message input by the direct memory access controller in a pipeline form and generates a corresponding transaction layer message; the direct memory access controller receives the chip access message, outputs the data to the outside of the device through a direct chip access interface, and / or receives external input data through a direct chip access interface and converts it into a chip access message.

[0009] Preferably, the logic manager includes: a receiving module, a sending module, a slave endpoint module, a master endpoint module and an interface dependency module, specifically including: the receiving module is used to receive transaction layer messages, parse and identify the transaction layer message type, and transmit the transaction layer messages to the master endpoint module or the slave endpoint module after decoding; the sending module is used to receive transaction layer messages generated by the master endpoint module or the slave endpoint module, and transmit the transaction layer messages to the interface controller; the slave endpoint module is used to parse the base address space for reading and writing data in the transaction layer messages, and generate corresponding bus signals for transmission to the direct memory access interface; the master endpoint module is used to determine whether the transaction layer message is an expected reply, and / or, to generate a chip access message in a specified format; the interface dependency module serves as a data interface between the master endpoint module and the direct memory access interface, and as a data interface between the slave endpoint module and the direct memory access interface.

[0010] Preferably, the slave endpoint module includes: a slave endpoint processing component, an interrupt controller and a local register group, specifically including: the slave endpoint processing component exchanges data with the direct memory access interface through a signal bus, and is used to complete the corresponding transaction layer message processing when the device is used as a slave endpoint; the interrupt controller parses the interrupt signal generated by the direct memory access interface and generates an interrupt signal submitted to the CPU; the local register group is used to save the data transmission status in the PCIe interface so that the logic manager can obtain the data transmission status of the PCIe interface.

[0011] Preferably, the master endpoint module includes: a master endpoint processing component, a request state machine, a packet cache, a read response tracking component and a reply cache, specifically including: the master endpoint processing component is used to complete the corresponding transaction layer message processing when the device is used as a master endpoint; the request state machine is used to process the data packet from the direct memory access interface, so that the device converts the data packet into a transaction layer message in a pipeline form; the packet cache is used to cache the data packet from the direct memory access interface; the read response tracking component is used to process the read response completion message of the transaction layer message, so that the direct memory access interface obtains the response to each transaction layer message, sorts the transaction layer messages and converts them into data packets in a specified format, and sends the converted data packets to the direct memory access interface; the reply cache is used to cache the transaction layer completion message of the CPU's effective reply.

[0012] In a second aspect, the present invention provides a method for multi-threaded transmission, characterized in that the device provided in the first aspect is used, specifically including: when a peripheral device needs to pull CPU data, the device generates a corresponding memory read request, obtains corresponding data in the CPU according to the memory read request, the CPU encapsulates the corresponding data into a transaction layer message and sends it to the device, and the device pulls the data in the transaction layer message to the peripheral device through a direct memory access interface; when the peripheral device actively transmits data to the CPU, the device generates a corresponding memory write request, assembles the data obtained by the direct memory access interface into a corresponding transaction layer message according to the memory write request, and pushes the data to the corresponding data page address through the transaction layer message for use by the CPU when it is idle.

[0013] Preferably, when the transaction layer message is a configuration message of PCIe or a direct memory access interface, the device generates a corresponding memory read request, obtains corresponding data in the CPU according to the memory read request, and the CPU encapsulates the corresponding data into a transaction layer message and sends it to the device, specifically including: the CPU encapsulates the data required for configuration into a corresponding transaction layer message and sends it to the receiving module, the receiving module parses the memory read request or memory write request in the encapsulated transaction layer message, and sends the transaction layer message to the slave endpoint module; the slave endpoint module parses the base address in the transaction layer message, and uses the request state machine to generate a corresponding bus signal, transmits the bus signal to the direct memory access interface through the signal bus, and the direct memory access interface executes the configuration processing in the transaction layer message.

[0014] Preferably, when the transaction layer message is a read response completion message, the corresponding data in the CPU is obtained according to the memory read request, the CPU encapsulates the corresponding data into a transaction layer message and sends it to the device, and the device pulls the data in the transaction layer message to the peripheral device through the direct memory access interface, specifically including: the receiving module sends the transaction layer message to the main endpoint module, the main endpoint module compares the received transaction layer message with the request information waiting for a reply; when the transaction layer message is the expected reply, a chip access message in a specified format is generated according to the transaction layer message, and the chip access message is sent to the direct memory access interface.

[0015] Preferably, the method of assembling the data obtained by the direct memory access interface into a corresponding transaction layer message according to the memory write request, and pushing the data to the corresponding data page address through the transaction layer message, also includes: when the data is written, obtaining the data page address and task number sent by the CPU from the endpoint module, and sending the data page address to the direct memory access interface through the signal bus; after the corresponding data page is used up and released, the direct memory access interface returns the released data page address to the CPU.

[0016] Preferably, when the peripheral device sends data to the CPU, the data obtained by the direct memory access interface is assembled into a corresponding transaction layer message according to the memory write request, and the data is pushed to the corresponding data page address through the transaction layer message, which specifically includes: the direct memory access interface initiates a memory write request for writing data, the main endpoint module encapsulates the chip access message slices, and sends out a corresponding transaction layer message; when the data is written to the data page, the CPU receives an interrupt sent by the memory access interface indicating that the data has been sent, and the CPU knows that the data is available based on the interrupt.

[0017] Preferably, the data obtained by the direct memory access interface is assembled into a corresponding transaction layer message according to the memory write request, and the data is pushed to the corresponding data page address through the transaction layer message, specifically including: when the DMA pushes the data to the corresponding data page address, an interrupt request signal is sent to the receiving module; the receiving module uses the interrupt controller to parse the interrupt request signal and generates a corresponding interrupt signal; the interrupt signal is sent to the CPU through the sending module to trigger an interrupt of the CPU.

[0018] Compared with the prior art, the beneficial effects of the present invention are as follows: through the access device provided by the present invention, a bus system with a rosette structure is formed using a multi-layer ring bus, and different subsystems or submodules are managed using different ring buses, which has portability and scalability; through the access protocol provided by the present invention, a unified message mechanism for software and hardware is realized; through the access method provided by the present invention, multi-layer addressing based on the main ring and sub-ring is used to improve processing efficiency and performance. The present invention is suitable for scenarios with ultra-large-scale chips and complex address spaces, and can achieve fast and efficient access to registers and table entries. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 A schematic diagram of the structure of a register access device in a super-large-scale chip provided by an embodiment of the present invention;

[0021] Figure 2 A schematic diagram of the structure of a register node in an access device provided by an embodiment of the present invention;

[0022] Figure 3 A schematic diagram of the structure of a master node in an access device provided by an embodiment of the present invention;

[0023] Figure 4 A schematic diagram of the structure of a cross node in an access device provided by an embodiment of the present invention;

[0024] Figure 5 A schematic diagram of an access protocol message structure in an access device provided in an embodiment of the present invention;

[0025] Figure 6 A schematic diagram of another access protocol message structure in an access device provided in an embodiment of the present invention;

[0026] Figure 7 A schematic diagram of a usage scenario of a method for accessing registers in a super-large-scale chip provided by an embodiment of the present invention;

[0027] Figure 8 A flowchart of a method for accessing registers in a super-large-scale chip provided by an embodiment of the present invention;

[0028] Fig. 9 A flowchart of another method for accessing registers in a super-large-scale chip provided by an embodiment of the present invention;

[0029] Fig.10 A flowchart of another method for accessing registers in a super-large-scale chip provided by an embodiment of the present invention;

[0030] Fig.11 A schematic diagram of a data transmission process in an access method provided in an embodiment of the present invention;

[0031] Fig.12 It is a schematic diagram of the existing PCIe bus structure;

[0032] Fig.13 A schematic diagram of the structure of a multi-thread transmission device provided by an embodiment of the present invention;

[0033] Fig.14 A schematic diagram of the structure of a logic manager in a multi-thread transmission device provided by an embodiment of the present invention;

[0034] Fig.15 A schematic diagram of the structure of a slave endpoint module and a master endpoint module in a multi-thread transmission device provided by an embodiment of the present invention;

[0035] Fig.16 A schematic diagram of the data interaction process between PCIe Logic and DMA channel architecture in a multi-threaded transmission device provided by an embodiment of the present invention;

[0036] Fig.17 A flow chart of a multi-thread transmission method provided by an embodiment of the present invention;

[0037] Fig.18 A schematic diagram of the message interoperation process between DMA and PCIe in the multi-threaded transmission method provided by an embodiment of the present invention;

[0038] Fig.19 A schematic diagram of a data transmission process of a multi-threaded transmission method provided by an embodiment of the present invention in a certain scenario;

[0039] Fig. 20 A schematic diagram of the use of the multi-thread transmission device and method provided by an embodiment of the present invention in a certain scenario;

[0040] Fig.21 A schematic diagram of the data transmission process of the multi-threaded transmission device and method provided in an embodiment of the present invention in a certain scenario. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0042] The present invention is an architecture of a specific functional system, so the specific embodiments mainly illustrate the functional logical relationship between the various structural modules, and do not limit the specific software and hardware implementation methods.

[0043] In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0044] Embodiment 1:

[0045] In order to enable fast and efficient access to chip registers or table entries and optimize the fast addressing access of ultra-large-scale chips, this embodiment proposes an access device for registers in ultra-large-scale chips. By using multiple ring buses to form a multi-layer flower ring bus structure, the register access delay is effectively reduced, the processing performance is increased, and the unified, safe, and supervisory chip access effect is ensured.

[0046] like Figure 1 , is a schematic diagram of the access device architecture of an embodiment of the present invention. The ultra-large-scale chip includes multiple subsystems or submodules. The registers on different subsystems or submodules can be connected using a ring bus. When addressing, the registers on each ring bus can be addressed separately, the address space used is small, and the data transmission path is short. Specifically, the access device includes: at least two ring buses, each of which is connected to at least one register node to be accessed (i.e. Figure 1 The ring bus connects the corresponding register group (i.e. Figure 1 Unit) in the ring bus for data exchange, and each register group contains one or more registers. Further, in a general scenario, each subsystem or submodule is distributed in multiple clock domains, and the clock signals of each clock domain can be the same or different. In this embodiment, in order to avoid clock asynchrony, the subsystems or submodules in each ring bus need to be located in the same clock domain.

[0047] In this embodiment, in order to facilitate the management of the communication between the ring bus and the external interface of the chip, the external interface will not be mounted on each ring bus, but multiple ring buses are organized into a multi-layer rosette structure, which mainly includes three key nodes, namely the master node (Master), the branch node (Branch) and the register node (Nest). Master and Branch are used to divert and aggregate data on different transmission channels between the main ring and the sub-ring. In the specific implementation, the ring bus where the master clock node of the clock domain is located is used as the main ring. The main ring exchanges data with the device outside the chip through the direct memory access interface and manages the sub-ring mounted on it; the ring bus that does not contain the master clock node of the clock domain is used as the sub-ring, and each sub-ring exchanges data with the main ring through a branch node of the clock domain. All register nodes in the subsystem of one or more sub-rings in the same clock domain of the chip can be connected in each sub-ring. The branch node is located at the intersection of the main ring and the sub-ring to complete the clock domain crossing of the data, as well as the diversion and aggregation functions of data on different sub-rings. In actual implementation, the level of the multi-layer ring bus can be determined according to the level of the chip system structure. Figure 1 Taking the rosette structure composed of a two-layer ring bus as an example, when there are more layers of structures, the sub-ring of the next layer can be mounted on the sub-ring through the branch node, but different sub-rings cannot cross each other.

[0048] In a specific scenario, such as Figure 1 As shown, the peripheral device interface is a fast peripheral component interconnect express (PCIe) interface, which is a high-speed serial computer expansion bus standard; the direct memory access interface (DMA) is a high-speed data transmission operation that allows data to be directly read and written between peripheral devices and memory, without going through the CPU or requiring CPU intervention. DMA and PCIe can be channels for high-speed data transmission in hardware. In this scenario, when external software (SW) needs to access registers in the chip, it needs to write the required data to the DMA cache through the CPU, and the DMA controller and PCIe interface move the data to the Master node, and then enter the main ring through the Master node. In actual implementation, the number of Master nodes on the main ring can be determined according to the number of external interfaces or DMAs that need to interact with data, and the number of sub-rings can be determined according to the number of subsystems, sub-modules or clock domains. Each sub-ring can only be mounted on one main ring.

[0049] like Figure 2As shown in the figure, it is a block diagram of the Nest node on the sub-ring, including: register data queue (first input first output, abbreviated as FIFO), channel (Pipe) module, event (Event) module and register data aggregation (i.e. Figure 2 The register data queue caches the input data of the sub-ring and pushes the input data to the channel module; the channel module writes the input data to the specified register or table item in the register group through the access interface, or the channel module obtains the output data of the specified register in the register group or the output data of the table item through the access interface, and pushes the output data to the register data aggregation module; the event module obtains the event data reported by the register group through the event interface, and pushes the event data to the register data aggregation module; the register data aggregation module receives the output data and event data, and merges the output data and event data into one path and outputs them to the sub-ring.

[0050] In the specific implementation, the group ID (Unit Identity Document, abbreviated as UID) can be used to identify the register node where the register to be accessed is located. The FIFO receives the input data passed in on the sub-ring. The Pipe module extracts the UID in the input data and determines whether it matches the register node address it manages. If the UID matches the address of the register node, the access address and operation instructions in the input data are parsed, and the operation instructions are sent to the register group to which it is connected through the access interface to perform the specific access operation. Otherwise, the input data is output to the next Nest node. When the access operation is completed, the Nest node receives the reply data of the register group to the operation instruction and returns it to the sub-ring. At the same time, the Event module is responsible for collecting the alarm information of the register and actively sending the alarm information to the sub-ring.

[0051] Furthermore, there is also a Nest node on the main ring, which can be used as a register group or table entry to connect to peripheral devices, so that the access device can directly access a specific register group or management table entry of a peripheral device through the Nest node. A specific register group or table entry of a peripheral device can be connected to the Nest node on the main ring through a specific interface. The Nest node on the main ring can also identify and collect data matching the UID based on its own unique UID, and parse the data into operating instructions of the register or table entry to access the corresponding register and table entry; at the same time, the Nest node is also responsible for specifying the access to the register or table entry and reporting the Event event to the CPU.

[0052] like Figure 3 As shown in the figure, it is the master node block diagram, including: main ring receiving queue (FIFO_rx), main ring sending queue (FIFO_tx), main ring aggregation module ( Figure 3 "aggregation" in) and the main ring split module ( Figure 3 In addition, in some implementation scenarios, the main ring local queue (Local FIFO) can also be used to manage data that does not need to be output to the outside or needs to continue to be transmitted on the main ring in some scenarios. Specifically: The main ring receive queue caches the input data passed in by the direct memory access interface, and pushes the input data to the main ring aggregation module. The main ring send queue caches the output data passed in by the main ring shunt module, and outputs the output data through the direct memory access interface. The main ring aggregation module obtains the output data pushed by the main ring receive queue and the main ring local queue, merges the output data into one channel, and then outputs it to the main ring. The output data includes the input data passed in by the direct memory access interface and the data shunted by the main ring shunt module that needs to continue to be transmitted on the main ring. When merging, the data of the two channels are only passed into the same transmission channel, and no data connection or merging is performed. The main ring shunt module receives input data from the main ring and shunts the input data to the main ring send queue and the main ring local queue. Data that needs to be output to the outside is shunt to the main ring send queue, and data that needs to continue to be transmitted on the main ring is shunt to the main ring local queue. The main ring local queue caches the input data from the main ring shunt module and pushes the input data to the main ring aggregation module.

[0053] In the specific implementation, the MasterID can be used to distinguish the data that is about to enter the main ring and the data returned by the main ring. When the data enters the Master node, the MasterID is added to it and recorded, and then the data with the MasterID added is transmitted to the main ring; when the data returned from the main ring enters the Master node, the main ring shunt module determines whether the MasterID of the data matches the recorded MasterID. If it matches, the corresponding data is extracted and returned to the DMA. For data with unmatched MasterID, it is transparently transmitted to the main ring aggregation module through the main ring local queue and continues to be transmitted on the main ring.

[0054] Furthermore, the main ring shunt module may discard the message according to the discard signal. When the message contains the discard signal, the main ring shunt module will discard the message.

[0055] like Figure 4 As shown in the figure, it is a block diagram of the Branch node, including: sub-ring diversion module ( Figure 4 "Diversion" in the sub-ring aggregation module ( Figure 4Aggregation in), sub-ring input queue (asynchronous FIFO1) and sub-ring output queue (asynchronous FIFO2). In the specific implementation, the Branch node needs to connect the different clock domains of the main ring and the sub-ring. In order to realize cross-clock domain caching, the sub-ring input queue and the sub-ring output queue need to use asynchronous cache queues. Specifically: the sub-ring shunt module is located in the clock domain of the main ring. The sub-ring shunt module receives the input data transmitted by the main ring, and sends the input data that needs to be processed by the current sub-ring into the sub-ring input queue so that the data enters the current sub-ring, and sends the input data that needs to be processed by other sub-rings into the aggregation module so as to continue to be transmitted on the main ring. The sub-ring aggregation module is located in the clock domain of the main ring. The sub-ring aggregation module receives the output data in the sub-ring shunt module and the sub-ring output queue, and merges the output data into one path and then outputs it to the main ring, wherein the output data of the sub-ring shunt module is the data that needs to continue to be transmitted on the main ring, and the output data in the sub-ring output queue is the data output by the register in the current sub-ring. Similarly, when merging, only the data transmission channels are merged, and no data connection or merging is performed. The sub-ring input queue receives the input data from the sub-ring shunt module according to the main ring clock, and pushes the input data to the sub-ring according to the sub-ring clock. The sub-ring output queue receives the output data from the sub-ring according to the sub-ring clock, and pushes the output data to the sub-ring aggregation module according to the main ring clock.

[0056] In actual implementation, when the input data transmitted on the main ring passes through each Branch node, the Branch node diverts the input data on the main ring based on the UID of the data. In order to facilitate addressing, the UIDs of all register groups on each sub-ring can use a continuous address range. The sub-ring diversion module extracts the UID of the data and performs range matching on the UID. When the UID is within the address range of the current sub-ring, it meets the UID condition of the current Branch node, and the input data passes through the Branch node to the current sub-ring; otherwise, the input data is transparently transmitted to the sub-ring aggregation module. The sub-ring aggregation module aggregates the transparently transmitted data and the data returned from the sub-ring, and then continues to transparently transmit along the main ring to the next Branch node and then returns to the main ring for transmission. On the other hand, for the data returned from the sub-ring to the main ring, after crossing the clock domain through the Branch node, it continues to be transmitted along the main ring together with the transparently transmitted data.

[0057] It can be seen that in the access device provided in this embodiment, a multi-layer garland structure surrounding the entire chip is used to access registers or table entries on the chip, spanning multiple subsystems through different sub-rings, and associating different sub-rings through the main ring, so that chip access messages can be transmitted unidirectionally on the multi-layer ring bus of the garland structure. Multiple information can be transmitted on each ring bus at the same time, and access to subsystems on different ring buses does not affect each other, and is returned to the CPU via the shortest path after the access is completed. The access device provided in this embodiment is suitable for fast addressing access in ultra-large-scale and ultra-large address space scenarios, improves register access efficiency, reduces access latency, and realizes direct reporting and rapid processing of collaborative events or errors, thereby improving the overall performance of software and hardware.

[0058] Embodiment 2:

[0059] In the access device for registers in the ultra-large-scale chip provided in the above embodiment 1, in order to facilitate addressing and management of data, the data can be encapsulated according to a specified access protocol. In this embodiment, an access protocol that can be used is provided. It can be understood that the definition of the access protocol is only used as a reference for the form of access protocol that can be used in actual implementation, and is not used as a limitation on the scope of protection.

[0060] The access protocol provided in this embodiment is used to access registers and table entries in the chip, and is transmitted unidirectionally in the access device provided in Example 1. Its message format is as follows: Figure 5 As shown, in order to match the common communication protocol, the message includes 16 bytes of header information, which includes an address part and an attribute part; in order to adapt to the data bit width supported by different registers, the message also includes a variable length data part. In the embodiments of the present invention, the data message encapsulated by the access protocol provided by this embodiment is referred to as a message for short without causing ambiguity.

[0061] The address part includes the group ID (UID) and the access address (Addr). The group ID is used to match the corresponding sub-ring and register node, and the access address is used to match the corresponding register in the register group. Figure 5It can be seen that the access address is a two-segment addressing: {UID+Addr}, which can better support large address spaces. UID is used to match and find the corresponding sub-ring and Nest. Each Nest has a unique UID, and the Nest address in each sub-ring is in the same address range. It is more efficient to use range matching when matching sub-rings. After entering the corresponding sub-ring, the UID is further used to accurately match the destination Nest. Using this method for addressing, each message only needs to pass through part of the main ring + part of the sub-ring to reach the destination Nest, which greatly shortens the path taken by the message and can reduce the search delay. Addr is used to match and find the corresponding register in the Nest. The address space in the ultra-large-scale chip is very complex, and the original linear address is not suitable. The two-segment addressing can better support large-scale address space.

[0062] The attribute part is used to carry the attribute information of the protocol message, so that the access device can process the protocol message according to the attribute information.

[0063] The attribute part usually needs to include the OpCode field, the value of which is the operator for register access: Read (Rd) is read, indicating that the data in the register needs to be read; Write (Wr) is write, indicating that data needs to be written to the register; ReadWrite (RdWr) is read-clear, indicating that the register data is read first, and then all 0 values ​​are written to the register to clear the register.

[0064] Furthermore, in a specific implementation, since the DMA operation is task-oriented, and PCIe and DMA can support multi-threaded data reading and writing to execute multiple tasks simultaneously, the attribute part can include a task ID (JobId) field to identify a specific task. The task ID field is used to identify each register access task initiated by the external CPU, and the value of the task ID field is mapped one-to-one with the data page address of the external CPU. By using the JobID field, the software running on the CPU can initiate one or more register access request Jobs at a time. In order to facilitate data transmission, in this embodiment, each task can apply for one or more memory pages (Page), and each Page stores one or more chip access messages (Lizard messages), and the size of the Page can be configured according to the actual needs of data reading and writing. In this way, the device in Example 1 can support multi-user multi-tasking, batch reading and writing, and pipeline processing. In the specific implementation, when the software running on the external CPU initiates a memory access task, the software will map the task ID of the memory access task with the data page address (page Addr), so that the DMA on the chip can determine which page to obtain data through the task ID and directly fetch the data to the chip; if it is a reply message from the chip, it will request a free data page address (free page Addr) from the external CPU in the DMA, map the task ID with the page Addr, transfer the output data to the page in the external CPU, and the CPU can obtain the data replied by the chip. In the actual implementation, Lizard messages can include messages sent by the CPU to the chip, messages replied by the chip to the CPU, and messages notified by the chip to the CPU of events.

[0065] The data part carries the data that needs to be written into the register, or carries the data obtained from the register, or carries the data actively reported by the register. In the specific implementation, the Data field is used to store specific register field data. The field segment used is Figure 5 Indicated in.

[0066] Furthermore, in order to facilitate the definition of the boundaries of a single message, in the access protocol provided in this embodiment, data verification ensures the reliability of data transmission. Verification errors can be filled in the message Corrupt field, skipping the operation and returning to SW, which decides whether to retransmit.

[0067] The device provided in Example 1 includes multiple sub-rings, and the multiple sub-rings are connected to the same main ring, and each sub-ring is connected to registers in different subsystems. In some scenarios, the clock domains of different subsystems may be different, and congestion may occur in the transmission process of the message when accessing the local register and the table entry. In order to ensure the reliability of the message in transmission, each ring has a back pressure mechanism (BackPressure, abbreviated as BP) to support the flow control of the Bursts access scenario. Specifically: when any register node has a burst state and reaches the upper limit of the processing capacity, the back pressure domain of the protocol message in the storage data queue of the previous level register node is set to the first signal value to instruct the register data queue to suspend data push; when the register node resumes normal operation, the back pressure domain of the protocol message in the storage data queue of the previous level register node is set to the second signal value to instruct the register data queue to resume data push. In actual implementation, the high level is used as the first signal value and the low level is used as the second signal value. When a certain Nest on the ring bus has Bursts and reaches the upper limit of the processing capacity, the back pressure signal transmitted to the previous Nest will be pulled high. At this time, the data of the previous Nest will be blocked until the back pressure of the next stage is lowered, and the data will continue to be transmitted to the next stage. Since the Nest is equipped with a register data queue for caching, it can determine whether to back pressure the previous stage by detecting whether the amount of data cached in the queue exceeds the waterline. The back pressure mechanism can effectively avoid congestion and is better suitable for Bursts access scenarios. When Flush is pulled high, the cached data in the current subsystem is quickly cleared to meet the scenario requirements during software upgrades.

[0068] In the access protocol provided in this embodiment, the domain segments of the attribute part can be set according to the actual access needs and control needs. The following simply provides some domain segment definitions that can be used as a reference. It can be understood that the following domain segment definitions are only design examples of access protocols in specific scenarios and are not intended to limit the scope of protection.

[0069] In some scenarios, in order to meet the event or error reporting requirements of the register, in the access protocol provided in this embodiment, the data part of the message is also used to carry alarm (Alert) events or abnormal events, and can also support defect subscription of the register. When used for reporting, the message is sent from Nest and sent to the CPU through the access device. The JobId of the event (Event) uses a specified fixed value and is reported directly to the CPU. The CPU can obtain all the information without reading the register separately. Events can be selectively blocked and subscribed to effectively avoid burst message overflow. In this scenario, the data format of the access protocol is as follows Figure 6 As shown, the bold part is the valid domain segment.

[0070] In some scenarios, the attribute part can also support error identification and monitoring functions. For example, using the specified field value in the message to indicate the following information: whether the parity check or cyclic redundancy check of the message has passed, whether the message has reached the specified address, whether the register corresponding to the address exists, and the number of sent and received messages.

[0071] In order to avoid congestion between software flows, when using the access protocol provided in this embodiment for data transmission, if it is a high-priority service, it will be processed faster and will not be blocked by other flows. This is due to the fact that DMA is based on task processing and software flows cannot share DMA Pages. Messages are only transmitted on the ring bus and the destination sub-ring. To increase performance, message reordering can be allowed. DMA supports reordering and job distinction. For DMA read operations, because DMA can achieve reorganization and reordering, it is allowed to initiate additional read operations before the first read reply is received, thereby better improving read efficiency.

[0072] The access protocol provided in this embodiment can meet the data transmission needs of the ring bus system in Embodiment 1 and complete the basic functions of chip configuration and status monitoring. The access protocol has the following specific advantages:

[0073] 1) The message of the access protocol starts from the software system SW, passes through PCIe and DMA, is transmitted through the multi-layer ring bus system surrounding the chip, and finally returns to SW through PCIe and DMA, meeting the data transmission needs of the access device of Example 1.

[0074] 2) SeqNo is used to identify the position of the message in the Page, thereby allowing the message to be reordered. The access path is optimized through a multi-layer ring bus to ensure low latency in accessing the device.

[0075] 3) Using the two-segment address structure of UID+Addr, messages can be transmitted in the form of a wreath in different sub-rings, making the sub-rings flexible and scalable.

[0076] 4) Use the variable-length data portion and the Length field to support variable-length register data bit widths.

[0077] 5) Use the JobID field to identify each different access task, support DMA multi-threading and priority, and support multi-user multi-task pipeline operation.

[0078] 6) The data part of the message can carry event data, support a fast event reporting mechanism, and allow the bottom layer to send event or error messages directly to the CPU, facilitating fast event processing.

[0079] Embodiment 3:

[0080] Based on the device for accessing registers in a very large-scale chip provided in the above-mentioned embodiment 1, the present invention further provides a method for accessing registers in a very large-scale chip.

[0081] The access method provided in this embodiment is implemented in the following scenarios: Figure 7 As shown in the figure, the access request is initiated by the Software Development Kit (SDK) running on the CPU and driven by the MSG (Message, abbreviated as MSG) module. The MSG module accesses the chip through the chip driver running in the kernel space, supports the sending of single or batch read / write messages, and is used to provide other applications with an interface for accessing the chip or debugging, such as: Table entry read / write, chip important module configuration, Event event acquisition, and register read / write, etc.

[0082] like Figure 8 As shown, the method for accessing registers in a very large-scale chip provided by an embodiment of the present invention can be implemented in the following manner.

[0083] Step 101: The external CPU transmits the input data to the main node through the direct access interface. The input data is transmitted unidirectionally along the main ring starting from the main node, and the input data matching each sub-ring is transmitted to the sub-ring through the corresponding branch node. The input data is transmitted unidirectionally along the sub-ring starting from the branch node until it reaches the corresponding register node on the sub-ring.

[0084] The main ring exchanges data with devices outside the chip through the direct memory access interface. Specifically, the external CPU transmits input data to the direct memory access interface through the peripheral device interface, and the direct access interface transmits input data to the main node. The input data is transmitted from the main node along the main ring to the corresponding register node on the main ring, or the input data of each sub-ring is transmitted to the sub-ring through the branch node. The branch node receives the input data transmitted from the main ring, and the input data is transmitted from the branch node along the sub-ring to the corresponding register group on the sub-ring.

[0085] Step 102: The output data of the register node on the sub-ring continues to be transmitted unidirectionally along the sub-ring until it returns to the branch node. The branch node transmits the output data to the main ring. The output data of each sub-ring continues to be transmitted unidirectionally along the main ring until the output data returns to the main node. The main node transmits the output data to the external CPU through the direct memory access interface.

[0086] Each sub-ring exchanges data with the main ring through a branch node. Specifically, the output data of the register node on the sub-ring continues to be transmitted unidirectionally along the sub-ring until it returns to the branch node, and the branch node transmits the output data to the main ring. The output data of each sub-ring or the output data of the register group on the main ring continues to be transmitted unidirectionally along the main ring until the output data returns to the main node. The main node passes the output data to the direct memory access interface, and the direct memory access interface transmits the output data to the external CPU through the peripheral device interface.

[0087] After step 101 to step 102 provided in this embodiment, the reading and writing of register data can be quickly completed through the device provided in embodiment 1.

[0088] like Fig. 9 As shown, in the method for accessing a register in a super-large-scale chip provided by an embodiment of the present invention, when data is written to the register or an operation instruction is sent to the register, the specific steps for writing data to the register are as follows:

[0089] Step 201: According to a specified access protocol, the external CPU encapsulates data for register access as input data.

[0090] When the user thread in the SDK needs to access the register, in order to use the access device provided in Example 1 for data transmission, it is first necessary to encapsulate the access request and the access address as input data according to the specified access protocol, and the encapsulated input data is transmitted in the access device provided in Example 1 in the form of a message. For the sake of simplicity of description, the access protocol provided in Example 2 is used as the specified access protocol in this embodiment. In actual implementation, the access protocol can be defined and used according to actual needs. Figure 7 In the figure, #job1, job2, ..., #jobn are the JobIds of different access requests, and their transmission directions are indicated by dotted arrows.

[0091] Step 202: input data is transmitted from the direct memory access interface to the access device provided in Example 1. The input data enters the main ring through the main node and is transmitted unidirectionally in the main ring in a first direction.

[0092] The input data enters the auto send thread of the MSG module, and is then pushed to the DMA in the chip by the MSG module through PCIe. The data path for the input data to be transmitted in the chip is the access device provided in Example 1, wherein the master node located on the main ring in the access device is the one that interacts with the outside world, so the input data first enters the main ring through the master node. In actual implementation, the first direction can be selected as clockwise or counterclockwise as needed.

[0093] Step 203: according to the group ID in the input data, the input data is transmitted to the corresponding sub-ring through the corresponding branch node on the main ring, and is unidirectionally transmitted in the sub-ring in the second direction.

[0094] The access protocol provided in Example 2 uses a two-segment address encoding, including a group ID (UID) and an access address (Addr). Among them, the UID is used to match the Uint that the input data needs to access, and each Nest corresponds to a Uint. Therefore, the Nest that the message needs to enter can be determined by the Unit address associated with the Nest. In order to facilitate address matching, the addresses of all Units on each sub-ring are included in the address range of the sub-ring, and the input data can be quickly transferred to the sub-ring where the Nest to be accessed is located. Since the data is transmitted independently in each ring bus, in actual implementation, the second direction can be the same as the first direction, or it can be different from the first direction.

[0095] Step 204: According to the group ID in the input data, the input data is transferred to the corresponding register node on the sub-ring, and the corresponding register is accessed according to the access address.

[0096] After the input data reaches the corresponding Nest, the register to be accessed can be found in the Unit corresponding to the Nest according to the Addr.

[0097] Step 205: Write the data portion of the input data into the corresponding register, or obtain the data in the register according to the operation indicated by the attribute portion of the input data.

[0098] After finding the register to be accessed, the corresponding operation can be performed on the register according to the operation instructions in the input data.

[0099] After steps 201 to 205 provided in this embodiment, the access request sent by the SDK can be sent to the corresponding register.

[0100] On the other hand, Fig.10 As shown, in the method for accessing registers in a super-large-scale chip provided by an embodiment of the present invention, when data in a register is obtained or a register reports an event, the specific steps for reading data from the register are as follows:

[0101] Step 301: encapsulate the acquired data or reported event data into output data according to the specified access protocol.

[0102] In order to use the access device provided in Example 1 for data transmission, it is necessary to encapsulate the register data and the reported events into output data according to the same access protocol, and the encapsulated output data is transmitted in the form of a message in the access device provided in Example 1. Similarly, the range protocol provided in Example 2 is also used as an example for explanation below.

[0103] Step 302: The output data is transmitted on the sub-ring in the second direction back to the branch node on the current sub-ring, and enters the main ring through the branch node.

[0104] The output data continues to be transmitted in the sub-ring in the same direction as the input data until it returns to the Branch, and then returns to the main ring through the Branch.

[0105] Step 303: The output data is transmitted back to the master node on the primary ring in the first direction, and is output to the direct memory access interface through the master node.

[0106] After returning to the main ring, the output data continues to be transmitted in the main ring in the same direction as the input data until it returns to the Master, and then is output by the Master to the receiving thread (Receive Tread) of the MSG module. Figure 7 In the figure, #job1, job2, ... #jobn indicated by the solid arrows are the output data of the same JobId input data, so they need to be returned to the UserThread for processing; #jobE indicated by the solid arrow is the output data of the register reporting event, which needs to be output to a separate event processing thread (Event Thread) for corresponding event processing. Another fast mode is supported, where the task ID is fixed to F, and the output data (i.e., Turbo data packet) returned by the write message is recognized and directly discarded by the hardware. The user does not have to wait for a reply, and excellent throughput can be achieved when the table item is upgraded.

[0107] After steps 201 to 203 provided in this embodiment, the data returned by the register can be sent back to the SDK.

[0108] In actual implementation, the data in each ring bus is transmitted unidirectionally, and the data transmission directions in different ring buses can be the same or different. Fig.11As shown in the figure, the first direction and the second direction of transmission on all ring buses are clockwise. The message transmission path to the register is represented by a solid arrow, and the message transmission path returned by the register is represented by a dotted arrow. When it is necessary to access the Nest B node, the message enters the access device from the Master node, is transmitted in a clockwise direction to the Branch A node, and enters the sub-ring from the Branch A node; then the message starts to be transmitted clockwise in the sub-ring from the Branch A node, passes through the Nest A node, and accesses the corresponding register after reaching the Nest B node. After completing the access to the register, the Nest B node returns to the sub-ring, continues to transmit clockwise on the sub-ring, passes through the Nest C node, returns to the Branch A node, and then returns to the main ring from the Branch A node; after returning to the main ring, it continues to transmit clockwise on the main ring, passes through the Branch B node, returns to the Master node, and then outputs it outside the chip from the Master node. It can be seen that using the access device provided in this embodiment, the access path to a register only needs to pass through a main ring and a sub-ring, and only needs to pass through the registers in one subsystem without passing through the sub-ring where the Branch B node is located. There is no need to perform address matching on the registers in all subsystems in the entire chip. Since the number of registers in a subsystem is much lower than the total number of registers in the chip, the access method provided in this embodiment can significantly shorten the access path length of the registers.

[0109] In a specific scenario, a single read operation can be performed. Since different subsystems have different UIDs, the target subsystem can be found through the UID, and then the target register can be found through the Addr. In another specific scenario, a write operation is performed on a read-only register, and a register read error will occur.

[0110] At the same time, since the access device of Example 1 includes multiple independent ring buses, and the access tasks can be distinguished by JobId in the access protocol of Example 2, the access method provided in this embodiment also supports batch reading and writing of registers.

[0111] The method for accessing registers in a super-large-scale chip provided in this embodiment can quickly access registers in super-large-scale chips and complex address scenarios based on the access device provided in embodiment 1 and the access protocol provided in embodiment 2, and can support batch access, and has high practicality. The method is both scalable, fast and efficient. It has guiding significance for the technical development in the field of chip access.

[0112] Embodiment 4:

[0113] PCIe is a high-speed serial bus used to connect various peripheral devices. The PCIe bus is mainly divided into three protocol layers. From bottom to top, they are the physical layer, data link layer, and transaction layer. Each layer has the ability to send and receive data packets at the corresponding layer. Data is generated at the user layer of the device, and a transaction layer packet (Transaction LayerPacket, abbreviated as TLP) is generated at the transaction layer. It is packaged layer by layer and transmitted to the transmission interface (Transmit, abbreviated as TX) of the physical layer of the device. TX pushes the packaged complete data frame to the PCIe link. The peer device receives the data packet through the receiving port (Receive, abbreviated as RX), and then parses the data packet layer by layer and uploads it to the user layer of the peer device.

[0114] by Fig.12 Taking the existing PCIe bus structure as an example, the three-layer functions of the PCIe controller (PCIe Core) are as follows:

[0115] (1) The physical layer mainly implements link training and initialization, encoding and decoding, etc., and is used to connect the serializer / deserializer (SERializer / DESerializer, abbreviated as SerDes) to achieve physical transmission;

[0116] (2) The data link layer is mainly responsible for creating (sending) or parsing (receiving) data link layer packets (Data Link Layer Packet, abbreviated as DLLP), and implements CRC error detection and correction, sequence-preserving retransmission, flow control, and power management functions;

[0117] (3) The transaction layer is mainly responsible for creating (sending) or parsing (receiving) transaction layer messages TLP packets, flow control, quality of service (QoS), transaction sorting, etc.

[0118] DMA transfer is a way to transfer massive data between a PCIe interface peripheral device and host memory or between host memory and a PCIe interface peripheral device. Hereinafter, the PCIe interface peripheral device is referred to as an endpoint device. In general usage scenarios, DMA read and write transfers are usually initiated by the endpoint device. Whether it is DMA read or DMA write, the endpoint device needs to submit an interrupt request through the PCIe interface to inform the host. Although the current DMA reduces the involvement of the CPU, it does not support multiple users, and the next read and write may be initiated after the previous read and write is completed, which limits performance and efficiency.

[0119] In the traditional PCIe system, the Master device generates and sends PCIe packets (TLP) as the initiator, and the Slave device receives and decodes the TLP packets. Usually, the CPU acts as the Master device and initiates read and write operations to the memory in the peer peripheral. However, the CPU may be busy when the response is returned and cannot receive and process it in time, or due to the delay in the response of the read operation inside the peripheral device, the channel back pressure may be blocked, thereby affecting the performance of the CPU.

[0120] To effectively improve this problem, the most effective method is to use DMA. DMA does not require CPU participation, so it does not occupy CPU resources and is suitable for large-capacity data transmission. However, its disadvantage is that the real-time performance is poor and the CPU can only participate in control through interrupts. Therefore, this method also has the following technical problems:

[0121] 1. When data is transmitted between the existing CPU and PCIe devices, either the CPU acts as the Master and the peripheral device acts as the Slave, or the peripheral device acts as the Master and the CPU acts as the Slave. If different types of data are transmitted bidirectionally between the peripheral device and the CPU, both Master / Slave modes must be supported;

[0122] 2. If the peripheral actively reports data that needs to be transmitted to the CPU, it is generally interrupted to allow the CPU to receive it. Frequent interrupts will occupy CPU resources.

[0123] 3. When the device reads TLP from the CPU, the next TLP read can only be initiated after the previous read response (Completion) is returned. If the read delay is high, it will greatly affect the transmission performance. Therefore, it is necessary to initiate additional read requests before receiving the first TLP read completion, so as to support DMA multi-threaded transmission;

[0124] 4. When the user has multiple data transmission task requirements, especially when there is a priority transmission requirement within the limited range of the PCIe controller, the existing DMA cannot prioritize and adjust high-priority tasks according to user needs.

[0125] In order to solve the above technical problems, further improve transmission performance and transmission efficiency, and reduce the number of interactions between the host and hardware and the number of interrupts generated, this embodiment provides a multi-threaded transmission device, so that DMA can support multi-threaded processing and priority transmission.

[0126] like Fig.13As shown, the device includes: a serial deserializer (PCIe SerDes), an interface controller (PCIe Core), a logic manager (PCIe Block Interface Logic, referred to as PCIe Logic) and a direct memory access controller (DMAController, hereinafter referred to as DMA controller).

[0127] The PCIe interface is connected to the CPU through a serial deserializer, which deserializes the received physical layer message into a transaction layer message (TLP message) and inputs it into the interface controller, and serializes the transaction layer message generated by the interface controller into a physical layer code stream and outputs it to the CPU.

[0128] The interface controller processes the transaction layer messages input by the serial deserializer or the logic manager, and / or generates the transaction layer messages that need to be output by the serial deserializer or the logic manager. In actual implementation, the serial deserializer (PCIeSerDes) and the interface controller (PCIe Core) can select the standard IP core that meets the needs, and the PCIeCore can also be expanded as needed.

[0129] In the device provided in this embodiment, in order to allow PCIe to obtain lower transmission latency and increase processing performance, a logic manager (PCIe Logic) is added between the PCIeCore and the DMA controller to distribute and process data. The logic manager interacts with the interface controller through transaction layer messages. The logic manager generates chip access messages of a specified format from the transaction layer messages, and outputs the chip access messages to the direct memory access controller in a pipeline form, and / or receives chip access messages input by the direct memory access controller in a pipeline form and generates corresponding transaction layer messages. Fig.13 As shown, PCIe internal TLP messages are transmitted between PCIe Core and PCIe Logic. When PCIe Core receives a PCIe TLP message, it will detect the correctness of the format and determine whether it is a flow control message or a configuration message. If it is a flow control message, it will be terminated in the PCIe Core; if it is a configuration message, it will be submitted to PCIe Logic for subsequent processing or forwarding by PCIe Logic. In actual implementation, in order to facilitate the transmission of TLP messages, the logic manager and the interface controller can use the TLP interface to communicate with each other, or other bus interfaces such as AXI (Advanced eXtensible Interface) can be selected as needed.

[0130] The direct memory access controller receives a chip access message, outputs data to the outside of the device through a direct chip access interface, and / or receives external input data through a direct chip access interface and converts it into a chip access message.

[0131] like Fig.14 As shown, the logic manager includes: a receiving module (RX Transaction decoder, abbreviated as RXdecoder), a sending module (TX Transaction Arbitration, abbreviated as TX Arbitration), a slave endpoint module (pcie_slave), a master endpoint module (pcie_master) and an interface dependency module (interface Shim). The receiving module is used to receive transaction layer messages, parse and identify the transaction layer message type, and transmit the transaction layer message to the master endpoint module or the slave endpoint module after decoding; the sending module is used to receive the transaction layer message generated by the master endpoint module or the slave endpoint module, and transmit the transaction layer message to the interface controller; the slave endpoint module is used to parse the base address space of the data read and write in the transaction layer message, and generate the corresponding bus signal to transmit to the direct memory access interface; the master endpoint module is used to determine whether the transaction layer message is an expected reply, and / or, to generate a chip access message of a specified format; the interface dependency module serves as a data interface between the master endpoint module and the direct memory access interface, and as a data interface between the slave endpoint module and the direct memory access interface.

[0132] like Fig.15 As shown, the slave endpoint module includes: a slave endpoint processing component (Slave), an interrupt controller (interruptManager) and a local register group (Local Registers). The slave endpoint processing component exchanges data with the direct memory access interface through a signal bus, and is used to complete the corresponding transaction layer message processing when the device is used as a slave endpoint; the interrupt controller parses the interrupt signal generated by the direct memory access interface and generates an interrupt signal submitted to the CPU; the local register group is used to save the data transmission status in the PCIe interface so that the logic manager can obtain the data transmission status of the PCIe interface.

[0133] like Fig.15As shown, the master endpoint module includes: a master endpoint processing component (Master), a request state machine (Request State Machine), a packet buffer (Packet Buffer), a read response tracking component (Completion Track & Reorder) and a reply buffer (Fragment Buffer). The master endpoint processing component is used to complete the corresponding transaction layer message processing when the device is used as a master endpoint; the request state machine is used to process data packets from the direct memory access interface, so that the device converts the data packets into transaction layer messages in a pipeline form; the packet buffer is used to cache data packets from the direct memory access interface; the read response tracking component is used to process the read response completion message of the transaction layer message, so that the direct memory access interface obtains the response to each transaction layer message, sorts the transaction layer messages and converts them into data packets in a specified format, and sends the converted data packets to the direct memory access interface; the reply buffer is used to cache the transaction layer completion messages that the CPU effectively replies to.

[0134] like Fig.16 As shown, the data interaction between PCIe Logic and DMA channel architecture can be triggered by message messages or signals, such as read / write requests or data pull / push signals, etc. For details, please refer to the following process.

[0135] (1) When writing PCIe / DMA related configurations: The receiving module (pcie_rx) receives a memory write request (MemoryWrite, abbreviated as Mwr) TLP. If it is recognized as accessing the local register (BAR0 register), it is forwarded to pcie_slave through the SlaveRx interface and the local register is configured through RegBus without a reply.

[0136] (2) When reading PCIe / DMA related configurations: pcie_rx receives a memory read request (Memory Read, abbreviated as Mrd) TLP, identifies it as accessing the local register (BAR0 register), and forwards it to pcie_slave through the receiving interface (SlaveRx) of the slave endpoint module, reads the local register configuration through RegBus, and then pcie_slave sends the response (response) of the register read to the sending module (pcie_tx) through the sending interface (SlaveTx) of the slave endpoint, and pcie_tx encapsulates it into a data read completion (Completion with data, abbreviated as Cpld) TLP and sends it back to the CPU.

[0137] (3) When DMA reads data, but it is not a DMA read-associated configuration process: DMA initiates a data pull request (PullReq), pcie_master sends a request to read the dynamic random access memory (DRAM) to pcie_tx through the receiving interface (MasterTx) of the master endpoint module, and pcie_tx encapsulates it into MrdTLP and sends it to the root endpoint (Root Complex, abbreviated as RC) of the CPU; after the CPU's RC takes out the data from the DRAM, it sends it to pcie_rx through Cpld TLP. pcie_rx recognizes it as the returned read DRAM data, and then sends the read data to pcie_master through MasterRx, and pcie_master returns it to DMA through PullResp.

[0138] (4) When DMA writes data, but it is not a DMA write-associated configuration process: DMA initiates a data push request (PushReq), pcie_master sends a DRAM write request (the request includes the data to be written) to pcie_tx through MasterTx, pcie_tx encapsulates it into Mwr TLP and sends it to the CPU's RC, and the CPU's RC writes the data into DRAM.

[0139] (5) When transmitting an interrupt signal, the PCIe standard interrupt process can be used, or the above data reading and writing process can be adjusted.

[0140] In the above data reading and writing process, PCIe Logic will convert all device node accesses to PCIe's BAR0 address space into signal bus request (RegBusReq) operations. At this time, the CPU acts as the master endpoint to dominate the operation. When the CPU wants to transfer data, it initiates a write access to the DMA RX register, writes the JobId and Page address to the BAR0 space, and PCIeLogic initiates a RegBus write request. The data is transmitted to the DMA through the RegBus, and the DMA learns the current JobId and Page address. The CPU will also pre-allocate a free page address for the DMA and write it into the DMA TX register, so that when the DMA has data to transfer to the CPU, it can be directly pushed to the free address space.

[0141] The multi-threaded transmission device provided in this embodiment, relative to the existing PCIe and DMA communication interfaces, additionally adds an interconnection interface logic manager (PCIe Logic Interface Logic) between the PCIe and DMA engines, so that data transmission can take different transmission paths according to different types of data, and supports Master / Slave mode. During the transmission process, the DMA operation does not have to wait for the previous read response to return, and can directly initiate additional TLP read operations. The transmission tasks do not have to be delivered in sequence, and the TLP order preservation and reordering mechanism is supported before being sent to the DMA engine, thereby supporting multi-threaded DMA and improving transmission efficiency.

[0142] Embodiment 5:

[0143] Based on the multi-thread transmission device provided in the above-mentioned embodiment 4, the present invention also provides a multi-thread transmission method for managing the data transmission process in the device.

[0144] like Fig.17 As shown, the specific steps of the multi-thread transmission method provided by the embodiment of the present invention are as follows.

[0145] Step 401: When the peripheral device needs to pull CPU data, the device generates a corresponding memory read request, obtains the corresponding data in the CPU according to the memory read request, and the CPU encapsulates the corresponding data into a transaction layer message and sends it to the device. The device pulls the data in the transaction layer message to the peripheral device through the direct memory access interface.

[0146] In actual implementation, data is exchanged between the RC of the CPU and the PCIe interface through TLP messages. When the CPU needs to send data to a peripheral device, the RC of the CPU encapsulates the data into a TLP message, and then sends the message to the receiving module in the device provided in Example 3 through the PCIe interface. After being processed by the corresponding channel in the device, it is sent to the peripheral device through the DMA interface, and then the peripheral device decapsulates the TLP message to obtain the corresponding data.

[0147] Therefore, when the peripheral device needs to read data from the CPU, it will read the data in the form of a pull (PullReq) request. After receiving the PullReq signal, the CPU initiates the corresponding data pull task. The PCIe controller RC in the CPU directly takes out the data from the DRAM and encapsulates the data into a transaction layer message (compoletion TLP) for replying to the completed read as a response, and sends the compoletion TLP to the receiving module in the form of PullResp. Since the CPU has sent the data page address that the peripheral device needs to read to the configuration space BAR0 in advance in the form of a task, the DMA controller directly pulls the data page data to the DMA interface according to the data page address stored in BAR0, thereby completing the data reading without CPU intervention. In the above process, the process of the CPU taking data and the process of the DMA controller moving data are independent of each other. Therefore, regardless of whether the DMA controller has completed the data pull, the DMA can start a new data reading task again, and the CPU can also issue new tasks multiple times, thereby realizing multi-threaded data transmission.

[0148] Step 402: When the peripheral device actively transmits data to the CPU, the apparatus generates a corresponding memory write request, assembles the data obtained by the direct memory access interface into a corresponding transaction layer message according to the memory write request, and pushes the data to the corresponding data page address through the transaction layer message for use by the CPU when it is idle.

[0149] When the CPU needs to read data from a peripheral device, the peripheral device encapsulates the data into a TLP message, and then sends the message to the direct memory access controller in the device provided in Example 3 through the DMA interface. After being processed by the corresponding channel in the device, it is sent to the CPU through the PCIe interface, and then the CPU unpacks the TLP message to obtain the corresponding data.

[0150] Therefore, when the peripheral device wants to actively transfer data to the CPU, the data is written in a push manner. After the CPU receives the interrupt notification signal that the data has been written, it asynchronously sends the free memory page address to BAR0. The DMA controller directly pushes the data to the free memory page address through DMA (all data pages in the CPU receiving pool are initially configured to be free). The CPU does not need to participate in the reception, and the data can be directly retrieved when the CPU is free. The use of data pages and timed release configurable methods can reduce the number of interactions between the host and the hardware and the number of interrupts generated.

[0151] After step 401 to step 402 provided in this embodiment, data transmission between PCIe and DMA can be completed without CPU intervention.

[0152] In the above process, the TLP message is generated by an external device, and the DMA can directly push the Memory Write data to the CPU's Memory. The Root Complex module in the CPU can directly retrieve the data from the DRAM and return the completion TLP reply message without involving the processor. Therefore, before the first Read is received, additional read requests can also be initiated, achieving a pipeline access effect, so that the data transmission process in each direction can support multi-threaded transmission. In actual implementation, users can initiate multiple transmission tasks and set the priority requirements of each task. DMA gives priority to high-priority tasks based on the principle of high-priority priority. The combined use of PCIe and DMA multi-threading realizes the high-speed transfer of large amounts of data, releases the CPU's computing power and processing waiting time for data transmission, expands the use scenarios of DMA multi-threading, and further improves transmission efficiency.

[0153] Based on the method provided in this embodiment, Fig.15 In the hardware architecture shown, the process of message transmission in PCIe Logic is divided into the following four parts:

[0154] (1) The solid arrow is the process of the CPU sending configuration tasks to PCIe / DMA. The CPU encapsulates the data required for configuration into the corresponding transaction layer message and sends it to the receiving module. The receiving module parses the memory read request or memory write request in the encapsulated transaction layer message and sends the transaction layer message to the slave endpoint module; the slave endpoint module parses the base address in the transaction layer message and uses the request state machine to generate the corresponding bus signal, which is transmitted to the direct memory access interface through the signal bus, and the direct memory access interface performs the configuration processing in the transaction layer message. Specifically: In the above process, the CPU acts as the master and the peripheral device acts as the slave. The CPU encapsulates the configuration data into a compoletion TLP and sends the TLP to the receiving module through the PCIe interface. When the receiving module parses the TLP as a memory request for the PCIe base address register space, it sends the TLP to the slave endpoint module. The slave parses the TLP to obtain the BAR0 starting address, and uses the request state machine to generate the RegBus bus signal and transmits it to the DMA, which performs the corresponding configuration processing. On the other hand, when the peripheral device completes the configuration, it will also encapsulate the JobID related to the configuration task and the Page address used to complete the use into a recovery completion message and return it to the CPU, so that the CPU can know the configuration completion status.

[0155] (2) The dotted arrow is the process of DMA moving data from the CPU. When the transaction layer message is a read response completion message, the receiving module sends the transaction layer message to the master endpoint module, and the master endpoint module compares the received transaction layer message with the request information waiting for reply; when the transaction layer message is the expected reply, a chip access message of the specified format is generated according to the transaction layer message, and the chip access message is sent to the direct memory access interface. Specifically: When the RX decoder parses the TLP as a completion message, it sends the TLP to the master endpoint processing component, and then sends it to the DMA send port (RxDma). After receiving the TLP message, the master endpoint processing component will first compare it with a series of request information waiting for reply. If it is not the expected reply, it will be discarded or an error flag will be added. If it is the expected reply, it will be placed in the FragmentBuffer. The master endpoint processing component is responsible for terminating the PCIe transaction. The TLP messages in each job will be assembled and sorted to generate a chip access message of the specified format and sent to the DMA controller. Furthermore, in order to avoid errors caused by reply timeouts, each reply is equipped with a timer, if a reply is lost, the reply will be discarded and the corresponding timeout error will be alerted to the PCIe Core.

[0156] In the above process, when data is written, the data page address and task number sent by the CPU are obtained from the endpoint module, and the data page address is sent to the direct memory access interface through the signal bus; after the corresponding data page is used up and released, the direct memory access interface returns the released data page address to the CPU. Specifically: The CPU can send the JobId and data page address (Page Address) of the Page to the DMA through the signal bus (RegBus) through a memory write request. After the used Page is released, the DMA will return the Page Address to the CPU, and the CPU obtains the released PageAddress through a memory read request for subsequent use. In this processing flow, the CPU acts as the master endpoint (Master) to send a memory read request or a memory write request to the peripheral device, and PCIe acts as a slave endpoint (Slave) to passively receive the CPU's memory read request or memory write request, thereby completing the corresponding response.

[0157] (3) The dotted arrows represent the process of DMA moving data to the CPU. When the peripheral device sends data to the CPU, the direct memory access interface initiates a memory write request for writing data. The master endpoint module encapsulates the chip access message slices and sends the corresponding transaction layer message. When the data is written to the data page, the CPU receives an interrupt from the memory access interface indicating that the data has been sent. The CPU learns that the data is available based on the interrupt. Specifically: If DMA needs to send data to the CPU, DMA initiates a PCIe transaction. The master endpoint processing component encapsulates the chip access message slices and sends a PCIe TLP message. The DMA send port (TxDma) sends the reply message after the access to the PCIe master endpoint processing component, and then returns it to the CPU via Tx Arbitration.

[0158] (4) The dotted arrows represent the interrupt signal flow. When enough data is accumulated in the DMA cache, or a certain data in the DMA has been waiting for a long enough time, the DMA pushes the data to the corresponding data page address and sends an interrupt request signal to the receiving module; the receiving module uses the interrupt controller to parse the interrupt request signal and generate a corresponding interrupt signal; the interrupt signal is sent to the CPU through the sending module to trigger the CPU interrupt. Specifically: when the peripheral device pushes data to the CPU, after the DMA has pushed the data to the data page address, or while pushing, an interrupt (Message Signaled Interrupts, abbreviated as MSI) request signal will be issued to notify the CPU that the data can be accessed. At this time, the PCIe device receives the interrupt request signal from the external DMA, and the interrupt controller parses these signals and generates an interrupt signal. The interrupt signal is sent to the CPU to trigger the CPU interrupt, such as notifying the CPU that Pages are available.

[0159] It can be seen from the above transmission process that the four processes in PCIe Logic do not affect each other, and the messages can be processed in a pipeline manner, which improves the efficiency of data transmission and processing and facilitates multiple users to access the chip at the same time without affecting each other.

[0160] Based on the above data transmission process, in the method provided in this embodiment, the following can be used: Fig.18 The operation flow shown completes the message interoperation between DMA and PCIe.

[0161] When DMA needs to read data in the CPU's Page, DMA initiates a read request to PCIe Logic in the form of a PullReq request, and then receives a completion response from PullResp. When PCIe receives the response data of PullReq, PCIe Logic returns the data to DMA in the form of a Pull Response, and the message in the Page is moved to DMA. When DMA has data to transfer to the CPU, DMA initiates a write request to PCIe Logic in the form of a Push, and directly pushes the data to the CPU's receiving pool Page.

[0162] In actual implementation, the flow control signal AF (Almost full) can be used to control the transmission process. The AF signal is an indication signal used for data back pressure between PCIe Logic and DMA to avoid data overflow. For example: PushAF corresponding to Push, PullReqAF corresponding to PullReq, and PullRespAF corresponding to PullResp. The Pull operation can be divided into PullReq and PullResp through the flow control signal, so that the data request and reply acceptance have their own independent control signals, thereby improving performance and avoiding blocking or data overflow.

[0163] In the above Pull and Push methods, the chip DMA completes data movement in the form of a master endpoint without the involvement of the CPU. This greatly improves the utilization of DMA and PCIe channels, allowing data to be continuously moved in a pipeline manner. At the same time, because of the cooperation of Job and Page, there is no need to wait for the CPU to take away the data. As long as the Free Page is used to operate the data in the memory, the data returned by the chip can be moved to the CPU.

[0164] In actual scenarios, the method provided in this embodiment can not only complete the data transmission between the CPU and the on-chip registers, but also solve the bottleneck of data communication between the host and the external storage device. Fig.19In the scenario shown, the DMA controller logic design mainly completes the function of actively initiating DMA read and write tasks with the PCIe card device as the Master device. The DMA control status register is mapped in the BAR0 space of the PCIe device. The data transmission direction of the DMA write operation is from the PCIe card to the system host memory. The task of the DMA write transaction is to transfer the data read from the DDR3 SDRAM as external storage to the system memory through the PCIe hard core in DMA mode. The DMA control status register will receive the memory write transaction initiated by the system host to the BAR0 space of the PCIe device. This transaction is to configure the DMA transfer write destination address (PageAddress), DMA transfer length (Page Range) and other DMA working parameters. Then the sending engine starts to send (push) DMA write data to the system host. The task of the DMA read transaction is to read the data of the specified size from the specified address in the system memory to the PCIe device. This transaction is realized by initiating a memory read transaction to the system host through the PCIe device. DMA reads and transfers the data in the system memory to the PCIe device and transfers it to the DDR3 SDRAM. When completing a DMA read or write transaction, the DMA controller decides whether to initiate an MSI interrupt based on the interrupt mask status. When the system host receives an interrupt initiated by the PCIe device, it processes the DMA transfer result.

[0165] The multi-thread transmission method provided in this embodiment has the following beneficial effects:

[0166] 1. From the endpoint side, by supporting both Master / Slave modes, the limitations of the device in hardware design are broken, more transmission channel options are available, high-priority data is transmitted first, and DMA multi-threaded transmission is supported, thereby improving transmission performance and creating more economic benefits;

[0167] 2. From the CPU side, based on task-oriented data transmission, it can meet the needs of multiple users and multiple threads, and carry more user needs within limited resources. Therefore, it can also create more economic benefits from the CPU perspective;

[0168] 3. From the perspective of two-way transmission, when both ends have data transmission needs, they have the right to actively read and write data, which facilitates the timeliness and flexibility of data transmission, while supporting priority processing of high-priority data, greatly improving transmission efficiency and performance.

[0169] Embodiment 6:

[0170] The multi-thread transmission device provided in Example 4 and the multi-thread transmission method provided in Example 5 can be implemented in some specific implementations through the specific implementations in this embodiment. It can be understood that the specific implementations provided in this embodiment are only used to illustrate the specific implementation process of the methods or devices in Examples 1-5 in certain specific scenarios, and are not intended to limit the scope of protection.

[0171] like Fig. 20 As shown, it is a schematic diagram of the hardware structure for accessing chip registers in a specific scenario. Using the device provided in Example 4, the CPU is connected to the internal rosette structure bus of the chip through PCIe+DMA, and the entire system is divided into a chip hardware part and an off-chip CPU software part; DMA and PCIe transmit data at high speed through hardware according to the method provided in Example 5.

[0172] Multiple subsystems inside the chip are distributed in multiple clock domains. The ring where the Master is located is the main ring, which is used to mount access interfaces and sub-rings; the ring where the Branch and Nest are located is the sub-ring, which is the various subsystems and register groups of the chip. The Master is used for data exchange between the CPU and the DMA controller; the Branch is located at the intersection of the main ring and the sub-ring, completing the cross-clock domain, diversion, and aggregation functions of the Lizard data. The software SW accesses the chip, and writes a custom Lizard message to the DMA cache through the CPU. The DMA controller and the PCIe interface move the data to the Master. The Branch diverts the data on the main ring based on the UID field in the extracted message. The Lizard packets with matching UIDs cross the clock domain to enter the sub-ring, and the packets that do not match continue to be transparently transmitted along the main ring. For the packets returned from the sub-ring to the main ring, after crossing the clock domain through the Branch, they are aggregated and output along the main ring together with the transparently transmitted Lizard packets. The transparently transmitted packets have a higher priority than the packets from the Branch. When the Lizard data packet that completes the target register access appears on the main ring where the Master is located, the Master extracts the data and returns it to the DMA, and then returns it to the CPU. Nest is the register group of the sub-module inside the subsystem. Based on its own unique UID, it identifies and collects the Lizard packets that match the UID, parses the Lizard packets into register operation instructions, and accesses local registers and table entries; in addition, Nest is also responsible for accessing local registers / table entries and reporting Event events to the CPU. Event events have high priority and can be transferred to the CPU by DMA first.

[0173] In actual implementation, DMA operations are task-oriented, and JobId is used to identify a specific task. Software SW can initiate one or more jobs at a time, and each task can apply for one or more pages to store multiple Lizard messages. Fig.21As shown. The thick arrows are operations of reading data from DRAM / writing data to DRAM. At this time, the PCIe of the peripheral device acts as the master and the DMA acts as the slave. These two types of operations follow the requirements of DMA read and write operations. At this time, the peripheral chip acts as the Master device. The thin arrows are operations of configuring DMA-related registers. At this time, the CPU acts as the master and the PCIe of the peripheral device acts as the slave. At this time, the peripheral chip acts as the Slave device. RxDma can identify jobs of different priorities and go through different FIFO queues. TxDma can identify Response messages or Event messages to go through the corresponding FIFO queues. Used pages will be released. Interrupts are used to notify the CPU that a DMA Page has been sent or received. It can be seen from the above process that in the actual data transmission process, Mwr writes the DMA page address into the BAR0 register through the task channel of the thin arrow, and then DMA moves the data from the corresponding page address through the thick arrow channel. The task issuance process and the data reading and writing process are completed independently using different channels, thereby realizing multi-threaded parallel execution of multiple read and write tasks.

[0174] In the above scenario, the complete process of register access is as follows:

[0175] Step 501: The SW on the CPU issues an access request. When the access request is called for the first time, the SW will apply for a new Page and write a Lizard message in the DMA memory to prepare for sending.

[0176] Step 502: SW completes a Page and writes the Page address and JobId into a Job FIFO of RxDma by writing the DMA register. In actual implementation, multiple Job FIFOs can be used to distinguish the high and low priorities of different Jobs.

[0177] Step 503: RxDma obtains a job from the Job FIFO, pulls the Page data corresponding to the job from the DRAM by reading data via DMA, and adds information such as JobId and SeqNo in the message, and sends it packet by packet to the ring bus of the access device.

[0178] Step 504: When the DMA Page has been sent, RxDma sends it back to SW via the Done FIFO.

[0179] Step 505: The Lizard message enters the main ring through the Master, and is matched one by one along the multiple sub-rings mounted on the main ring until it enters the corresponding sub-ring according to the packet UID. Since different sub-rings are mounted at different locations on the main ring, and the processing time in different sub-rings is different, the transmission order of the message returned to the main ring on the main ring may be different from that when it enters the main ring, and the returned data packets may need to be re-sorted in the required order.

[0180] Step 506: TxDma checks the integrity of the returned message. Whenever a new JobId appears, Free FIFO releases a new DMA Page and then writes the message to the corresponding location according to SeqNo. Each returned packet will be written to its corresponding DMA Page.

[0181] Step 507: TxDma obtains the whereabouts of all packets returned by the Job through SeqNo and JobLast information.

[0182] Step 508: When all packets including the last one are received, TxDma sends them to Resp FIFO. When the FIFO has enough entries, or an entry has been waiting for a long enough time, an interrupt is generated to inform the CPU that the received Pages are available.

[0183] Step 509: TxDma directly pushes the data to be sent to the CPU. Regardless of whether the CPU has already retrieved the data, TxDma starts processing the next Page.

[0184] Step 510: The incoming Event packet will also be stored in a Page. When the Page has enough entries, or an entry has been waiting for a long enough time, an interrupt will be generated to inform the CPU that the received Pages are available. However, if an Event is marked as the highest priority, the Page will be sent out immediately.

[0185] After steps 501 to 510 provided in this embodiment, the complete register access process can be implemented, and the management and control of the message can be achieved.

[0186] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A multi-thread transmission device, characterized in that: include: Serializers, deserializers, interface controllers, logic managers, and direct memory access controllers, including: The PCIe interface is connected to the CPU through a serial deserializer, which deserializes the received physical layer message into a transaction layer message and inputs it into the interface controller, and serializes the transaction layer message generated by the interface controller into a physical layer code stream and outputs it to the CPU; The interface controller processes the transaction layer message input by the serial deserializer or the logic manager, and / or generates the transaction layer message to be output by the serial deserializer or the logic manager; The logic manager interacts with the interface controller through transaction layer messages. The logic manager generates chip access messages of a specified format from the transaction layer messages, and outputs the chip access messages to the direct memory access controller in a pipeline form, and / or receives chip access messages input by the direct memory access controller in a pipeline form and generates corresponding transaction layer messages; The direct memory access controller receives a chip access message, outputs data to the outside of the device through a direct chip access interface, and / or receives external input data through a direct chip access interface and converts it into a chip access message.

2. The multi-thread transmission device according to claim 1, characterized in that: The logic manager includes: a receiving module, a sending module, a slave endpoint module, a master endpoint module and an interface dependency module, specifically including: The receiving module is used to receive the transaction layer message, parse and identify the transaction layer message type, and transmit the transaction layer message to the master endpoint module or the slave endpoint module after decoding; The sending module is used to receive the transaction layer message generated by the master endpoint module or the slave endpoint module, and transmit the transaction layer message to the interface controller; The slave endpoint module is used to parse the base address space for data reading and writing in the transaction layer message, and generate corresponding bus signals for transmission to the direct memory access interface; The master endpoint module is used to determine whether the transaction layer message is an expected reply, and / or to generate a chip access message in a specified format; The interface dependency module serves as a data interface between the master endpoint module and the direct memory access interface, and serves as a data interface between the slave endpoint module and the direct memory access interface.

3. The multi-thread transmission device according to claim 2, characterized in that: The slave endpoint module includes: a slave endpoint processing component, an interrupt controller and a local register group, specifically including: The slave endpoint processing component exchanges data with the direct memory access interface via the signal bus, and is used to complete corresponding transaction layer message processing when the device is used as a slave endpoint; The interrupt controller analyzes the interrupt signal generated by the direct memory access interface and generates an interrupt signal submitted to the CPU; The local register group is used to save the data transmission status in the PCIe interface so that the logic manager can obtain the data transmission status of the PCIe interface.

4. The multi-thread transmission device according to claim 2, characterized in that: The master endpoint module includes: a master endpoint processing component, a request state machine, a packet cache, a read response tracking component and a reply cache, specifically including: The master endpoint processing component is used to complete the corresponding transaction layer message processing when the device is used as a master endpoint; The request state machine is used to process a data packet from the direct memory access interface so that the device converts the data packet into a transaction layer message in a pipeline form; The packet cache is used to cache packets from the direct memory access interface; The read response tracking component is used to process the read response completion message of the transaction layer message, so that the direct memory access interface obtains the response to each transaction layer message, sorts the transaction layer message and converts it into a data packet of a specified format, and sends the converted data packet to the direct memory access interface; The reply buffer is used to cache the transaction layer completion messages that the CPU effectively replies to.

5. A multi-thread transmission method, characterized in that: The device for multi-thread transmission using any one of claims 1 to 4 specifically comprises: When the peripheral device needs to pull CPU data, the device generates a corresponding memory read request, obtains the corresponding data in the CPU according to the memory read request, and the CPU encapsulates the corresponding data into a transaction layer message and sends it to the device, and the device pulls the data in the transaction layer message to the peripheral device through the direct memory access interface; When the peripheral device actively transmits data to the CPU, the device generates a corresponding memory write request, assembles the data obtained by the direct memory access interface into a corresponding transaction layer message according to the memory write request, and pushes the data to the corresponding data page address through the transaction layer message for use by the CPU when it is idle.

6. A multi-thread transmission method according to claim 5, characterized in that: When the transaction layer message is a configuration message of a PCIe or direct memory access interface, the device generates a corresponding memory read request, obtains corresponding data in the CPU according to the memory read request, and the CPU encapsulates the corresponding data into a transaction layer message and sends it to the device, specifically including: The CPU encapsulates the data required for configuration into a corresponding transaction layer message and sends it to the receiving module. The receiving module parses the memory read request or memory write request in the encapsulated transaction layer message and sends the transaction layer message to the slave endpoint module. The base address in the transaction layer message is parsed from the endpoint module, and the corresponding bus signal is generated using the request state machine. The bus signal is transmitted to the direct memory access interface through the signal bus, and the direct memory access interface performs the configuration processing in the transaction layer message.

7. The multi-thread transmission method according to claim 5, characterized in that: When the transaction layer message is a read response completion message, the corresponding data in the CPU is obtained according to the memory read request, the CPU encapsulates the corresponding data into a transaction layer message and sends it to the device, and the device pulls the data in the transaction layer message to the peripheral device through the direct memory access interface, specifically including: The receiving module sends the transaction layer message to the main endpoint module, and the main endpoint module compares the received transaction layer message with the request information waiting for reply; When the transaction layer message is an expected reply, a chip access message of a specified format is generated according to the transaction layer message, and the chip access message is sent to the direct memory access interface.

8. The multi-thread transmission method according to claim 5, characterized in that: The method further comprises: assembling the data acquired by the direct memory access interface into a corresponding transaction layer message according to the memory write request, and pushing the data to the corresponding data page address through the transaction layer message. When data is written, the data page address and task number sent by the CPU are obtained from the endpoint module, and the data page address is sent to the direct memory access interface through the signal bus; After the corresponding data page is used up and released, the direct memory access interface returns the released data page address to the CPU.

9. The multi-thread transmission method according to claim 5, characterized in that: When the peripheral device sends data to the CPU, the data obtained by the direct memory access interface is assembled into a corresponding transaction layer message according to the memory write request, and the data is pushed to the corresponding data page address through the transaction layer message, which specifically includes: The direct memory access interface initiates a memory write request for writing data, and the master endpoint module encapsulates the chip access message slices and sends out the corresponding transaction layer message; When data is written to the data page, the CPU receives an interrupt from the memory access interface indicating that the data has been sent, and the CPU learns that the data is available based on the interrupt.

10. The multi-thread transmission method according to claim 5, characterized in that: The step of assembling the data acquired by the direct memory access interface into a corresponding transaction layer message according to the memory write request, and pushing the data to the corresponding data page address through the transaction layer message, specifically includes: When DMA pushes data to the corresponding data page address, it sends an interrupt request signal to the receiving module; The receiving module uses the interrupt controller to parse the interrupt request signal and generate a corresponding interrupt signal; The interrupt signal is sent to the CPU through the sending module to trigger the interrupt of the CPU.

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