Apparatus and method for multi-threaded transmission

Abstract

The application relates to the field of data transmission, in particular to a multi-thread transmission device and method. The device comprises a serial deserializer, an interface controller, a logic manager and a direct memory access controller; received physical layer messages are deserialized into transaction layer messages and input to the interface controller, and transaction layer messages generated by the interface controller are serialized into physical layer code streams and output to a CPU; the interface controller processes transaction layer messages input by the serial deserializer or the logic manager; the logic manager generates chip access messages of a specified format from the transaction layer messages and outputs the chip access messages to the direct memory access controller in a pipeline form; and the direct memory access controller receives the chip access messages. The application can be applied to a super-large chip and a scene with complex address space, and can realize fast and efficient register and table item access.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of data transmission, in particular to a multi-thread transmission device and method. BACKGROUND

[0002] With the rapid development of super large scale chips (Chip), there are more and more registers in the chip, the address space scene is more and more complex, and the access demand of the registers and table entries is more and more rich. The register access function is a very important part of chip design. In the working and designing process of super large scale chips, a large number of registers of various functional subsystems and submodules need to be accessed or debugged by the system, which requires the chip to provide a unified register access interface and a complete register access mechanism, and to ensure low latency, fast and efficient, accurate and complete access efficiency.

[0003] The traditional switching chip and network processor access the registers of each hardware module on the chip mostly in the form of bus, and each module shares the same bus in time. When the chip scale is large, the number of registers is large, the address space is complex, or the access frequency is high, the existing shared bus access mode will increase the access latency and even cause congestion, reduce the efficiency, and affect the processing performance of the central processing unit (CPU) for managing the chip and the chip itself.

[0004] On the other hand, the traditional chip bottom event or error is mostly informed to the CPU in the form of polling, and the cumbersome polling mechanism will occupy the CPU processing time, which is low in efficiency. Even if it is changed to CPU interrupt mode, if frequent interrupts occur, and the CPU needs to read related registers to obtain detailed exception information, it will also seriously affect the processing efficiency of the CPU and the chip.

[0005] In view of this, how to overcome the defects of the prior art and solve the phenomenon that the use of a shared bus affects the register access performance in the prior art is a problem to be solved in the technical field. SUMMARY

[0006] In view of the above defects or improvement needs of the prior art, the present application solves the problem of the phenomenon that the use of a shared bus affects the register access performance in the prior art.

[0007] The embodiment of the present application adopts the following technical scheme:

[0008] In a first aspect, the present application provides a multi-thread transmission device, which specifically comprises a serial deserializer, an interface controller, a logic manager and a direct memory access controller, and specifically comprises: a PCIe interface connected with a CPU through the serial deserializer, which inputs the transaction layer message received after being deserialized from the physical layer message to the interface controller, and outputs the transaction layer message generated by the interface controller to the CPU after being serialized from the physical layer code stream; the interface controller processes the transaction layer message input by the serial deserializer or the logic manager, and / or generates the transaction layer message to be output by the serial deserializer or the logic manager; the logic manager and the interface controller interact through the transaction layer message, the logic manager generates the chip access message in a specified format from the transaction layer message, and outputs the chip access message to the direct memory access controller in a pipeline form, and / or receives the chip access message input by the direct memory access controller in a pipeline form, and generates the corresponding transaction layer message; the direct memory access controller receives the chip access message, and outputs the data to the outside of the device through the direct chip access interface, and / or receives the data input from the outside through the direct chip access interface, and converts the data into the chip access message.

[0009] Preferably, the logic manager comprises a receiving module, a sending module, a slave endpoint module, a master endpoint module and an interface dependent module, and specifically comprises: the receiving module is used for receiving the transaction layer message, identifying the type of the transaction layer message, and transmitting the transaction layer message to the master endpoint module or the slave endpoint module after being decoded; the sending module is used for receiving the transaction layer message generated by the master endpoint module or the slave endpoint module, and transmitting the transaction layer message to the interface controller; the slave endpoint module is used for parsing the base address space of the data read and write of the transaction layer message, and generating the corresponding bus signal to be transmitted to the direct memory access interface; the master endpoint module is used for determining whether the transaction layer message is the expected reply, and / or generating the chip access message in a specified format; and the interface dependent module is used as the data interface between the master endpoint module and the direct memory access interface, and as the data interface between the slave endpoint module and the direct memory access interface.

[0010] Preferably, the slave endpoint module comprises a slave endpoint processing component, an interrupt controller and a local register group, and specifically comprises: the slave endpoint processing component exchanges data with the direct memory access interface through the signal bus, and is used for completing the corresponding transaction layer message processing when the device is used as the slave endpoint; the interrupt controller analyzes the interrupt signal generated by the direct memory access interface, and generates the interrupt signal to be submitted to the CPU; and the local register group is used for saving the data transmission state in the PCIe interface, so that the logic manager obtains the data transmission state of the PCIe interface.

[0011] Preferably, the master endpoint module comprises a master endpoint processing component, a request state machine, a packet buffer, a read response tracking component and a reply buffer, and specifically comprises: the master endpoint processing component is used to complete corresponding transaction layer packet processing when the device is used as a master endpoint; the request state machine is used to process data packets from the direct memory access interface, so that the device converts the data packets into transaction layer packets in a pipeline manner; the packet buffer is used to buffer data packets from the direct memory access interface; the read response tracking component is used to process read response completion packets of transaction layer packets, so that the direct memory access interface obtains responses to each transaction layer packet, sorts the transaction layer packets and converts them into data packets in a specified format, and sends the converted data packets to the direct memory access interface; and the reply buffer is used to buffer CPU valid reply transaction layer completion packets.

[0012] In a second aspect, the application provides a multi-thread transmission method, characterized by using the device provided in the first aspect, and specifically comprising: when the peripheral device needs to pull CPU data, the device generates a corresponding memory read request, obtains corresponding data in the CPU according to the memory read request, the CPU side encapsulates the corresponding data into a transaction layer packet and sends it to the device, and the device pulls the data in the transaction layer packet to the peripheral device through the direct memory access interface; when the peripheral device actively transmits data to the CPU, the device generates a corresponding memory write request, assembles data obtained by the direct memory access interface into a corresponding transaction layer packet according to the memory write request, and pushes the data to a corresponding data page address through the transaction layer packet for the CPU to use when idle.

[0013] Preferably, when the transaction layer packet is a PCIe or direct memory access interface configuration packet, the device generates a corresponding memory read request, obtains corresponding data in the CPU according to the memory read request, and the CPU side encapsulates the corresponding data into a transaction layer packet and sends it to the device, and specifically comprises: the CPU encapsulates data to be used during configuration into a corresponding transaction layer packet and sends it to the receiving module, the receiving module parses the memory read request or memory write request in the encapsulated transaction layer packet, and sends the transaction layer packet to the slave endpoint module; the slave endpoint module parses the base address in the transaction layer packet, and uses the request state machine to generate a corresponding bus signal, transmits the bus signal to the direct memory access interface through the signal bus, and executes the configuration processing in the transaction layer packet by the direct memory access interface.

[0014] Preferably, when the transaction layer message is a read response completion message, the CPU encapsulates the corresponding data into a transaction layer message and sends it to the device, and the device pulls the data in the transaction layer message to the peripheral device through the direct memory access interface, specifically comprising: the receiving module sends the transaction layer message to the host endpoint module, and the host endpoint module compares the received transaction layer message with the request information waiting for a reply; when the transaction layer message is the expected reply, a chip access message in a specified format is generated according to the transaction layer message, and the chip access message is sent to the direct memory access interface.

[0015] Preferably, the data obtained by the direct memory access interface according to the memory write request is assembled into a corresponding transaction layer message, and the data is pushed to the corresponding data page address through the transaction layer message, and further comprising: when the data is written, the data page address and the task number sent by the CPU are obtained from the endpoint module, and the data page address is sent to the direct memory access interface through the signal bus; after the corresponding data page is used and released, the direct memory access interface returns the released data page address to the CPU.

[0016] Preferably, when the peripheral device sends data to the CPU, the data obtained by the direct memory access interface according to the memory write request is assembled into a corresponding transaction layer message, and the data is pushed to the corresponding data page address through the transaction layer message, specifically comprising: the direct memory access interface initiates a memory write request for writing data, the host endpoint module encapsulates the chip access message slice and sends a corresponding transaction layer message; when the data is written to the data page, the CPU receives the interrupt sent by the memory access interface that the data has been sent, and the CPU knows that the data is available according to the interrupt.

[0017] Preferably, the data obtained by the direct memory access interface according to the memory write request is assembled into a corresponding transaction layer message, and the data is pushed to the corresponding data page address through the transaction layer message, specifically comprising: when the DMA pushes the data to the corresponding data page address, an interrupt request signal is sent to the receiving module; the receiving module parses the interrupt request signal using an interrupt controller and generates a corresponding interrupt signal; the interrupt signal is sent to the CPU through the sending module to trigger the interrupt of the CPU.

[0018] Compared with the prior art, the application has the beneficial effects that: the access device provided by the application uses a multi-layer ring bus to form a bus system in a wreath structure, different subsystems or submodules are managed by using different ring buses, and the access device has portability and scalability; the access protocol provided by the application realizes a software and hardware unified message mechanism; and the access method provided by the application improves processing efficiency and performance based on multi-layer addressing of a main ring and a subring. The application is suitable for a super-large chip, an address space complex scene, and can realize fast and efficient register and table item access. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the application, the drawings needed to be used in the embodiments of the application will be briefly introduced. Obviously, the drawings described below are only some of the embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0020] Figure 1 A structural schematic diagram of the access device of the register in the super-large chip provided by the embodiments of the application is shown in the figure.

[0021] Figure 2 A structural schematic diagram of the register node in the access device provided by the embodiments of the application is shown in the figure.

[0022] Figure 3 A structural schematic diagram of the main node in the access device provided by the embodiments of the application is shown in the figure.

[0023] Figure 4 A structural schematic diagram of the cross node in the access device provided by the embodiments of the application is shown in the figure.

[0024] Figure 5 A structural schematic diagram of the access protocol message structure in the access device provided by the embodiments of the application is shown in the figure.

[0025] Figure 6 Another access protocol message structure in the access device provided by the embodiments of the application is shown in the figure.

[0026] Figure 7 A use scenario schematic diagram of the access method of the register in the super-large chip provided by the embodiments of the application is shown in the figure.

[0027] Figure 8 A flowchart of the access method of the register in the super-large chip provided by the embodiments of the application is shown in the figure.

[0028] Figure 9 A flowchart of another access method of the register in the super-large chip provided by the embodiments of the application is shown in the figure.

[0029] Figure 10 The flow chart of another access method of a register in a super-large scale chip provided by an embodiment of the present application is shown in FIG. 6.

[0030] Figure 11 The schematic diagram of a data transmission process in the access method provided by an embodiment of the present application is shown in FIG. 7.

[0031] Figure 12 The schematic diagram of an existing PCIe bus structure is shown in FIG. 8.

[0032] Figure 13 The schematic diagram of the structure of a multi-thread transmission device provided by an embodiment of the present application is shown in FIG. 9.

[0033] Figure 14 The schematic diagram of the structure of a logic manager in the multi-thread transmission device provided by an embodiment of the present application is shown in FIG. 10.

[0034] Figure 15 The schematic diagram of the structure of a slave endpoint module and a master endpoint module in the multi-thread transmission device provided by an embodiment of the present application is shown in FIG. 11.

[0035] Figure 16 The schematic diagram of a data interaction process between a PCIe Logic and a DMA channel architecture in the multi-thread transmission device provided by an embodiment of the present application is shown in FIG. 12.

[0036] Figure 17 The flow chart of a multi-thread transmission method provided by an embodiment of the present application is shown in FIG. 13.

[0037] Figure 18 The schematic diagram of a message interoperation process between a DMA and a PCIe in the multi-thread transmission method provided by an embodiment of the present application is shown in FIG. 14.

[0038] Figure 19 The schematic diagram of a data transmission process in a certain scenario of the multi-thread transmission method provided by an embodiment of the present application is shown in FIG. 15.

[0039] Figure 20 The schematic diagram of the usage mode of the multi-thread transmission device and method provided by an embodiment of the present application in a certain scenario is shown in FIG. 16.

[0040] Figure 21 The schematic diagram of a data transmission process in a certain scenario of the multi-thread transmission device and method provided by an embodiment of the present application is shown in FIG. 17. DETAILED DESCRIPTION

[0041] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0042] The present application is a kind of architecture of specific function system, therefore in specific embodiment, the function logical relationship of each structure module is mainly explained, and the specific software and hardware implementation are not limited.

[0043] In addition, the technical features involved in each embodiment of the application described below can be combined with each other as long as there is no conflict. The present application will be described in detail below in conjunction with the drawings and examples.

[0044] Embodiment 1:

[0045] In order to quickly and efficiently access the registers or table items of the chip, and optimize the fast addressing access of the super large scale chip, the embodiment provides an access device for registers in a super large scale chip. A plurality of ring buses are used to form a multi-layer flower ring bus structure, which effectively reduces the register access delay, increases the processing performance, and ensures the unified, safe and supervised access effect of the chip.

[0046] As Figure 1 shown, the access device architecture schematic diagram of the embodiment of the present application is shown, which includes a plurality of subsystems or submodules inside the super large scale chip. The registers on different subsystems or submodules can be connected by using a ring bus respectively. When addressing, the registers on each ring bus can be addressed respectively, the address space used is smaller, and the data transmission path is shorter. Specifically, the access device includes: at least two ring buses, at least one register node (i.e. Nest in Figure 1 ) to be accessed is connected on each ring bus, and the ring bus interacts with the corresponding register group (i.e. Unit in Figure 1 ) through the register node. Each register group contains one or more registers. Further, in a general scenario, each subsystem or submodule is distributed in a plurality of clock domains, and the clock signals of each clock domain can be the same or different. In the embodiment, in order to avoid clock desynchronization, the subsystem or submodule in each ring bus needs to be located in the same clock domain.

[0047] In this embodiment, in order to facilitate the management of the communication of the external interface of the ring bus and the chip, the external interface is not mounted on each ring bus, but a plurality of ring buses are organized into a multi-layer wreath structure, which mainly includes three key nodes, namely a master node (Master), a branch node (Branch) and a register node (Nest). The Master and the Branch are used to split and aggregate data on different transmission channels between the main ring and the sub-ring. In a specific implementation, the ring bus on which the master clock node of the clock domain is located is taken as the main ring, the main ring interacts with the external device of the chip through a direct memory access interface, and manages the sub-ring mounted thereon; the ring bus not containing the master clock node of the clock domain is taken as the sub-ring, each sub-ring interacts with the main ring through a branch node of a clock domain, and each sub-ring can be connected to all register nodes in one or more subsystems of the same clock domain of the chip. The branch node is located at the intersection of the main ring and the sub-ring, and completes the clock domain crossing of data, as well as the splitting and aggregation of data on different sub-rings. In actual implementation, the level of the multi-layer ring bus can be determined according to the level of the chip system structure, Figure 1 Taking the wreath structure composed of two-layer ring buses as an example, when there are more layers of structures, the next layer of sub-ring can be mounted on the sub-ring through the branch node, but the sub-rings cannot be crossed.

[0048] In a specific scenario, as shown in the figure, Figure 1 The peripheral device interface is a peripheral component interconnect express (PCIe) interface, which is a high-speed serial computer expansion bus standard; the direct memory access (DMA) interface is a high-speed data transmission operation, which allows data to be read and written directly between a peripheral device and a memory without passing through a CPU or without the intervention of the CPU. The DMA and the PCIe can transmit data in a hardware manner. In this scenario, when the external software (SW) needs to access the registers in the chip, the CPU needs to write the required data into the DMA cache, the DMA controller and the PCIe interface move the data to the Master node, and then the data enters the main ring through the Master node. In actual implementation, the number of Master nodes on the main ring can be determined according to the number of external interfaces or the number of DMAs required for data interaction, and the number of sub-rings can be determined according to the number of subsystems, sub-modules or clock domains. Each sub-ring can only be mounted on one main ring.

[0049] As shown in the figure, Figure 2The following is a diagram of the Nest node on the sub-ring, which includes: register data queue (first input first output, abbreviated as FIFO), channel (Pipe) module, event (Event) module and register data aggregation (i.e. Figure 2 The register data queue caches the input data of the sub-ring and pushes the input data to the channel module; the channel module writes the input data to the specified register or table item in the register group through the access interface, or the channel module obtains the output data of the specified register in the register group or the output data of the table item through the access interface, and pushes the output data to the register data aggregation module; the event module obtains the event data reported by the register group through the event interface and pushes the event data to the register data aggregation module; the register data aggregation module receives the output data and event data, merges the output data and event data into one path, and outputs it to the sub-ring.

[0050] In a specific implementation, the group ID (Unit Identity Document, abbreviated as UID) can be used to identify the register node where the register to be accessed is located. The FIFO receives the input data passed in on the sub-ring. The Pipe module extracts the UID in the input data and determines whether it matches the register node address it manages. If the UID matches the address of this register node, the access address and operation instructions in the input data are parsed, and the operation instructions are sent to the register group to which it is connected through the access interface to perform the specific access operation. Otherwise, the input data is output to the next Nest node. When the access operation is completed, the Nest node receives the register group's reply data to the operation instruction and returns it to the sub-ring. At the same time, the Event module is responsible for collecting the alarm information of the register and actively sending the alarm information to the sub-ring.

[0051] Furthermore, a Nest node also exists on the main ring. This Nest node can be used as a register group or table entry for connecting peripheral devices, allowing access devices to directly access specific register groups or management table entries of peripheral devices through the Nest node. Specific register groups or table entries of peripheral devices can be connected to the Nest node on the main ring through a specific interface. The Nest node on the main ring can also identify and collect data matching the UID based on its own unique UID, and parse the data into operating instructions for registers or table entries to access the corresponding registers and table entries. At the same time, the Nest node is also responsible for accessing the specified registers or table entries and reporting Event events to the CPU.

[0052] like Figure 3 The following is a block diagram of the Master node, including: the main ring receiving queue (FIFO_rx), the main ring sending queue (FIFO_tx), the main ring aggregation module (Figure 3 Aggregation) and the main ring split module ( Figure 3 In addition, in some implementation scenarios, the main ring local queue (Local FIFO) can also be used to manage data that does not currently need to be output to the outside or data that needs to continue to be transmitted on the main ring in some scenarios. Specifically: The main ring receive queue caches the input data passed in by the direct memory access interface, and pushes the input data to the main ring aggregation module. The main ring send queue caches the output data passed in by the main ring diversion module, and outputs the output data through the direct memory access interface. The main ring aggregation module obtains the output data pushed by the main ring receive queue and the main ring local queue, merges the output data into one channel, and then outputs it to the main ring. The output data includes the input data passed in by the direct memory access interface and the data diverted by the main ring diversion module that needs to continue to be transmitted on the main ring. When merging, the data of the two channels are only passed into the same transmission channel, and no data connection or merging is performed. The main ring's traffic diversion module receives incoming data from the main ring and distributes it to the main ring's transmit queue and local queue. Data destined for external transmission is diverted to the main ring's transmit queue, while data destined for continued transmission on the main ring is diverted to the local queue. The local queue buffers incoming data from the main ring's traffic diversion module and pushes it to the main ring's aggregation module.

[0053] In specific implementations, the MasterID can be used to distinguish between data about to enter the main ring and data returned by the main ring. When data enters the Master node, the MasterID is added to it and recorded, and the data with the MasterID added is then transmitted to the main ring. When data returned from the main ring enters the Master node, the main ring diversion module determines whether the data's MasterID matches the recorded MasterID. If so, the corresponding data is extracted and returned to the DMA. Data with unmatched MasterIDs is transparently transmitted through the main ring local queue to the main ring aggregation module for further transmission on the main ring.

[0054] Furthermore, the main ring shunt module may discard the message according to the discard signal. When the message contains the discard signal, the main ring shunt module will discard the message.

[0055] like Figure 4 The diagram shows the Branch node, which includes: Sub-ring shunt module ( Figure 4 "Diversion" in the sub-ring aggregation module ( Figure 4sub-ring input queue (asynchronous FIFO1) and sub-ring output queue (asynchronous FIFO2). In a specific implementation, the Branch node needs to connect the different clock domains of the main ring and the sub-ring, and in order to realize cross-clock domain buffering, the sub-ring input queue and the sub-ring output queue need to use asynchronous buffering queues. Specifically: the sub-ring splitting module is located in the clock domain of the main ring, and the sub-ring splitting module receives the input data transmitted by the main ring, sends the input data that needs to be processed by the current sub-ring into the sub-ring input queue so that the data enters the current sub-ring, and sends the input data that needs to be processed by other sub-rings into the aggregation module so as to continue transmission on the main ring. The sub-ring aggregation module is located in the clock domain of the main ring, and the sub-ring aggregation module receives the output data in the sub-ring splitting module and the sub-ring output queue, and combines the output data into one path and then outputs to the main ring, wherein the output data of the sub-ring splitting module is the data that needs to continue to be transmitted on the main ring, and the output data in the sub-ring output queue is the data output by the registers in the current sub-ring. Similarly, when combining, only the data transmission channel is combined, and no data connection or combination is performed. The sub-ring input queue receives the input data transmitted by the sub-ring splitting module according to the clock of the main ring, and pushes the input data to the sub-ring according to the clock of the sub-ring. The sub-ring output queue receives the output data of the sub-ring according to the clock of the sub-ring, and pushes the output data to the sub-ring aggregation module according to the clock of the main ring.

[0056] In actual implementation, when the input data transmitted on the main ring passes through each Branch node, the Branch node splits the input data on the main ring based on the UID of the data. In order to facilitate addressing, the UIDs of all register groups on each sub-ring can use a continuous address range, and the sub-ring splitting module extracts the UID of the data, and when the UID is within the address range of the current sub-ring, it meets the UID condition of the current Branch node, and the input data is processed by the current sub-ring through the Branch node; otherwise, the input data is transparently transmitted to the sub-ring aggregation module, the sub-ring aggregation module aggregates the transparently transmitted data and the data returned from the sub-ring, and then continues to transparently transmit to the next Branch node along the main ring and then returns to the main ring for transmission. On the other hand, for the data returned from the sub-ring to the main ring, after crossing the clock domain through the Branch node, it continues to be transmitted along the main ring together with the transparently transmitted data.

[0057] It can be seen that, in the access device provided in the embodiment, the register or table item on the chip is accessed using the multi-layer wreath structure surrounding the whole chip, different sub-rings are crossed to access multiple subsystems, and different sub-rings are associated through the main ring, so that the chip access message can be transmitted in one direction on the multi-layer ring bus of the wreath structure. Multiple information can be transmitted on each ring bus at the same time, the access subsystems on different ring buses do not affect each other, and the CPU is returned in the shortest path after the access ends. The access device provided in the embodiment is suitable for fast addressing and accessing in a super-large-scale and super-large address space scenario, improves the access efficiency of the register, reduces the access time delay, and realizes direct reporting of cooperative events or errors for fast processing, thereby improving the overall performance of the software and hardware.

[0058] Embodiment 2

[0059] In the access device of the register in the super-large-scale chip provided in the above embodiment 1, in order to facilitate addressing and managing data, the data can be encapsulated according to a specified access protocol. An available access protocol is provided in the embodiment, and it can be understood that the definition of the access protocol is only used as a reference for the form of the available access protocol in actual implementation, and is not a limitation on the protection scope.

[0060] The access protocol provided in the embodiment is used to access the register and table item in the chip and is transmitted in one direction in the access device provided in the embodiment 1. The message format is as shown in Figure 5 In order to match the general communication protocol, the message includes 16 bytes of packet header information, and the packet header information includes an address part and an attribute part; in order to adapt to the data bit width supported by different registers, the message also includes a variable-length data (Data) part. In each embodiment of the present application, the data message encapsulated according to the access protocol provided in the embodiment is simply referred to as a message without causing ambiguity.

[0061] The address part includes a group ID (UID) and an access address (Addr), the group ID is used to match the corresponding sub-ring and register node, and the access address is used to match the corresponding register in the register group. The UID is used to match the corresponding sub-ring and register node, and the access address is used to match the corresponding register in the register group. Figure 5It can be seen that the access address is two-segment addressing: {UID+Addr}, which can better support large address space. UID is used to match the corresponding sub-ring and Nest. Each Nest has a unique UID, and the Nest addresses in each sub-ring are located in the same address range. Range matching is more efficient when matching the sub-ring, and after entering the corresponding sub-ring, UID is further used to accurately match the destination Nest. Using this way of addressing, each packet only needs to pass through part of the main ring + part of the sub-ring to reach the destination Nest, greatly shortening the path of the packet and reducing the lookup delay. Addr is used to match the corresponding register in the Nest. In a very large scale chip, the address space is very complex, and the original linear address is not suitable. Two-segment addressing can better support large-scale address space.

[0062] The attribute part is used to carry the attribute information of the protocol packet, so that the access device can process the protocol packet according to the attribute information.

[0063] The attribute part usually needs to include an OpCode field, the value of which is the operator when accessing the register: Read (Rd) is read, indicating that the data in the register needs to be read; Write (Wr) is write, indicating that data needs to be written to the register; ReadWrite (RdWr) is read and clear, indicating that the register data is first read, and then all 0 values are written to the register to clear the register.

[0064] Further, in the implementation, the DMA operation is task-oriented, and the PCIe and DMA can support multi-threaded data read-write mode to execute multiple tasks simultaneously, therefore, the attribute part can contain a task ID (JobId) field to identify a specific task. The task ID field is used to identify each register access task initiated by the external CPU, and the value of the task ID field is one-to-one mapped with the data page address of the external CPU. By using the JobID field, the software running on the CPU can initiate one or more register access request Jobs at a time. In order to facilitate data transmission, in the embodiment, each task can apply for one or more memory pages (Page), and each Page stores one or more chip access messages (Lizard message). The size of the Page can be configured according to the actual needs of data read-write. In this way, the device in embodiment 1 can support multi-user multi-task, batch read-write and pipeline processing. In the implementation, when the software running on the external CPU initiates a memory access task, the software will map the task ID of the memory access task with the data page address (page Addr), so that the DMA on the chip can determine which page data to obtain through the task ID, and directly take the data to the chip; if it is a reply message of the chip, the DMA will request a free data page address (free page Addr) from the external CPU, map the task ID with the page Addr, and transmit the output data to the page in the external CPU, so that the CPU can obtain the data replied by the chip. In the actual implementation, the Lizard message can include a message sent by the CPU to the chip, a message replied by the chip to the CPU, and a message for event notification from the chip to the CPU.

[0065] The data part carries data that needs to be written into the register, or carries data obtained from the register, or carries data actively reported by the register. In the implementation, the Data field is used to store specific register domain data, and the domain segment used is indicated in Figure 5 .

[0066] Further, in order to facilitate the definition of the boundary of a single message, in the access protocol provided by the embodiment, the data verification ensures the reliability of data transmission, and the verification error can be filled in the message Corrupt field, the skip operation is returned to the SW, and the SW decides whether to retransmit.

[0067] The device provided in Embodiment 1 comprises a plurality of sub-rings connected to the same main ring, and each sub-ring is connected to a register in a different subsystem. In some scenarios, the clock domains of different subsystems can be different, and congestion can occur in the transmission of a message accessing a local register and a table item. To ensure the reliability of the message in transmission, a back pressure mechanism (BP) is provided on each ring to support the flow control of the burst access scenario. Specifically, when any register node enters a burst state and reaches the upper limit of processing capacity, the back pressure field of the protocol message in the register data queue of the previous register node is set to a first signal value to indicate that the register data queue suspends data pushing; when the register node returns to normal operation, the back pressure field of the protocol message in the register data queue of the previous register node is set to a second signal value to indicate that the register data queue resumes data pushing. In actual implementation, a high level is used as the first signal value, and a low level is used as the second signal value. When a burst occurs in a Nest on the ring bus and reaches the upper limit of processing capacity, the back pressure signal transmitted to the previous Nest is pulled high, and the data of the previous Nest is blocked at this time. The data will continue to be transmitted to the next stage until the back pressure of the next stage is pulled low. Since the register data queue for buffering is provided in the Nest, it can be determined whether to back pressure the previous stage by detecting whether the amount of data buffered in the queue exceeds the water line. The back pressure mechanism can effectively avoid congestion and better adapt to the burst access scenario. When Flush is pulled high, the buffered data in the current subsystem is quickly cleared to meet the scenario requirements during software upgrade.

[0068] In the access protocol provided in the embodiment, the domain segment of the attribute part can be set according to actual access needs and control needs. The following simply provides some domain segment definitions that can be used as a reference. It can be understood that the following domain segment definitions are only design examples of the access protocol in specific scenarios and do not limit the protection scope.

[0069] In some scenarios, in order to meet the event or error reporting requirements of the register, in the access protocol provided in the embodiment, the data part of the message is also used to carry an alert event or an abnormal event, and the defect subscription of the register can also be supported. When reporting, the message is sent from the Nest to the CPU through the access device. The JobId of the event uses a specified fixed value, which is directly reported to the CPU, and the CPU can obtain all the information without reading the register. The event can be selectively shielded and subscribed, which effectively avoids burst message overflow. In this scenario, the data format of the access protocol is as shown in the following table. The bold part is the effective domain segment. Figure 6

[0070] ​In some scenarios, the attribute part can also support error identification and monitoring functions. For example, using the specified domain value in the message to indicate the following information: whether the parity check or cyclic redundancy check of the message passes, whether the message has reached a specified address, whether the register corresponding to the address exists, the number of transceiving count of the message, and the like.

[0071] In order to avoid congestion between various software streams, when using the access protocol provided by the embodiment to perform data transmission, if it is a high-priority service, it will be processed faster and will not be blocked by other streams. This is due to the fact that DMA is based on task processing, and software streams cannot share DMA Page. Messages are only transmitted on the ring bus and the destination sub-ring. In order to increase performance, message reordering can be allowed, and DMA supports reordering and distinguishes Job. As for DMA read operation, because DMA can realize reordering and reordering, additional read operations are allowed before the first read reply is received, so that read efficiency can be better improved.

[0072] The access protocol provided by the embodiment can meet the data transmission needs of the ring bus system in Embodiment 1 and complete the basic functions of chip configuration and state monitoring. The access protocol has the following advantages:

[0073] 1) The message of the access protocol starts from the software system SW, passes through PCIe and DMA, is transmitted through the multi-layer ring bus system surrounding the chip, and finally returns to SW through PCIe and DMA, which meets the data transmission needs of the access device of Embodiment 1.

[0074] 2) The SeqNo is used to identify the position of the message in the Page, so that the message reordering is allowed. The multi-layer ring bus is used to optimize the access path, so as to ensure the low latency of the access device.

[0075] 3) The two-segment address structure of UID+Addr is used, so that the message can be transmitted in the form of garland in different sub-rings, and the sub-ring has flexible expansion.

[0076] 4) The variable-length data part and the Length field are used to support the variable-length register data bit width.

[0077] 5) The JobID field is used to identify each different access task, support DMA multi-threading and priority, and support multi-user multi-task pipeline operation.

[0078] 6) The data part of the message can carry event data, support a fast event reporting mechanism, allow the bottom layer to directly send events or error messages to the CPU, and facilitate fast event processing.

[0079] Embodiment 3:

[0080] Based on the register access device in the super large scale chip provided in the above embodiment 1, the application further provides a register access method in a super large scale chip.

[0081] The access method provided in the embodiment is implemented in the scene as shown in Figure 7 The access request is initiated by a software development kit (SDK) running on a CPU and is driven by a MSG module. The MSG module accesses the chip through a chip driver running in a kernel space, supports single or batch read / write message delivery, and provides an interface for accessing the chip or debug for other applications, such as Table entry read / write, chip important module configuration, Event event acquisition, and register read / write.

[0082] As shown in Figure 8 The register access method in the super large scale chip provided in the embodiment of the application can be implemented in the following way.

[0083] Step 101: The external CPU transmits input data into the master node through a direct access interface, the input data is unidirectionally transmitted by the master node along the main ring, and the input data matching each sub-ring is transmitted into the sub-ring through the corresponding branch node, the input data is unidirectionally transmitted by the branch node along the sub-ring, and the input data reaches the corresponding register node on the sub-ring.

[0084] The main ring interacts with the device outside the chip through a direct memory access interface. Specifically, the external CPU transmits input data into the direct memory access interface through a peripheral device interface, the direct access interface transmits the input data into the master node, the input data is unidirectionally transmitted by the master node along the main ring to the corresponding register node on the main ring, or the input data of each sub-ring is transmitted into the sub-ring through the branch node. The branch node receives the input data transmitted by the main ring, the input data is unidirectionally transmitted by the branch node along the sub-ring, and the input data reaches the corresponding register group on the sub-ring.

[0085] Step 102: The output data of the register node on the sub-ring continues to be unidirectionally transmitted along the sub-ring until it returns to the branch node, the branch node transmits the output data to the main ring, the output data of each sub-ring continues to be unidirectionally transmitted along the main ring until the output data returns to the master node, and the master node transmits the output data to the external CPU through the direct memory access interface.

[0086] Each sub-ring interacts with the main ring through a branch node, specifically: the output data of the register node on the sub-ring continues to be transmitted unidirectionally along the sub-ring until it returns to the branch node, and the branch node transmits the output data to the main ring. The output data of each sub-ring or the output data of the register group on the main ring continues to be transmitted unidirectionally along the main ring until the output data returns to the main node, and the main node transmits the output data to the direct memory access interface, and the direct memory access interface transmits the output data to the external CPU through the peripheral device interface.

[0087] After the steps 101-102 provided in the embodiment, the reading and writing of the register data can be quickly completed through the device provided in Embodiment 1.

[0088] As shown in Figure 9 The specific steps of writing data into the register when writing data into the register or sending an operation instruction to the register in the access method of the register in the super-large-scale chip provided by the embodiment of the application are as follows:

[0089] Step 201: According to the specified access protocol, the external CPU encapsulates the data for register access into input data.

[0090] When the user thread (User Thread) in the SDK needs to access the register, in order to utilize the access device provided in Embodiment 1 to transmit data, first, the access request and access address need to be encapsulated into input data according to the specified access protocol, and the encapsulated input data is transmitted in the form of a message in the access device provided in Embodiment 1. In order to describe simply, the access protocol provided in Embodiment 2 is taken as the specified access protocol in this embodiment, and in actual implementation, the access protocol can be defined and used according to actual needs. Figure 7 In the figure, #job1, job2, …, #jobn are JobIds of different access requests, and the transmission direction is indicated by a dashed arrow.

[0091] Step 202: The input data is transmitted from the direct memory access interface into the access device provided in Embodiment 1, and the input data enters the main ring through the main node and is transmitted unidirectionally in the first direction in the main ring.

[0092] The input data enters the Auto Send Thread of the MSG module, and then is pushed to the DMA in the chip by the MSG module through PCIe. The data path (Datapath) of the input data in the chip is the access device provided in Embodiment 1, and the main node located on the main ring in the access device interacts with the outside for data. Therefore, the input data first enters the main ring through the main node. In actual implementation, the first direction can be selected as the clockwise direction or the counterclockwise direction according to needs.

[0093] Step 203: According to the group ID in the input data, the input data is transferred to the corresponding sub-ring through the corresponding branch node on the main ring, and is unidirectionally transmitted in the sub-ring in the second direction.

[0094] The access protocol provided in Example 2 uses a two-segment address encoding, including a group ID (UID) and an access address (Addr). Among them, the UID is used to match the Uint that the input data needs to access, and each Nest corresponds to a Uint. Therefore, the Nest that the message needs to enter can be determined by the Unit address associated with the Nest. In order to facilitate address matching, the addresses of all Units on each sub-ring are included in the address range of the sub-ring, and the input data can be quickly transferred to the sub-ring where the Nest to be accessed is located. Since data is transmitted independently in each ring bus, in actual implementation, the second direction can be the same as the first direction or different from the first direction.

[0095] Step 204: According to the group ID in the input data, the input data is transferred to the corresponding register node on the sub-ring, and the corresponding register is accessed according to the access address.

[0096] After the input data reaches the corresponding Nest, the register to be accessed can be found in the Unit corresponding to the Nest according to the Addr.

[0097] Step 205: Write the data portion of the input data into the corresponding register, or obtain the data in the register according to the operation indicated by the attribute portion of the input data.

[0098] After finding the register to be accessed, the corresponding operation can be performed on the register according to the operation instructions in the input data.

[0099] After steps 201 to 205 provided in this embodiment, the access request sent by the SDK can be sent to the corresponding register.

[0100] On the other hand, Figure 10 As shown, in the method for accessing registers in a very large-scale chip provided by an embodiment of the present invention, when data in a register is obtained or a register reports an event, the specific steps for reading data from the register are as follows:

[0101] Step 301: Encapsulate the acquired data or reported event data into output data according to a specified access protocol.

[0102] In order to transmit data by using the access device provided in Embodiment 1, the register data and the reporting event are encapsulated into output data according to the same access protocol, and the encapsulated output data is transmitted in the form of a message in the access device provided in Embodiment 1. Similarly, the following also takes the range protocol provided in Embodiment 2 as an example for description.

[0103] Step 302: The output data is transmitted in the second direction on the sub-ring back to the branch node on the current sub-ring, and enters the main ring through the branch node.

[0104] The output data continues to be transmitted in the same direction as the input data in the sub-ring until it returns to Branch, and then returns to the main ring through Branch.

[0105] Step 303: The output data is transmitted in the first direction on the main ring back to the master node, and is output to the direct memory access interface through the master node.

[0106] After returning to the main ring, the output data continues to be transmitted in the same direction as the input data in the main ring until it returns to Master, and then is output to the receive thread (Receive Tread) of the MSG module. Figure 7 In the figure, the solid arrows denoted #job1, #job2,..., and #jobn are output data of the same JobId input data, and thus need to be returned to the UserThread for processing. The solid arrow denoted #jobE is output data of a register reporting event, and thus needs to be output to a separate event processing thread (Event Thread) for corresponding event processing. In addition, a fast mode is supported, in which the task ID is fixed as F, the output data (i.e., Turbo data packet) of the write-in message returned by the hardware is directly discarded, the user does not need to wait for a reply, and when the table entry is upgraded and updated, excellent throughput can be achieved.

[0107] After the steps 201-203 provided in the embodiment, the data returned by the register can be sent back to the SDK.

[0108] In actual implementation, the data in each ring bus is transmitted in one direction, and the transmission directions of the data in different ring buses can be the same or different. In a specific scenario, for example, Figure 11As shown, the first direction and the second direction transmitted on all ring buses are clockwise, and the message transmission path transmitted to the register is indicated by a solid arrow, and the message transmission path returned by the register is indicated by a dashed arrow. When the Nest B node needs to be accessed, the message is entered into the access device by the Master node, transmitted to the Branch A node in the clockwise direction, and entered into the sub-ring by the Branch A node; then transmitted clockwise in the sub-ring starting from the Branch A node, transmitted through the Nest A node, and after reaching the Nest B node, the corresponding register is accessed. After the register access is completed, the sub-ring is returned by the Nest B node, and the transmission continues clockwise on the sub-ring, transmitted through the Nest C node, returned to the Branch A node, and then returned to the main ring by the Branch A node; after returning to the main ring, the transmission continues clockwise on the main ring, transmitted through the Branch B node, returned to the Master node, and then output outside the chip by the Master node. As can be seen, using the access device provided in the embodiment, the access path of a register only needs to pass through one main ring and one sub-ring, only needs to pass through the registers in one subsystem, and does not need to pass through the sub-ring where the Branch B node is located, and does not need to perform address matching on all registers in all subsystems in the chip. Since the number of registers in one subsystem is much lower than the total number of registers in the chip, the access method provided in the embodiment can significantly shorten the register access path length.

[0109] In a specific scenario, a single read operation can be performed. Since different subsystems have different UIDs, the target subsystem can be found through the UID, and the target register can be found through the Addr. In another specific scenario, a write operation is performed on a read-only register, and a register read error occurs.

[0110] Meanwhile, since the access device in Embodiment 1 includes multiple independent ring buses, and the access protocol in Embodiment 2 can distinguish access tasks through the JobId, the access method provided in the embodiment also supports batch reading and writing of registers.

[0111] The access method for registers in a super-large-scale chip provided in the embodiment can quickly access registers in a super-large-scale chip and a complex address scenario based on the access device provided in Embodiment 1 and the access protocol provided in Embodiment 2, and can support batch access, and has high practicability. The method is scalable, fast and efficient. It has guiding significance for the development of chip access technology.

[0112] Embodiment 4:

[0113] PCIe is a high-speed serial bus used to connect various peripheral devices. The PCIe bus is mainly divided into three protocol layers. From bottom to top, they are physical layer, data link layer and transaction layer, each layer has the ability to send and receive corresponding layer data packets. Data is generated in the user layer of the device, and the transaction layer packet (Transaction Layer Packet, abbreviated as TLP) is generated in the transaction layer, which is packaged layer by layer and transmitted to the transmit interface (Transmit, abbreviated as TX) of the device physical layer. TX pushes the complete data frame package to the PCIe link, and the opposite device receives the data packet through the receive port (Receive, abbreviated as RX), and then parses the data packet layer by layer and uploads it to the user layer of the opposite device.

[0114] With Figure 12 The existing PCIe bus structure in the prior art is taken as an example, wherein the three-layer functions of the PCIe controller (PCIe Core) are as follows:

[0115] (1) The physical layer is mainly to realize link training and initialization, coding and decoding, etc., and is used to connect a SERializer / DESerializer (SerDes) to realize physical transmission;

[0116] (2) The data link layer is mainly responsible for creating (sending) or parsing (receiving) data link layer packets (Data Link Layer Packet, abbreviated as DLLP), and realizes CRC error detection and correction, reordering retransmission, flow control and power management functions;

[0117] (3) The transaction layer is mainly responsible for creating (sending) or parsing (receiving) transaction layer packet TLP, traffic control, quality of service (Quality of Service, abbreviated as Qos), transaction ordering, etc.

[0118] DMA transmission is a way to realize massive data transmission between the peripheral device of the PCIe interface and the host memory or the host memory and the peripheral device of the PCIe interface. The peripheral device of the PCIe interface is referred to as an endpoint device. In general use scenarios, DMA read and write transmission is usually initiated by the endpoint device, and whether it is DMA read or DMA write, the endpoint device needs to submit an interrupt request through the PCIe interface to inform the host. Although the current DMA reduces the participation of the CPU, it does not support multiple users, and the performance and efficiency are limited.

[0119] In the traditional PCIe system, the Master device generates and sends PCIe packets (TLP) as initiator, and the Slave device receives and decodes the TLP packets. Usually, the CPU is the Master device, and initiates read / write operation to the memory (Memory) in the opposite end peripheral device. However, due to the busy state of the CPU in response to the return, it cannot receive and process in time, or due to the delay of the internal read operation response of the peripheral device, it may cause channel back pressure blockage, and further affect the performance of the CPU.

[0120] To effectively improve this problem, the most effective method is to use DMA. DMA does not require the participation of CPU, so it does not occupy CPU resources, and is suitable for large capacity data transmission, but the disadvantage is that the real-time performance is poor, and the CPU can only participate in control through interruption, therefore, this method also has the following technical problems:

[0121] 1. When transmitting data between the existing CPU and PCIe device, either the CPU is the Master and the peripheral device is the Slave, or the peripheral device is the Master and the CPU is the Slave. If the peripheral device and the CPU transmit different types of data in both directions, the Master / Slave mode needs to be supported at the same time;

[0122] 2. If the peripheral device has data to be actively reported and needs to be transmitted to the CPU, the CPU usually receives through interruption. If the interruption is frequent, it will occupy the CPU resources;

[0123] 3. When the device performs TLP read to the CPU, the next TLP read can be initiated only after the current read response (Completion) is returned. If the read delay is high, it will greatly affect the transmission performance. Therefore, additional read requests can be initiated before the first TLP read completion is received, which can support DMA multi-thread transmission;

[0124] 4. When the user has multiple data transmission task requirements, especially when there is a priority transmission requirement within the limited range of the PCIe controller, the existing DMA cannot prioritize and adjust the high priority task according to the user's requirements.

[0125] In order to solve the above technical problems, further improve the transmission performance and transmission efficiency, and reduce the number of host and hardware interactions and the number of interruptions, the embodiment provides a multi-thread transmission device, which enables DMA to support multi-thread processing and priority transmission.

[0126] As Figure 13As shown, the device includes a serial deserializer (PCIe SerDes), an interface controller (PCIe Core), a logic manager (PCIe Block Interface Logic, referred to as PCIe Logic hereinafter), and a direct memory access controller (DMA Controller, referred to as DMA controller hereinafter).

[0127] The PCIe interface is connected with the CPU through the serial deserializer, and the physical layer message received is deserialized into a transaction layer message (TLP message) and input to the interface controller, and the transaction layer message generated by the interface controller is serialized into a physical layer code stream and output to the CPU.

[0128] The interface controller processes the transaction layer message input by the serial deserializer or the logic manager, and / or generates a transaction layer message that needs to be output through the serial deserializer or the logic manager. In actual implementation, the serial deserializer (PCIe SerDes) and the interface controller (PCIe Core) are selected as standard IP cores according to needs, and the PCIe Core can also be extended according to needs.

[0129] In the device provided in the embodiment, in order to obtain lower transmission delay and increase processing performance of the PCIe, a logic manager (PCIe Logic) is added between the PCIe Core and the DMA controller for distributing processing data. The logic manager and the interface controller interact through transaction layer messages, the logic manager generates chip access messages in a specified format from the transaction layer messages, and outputs the chip access messages to the direct memory access controller in a pipeline form, and / or receives the chip access messages input by the direct memory access controller in a pipeline form, and generates corresponding transaction layer messages. As shown in the figure, Figure 13 As shown, the PCIe Core and the PCIe Logic transmit PCIe internal TLP messages. When the PCIe Core receives the PCIe TLP message, it detects the correctness of the format, and judges whether it is a flow control message or a configuration message. If it is a flow control message, it will be terminated in the PCIe Core; if it is a configuration message, it will be submitted to the PCIe Logic for subsequent processing or forwarding by the PCIe Logic. In actual implementation, in order to facilitate the transmission of TLP messages, the logic manager and the interface controller can use a TLP interface for intercommunication, or other bus interfaces such as AXI (Advanced eXtensible Interface) can be selected according to needs.

[0130] The direct memory access controller receives a chip access packet, outputs data to the outside of the device through the direct chip access interface, and / or receives externally input data through the direct chip access interface and converts the data into a chip access packet.

[0131] As shown in Figure 14 The logic manager includes a receiving module (RX Transaction decoder, RX decoder for short), a sending module (TX Transaction Arbitration, TX Arbitration for short), a slave endpoint module (pcie_slave), a master endpoint module (pcie_master), and an interface dependency module (interface Shim). The receiving module is configured to receive a transaction layer packet, identify a transaction layer packet type, and transmit the transaction layer packet to the master endpoint module or the slave endpoint module after decoding the transaction layer packet. The sending module is configured to receive a transaction layer packet generated by the master endpoint module or the slave endpoint module, and transmit the transaction layer packet to an interface controller. The slave endpoint module is configured to parse a base address space of data read / write in the transaction layer packet, and generate a corresponding bus signal and transmit the bus signal to a direct memory access interface. The master endpoint module is configured to determine whether the transaction layer packet is an expected reply, and / or generate a chip access packet in a specified format. The interface dependency module serves as a data interface between the master endpoint module and the direct memory access interface, and serves as a data interface between the slave endpoint module and the direct memory access interface.

[0132] As shown in Figure 15 The slave endpoint module includes a slave endpoint processing component (Slave), an interrupt controller (interruptManager), and a local register group (Local Registers). The slave endpoint processing component exchanges data between a signal bus and the direct memory access interface, and is configured to complete corresponding transaction layer packet processing when the device is used as a slave endpoint. The interrupt controller parses an interrupt signal generated by the direct memory access interface, and generates an interrupt signal submitted to a CPU. The local register group is configured to save a data transmission state in a PCIe interface, so that the logic manager obtains the data transmission state of the PCIe interface.

[0133] As shown in Figure 15As shown, the master endpoint module includes: a master endpoint processing component (Master), a request state machine (Request State Machine), a packet buffer (Packet Buffer), a read response tracking component (Completion Track & Reorder), and a reply buffer (Fragment Buffer). The master endpoint processing component is used to complete the corresponding transaction layer packet processing when the device is used as a master endpoint; the request state machine is used to process the data packet from the direct memory access interface, so that the device converts the data packet into a transaction layer packet in a pipeline form; the packet buffer is used to buffer the data packet from the direct memory access interface; the read response tracking component is used to process the read response completion packet of the transaction layer packet, so that the direct memory access interface obtains the response to each transaction layer packet, converts the transaction layer packet into a data packet in a specified format after sorting the transaction layer packet, and sends the converted data packet to the direct memory access interface; and the reply buffer is used to buffer the CPU valid reply transaction layer completion packet.

[0134] As shown in Figure 16 The data interaction between the PCIe Logic and the DMA channel architecture can be triggered by a message packet or a signal, such as a read / write request or a data pull / push signal. The specific process can be referred to as follows.

[0135] (1) When writing PCIe / DMA related configurations: the receiving module (pcie_rx) receives a memory write request (Memory Write, abbreviated as Mwr) TLP, and if it is identified as accessing a local register (BAR0 register), it is forwarded to pcie_slave through the SlaveRx interface, and the local register is configured through the RegBus, and no reply is required.

[0136] (2) When reading PCIe / DMA related configurations: pcie_rx receives a memory read request (Memory Read, abbreviated as Mrd) TLP, and if it is identified as accessing a local register (BAR0 register), it is forwarded to pcie_slave through the receiving interface (SlaveRx) of the slave endpoint module, and the local register configuration is read through the RegBus, and then the response (response) of the read register is sent to the sending module (pcie_tx) through the sending interface (SlaveTx) of the slave endpoint by pcie_slave, and pcie_tx encapsulates it as a data read completion (Completion with data, abbreviated as Cpld) TLP and sends it back to the CPU.

[0137] (3) When DMA reads data, but not the configuration process associated with DMA read: DMA initiates a data pull request (PullReq), pcie_master sends a read dynamic random access memory (DRAM) request through the MasterTx interface of the master endpoint module to pcie_tx, pcie_tx encapsulates as MrdTLP and sends to the root endpoint (RC) of the CPU; After the CPU's RC fetches data from the DRAM, it is sent to pcie_rx through Cpld TLP, pcie_rx identifies the returned read DRAM data, and then sends the read data to pcie_master through MasterRx, and pcie_master returns to DMA through PullResp.

[0138] (4) When DMA writes data, but not the configuration process associated with DMA write: DMA initiates a data push request (PushReq), pcie_master sends a DRAM write request (which contains the data to be written) to pcie_tx through MasterTx, pcie_tx encapsulates as Mwr TLP and sends to the RC of the CPU, and the RC of the CPU writes data into the DRAM.

[0139] (5) When transmitting an interrupt signal, the PCIe standard interrupt process can be used, or the above data read / write process can be adjusted.

[0140] In the above data read / write process, PCIe Logic converts all device node accesses to the PCIe BAR0 address space into signal bus request (RegBusReq) operations. At this time, the CPU acts as the master endpoint to guide the operation, and when the CPU wants to transmit data, it initiates a write access to the DMA RX register, writes the JobId and Page address into the BAR0 space, PCIe Logic initiates a RegBus write request, and the data is transmitted to the DMA through the RegBus. The DMA learns the current JobId and Page address. The CPU also pre-allocates a free Page address for the DMA and writes it into the DMA TX register, so that when the DMA has data to transmit to the CPU, it can directly push it to the free address space.

[0141] The device for multi-thread transmission provided by the embodiment additionally increases a PCIe Logic Interface Logic of the interconnection interface of the PCIe and the DMA engine relative to the existing PCIe and DMA communication interface, so that the data transmission can be transmitted along different transmission paths according to different types of data, and the Master / Slave mode is supported. In the transmission process, the DMA operation can directly initiate an additional TLP read operation without waiting for a previous read response to return, and the transmission task does not have to be delivered in sequence, and the TLP ordering and rearrangement mechanism is supported before being sent to the DMA engine, so that the multi-thread DMA is supported, and the transmission efficiency is improved.

[0142] Embodiment 5

[0143] On the basis of the device for multi-thread transmission provided by the above-mentioned embodiment 4, the application further provides a multi-thread transmission method for managing the data transmission process in the device.

[0144] As shown in Figure 17 The specific steps of the multi-thread transmission method provided by the embodiment of the application are as follows.

[0145] Step 401: When the peripheral device needs to pull the CPU data, the device generates a corresponding memory read request, obtains the corresponding data in the CPU according to the memory read request, the CPU side encapsulates the corresponding data into a transaction layer packet and sends it to the device, and the device pulls the data in the transaction layer packet to the peripheral device through a direct memory access interface.

[0146] In actual implementation, the RC of the CPU and the PCIe interface are connected through a TLP packet for data interaction. When the CPU needs to send data to the peripheral device, the RC of the CPU encapsulates the data into a TLP packet, and then sends the packet to the receiving module in the device provided by the embodiment 3 through the PCIe interface. After being processed by the corresponding channel in the device, the data is sent to the peripheral device through the DMA interface, and then the TLP packet is disencapsulated by the peripheral device to obtain the corresponding data.

[0147] Therefore, when the peripheral device needs to read data from the CPU, the data reading is performed in a pull (PullReq) request mode. After receiving the PullReq signal, the CPU initiates a corresponding data pull task. The PCIe controller RC in the CPU directly takes data from the DRAM and encapsulates the data into a completion TLP (transaction layer packet) as a response to the read completion, and sends the completion TLP to the receiving module through the PullResp mode. Since the CPU has previously sent the data page address required to be read by the peripheral device to the configuration space BAR0 in the form of a task, the DMA controller directly pulls the data page data to the DMA interface according to the data page address stored in the BAR0, thereby completing the data reading without intervention of the CPU. In the above process, the process of taking data by the CPU and the process of moving data by the DMA controller are independent of each other. Therefore, whether the DMA controller has completed the data pull or not, the DMA can start a new data reading task again, and the CPU can issue a new task multiple times, thereby realizing multi-threaded data transmission.

[0148] Step 402: When the peripheral device actively transmits data to the CPU, the device generates a corresponding memory write request, encapsulates the data obtained by the direct memory access interface into a corresponding transaction layer packet according to the memory write request, and pushes the data to a corresponding data page address through the transaction layer packet for use by the CPU when idle.

[0149] When the CPU needs to read data from the peripheral device, the peripheral device encapsulates the data into a TLP packet, and then sends the packet to the direct memory access controller in the device provided in Embodiment 3 through the DMA interface. After being processed by a corresponding channel in the device, the packet is sent to the CPU through the PCIe interface, and then the CPU decapsulates the TLP packet to obtain the corresponding data.

[0150] Therefore, when the peripheral device wants to actively transmit data to the CPU, the data is written in a push (Push) mode. After receiving the interrupt notification data write signal, the CPU asynchronously sends an idle memory page address to the BAR0. The DMA controller directly pushes the data to the idle memory page address (initially configured to be idle for all data pages in the CPU receiving pool) through the DMA mode without intervention of the CPU. When the CPU is idle, the CPU can directly take data. The use of the page and the timing release can reduce the number of interactions between the host and the hardware and the number of interrupts.

[0151] After the steps 401-402 provided in the embodiment, the data transmission between the PCIe and the DMA can be completed without intervention of the CPU.

[0152] In the above process, the TLP message is generated by an external device, the DMA can directly push the Memory Write data into the CPU's Memory, the Root Complex module in the CPU can directly take out the data from the DRAM and return the completion TLP reply message, without involving the processor. Therefore, before the first Read is received, additional read requests can also be initiated, achieving a pipelined access effect, so that the data transmission process in each direction can support multi-threaded transmission. In actual implementation, the user can initiate multiple transmission tasks and set the priority requirements of each task, and the DMA processes high-priority tasks in priority according to the high-priority processing principle. The combination of PCIe and DMA multi-threading realizes the high-speed transfer of a large amount of data, releases the CPU's computing power and processing waiting time in data transmission, expands the use scenario of DMA multi-threading, and further improves the transmission efficiency.

[0153] Based on the method provided in the embodiment, in Figure 15 In the hardware architecture shown, the process of message transmission in the PCIe Logic is divided into the following four parts:

[0154] (1) The solid arrow is the process of the CPU issuing a configuration task to the PCIe / DMA. The CPU encapsulates the data to be used during configuration as a corresponding transaction layer message and sends it to the receiving module. The receiving module parses the memory read request or memory write request in the encapsulated transaction layer message and sends the transaction layer message to the slave endpoint module. The slave endpoint module parses the base address in the transaction layer message and uses the request state machine to generate the corresponding bus signal. The bus signal is transmitted to the direct memory access interface through the signal bus, and the direct memory access interface executes the configuration processing in the transaction layer message. Specifically: in the above process, the CPU is the master and the peripheral device is the slave. The CPU encapsulates the configuration data as a completion TLP and sends the TLP to the receiving module through the PCIe interface. When the receiving module parses that the TLP is a Memory request to the PCIe base address register space, it will send the TLP to the slave endpoint module. The slave parses the TLP to obtain the BAR0 start address and uses the request state machine to generate the RegBus bus signal to transmit to the DMA, which executes the corresponding configuration processing. On the other hand, when the peripheral device completes the configuration, it will also encapsulate the JobID related to the configuration task and the Page address used into a recovery completion message and return it to the CPU, so that the CPU knows the configuration completion status.

[0155] (2) The dotted arrow is the flow of DMA moving data from CPU. When the transaction layer message is a read response completion message, the receiving module sends the transaction layer message to the master endpoint module, and the master endpoint module compares the received transaction layer message with the request information waiting for a reply; when the transaction layer message is the expected reply, a chip access message in a specified format is generated according to the transaction layer message, and the chip access message is sent to the direct memory access interface. Specifically: when the RX decoder parses that the TLP is a completion message, the TLP is sent to the master endpoint processing component, and then sent to the DMA sending port (RxDma). After the master endpoint processing component receives the TLP message, it will first compare with a series of request information waiting for a reply, if it is not the expected reply, it will be discarded or added to the error flag, if it is the expected reply, it will be placed in the FragmentBuffer. The master endpoint processing component is responsible for terminating the PCIe transaction, and the TLP message in each Job will be assembled and sorted to generate a chip access message in a specified format and sent to the DMA controller. Further, in order to avoid errors caused by reply timeout, each reply is provided with a timer, and if a reply is lost, the corresponding timeout error is reported to the PCIe Core.

[0156] In the above process, when data is written, the data page address and task number sent by the CPU are obtained from the endpoint module, and the data page address is sent to the direct memory access interface through the signal bus; after the corresponding data page is used and released, the direct memory access interface returns the released data page address to the CPU. Specifically: the CPU can send the JobId and data page address (Page Address) of the Page to the DMA through the signal bus (RegBus) through a memory write request. After the used Page is released, the DMA returns the Page Address to the CPU, and the CPU obtains the released Page Address through a memory read request for subsequent use. In this processing flow, the CPU acts as a master (Master) to issue a memory read request or a memory write request to the peripheral device, and the PCIe acts as a slave (Slave) to passively receive the memory read request or the memory write request of the CPU, thereby completing the corresponding response.

[0157] (3) The dotted arrow represents the flow of DMA moving data to the CPU. When the peripheral device sends data to the CPU, the direct memory access interface initiates a memory write request for writing data, and the host endpoint module encapsulates the chip access packet slice and sends the corresponding transaction layer packet. When the data is written to the data page, the CPU receives the data sent interrupt sent by the memory access interface, and the CPU knows that the data is available according to the interrupt. Specifically, if DMA needs to send data to the CPU, DMA initiates a PCIe transaction, and the host endpoint processing component encapsulates the chip access packet slice and sends a PCIe TLP packet. The DMA sending port (TxDma) sends the access reply packet to the PCIe host endpoint processing component, and then returns to the CPU via Tx Arbitration.

[0158] (4) The dotted line arrow represents the interrupt signal flow. When the DMA cache accumulates enough data, or a certain data in the DMA waits for a long enough time, the DMA pushes the data to the corresponding data page address, and sends an interrupt request signal to the receiving module. The receiving module uses the interrupt controller to parse the interrupt request signal and generates a corresponding interrupt signal. The sending module sends the interrupt signal to the CPU to trigger the interrupt of the CPU. Specifically, when the peripheral device pushes data to the CPU, after the DMA has pushed the data to the data page address, or at the same time, an interrupt (Message Signaled Interrupts, MSI for short) request signal is sent to notify the CPU that the data can be accessed. At this time, the PCIe device receives the interrupt request signal from the external DMA, the interrupt controller parses these signals and generates an interrupt signal. The interrupt signal is sent to the CPU to trigger the interrupt of the CPU, such as notifying the CPU that the Pages can be accessed.

[0159] From the above transmission flow, it can be seen that the four flows in the PCIe Logic do not affect each other, and the packets can be processed in a pipelined manner, improving the efficiency of data transmission and processing, and facilitating multiple users to access the chip without affecting each other.

[0160] Based on the above data transmission flow, the method provided in the embodiment can use the operation flow as shown in Figure 18 to complete the packet interoperation between DMA and PCIe.

[0161] When DMA needs to read data in the Page of CPU, DMA initiates a read request to PCIe Logic in a PullReq request mode, and then receives a completion reply from PullResp. When PCIe receives the reply data of PullReq, PCIe Logic returns the data to DMA in a Pull Response mode, so that the message in the Page is moved to DMA. When DMA has data to be transmitted to CPU, DMA initiates a write request to PCIe Logic in a Push mode, and directly pushes the data to the receiving pool Page of CPU.

[0162] In actual implementation, a flow control signal AF (Almost full) can be used to control the transmission process. The AF signal is an indication signal, and is used for data back pressure between PCIe Logic and DMA, so as to avoid data overflow. For example, PushAF corresponding to Push, PullReqAF corresponding to PullReq, and PullRespAF corresponding to PullResp. Through the flow control signal, the Pull operation can be divided into PullReq and PullResp, so that data request and reply acceptance have independent control signals respectively, so that the performance can be improved, and blocking or data overflow can be avoided.

[0163] In the above Pull and Push modes, the chip DMA completes data movement in a master endpoint mode, without the participation of CPU. In this way, the utilization rate of DMA and PCIe channel is greatly improved, so that data is continuously moved in a pipeline mode. At the same time, because of the cooperation of Job and Page, it is not necessary to wait for CPU to take away data. As long as the data returned by the chip is moved to CPU for memory data operation using the Free Page, the data returned by the chip can be moved to CPU.

[0164] In actual scenarios, the method provided in the embodiment can not only complete data transmission between CPU and on-chip registers, but also solve the bottleneck of data communication between a host and an external storage device. For example, Figure 19In the shown scenario, the DMA controller logic design mainly completes the function of actively initiating DMA read / write task with PCIe board device as Master device. The DMA control state register is mapped in the BAR0 space of the PCIe device. The data transmission direction of DMA write operation is from the PCIe board to the system host memory. The working task of DMA write transaction is to transmit the data read from the DDR3 SDRAM as external storage to the system memory through the PCIe hard core in the DMA mode. The DMA control state register will receive the memory write transaction initiated by the system host to the BAR0 space of the PCIe device. This transaction is to configure the DMA working parameters such as write destination address (Page Address), DMA transmission length (Page Range), etc. Then the sending engine starts to push the DMA write data to the system host. The working task of DMA read transaction is to read the data of specified size from the position of specified address in the system memory to the PCIe device. This transaction is realized by initiating the memory read transaction from the PCIe device to the system host. The DMA reads the data in the system memory and transmits it to the PCIe device and then to the DDR3 SDRAM. When the DMA read / write transaction is completed, the DMA controller decides whether to initiate the MSI interrupt according to the interrupt mask state. When the system host receives the interrupt initiated by the PCIe device, it will process the DMA transmission result.

[0165] The multi-thread transmission method provided by the embodiment has the following beneficial effects:

[0166] 1. From the endpoint side, by simultaneously supporting Master / Slave mode, breaking the limitation of device in hardware design, having more choices of transmission channels, supporting high-priority data priority transmission, supporting DMA multi-thread transmission, thereby improving transmission performance and creating more economic benefits;

[0167] 2. From the CPU side, according to the task-oriented data transmission, meeting the multi-user multi-thread demand, carrying more user demand in limited resources, therefore, from the CPU perspective, it can also create more economic benefits;

[0168] 3. From the perspective of bidirectional transmission, when both ends have data transmission demand, they have the right to actively read and write data, which facilitates the timeliness and flexibility of data transmission, and supports high-priority data priority processing, greatly improving transmission efficiency and performance.

[0169] Embodiment 6:

[0170] Based on the multi-threaded transmission device provided in Embodiment 4 and the multi-threaded transmission method provided in Embodiment 5, in some specific embodiments, the specific implementation in this embodiment can be implemented. It can be understood that the specific implementation provided in this embodiment is only used to illustrate the specific implementation process of the method or device in Embodiments 1-5 in some specific scenarios, and is not a limitation on the protection scope.

[0171] As shown in Figure 20 , it is a schematic diagram of a hardware structure for chip register access in a specific scenario. The device provided in Embodiment 4 is used to connect the CPU and the internal flower ring structure bus of the chip through PCIe+DMA, and the whole system is divided into a chip hardware part and an off-chip CPU software part; the DMA and PCIe transmit data at high speed through the hardware mode according to the method provided in Embodiment 5.

[0172] The plurality of subsystems inside the chip are distributed in a plurality of clock domains. The ring where the Master is located is the main ring, which is used to mount the access interface and the sub-ring. The rings where the Branch and the Nest are located are the sub-rings, which are the register groups of each subsystem of the chip. The Master is used for data interaction between the CPU and the DMA controller. The Branch is located at the intersection of the main ring and the sub-ring, and completes the cross-clock domain and distribution / aggregation functions of the Lizard data. The software SW accesses the chip, and writes the self-defined Lizard packet into the DMA cache through the CPU. The DMA controller and the PCIe interface move the data to the Master. The Branch distributes the data on the main ring based on the UID field in the extracted packet. The Lizard packet matching the UID enters the sub-ring across the clock domain, and the non-matching packet continues to be transmitted along the main ring. For the packet returned to the main ring from the sub-ring, after being crossed by the Branch, it is aggregated and output along the main ring together with the transparently transmitted Lizard packet. The transparently transmitted packet has a higher priority than the packet from the Branch. When the Lizard data packet completing the target register access appears on the main ring where the Master is located, the Master extracts the data and returns it to the DMA, and then returns it to the CPU. The Nest is the register group of the internal sub-module of the subsystem, which identifies and collects the Lizard packet matching the UID based on the unique UID of itself, parses the Lizard packet into the operation instruction of the register, and accesses the local register / table item. In addition, the Nest is also responsible for the access of the local register / table item and the reporting of the Event event to the CPU. The Event event has a high priority and can be transmitted to the CPU by the DMA in priority.

[0173] In actual implementation, the DMA operation is task-oriented, and JobId is used to identify a specific task. The software SW can initiate one or more Jobs at a time, and each task can apply one or more Pages to store a plurality of Lizard packets. The specific operation is as follows Figure 21The thick arrow is the operation of reading data from the DRAM / writing data to the DRAM, at this time, the PCIe of the peripheral device is the master, the DMA is the salver, the two types of operations follow the DMA read-write operation requirements, at this time, the peripheral chip is the master device. The thin arrow is the operation of configuring the DMA related register, at this time, the CPU is the master, the PCIe of the peripheral device is the slave, at this time, the peripheral chip is the slave device. The RxDma can identify different priority Jobs and go to different FIFO queues, the TxDma can identify the Response message or the Event message to go to the corresponding FIFO queue. The used Page is released. The interrupt is used to notify the CPU that a DMA Page has been sent or has been received. From the above process, it can be seen that, in the actual data transmission process, the Mwr writes the DMA page address into the BAR0 register through the task channel of the thin arrow, and then the DMA moves the data through the corresponding page address through the thick arrow channel, and the task issuing process and the data read-write process use different channels to be completed independently, so that multiple read-write tasks are performed in multiple threads in parallel.

[0174] In the above scenario, the complete process of register access is as follows:

[0175] Step 501: SW on the CPU issues an access request, when the access request is called for the first time, the SW will apply for a new Page, and write the Lizard message in the DMA memory to prepare for sending.

[0176] Step 502: The SW completes a Page, and writes the Page address and JobId into a Job FIFO of the RxDma through the way of writing the DMA register. In actual implementation, multiple Job FIFOs can be used to distinguish the high and low priority of different Jobs.

[0177] Step 503: The RxDma gets a Job from the Job FIFO, and pulls the Page data corresponding to the Job from the DRAM through the way of DMA reading data, and adds the JobId, SeqNo and other information in the message, and sends the packets to the ring bus of the access device one by one.

[0178] Step 504: When the DMA Page has been sent, the RxDma sends it back to the SW through the Done FIFO.

[0179] Step 505: The Lizard packet enters the main ring through the Master, and is matched one by one along the multiple sub-rings mounted on the main ring, until it enters the corresponding sub-ring according to the packet UID. Since the mounting positions of different sub-rings on the main ring are different, and the processing time in different sub-rings is different, the transmission order of the packet returning to the main ring on the main ring may be different from that when it enters the main ring, and the returned packet may need to be reordered according to the required order.

[0180] Step 506: TxDma checks the integrity of the returned packet. Whenever a new JobId appears, a new DMA Page is released by the Free FIFO, and then the packet is written to the corresponding position according to the SeqNo. Each returned packet is written to its corresponding DMA Page.

[0181] Step 507: TxDma obtains the whereabouts of all packets returned by the Job through the SeqNo and JobLast information.

[0182] Step 508: When all the packets including the last one are received, TxDma sends them to the Resp FIFO. When the FIFO has enough entries, or an entry has been waiting for a long enough time, an interrupt is generated to inform the CPU that the received Pages can be used.

[0183] Step 509: TxDma directly pushes the data to be sent to the CPU, regardless of whether the CPU has taken the data or not, and TxDma has started processing the next Page.

[0184] Step 510: The incoming Event packet is also saved in a Page, and when the Page has enough entries, or an entry has been waiting for a long enough time, an interrupt is generated to inform the CPU that the received Pages can be used. However, if a certain Event is marked as the highest priority, the Page will be sent out immediately.

[0185] After the steps 501-510 provided in the embodiment, the complete access process of the register is realized, and the management and control of the packet are realized.

[0186] The above only describes the preferred embodiments of the present application and is not used to limit the present application. Any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A multi-thread transmission device, characterized in that: include: Serializers (SERIDs), interface controllers, logic managers, and direct memory access controllers, including: The PCIe interface is connected to the CPU through a serial deserializer (SERD), which deserializes received physical layer messages into transaction layer messages and then inputs them into the interface controller. It also serializes the transaction layer messages generated by the interface controller into a physical layer code stream and outputs it to the CPU. The interface controller processes the transaction layer message input by the serial deserializer or the logic manager, and / or generates the transaction layer message to be output by the serial deserializer or the logic manager; The logic manager interacts with the interface controller via transaction layer messages. The logic manager generates chip access messages in a specified format from the transaction layer messages and outputs the chip access messages to the direct memory access controller in a pipelined manner. The logic manager also receives chip access messages input from the direct memory access controller in a pipelined manner and generates corresponding transaction layer messages. The direct memory access controller receives the chip access message and outputs the data to the outside of the device through the direct chip access interface, and / or receives external input data through the direct chip access interface and converts it into the chip access message; The logic manager includes: a receiving module, a sending module, a slave endpoint module, a master endpoint module and an interface dependency module; the receiving module is used to receive transaction layer messages, parse and identify the transaction layer message type, and transmit the transaction layer messages after decoding to the master endpoint module or the slave endpoint module; the sending module is used to receive transaction layer messages generated by the master endpoint module or the slave endpoint module, and transmit the transaction layer messages to the interface controller; the slave endpoint module is used to parse the base address space for data reading and writing in the transaction layer messages, and generate corresponding bus signals for transmission to the direct memory access interface; the master endpoint module is used to determine whether the transaction layer message is an expected reply, and / or, to generate a chip access message in a specified format; the interface dependency module serves as a data interface between the master endpoint module and the direct memory access interface, and as a data interface between the slave endpoint module and the direct memory access interface.

2. The multi-thread transmission device according to claim 1, characterized in that: The slave endpoint module includes: a slave endpoint processing component, an interrupt controller and a local register group, specifically including: The slave endpoint processing component exchanges data with the direct memory access interface via the signal bus, and is used to complete corresponding transaction layer message processing when the device is used as a slave endpoint; The interrupt controller analyzes the interrupt signal generated by the direct memory access interface and generates an interrupt signal submitted to the CPU; The local register group is used to save the data transmission status in the PCIe interface so that the logic manager can obtain the data transmission status of the PCIe interface.

3. The multi-thread transmission device according to claim 1, characterized in that: The master endpoint module includes: a master endpoint processing component, a request state machine, a packet cache, a read response tracking component and a reply cache, specifically including: The master endpoint processing component is used to complete corresponding transaction layer message processing when the device is used as a master endpoint; The request state machine is used to process data packets from the direct memory access interface so that the device converts the data packets into transaction layer messages in a pipeline manner; The packet cache is used to cache data packets from the direct memory access interface; The read response tracking component is used to process the read response completion message of the transaction layer message, so that the direct memory access interface obtains the response to each transaction layer message, sorts the transaction layer message and converts it into a data packet in a specified format, and sends the converted data packet to the direct memory access interface; The reply buffer is used to cache transaction layer completion messages that the CPU effectively replies to.

4. A multi-thread transmission method, characterized in that: The device for multi-thread transmission using any one of claims 1 to 3 specifically comprises: When a peripheral device needs to pull CPU data, the apparatus generates a corresponding memory read request, obtains the corresponding data in the CPU according to the memory read request, and the CPU encapsulates the corresponding data into a transaction layer message and sends it to the apparatus. The apparatus pulls the data in the transaction layer message to the peripheral device through the direct memory access interface; When the peripheral device actively transmits data to the CPU, the device generates a corresponding memory write request, assembles the data obtained by the direct memory access interface into a corresponding transaction layer message according to the memory write request, and pushes the data to the corresponding data page address through the transaction layer message for use by the CPU when it is idle.

5. The multi-thread transmission method according to claim 4, characterized in that: When the transaction layer message is a configuration message of a PCIe or direct memory access interface, the device generates a corresponding memory read request, obtains corresponding data in the CPU according to the memory read request, and the CPU encapsulates the corresponding data into a transaction layer message and sends it to the device, specifically including: The CPU encapsulates the data required for configuration into a corresponding transaction layer message and sends it to the receiving module. The receiving module parses the memory read request or memory write request in the encapsulated transaction layer message and sends the transaction layer message to the slave endpoint module. The endpoint module parses the base address in the transaction layer message and uses the request state machine to generate the corresponding bus signal. The bus signal is transmitted to the direct memory access interface through the signal bus, and the direct memory access interface performs the configuration processing in the transaction layer message.

6. The multi-thread transmission method according to claim 4, characterized in that: When the transaction layer message is a read response completion message, the CPU obtains the corresponding data in the memory read request, the CPU encapsulates the corresponding data into a transaction layer message and sends it to the device, and the device pulls the data in the transaction layer message to the peripheral device through the direct memory access interface, specifically including: The receiving module sends the transaction layer message to the master endpoint module, and the master endpoint module compares the received transaction layer message with the request information waiting for reply; When the transaction layer message is an expected reply, a chip access message in a specified format is generated according to the transaction layer message, and the chip access message is sent to the direct memory access interface.

7. The multi-thread transmission method according to claim 4, characterized in that: The method further comprises assembling the data obtained from the direct memory access interface into a corresponding transaction layer message according to the memory write request, and pushing the data to the corresponding data page address through the transaction layer message. When data is written, the data page address and task number sent by the CPU are obtained from the endpoint module, and the data page address is sent to the direct memory access interface through the signal bus; After the corresponding data page is used up and released, the direct memory access interface returns the released data page address to the CPU.

8. The multi-thread transmission method according to claim 4, characterized in that: When the peripheral device sends data to the CPU, the data obtained by the direct memory access interface is assembled into a corresponding transaction layer message according to the memory write request, and the data is pushed to the corresponding data page address through the transaction layer message, specifically including: The direct memory access interface initiates a memory write request for writing data. The master endpoint module encapsulates the chip access message slices and sends the corresponding transaction layer message. When data is written to the data page, the CPU receives an interrupt from the memory access interface indicating that the data has been sent. The CPU is informed that the data is available based on the interrupt.

9. The multi-thread transmission method according to claim 4, characterized in that: The step of assembling the data obtained from the direct memory access interface into a corresponding transaction layer message according to the memory write request, and pushing the data to the corresponding data page address through the transaction layer message specifically includes: When DMA pushes data to the corresponding data page address, it sends an interrupt request signal to the receiving module; The receiving module uses the interrupt controller to parse the interrupt request signal and generate the corresponding interrupt signal; The interrupt signal is sent to the CPU through the sending module to trigger the CPU interrupt.

Images