Prototype verification system and method for heterogeneous chip

Abstract

The invention provides a prototype verification system and method for a heterogeneous chip, and the method comprises the steps: generating a netlist file corresponding to each FPGA board card through a control terminal according to the RTL code of a to-be-verified heterogeneous chip and the configuration information of a connection board, and transmitting each netlist file to a prototype verification platform; the prototype verification platform sends a control instruction to at least one target FPGA board card according to each netlist file; wherein the control instruction is used for controlling all FPGA board cards including the target FPGA board card to enter a running state based on the corresponding netlist file through the target FPGA board card; and the prototype verification platform generates a prototype verification result of the heterogeneous chip to be verified according to the communication interaction states of all the FPGA board cards in the running state. Through the implementation of the scheme of the application, interconnection and intercommunication and hardware resource sharing among a plurality of FPGA board cards can be realized, and the prototype verification efficiency of heterogeneous chips is improved while the comprehensiveness of function point coverage in the prototype verification process is ensured.

Description

Technical Field

[0001] The present application relates to the field of chip manufacturing technology, and in particular to a prototype verification system and method for heterogeneous chips. Background Art

[0002] Heterogeneous (System-on-chip, SOC) chips refer to chips that integrate different types of processors on the same chip, which can give full play to the core advantages of various processors and improve overall performance. Compared with traditional chips, heterogeneous chips have more complex functions and larger scale, and the difficulty of prototyping heterogeneous chips is also higher. Before chip tape-out, it is necessary to conduct full coverage testing of the functions of heterogeneous chips.

[0003] Programmable heterogeneous chips can be compiled into different functional modules according to different application scenarios and reused in multiple application scenarios. As the scale of heterogeneous chips becomes larger and the functions become more complex, the prototype verification stage has great challenges in covering the functional points of heterogeneous chips and simulating and testing the application scenarios. In related technologies, the prototype verification of chips is usually implemented based on a single FPGA (Field-Programmable Gate Array) verification platform. For highly integrated and large-scale programmable heterogeneous chips, the hardware resources of a single FPGA may not be able to meet the full functional verification of heterogeneous chips. Since it is difficult to fully verify the functions and performance of heterogeneous chips, the performance of the produced chips may be inconsistent with expectations during actual application. Summary of the invention

[0004] The embodiments of the present application provide a prototype verification system and method for heterogeneous chips, which can at least solve the problem that the prototype verification test of heterogeneous chips is not comprehensive due to insufficient hardware resources.

[0005] In a first aspect, an embodiment of the present application provides a prototype verification system for heterogeneous chips, comprising: a verification platform, a control terminal respectively connected to the verification platform for communication, a connection board, and a plurality of FPGA boards; all FPGA boards are electrically connected to the connection board;

[0006] The control terminal is used to combine the RTL code of the heterogeneous chip to be verified and the configuration information of the connection board to generate the netlist files corresponding to each FPGA board, and send each netlist file to the verification platform;

[0007] A verification platform is used to send control instructions to at least one target FPGA board according to each netlist file, and the control instructions are used to instruct the target FPGA board to control all FPGA boards to enter the running state based on the corresponding netlist files; according to the communication interaction state of all FPGA boards in the running state, a prototype verification result of the heterogeneous chip to be verified is generated.

[0008] A second aspect of an embodiment of the present application provides a prototype verification method for a heterogeneous chip, which is applied to the prototype verification system described in the first aspect. The prototype verification method includes:

[0009] The control terminal combines the RTL code of the heterogeneous chip to be verified and the configuration information of the connection board to generate a netlist file corresponding to each FPGA board, and sends each netlist file to the prototype verification platform;

[0010] The prototype verification platform sends a control instruction to at least one of the target FPGA boards according to each netlist file; wherein the control instruction is used to control all FPGA boards including the target FPGA board through the target FPGA board to enter a running state based on the corresponding netlist file;

[0011] The prototype verification platform generates prototype verification results of the heterogeneous chip to be verified based on the communication interaction status of all FPGA boards in operation.

[0012] As can be seen from the above, according to the prototype verification system and method for heterogeneous chips provided by the present application, the control terminal combines the RTL code of the heterogeneous chip to be verified and the configuration information of the connection board to generate a netlist file corresponding to each FPGA board, and sends each netlist file to the prototype verification platform; the prototype verification platform sends a control instruction to at least one of the target FPGA boards according to each netlist file; wherein the control instruction is used to control all FPGA boards including the target FPGA board through the target FPGA board to enter the running state based on the corresponding netlist file; the prototype verification platform generates the prototype verification result of the heterogeneous chip to be verified according to the communication interaction state of all FPGA boards in the running state. In the present application, multiple FPGA board resources are integrated through the connection board, and the netlist files corresponding to each FPGA board are generated according to the RTL code of the heterogeneous chip to be verified and the configuration information of the connection board. Each netlist file is compiled separately by the verification platform and downloaded to the corresponding FPGA board for prototype verification. While ensuring the efficient use of FPGA hardware resources, the comprehensive test of the functions and performance of the heterogeneous chip can be completed. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A schematic diagram of the overall structure of a prototype verification device provided in the first embodiment of the present application;

[0014] Figure 2 A schematic diagram of the overall structure of a connecting plate provided in the first embodiment of the present application;

[0015] Figure 3 A basic flow chart of a prototype verification method provided for the second embodiment of the present application. DETAILED DESCRIPTION

[0016] In order to make the purpose, features, and advantages of the invention of this application more obvious and easy to understand, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0017] In the description of the embodiments of the present application, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0018] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0019] In the embodiments of the present application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0020] In related technologies, chip heterogeneity is not a simple addition of multiple processors, but requires optimization and innovation in hardware architecture, and a complete software environment to achieve interaction and data synchronization between heterogeneous computing acceleration units and central processing units, and to be compatible with the multi-threaded scheduling requirements of the operating system. Programmable heterogeneous chips are integrated with multiple cores and can be used for different needs such as scheduling and acceleration. There are many types of heterogeneous solutions depending on the application scenario, which can be CPU+FPGA, CPU+ASIC, CPU+GPU, or CPU+AI. These architectures all use the advantages of one architecture to make up for the shortcomings of another architecture to adapt to the user's application needs for multiple purposes. The complexity of the chip heterogeneous structure also brings challenges to the prototype verification process.

[0021] In some prototype verification schemes, FPGA can be used as the main control chip, and the synthesized netlist file can be downloaded to the FPGA for functional testing; however, for programmable heterogeneous chips, huge FPGA hardware resources are consumed. The large resource occupancy rate will lead to problems such as timing constraint errors in the netlist synthesis process, making it difficult to achieve test verification covering all functional points.

[0022] In order to solve the problem of insufficient hardware resources in related technologies leading to incomplete prototype verification testing of heterogeneous chips, the first embodiment of the present application provides a prototype verification system for heterogeneous chips, including a verification platform, a control terminal, a connection board, and multiple FPGA boards that are respectively connected to the verification platform for communication; all FPGA boards are electrically connected to the connection board; the control terminal is used to generate a netlist file corresponding to each FPGA board in combination with the RTL code of the heterogeneous chip to be verified and the configuration information of the connection board, and send each netlist file to the verification platform; the verification platform is used to send a control instruction to at least one target FPGA board according to each netlist file, the control instruction is used to instruct the target FPGA board to control all FPGA boards to enter a running state based on the corresponding netlist file; and a prototype verification result of the heterogeneous chip to be verified is generated according to the communication interaction state of all FPGA boards in the running state.

[0023] Specifically, the prototype verification system of the present application can perform prototype verification on programmable heterogeneous chips with ultra-large-scale integrated circuits. Each netlist file includes components (e.g., logic gates, registers, etc.) corresponding to the functional circuits of the heterogeneous chips to be verified and the connection relationships between them. Multiple FPGA board resources are integrated through a connecting board, and netlist files corresponding to each FPGA board are generated according to the RTL code of the heterogeneous chip to be verified and the configuration information of the connecting board. After separate compilation, they are downloaded to each FPGA board for prototype verification, which can complete comprehensive testing of the functions and performance of heterogeneous chips while ensuring efficient use of FPGA hardware resources.

[0024] like Figure 1 As shown, in some implementations, various FPGA boards, connection boards and other devices can be integrated into a prototype verification device, and a corresponding verification platform can be configured, so that communication interaction between the verification device and the control terminal can be achieved through the verification platform to complete the verification test.

[0025] Furthermore, in this embodiment, the multiple FPGA boards include a master FPGA board and a functional FPGA board; the master FPGA board is also connected to the control terminal; the master FPGA board is used to receive control instructions, and enter the running state in response to the control instructions, and send corresponding control signals to the functional FPGA board through the connecting board; the control signal is used to instruct the functional FPGA board to enter the running state.

[0026] Specifically, the main control FPGA board is connected to the control terminal, and the control terminal can be a PC host equipped with an application program, which can realize the control of the entire heterogeneous chip and perform netlist synthesis. In one embodiment, the target FPGA board can refer to the above-mentioned main control FPGA board, and the prototype verification platform can send control instructions to the main control FPGA board, and download each netlist file to the corresponding FPGA board respectively, so that each FPGA board including the main control FPGA board can be controlled by the main control FPGA board to run based on the corresponding netlist file. Further, in a specific embodiment, the main control FPGA board can send a control signal to the corresponding functional FPGA board through the connecting board based on the corresponding netlist file, that is, send an execution request; after receiving the execution request, the functional FPGA board can respond to the execution according to the execution request, and when the main control FPGA board receives the response signal of the functional FPGA board, it is determined that the handshake between the main control FPGA board and the functional FPGA board is successful, and the verification is passed.

[0027] In this embodiment, the target FPGA board may refer to the above-mentioned master FPGA board. The master FPGA board is provided with a processor, a bus and a JTAG interface; the processor and the connection board are connected via a bus, and the JTAG interface is connected to the control terminal. The verification system is also provided with an FPGA debugging board, which can realize the connection between the processor and the PC host through the JTAG interface. The PC host completes the control of the processor through the JTAG interface, so as to input, output and monitor signals, and observe and control the logic and state inside the FPGA board, thereby controlling the entire heterogeneous chip.

[0028] Furthermore, in this embodiment, the bus is an AXI (Advanced eXtensible Interface) bus, and the functional FPGA board is provided with heterogeneous modules. The AXI bus and the connection board, and the connection board and the heterogeneous modules are connected respectively through serial-to-parallel conversion modules; the heterogeneous modules are used to execute operating tasks determined based on the corresponding netlist files; the serial-to-parallel conversion modules are used to realize the conversion between serial data and parallel data; and the control signal is a parallel data signal corresponding to the operating task.

[0029] Specifically, the AXI bus is a high-performance, high-bandwidth, and scalable bus protocol, which is used in the verification system to connect heterogeneous modules to processors through a connection board to achieve efficient data transmission and management. The connection board in this embodiment can be a high-speed connection board. Considering that the data and address bit widths of the AXI bus are large and the rate is fast, the method of directly connecting to a high-speed adapter board may affect the normal operation of the AXI bus and make debugging difficult. This embodiment utilizes the IP tool in the design software, that is, using a serial-to-parallel conversion module, which can convert the bus signal of the AXI into a SerDes signal, and then expand the bus through a high-speed adapter board, so that the heterogeneous modules can be connected to the expanded AXI bus for data interaction, and efficiently complete the signal transmission between the heterogeneous modules and the AXI bus.

[0030] The heterogeneous module of this embodiment can realize accelerated data computing in the form of a coprocessor. Taking the video image heterogeneous chip as an example, the heterogeneous module is mainly responsible for accelerating the processing of computationally intensive tasks in the field of video images, using self-developed vector and matrix operation instructions to complete tasks such as filtering and pixel-level parallel operations, supporting double-precision floating-point and single-precision floating-point operations; special storage units can also be set up to meet the storage needs of the module; in addition, the heterogeneous module has an integrated DMA (Direct-Memory Access) unit for data transfer.

[0031] In some embodiments, the AXI bus can send an execution request for at least part of the running task to the heterogeneous module through the serial-to-parallel conversion module. If the heterogeneous module performs a running test in response to the execution request and feeds back the relevant results to the AXI bus through the serial-to-parallel conversion module and the high-speed connection board, it is determined that the verification is passed; if the processor cannot normally send the execution request to the heterogeneous module through the AXI bus, the high-speed connection board, and the serial-to-parallel conversion module, or the heterogeneous module cannot respond to the execution request corresponding to the AXI bus, it indicates that the verification fails and the heterogeneous chip needs to be structurally improved or redesigned.

[0032] It should be noted that during the transmission of data signals between the AXI bus and the heterogeneous modules, if the AXI bus is used as a signal transmitting end, the serial-to-parallel conversion module corresponding to the AXI bus is used to convert parallel data into serial data, and the serial-to-parallel conversion module corresponding to the heterogeneous module is used to convert serial data back into parallel data; if the AXI bus is used as a signal receiving end, the serial-to-parallel conversion module corresponding to the AXI bus is used to convert serial data into parallel data, and the serial-to-parallel conversion module corresponding to the heterogeneous module is used to convert parallel data back into serial data. In this way, efficient data transmission between the AXI bus and the heterogeneous modules is achieved.

[0033] Furthermore, in this embodiment, an APB (Advanced Peripheral Bus) bus is also connected between the processor and the connection board; the APB bus is connected to the processor and the connection board, and is used to read and write the registers of the heterogeneous modules through the connection board during the prototype verification process, so as to realize the communication interaction between the APB bus and the heterogeneous modules. Specifically, the APB bus is mainly for the processor to access the peripheral registers, and the control of the peripherals is realized by reading and writing the registers. In the verification system, the processor reads and writes the registers of the heterogeneous modules through the APB bus. The data and address bit width of the APB bus is small, and the rate is low, and it can be directly connected to the adapter board for expansion. In this way, the heterogeneous modules can be bound to the AXI bus and APB bus on the processor side through the high-speed connection board to realize the interconnection and intercommunication between the main control FPGA board and the functional FPGA board.

[0034] In some embodiments, the processor may also send an execution request for some running tasks to the heterogeneous module through the APB bus. If the heterogeneous module performs a running test in response to the execution request and feeds back relevant results to the APB bus, it is determined that the verification is passed. If the processor cannot normally send an execution request to the heterogeneous module through the APB bus or the high-speed connection board, or the heterogeneous module cannot respond to the execution request corresponding to the APB bus, it indicates that the verification fails and the heterogeneous chip needs to be structurally improved or redesigned.

[0035] Furthermore, if Figure 2 As shown, in this embodiment, the connecting board includes a first connector connected to the main control FPGA board, a second connector connected to the functional FPGA board, and a transmission channel connected between the first connector and the second connector; the transmission channel includes a first rate transmission channel corresponding to the AXI bus and a second rate transmission channel corresponding to the APB bus.

[0036] Specifically, the connection board supports bridging of SerDes pins and ordinary pin pins at the same time. The SerDes pins can be used to achieve high-speed transmission of the first rate transmission channel, and the pin pins can be used to achieve high-speed transmission of the second rate channel. The main control FPGA board can interact with the functional FPGA board at the heterogeneous module end through a high-speed adapter board to exchange data and read and write registers, realize the interconnection between the two FPGA boards, expand the hardware resources of the prototype verification platform, provide sufficient resource support for the prototype verification of heterogeneous chips, and cover the full-function verification of heterogeneous modules. In addition, REFCLK, that is, the reference clock signal, can also be set; REFCLK can provide a stable and accurate clock reference to ensure that each FPGA board in the system can operate according to the correct timing.

[0037] During the prototype verification process, the AXI bus and the APB bus can each correspond to one or more tasks. The AXI bus is also connected to a cache module, which is used to cache the task data corresponding to the running tasks that are not currently executed in multiple running tasks during the prototype verification process. The cache module can be a DDR board. The main control FPGA board can be defined as the CPU+bus end, and the functional FPGA board can be defined as the heterogeneous module end. The CPU+bus end and the heterogeneous module end can be run based on the corresponding netlist file respectively. The DDR board is integrated with DDR particles, which can be used to cache the intermediate data generated during the test process. For example, when a heterogeneous module is required to perform an accelerated running task, the processor stores the tasks and data to be processed in the cache module, and the DMA inside the heterogeneous module can transfer the task data and tasks in the cache module to the processing unit of the heterogeneous module through the bus and the high-speed connection board, complete the running task through the corresponding scheduling instructions and operation acceleration instructions, and return the result to the processor; when the processor receives the corresponding result response signal, it is determined that the verification is passed.

[0038] In this embodiment, the verification system also includes a reset module and a download module, and each FPGA board is connected to the reset module respectively; the reset module is used to synchronously control the power-on timing of all FPGA boards to avoid the bus locking caused by inconsistent reset timing during the prototype verification process; each FPGA board is also connected to the download module respectively to realize the download of FPGA bitstream files.

[0039] In this embodiment, when the control terminal executes the function of combining the RTL code of the heterogeneous chip to be verified and the configuration information of the connection board to generate a netlist file corresponding to each FPGA board, it is specifically used to: segment the RTL code of the heterogeneous chip to be verified, construct an engineering file corresponding to each FPGA board, and add a corresponding serial-to-parallel conversion IP to each engineering file; generate a constraint file according to the configuration information of the connection board; combine the engineering file and the constraint file for synthesis, and output the netlist file corresponding to each FPGA board.

[0040] Specifically, the control terminal can segment the RTL code under the total project of the heterogeneous chip based on the circuit structure characteristics and functional characteristics of the heterogeneous chip to be verified, and construct the engineering files corresponding to each FPGA board, that is, construct two independent projects for the CPU+bus end and the heterogeneous module end respectively. The configuration information of the connection board can be the specification information, model information, etc. of the interface and / or pins on the connection board. Pin constraints are performed according to the configuration information of the high-speed connection board (constraint files are obtained to generate the required netlist files), which can improve the accuracy and effectiveness of data transmission between the main control FPGA board and the functional FPGA board. Synthesis is the process of converting RTL code into an equivalent gate-level netlist. The synthesis tool generates a netlist representation of the logic gate based on the RTL code and the pin constraint file. In some specific embodiments, the synthesis process also includes steps such as timing optimization and area optimization to meet the design requirements of the heterogeneous chip and optimize the performance of the heterogeneous chip.

[0041] The second embodiment of the present application provides a prototype verification method for heterogeneous chips, which is applied to the prototype verification system described in the first embodiment, such as Figure 3 FIG. 1 is a basic flow chart of a prototype verification method for heterogeneous chips provided in the second embodiment of the present application. The prototype verification method includes:

[0042] Step 301: The control terminal generates a netlist file corresponding to each FPGA board card by combining the RTL code of the heterogeneous chip to be verified and the configuration information of the connection board, and sends each netlist file to the prototype verification platform.

[0043] Specifically, the RTL code of the heterogeneous chip is read and code segmented to build the engineering files corresponding to each FPGA board, and the pin constraints are performed according to the configuration information of the high-speed connection board to obtain the constraint files. Then the engineering files and constraint files of each FPGA board are integrated to obtain the required network standard files.

[0044] Step 302: The prototype verification platform sends control instructions to at least one of the target FPGA boards according to each netlist file.

[0045] Specifically, the control instruction is used to control all FPGA boards including the target FPGA board to enter the running state based on the corresponding netlist file through the target FPGA board. The FPGA board can determine the task data during its operation according to the corresponding netlist file, and then operate according to the task data.

[0046] In one embodiment, the target FPGA board may refer to the above-mentioned master FPGA board. The prototype verification platform may send control instructions to the master FPGA board and download each netlist file to the corresponding FPGA board respectively, so that the master FPGA board can control all FPGA boards including the master FPGA board to run based on the corresponding netlist files respectively. During the operation, the master FPGA board can test the functions corresponding to the CPU+bus, and the functional FPGA board can test the functions corresponding to the heterogeneous modules.

[0047] Step 303: The prototype verification platform generates a prototype verification result of the heterogeneous chip to be verified according to the communication interaction status of all FPGA boards in operation.

[0048] Specifically, after each FPGA board is in operation, the sending of control signals between the FPGA boards during operation and the response of the control signals can be detected to generate a prototype verification result of the heterogeneous chip to be verified.

[0049] Through the implementation of this embodiment, the control terminal combines the RTL code of the heterogeneous chip to be verified and the configuration information of the connection board to generate a netlist file corresponding to each FPGA board, and sends each netlist file to the prototype verification platform; the prototype verification platform sends a control instruction to at least one of the target FPGA boards according to each netlist file; wherein the control instruction is used to control all FPGA boards including the target FPGA board to enter the running state based on the corresponding netlist file through the target FPGA board; the prototype verification platform generates the prototype verification result of the heterogeneous chip to be verified according to the communication interaction state of all FPGA boards in the running state. In this embodiment, multiple FPGA board resources are integrated through the connection board, and the netlist files corresponding to each FPGA board are generated according to the RTL code of the heterogeneous chip to be verified and the configuration information of the connection board. After separate compilation, they are downloaded to two FPGA boards respectively through the verification platform for prototype verification, which can complete the comprehensive test of the functions and performance of the heterogeneous chip while ensuring the efficient use of FPGA hardware resources.

[0050] It can be understood that in this embodiment, the verification platform can be configured with a processor and a memory, and a computer program stored in the memory and can be run on the processor, and the memory is communicatively connected to the corresponding processor. The control terminal can also be configured with a processor and a memory, and a computer program stored in the memory and can be run on the processor, and the memory is communicatively connected to the corresponding processor. The above method is implemented by making the processor of the verification platform and the processor of the control terminal execute the corresponding computer program respectively. Among them, the verification platform and the control terminal can be configured with one or more processors.

[0051] The memory may be a high-speed random access memory (RAM) memory or a non-volatile memory, such as a disk memory. The memory is used to store executable program codes, and the processor is coupled to the memory.

[0052] Furthermore, an embodiment of the present application also provides a computer-readable storage medium, which may be disposed in the above-mentioned verification platform and / or control terminal.

[0053] The computer readable storage medium stores a computer program, and when the program is executed by the processor, the prototype verification method for heterogeneous chips in the aforementioned embodiment is implemented. Furthermore, the computer storable medium can also be a U disk, a mobile hard disk, a read-only memory (ROM), a RAM, a magnetic disk or an optical disk, and other media that can store program codes.

[0054] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0055] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0056] In addition, each functional module in each embodiment of the present application can be integrated into a processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or software functional modules.

[0057] If the integrated module is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a readable storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned readable storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard drives, ROM, RAM, magnetic disks, or optical disks.

[0058] It should be noted that, for the convenience of description, the aforementioned method embodiments are all described as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described action sequence, because according to the present application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0059] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0060] The above is a description of the prototype verification system and method for heterogeneous chips provided in this application. For technicians in this field, according to the ideas of the embodiments of this application, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on this application.

Claims

1. A prototype verification system for heterogeneous chips, characterized in that: It includes a verification platform, a control terminal, a connection board and a plurality of FPGA boards respectively connected to the verification platform for communication; all the FPGA boards are electrically connected to the connection board; The control terminal is used to generate a netlist file corresponding to each of the FPGA boards by combining the RTL code of the heterogeneous chip to be verified and the configuration information of the connection board, and send each of the netlist files to the verification platform; The verification platform is used to send control instructions to at least one target FPGA board card according to each of the netlist files, and the control instructions are used to instruct the target FPGA board card to control all of the FPGA boards to enter a running state based on the corresponding netlist files; and generate a prototype verification result of the heterogeneous chip to be verified according to the communication interaction state of all of the FPGA boards in the running state.

2. The prototype verification system according to claim 1, characterized in that: The plurality of FPGA boards include a master FPGA board and a functional FPGA board; the master FPGA board is also connected to the control terminal; The master FPGA board is used to receive the control instruction, enter the running state in response to the control instruction, and send a corresponding control signal to the functional FPGA board through the connecting board; the control signal is used to instruct the functional FPGA board to enter the running state.

3. The prototype verification system according to claim 2, characterized in that: The main control FPGA board is provided with a processor, a bus and a JTAG interface; the processor and the connection board are connected via the bus, and the JTAG interface is connected to the control terminal.

4. The prototype verification system according to claim 3, characterized in that: The bus is an AXI bus, and the functional FPGA board is provided with a heterogeneous module. The AXI bus and the connection board, and the connection board and the heterogeneous module are respectively connected through a serial-to-parallel conversion module; the heterogeneous module is used to execute an operation task determined based on the corresponding netlist file; the serial-to-parallel conversion module is used to realize the conversion between serial data and parallel data; the control signal is a parallel data signal corresponding to the operation task.

5. The prototype verification system according to claim 4, characterized in that: An APB bus is also connected between the processor and the connection board; the APB bus is connected to the processor and the connection board, and is used to read and write the registers of the heterogeneous module through the connection board during the prototype verification process, so as to realize the communication interaction between the APB bus and the heterogeneous module.

6. The prototype verification system according to claim 5, characterized in that: The connecting board includes a first connector connected to the main control FPGA board, a second connector connected to the functional FPGA board, and a transmission channel connected between the first connector and the second connector; the transmission channel includes a first rate transmission channel corresponding to the AXI bus and a second rate transmission channel corresponding to the APB bus.

7. The prototype verification system according to claim 4, characterized in that: The AXI bus is also connected to a cache module, and the cache module is used to cache task data corresponding to the running tasks that are not currently executed among the multiple running tasks.

8. The prototype verification system according to claim 1, characterized in that: The verification system also includes a reset module, and each of the FPGA boards is connected to the reset module respectively; the reset module is used to synchronously control the power-on timing of all the FPGA boards.

9. The prototype verification system according to claim 1, characterized in that: When the control terminal performs the function of combining the RTL code of the heterogeneous chip to be verified and the configuration information of the connection board to generate a netlist file corresponding to each of the FPGA boards, the control terminal is specifically used to: The RTL code of the heterogeneous chip to be verified is segmented, and an engineering file corresponding to each of the FPGA boards is constructed, and a corresponding serial-to-parallel conversion IP is added to each of the engineering files; a constraint file is generated according to the configuration information of the connection board; the engineering file and the constraint file are integrated to output a netlist file corresponding to each of the FPGA boards.

10. A prototype verification method for heterogeneous chips, characterized in that: Applied to the prototype verification system according to any one of claims 1 to 9, the prototype verification method comprises: The control terminal generates a netlist file corresponding to each of the FPGA boards by combining the RTL code of the heterogeneous chip to be verified and the configuration information of the connection board, and sends each of the netlist files to the prototype verification platform; The prototype verification platform sends a control instruction to at least one of the target FPGA boards according to each of the netlist files; wherein the control instruction is used to control all the FPGA boards including the target FPGA board through the target FPGA board to enter a running state based on the corresponding netlist file respectively; The prototype verification platform generates a prototype verification result of the heterogeneous chip to be verified according to the communication interaction status of all the FPGA boards in operation.

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