Parallel-in serial-out signal conversion circuit and digital micro-fluidic chip

Abstract

The invention discloses a parallel-in serial-out signal conversion circuit, and relates to the technical field of digital microfluidics, in particular to a parallel-in serial-out signal conversion circuit and a digital micro-fluidic chip, the parallel-in serial-out signal conversion circuit is applied to the digital micro-fluidic chip, and the parallel-in serial-out signal conversion circuit comprises a driving end, a first clock end, a second clock end, an output end, a parallel-in selection module and a register output module; the register output module is respectively connected with the merging selection module, the driving end, the second clock end and the output end; the driving end is used for accessing a driving voltage; the GOA circuit inherits the excellent performance of a traditional GOA circuit, the function of the GOA circuit is expanded, and the GOA circuit has a preset number function and can parallelly place data into a register; and the number setting ends transmit simultaneously, so that the data transmission rate is high.

Description

Technical Field

[0001] The present application relates to the field of digital microfluidics technology, and in particular to an input-to-output signal conversion circuit and a digital microfluidics chip. Background Art

[0002] In the prior art, GOA (Gate Driver on Array) can be used to realize the row-by-row scanning driving function of the liquid crystal panel. In the traditional active matrix liquid crystal display, the row scanning signal is realized by an external integrated circuit, and the use of GOA circuit drive saves the integrated circuit related to the scanning drive, realizing the reduction of the production cost of the liquid crystal display. The GOA circuit has two basic functions: the first is to output the gate scanning driving signal, drive the gate line in the panel, turn on the TFT in the display area, and charge the pixel; the second is the shift register function. When a gate scanning driving signal is output, the next gate scanning driving signal is output through clock control and passed on in sequence.

[0003] However, the existing GOA circuit cannot realize the preset number function, which leads to certain limitations in the use of microfluidic chips. It is impossible to put data into the register in parallel, and the transmission efficiency is low. Summary of the invention

[0004] The object of the present invention is to avoid the shortcomings of the prior art and provide a signal conversion circuit which can place data into a register in parallel and has high transmission efficiency.

[0005] The purpose of the present invention is achieved through the following technical solutions:

[0006] According to one aspect of the present invention, there is provided an in-line-to-serial signal conversion circuit, which is applied to a digital microfluidic chip, and comprises: a driving end, a first clock end, a second clock end, an output end, an in-line selection module and a register output module; the register output module is respectively connected to the in-line selection module, the driving end, the second clock end and the output end; the driving end is used to access a driving voltage; the first clock end is used to access a first clock signal; the second clock end is used to access a second clock signal; the in-line selection module comprises an input end, an enable end and a set end, and the in-line selection module further comprises a first transistor, a second transistor, a third transistor and a sixth transistor; the drain of the first transistor is connected to the input end, the drain of the second transistor is connected to the set end, the control electrode of the second transistor is connected to the enable end, and the drain and control electrode of the third transistor are connected to the driving end.

[0007] Specifically, the selection module is also incorporated including a fourth transistor; the drain of the fourth transistor is connected to the source of the third transistor and the control electrode of the first transistor; the control electrode of the fourth transistor is connected to the enable terminal; the source of the sixth transistor is separately connected to the register output module; the source of the fourth transistor is grounded.

[0008] More specifically, the sources of the first transistor and the second transistor are connected to the drain of the sixth transistor; and the control electrode of the first transistor is connected to the drain of the fourth transistor.

[0009] In the above, the register output module includes a register capacitor; a first end of the register capacitor is connected to the source of the sixth transistor, and a second end of the register capacitor is connected to the output end.

[0010] Furthermore, the registered output module also includes a fifth transistor, a seventh transistor and a tenth transistor; the control electrode and the drain of the fifth transistor are connected to the driving end; the source of the fifth transistor is connected to the drain of the tenth transistor; the drain of the seventh transistor is connected to the second clock end; the control electrode of the tenth transistor is connected to the source of the sixth transistor; and the source of the tenth transistor is grounded.

[0011] Furthermore, the register output module also includes a ninth transistor and an eleventh transistor; the control electrode of the eleventh transistor is connected to the drain of the tenth transistor; the drain of the eleventh transistor is connected to the control electrode of the ninth transistor and the control electrode of the seventh transistor.

[0012] Furthermore, the sources of the tenth transistor, the eleventh transistor and the ninth transistor are grounded; the drain of the ninth transistor and the source of the seventh transistor are connected to the second end of the parasitic capacitor.

[0013] The above also includes a reset module; the reset module is connected to the register output module, and the reset module is provided with a reset signal receiving end.

[0014] Furthermore, the reset module includes an eighth transistor; the control electrode of the eighth transistor is connected to the reset signal receiving end; and the drain electrode of the eighth transistor is connected to the second end of the parasitic capacitor.

[0015] According to another aspect of the present invention, a digital microfluidic chip is provided, which includes a plurality of parallel-input and serial-output units, wherein the parallel-input and serial-output units include the above-mentioned parallel-input and serial-output signal conversion circuit.

[0016] Beneficial effects of the present invention: The in-serial-out signal conversion circuit of the present application inherits the excellent performance of the traditional GOA circuit and expands its functions. It has a preset number function and can place data in parallel into a register; each preset number terminal transmits simultaneously, the data transmission rate is high, the sending speed is fast, and the signal width range of parallel transmission is larger, and the format requirements of the transmission signal are low. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 It is a schematic diagram of the principle of a serial-input-output signal conversion circuit according to an embodiment of the present application;

[0019] Figure 2 This is a waveform of a signal source setting and output result of a serial-to-output signal conversion circuit incorporated in an embodiment of the present application. Figure 1 ;

[0020] Figure 3 This is a waveform of a signal source setting and output result of a serial-to-output signal conversion circuit incorporated in an embodiment of the present application. Figure 2 ;

[0021] Figure 4 is a schematic diagram of a parallel-input and serial-output unit according to an embodiment of the present application;

[0022] Figure 5 is a schematic diagram of a five-stage cascade circuit of parallel-input and serial-output according to an embodiment of the present application;

[0023] Figure 6 is a waveform diagram of a cascade circuit signal source of an embodiment of the present application;

[0024] Figure 7 4 is a waveform diagram of the cascade circuit setting terminal and serial output according to an embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described through the implementation method with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present application.

[0026] In the description of the present invention, "several" means more than one, "many" means more than two, "greater than", "less than", "exceed", etc. are understood to exclude the number itself, and "above", "below", "within", etc. are understood to include the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing the technical features, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0027] In the description of the present invention, unless otherwise clearly defined, words such as "setting" should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meaning of the above words in the present invention in combination with the specific content of the technical solution.

[0028] In the description of the present invention, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0029] Example 1

[0030] like Figure 1 and Figure 4 As shown, a parallel-in serial-out signal conversion circuit is built into a parallel-in serial-out unit and applied to a digital microfluidic chip. The parallel-in serial-out signal conversion circuit includes: a driving end, a first clock end, a second clock end, an output end, a parallel-in selection module, a register output module and a reset module.

[0031] The register output module is respectively connected with the merge selection module, the reset module, the driving end, the second clock end and the output end.

[0032] The driving end is used to access the driving signal VDD; the first clock end is used to access the first clock signal CK; the second clock end is used to access the second clock signal XCK; and the output end is used to lead out the output signal OUT.

[0033] The reset module is connected to the register output module, and the reset module is provided with a reset signal receiving end for receiving a reset signal RESET.

[0034] The incorporation selection module includes an input terminal, an enable terminal and a set terminal, and the incorporation selection module also includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4 and a sixth transistor M6; the drain of the first transistor M1 is connected to the input terminal, the drain of the second transistor M2 is connected to the set terminal, the control electrode of the second transistor M2 is connected to the enable terminal, and the drain and control electrode of the third transistor M3 are connected to the driving terminal. The drain of the fourth transistor M4 is connected to the source of the third transistor M3 and the control electrode of the first transistor M1; the control electrode of the fourth transistor M4 is connected to the enable terminal; the source of the sixth transistor M6 is separately connected to the register output module; the source of the fourth transistor M4 is grounded. The sources of the first transistor M1 and the second transistor M2 are connected to the drain of the sixth transistor M6; the control electrode of the first transistor M1 is connected to the drain of the fourth transistor M4.

[0035] The input terminal is used to receive an input signal IN, the enable terminal is used to receive an enable signal EN, and the set terminal is used to receive a set signal SET.

[0036] Specifically, the register output module includes a register capacitor C1; a first end of the register capacitor C1 is connected to the source of the sixth transistor M6, and a second end of the register capacitor C1 is connected to the output end.

[0037] More specifically, the register output module further includes a fifth transistor M5, a seventh transistor M7, a ninth transistor M9, a tenth transistor M10 and an eleventh transistor M11.

[0038] The control electrode and drain electrode of the fifth transistor M5 are connected to the driving end; the source electrode of the fifth transistor M5 is connected to the drain electrode of the tenth transistor M10; the drain electrode of the seventh transistor M7 is connected to the second clock end;

[0039] The control electrode of the tenth transistor M10 is connected to the source electrode of the sixth transistor M6; the source electrode of the tenth transistor M10 is grounded. The control electrode of the eleventh transistor M11 is connected to the drain electrode of the tenth transistor M10; the drain electrode of the eleventh transistor M11 is connected to the control electrode of the ninth transistor M9 and the control electrode of the seventh transistor M7. The sources of the tenth transistor M10, the eleventh transistor M11 and the ninth transistor M9 are grounded; the drain electrode of the ninth transistor M9 and the source electrode of the seventh transistor M7 are connected to the second end of the parasitic capacitor C1.

[0040] More specifically, the reset module includes an eighth transistor M8; a control electrode of the eighth transistor M8 is connected to the reset signal receiving end; and a drain electrode of the eighth transistor M8 is connected to the second end of the parasitic capacitor C1.

[0041] In this embodiment, transistors M1 to M11 are all amorphous silicon thin film transistors, and the parasitic capacitor C1 is a parasitic capacitor of 12 pf. The drain of the first transistor M1 is controlled by the input signal IN; the drain of the second transistor M2 is controlled by the set signal SET, and the gate is controlled by the enable signal EN; the drain and gate of the third transistor M3 are controlled by the drive signal VDD; the gate of the fourth transistor M4 is controlled by the enable signal EN; the drain and gate of the fifth transistor M5 are controlled by the drive signal VDD, and the gate of the sixth transistor M6 is controlled by the first clock signal CK; the drain of the seventh transistor M7 is controlled by the second clock signal XCK, and the source leads to the output signal OUT; the gate of the eighth transistor M8 is controlled by the reset signal RESET.

[0042] The specific working principle, such as Figure 2 and Figure 3 As shown:

[0043] 1. Incorporate selection module

[0044] When the enable signal EN is at a high level, the second transistor M2, the third transistor M3 and the fourth transistor M4 are turned on, and the first transistor M1 is turned off. At this time, the set signal SET becomes the input signal of the circuit; when the enable signal EN is at a low level, the first transistor M1 and the third transistor M3 are turned on, and the second transistor M2 and the fourth transistor M4 are turned off. At this time, the input signal IN becomes the input signal of the circuit.

[0045] 2. Register output module

[0046] Phase ①: The input signal (here, the drain of the sixth transistor M6) is at a high level, the first clock signal CK is at a high level, the second clock signal XCK (external clock) is at a low level, the sixth transistor M6 is turned on, and the storage capacitor C1 stores the input signal.

[0047] Phase ②: The input signal (here refers to the drain of the sixth transistor M6) is at a low level, the first clock signal CK is at a low level, the second clock signal XCK is at a high level, the seventh transistor M7 is turned on, and the register capacitor C1 outputs the register signal, making the output signal OUT at a high level.

[0048] Phase ③: The input signal (here refers to the drain of the sixth transistor M6) is at a high level. At this time, the first clock signal CK is at a high level, the second clock signal XCK is at a low level, the sixth transistor M6, the ninth transistor M9, and the eleventh transistor M11 are turned on, which is conducive to the discharge of the capacitor, the seventh transistor M7 is turned off, and the output signal OUT is output at a low level.

[0049] 3. Reset module

[0050] When the reset signal RESET is at a high level, the eighth transistor M8 is turned on, and the output signal OUT is at a low level.

[0051] Depend on Figure 3 It can be seen from the simulation that when the set signal SET and the first clock signal CK are both at high level, the circuit shifts and outputs a high level signal. The GOA parallel-input and serial-output unit circuit of this structure can freely set the input signal and realize the shift register function of the signal.

[0052] According to another aspect of the present invention, a digital microfluidic chip is provided, which includes a plurality of parallel-input and serial-output units, wherein the parallel-input and serial-output units include the above-mentioned parallel-input and serial-output signal conversion circuit.

[0053] In this embodiment, if Figure 5 As shown, it is a five-stage cascade circuit of parallel input and serial output. Each parallel input and serial output unit is connected to the same enable signal EN, drive signal VDD, reset signal RESET, first clock signal CK and second clock signal XCK. Each parallel input and serial output unit is respectively connected to the corresponding set number signal SET ( Figure 5 SET1 to SET5 in the figure); and the output end of the preceding parallel-input and parallel-output unit is connected to the input end of the subsequent parallel-input and parallel-output unit. Figure 6 and Figure 7 It can be seen that when the set terminals SET of the parallel input are interval pulses, the units affect each other and can output the shift register signal in series. This signal is input in parallel and output in series, which can be used not only as GOA but also for transmitting detection signals.

[0054] In summary, the present application discloses an in-serial signal conversion circuit and a digital microfluidic chip, which inherit the excellent performance of the traditional GOA circuit and expand its functions. It has a preset number function, which can place data in parallel into the register; each setting end transmits simultaneously, the data transmission rate is high, the sending speed is fast, and the signal width range of parallel transmission is larger, and the format requirements of the transmission signal are low.

[0055] If the integrated unit described in the present application is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store program codes.

[0056] Note that the above are only preferred embodiments of the present application and the technical principles used. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present application. Therefore, although the present application is described in more detail through the above embodiments, the present application is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A serial-input and serial-output signal conversion circuit, used in digital microfluidic chips, It is characterized in that include: A driving end, a first clock end, a second clock end, an output end, an incorporation selection module and a register output module; The register output module is respectively connected to the merge selection module, the driving end, the second clock end and the output end; The driving end is used to access the driving voltage; The first clock terminal is used to access a first clock signal; the second clock terminal is used to access a second clock signal; The incorporated selection module includes an input terminal, an enable terminal and a set terminal, and the incorporated selection module also includes a first transistor, a second transistor, a third transistor and a sixth transistor; The drain of the first transistor is connected to the input terminal, the drain of the second transistor is connected to the set terminal, the control electrode of the second transistor is connected to the enable terminal, and the drain and control electrode of the third transistor are connected to the drive terminal.

2. The serial-input-output signal conversion circuit according to claim 1, Features: The incorporated selection module further includes a fourth transistor; The drain of the fourth transistor is connected to the source of the third transistor and the control electrode of the first transistor; the control electrode of the fourth transistor is connected to the enable terminal; The sources of the sixth transistors are connected to the register output modules separately; A source of the fourth transistor is grounded.

3. The parallel-in serial-out signal conversion circuit according to claim 2, Features: The source electrodes of the first transistor and the second transistor are connected to the drain electrode of the sixth transistor; The control electrode of the first transistor is connected to the drain of the fourth transistor.

4. A parallel-in serial-out signal conversion circuit according to claim 2 or 3, Features: The registered output module includes a registered capacitor; A first end of the parasitic capacitor is connected to the source of the sixth transistor, and a second end of the parasitic capacitor is connected to the output end.

5. The parallel-in serial-out signal conversion circuit according to claim 4, Features: The registered output module also includes a fifth transistor, a seventh transistor and a tenth transistor; The control electrode and the drain electrode of the fifth transistor are connected to the driving end; the source electrode of the fifth transistor is connected to the drain electrode of the tenth transistor; The drain of the seventh transistor is connected to the second clock terminal; The control electrode of the tenth transistor is connected to the source electrode of the sixth transistor; and the source electrode of the tenth transistor is grounded.

6. The parallel-in serial-out signal conversion circuit according to claim 5, Features: The registered output module also includes a ninth transistor and an eleventh transistor; The control electrode of the eleventh transistor is connected to the drain electrode of the tenth transistor; A drain of the eleventh transistor is connected to a control electrode of the ninth transistor and a control electrode of the seventh transistor.

7. The parallel-in serial-out signal conversion circuit according to claim 6, Features: Sources of the tenth transistor, the eleventh transistor and the ninth transistor are grounded; The drain of the ninth transistor and the source of the seventh transistor are connected to the second end of the parasitic capacitor.

8. A parallel-in serial-out signal conversion circuit according to claim 6 or 7, Features: Also includes a reset module; The reset module is connected to the register output module, and the reset module is provided with a reset signal receiving end.

9. The parallel-in serial-out signal conversion circuit according to claim 8, Features: The reset module includes an eighth transistor; The control electrode of the eighth transistor is connected to the reset signal receiving end; A drain of the eighth transistor is connected to the second end of the parasitic capacitor.

10. A digital microfluidic chip, It is characterized in that include: A plurality of parallel-in serial-out units, each of which comprises a parallel-in serial-out signal conversion circuit as claimed in any one of claims 1 to 9.

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