Semiconductor memory device and memory system

Abstract

A semiconductor memory device and a memory system are provided, the semiconductor memory device including: a first word line extending in a first direction; a first sub-word line driver including a first circuit and a second circuit connected to the first word line and spaced apart from each other in the first direction, in which the first circuit is configured to drive the first word line with a first voltage and the second circuit is configured to drive the first word line with a second voltage different from the first voltage; and a memory cell connected to the first word line between the first circuit and the second circuit.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2023-0072774, filed on Jun. 7, 2023, the disclosure of which is incorporated herein by reference. Technical Field

[0002] The present invention relates to integrated circuit devices and, more particularly, to integrated circuit memory devices. Background Art

[0003] A volatile semiconductor memory device such as a dynamic random access memory (DRAM) may perform a write operation or a read operation.

[0004] Recently, as the size of data stored in memory devices continues to increase and the manufacturing processes used to manufacture memory devices result in a reduction in device size within the memory devices, the distance between word lines selected in the row direction of the memory cells has gradually narrowed, such that each selected word line is spaced closer to adjacent unselected word lines. As will be appreciated by those skilled in the art, such a reduction in size and spacing can result in various defects by, for example, increasing the magnitude of electrical coupling between adjacent word lines. Summary of the invention

[0005] Embodiments of the present disclosure provide a semiconductor memory device having a sub word line driver therein that can improve a disable time of a word line and improve a coupling effect between adjacent word lines.

[0006] One or more embodiments of the present disclosure provide a semiconductor memory device, the semiconductor memory device comprising: a first word line extending along a first direction; and a sub-word line driver comprising a first circuit and a second circuit, the first circuit and the second circuit being connected to the first word line and spaced apart from each other along the first direction. The first circuit drives the first word line with a first voltage, and the second circuit drives the first word line with a second voltage different from the first voltage. A memory cell connected to the first word line is provided between the first circuit and the second circuit.

[0007] One or more embodiments of the present disclosure provide a semiconductor memory device, which includes: a cell array including memory cells; a first word line connected to the memory cells; a first block arranged on one side of the cell array and including a first circuit connected to the first word line to drive the first word line with a first voltage; and a second block arranged on the other side of the cell array and including a second circuit connected to the first word line to drive the first word line with a second voltage different from the first voltage.

[0008] One or more embodiments of the present disclosure provide a memory system, the memory system comprising: a cell array including a plurality of memory cells connected to a plurality of word lines; a memory controller outputting an address signal; a row decoder receiving the address signal and outputting a first signal for selecting a first word line from among the plurality of word lines based on the address signal, and a plurality of drive signals. A first sub-word line driver is provided, the first sub-word line driver comprising: a first transistor connected to one end of the first word line, the first transistor applying a first voltage to the first word line based on a first signal and a first drive signal among the plurality of drive signals; a second transistor applying a second voltage different from the first voltage to the first word line based on the first signal; and a third transistor connected to the other end of the first word line, and applying a second voltage to the first word line based on a second drive signal complementary to the first drive signal.

[0009] According to one or more embodiments of the present disclosure, an integrated circuit memory device is provided, the integrated circuit memory device comprising: an array of memory cells having word lines associated therewith; and a plurality of sub-word line drivers. The array of memory cells is arranged as rows of a plurality of memory cells spanning a plurality of columns of the array, and each of the plurality of rows has a corresponding word line associated therewith spanning the array (e.g., from a first side of the array to an opposite second side). A sub-word line driver is provided that includes a first circuit and a second circuit. Advantageously, the first circuit extends adjacent to the first side of the array, and the second circuit extends adjacent to the second side of the array. A first circuit electrically coupled to a first node of the word line on the first side of the array is configured to drive the word line with a pull-up voltage when the first circuit is activated. Conversely, a second circuit electrically coupled to a second node of the word line on the second side of the array is configured to drive the word line with a pull-down voltage when the second circuit is activated. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A block diagram of a memory device according to an embodiment is shown.

[0011] Figure 2 A layout of a memory device according to an embodiment is shown.

[0012] Figure 3 A circuit diagram of a sub-word line driver is shown.

[0013] Figure 4 Operation of a sub word line driver of a memory device using a timing diagram according to an embodiment is illustrated.

[0014] Figure 5 A structure of a sub word line driver according to an embodiment is shown.

[0015] Figure 6A circuit block diagram showing a memory device according to a structure of a sub-word line driver.

[0016] Figure 7 A circuit block diagram of a memory device including a sub word line driver according to an embodiment is shown.

[0017] Figure 8 A circuit block diagram of a memory device including a sub word line driver according to an embodiment is shown.

[0018] Fig. 9 A circuit block diagram of a memory device including a sub word line driver according to an embodiment is shown.

[0019] Fig.10 A circuit block diagram of a memory device including a sub word line driver according to an embodiment is shown.

[0020] Fig.11 A diagram showing simulation results of changes in word line voltage according to an embodiment.

[0021] Fig.12 A diagram showing simulation results of coupling between word lines according to an embodiment.

[0022] Fig.13 A block diagram of a memory system according to an embodiment is shown. DETAILED DESCRIPTION

[0023] In the following detailed description, only certain exemplary embodiments of the present invention have been shown and described simply by way of illustration. As those skilled in the art will appreciate, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

[0024] Therefore, the drawings and description are considered to be illustrative and not restrictive in nature. Throughout the specification, the same reference numerals represent the same elements. In addition, unless explicit expressions such as "one" or "single" are used, the singular form may also be intended to include the plural form. Terms including ordinal numbers (such as first, second, etc.) will only be used to describe various constituent elements and will not be interpreted as limiting these constituent elements. These terms can be used for the purpose of distinguishing one constituent element from other constituent elements.

[0025] Figure 1A block diagram of a memory device according to an embodiment is shown. The memory device 100 may be a volatile memory device (such as a dynamic random access memory (DRAM), including a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate SDRAM (LPDDR SDRAM), a graphic double data rate SDRAM (GDDR SDRAM), a Rambus DRAM (RDRAM), etc.). However, this is only an example, and the type of the memory device 100 may not be limited thereto.

[0026] The memory device 100 may respond to a control command signal CMD and an address signal ADDR received from an external host such as a central processing unit (CPU), an application processor (AP), or a system on chip (SoC), and may store data received through a data signal DQ or may output data as the data signal DQ.

[0027] like Figure 1 As shown in FIG. 1 , the memory device 100 may include a control logic 110, a row decoder 130, a sub-cell array 150, a sense amplifier 151, a column decoder 170, and an input / output (I / O) gating circuit 190. The sub-cell array 150 may include a plurality of memory cells MC, and the memory cells may be arranged in a plurality of memory banks 150a to 150h. Figure 1 1 and 2. Eight memory banks 150a to 150h are shown, but the number of memory banks is not limited thereto. Each of the memory banks 150a to 150h may include a plurality of memory cells MC arranged in a two-dimensional array having a plurality of memory cells arranged in crossed rows and columns. In an embodiment, a plurality of rows may be defined by a plurality of word lines WL, and a plurality of columns may be defined by a plurality of bit lines BL.

[0028] The control logic 110 controls the operation of the memory device 100. For example, the control logic 110 may generate a control signal so that the memory device 100 performs a read operation, a write operation, an offset calibration operation, etc. In an embodiment, the control logic 110 may receive a control command signal CMD and an address signal ADDR from an external host. The address signal ADDR may include a row address RA indicating a row in the sub-cell array 150 and a column address CA indicating a column in the sub-cell array 150. The row address RA may be provided to the row decoder 130, and the column address CA may be provided to the column decoder 170. In response, the row decoder 130 may select at least one word line of the plurality of word lines WL by referring to the row address, and the column decoder 170 may select at least one bit line of the plurality of bit lines BL by referring to the column address.

[0029] The row decoder 130 may select a row to be activated from among a plurality of rows of the subcell array 150 based on the row address RA. To this end, the row decoder 130 may apply a driving voltage to a word line corresponding to the row to be activated. In an embodiment, a plurality of row decoders 130a to 130h corresponding to a plurality of memory banks 150a to 150h may be provided.

[0030] The column decoder 170 may select a column to be activated from among a plurality of columns of the subcell array 150 based on the column address CA. To this end, the column decoder 170 may activate the sense amplifier 151 corresponding to the column address CA through the I / O gating circuit 190. In an embodiment, a plurality of column decoders 170a to 170h respectively corresponding to the plurality of memory banks 150a to 150h may be provided.

[0031] In an embodiment, the I / O gating circuit 190 may gate input / output data and may include a data latch for storing data read from the subcell array 150 and a write driver for writing data to the subcell array 150. The data read from the subcell array 150 may be sensed by the sense amplifier 151 and stored in the I / O gating circuit 190, and the I / O gating circuit 190 may operate as a data latch.

[0032] In an embodiment, a plurality of sense amplifiers 151a to 151h respectively corresponding to the plurality of memory banks 150a to 150h may be provided. The sense amplifier 151 may sense and amplify data of a memory cell connected to a selected bit line BL. The sense amplifier 151 may output data read from a memory cell to the outside through an I / O gating circuit 190.

[0033] On the other hand, in order to prevent the loss of data stored in the memory cell MC, the memory device (such as DRAM) requires a refresh operation, which includes periodically sensing and amplifying the data of the memory cell MC and restoring it to the memory cell MC. Specifically, the refresh operation of the DRAM includes a row activation operation and a row precharge operation. The row activation operation consists of such an operation: when the row activation signal is enabled, the word line WL selected by the row address is activated; and the data stored in the memory cell is sent to the bit line BL, sensed and amplified by the operation of the sense amplifier 151, and stored in the memory cell MC again. The row precharge operation consists of such an operation: the word line WL selected by the row precharge command is disabled and the data stored in the memory cell MC is maintained for a specific period of time. In DRAM, the period during which the row activation signal is activated and the row activation operation occurs is defined as tRAS, and the period during which the row precharge operation occurs is defined as tRP. For the refresh operation of the DRAM, tRAS and tRP must be longer than the minimum required time tRAS(min) and tRP(min), respectively.

[0034] Figure 2 FIG. 2 shows a layout of a memory device according to an embodiment. Figure 2 , the memory device 100 may include a plurality of sense amplifier blocks (SABs) 220, a plurality of sub-cell arrays (SCAs) 230 in which a plurality of memory cells are disposed, a plurality of connection circuit blocks (Conj) 240, and a plurality of sub-word line driver blocks (SWDBs) 250.

[0035] The plurality of sub word line driver blocks 250 may be disposed between the plurality of sub cell arrays 230 and along the Figure 2 The plurality of connection circuit blocks 240 may be disposed between the plurality of sub-word line blocks 250 in the second direction D2 and between the plurality of sense amplifier blocks 220 in the first direction D1.

[0036] Reference Figure 2, the row decoder 210 may respond to the row address RA input from the outside to output the word line enable signals NWEI0 and NWEI1 and the pre-decoding signals PXI0 to PXI3 for enabling the selected word line among the word lines WL. The connection circuit block 240 may provide the drive signals (PXID0, ..., PXID3, PXIB0, ..., PXIB3) to the sub word line driver block SWDB based on the pre-decoding signals (PXI0, ..., PXI3). For example, the connection circuit block 240 may provide the first drive signal (PXID0, ..., PXID3) and the complementary second drive signal (PXIB0, ..., PXIB3) to the sub word line driver block SWDB. For example, the connection circuit block 240 may output the first drive signal PXID1 through the first drive signal line 241, and may output the second drive signal PXIB1 through the second drive signal line 242. In addition, in an embodiment, each connection circuit block 240 may supply a voltage higher than the power supply voltage (e.g., a boost voltage VPP) to a selected word line, and may apply a voltage lower than the ground voltage (e.g., a reverse bias voltage VBB) to an unselected word line, but the present disclosure is not limited thereto.

[0037] Each sub-word line driver block 250 may include a plurality of sub-word line drivers SWD. The plurality of sub-word line drivers SWD may be respectively connected to a plurality of word lines WL, and the plurality of word lines WL are connected to the memory cells MC disposed in the sub-cell array 230. That is, when the word line WL is driven by the sub-word line driver SWD and the bit lines BL and BLB are selected, one memory cell MC corresponding thereto may be accessed. In an embodiment, the access operation mode may include a read operation and a write operation.

[0038] The plurality of sense amplifier blocks 220 may include a plurality of sense amplifiers. In an embodiment, the plurality of sense amplifiers may be connected to Figure 1 Specifically, during a read operation of the memory device 100, when a word line WL selected by a row address RA is enabled, the sense amplifier ( Figure 1 151) is driven. When the sense amplifier ( Figure 1 When the sensed cell data is loaded onto the corresponding bit line BL, the column address CA is selected so that the cell data is transmitted through the I / O gating circuit ( Figure 1 190) in is output to the outside.

[0039] Figure 3 FIG. 2 shows a circuit diagram of a sub-word line driver. Figure 3, the memory device may include a first sub word line driver 310 connected to the first word line WL0, a second sub word line driver 320 connected to the second word line WL1, a first sense amplifier SA0 connected to the first bit line BL0, and a second sense amplifier SA1 connected to the second bit line BL1. Memory cells MC1 to MC4 may be connected to the word lines WL0 and WL1 and the bit lines BL0 and BL1, and the memory cells MC1 to MC4 may be arranged in a sub cell array SCA.

[0040] The first sub-word line driver 310 and the second sub-word line driver 320 may be arranged in different sub-word line driver blocks SWDB. The first sub-word line driver 310 and the second sub-word line driver 320 may have the same structure. As shown, the first sub-word line driver 310 may include a driver circuit 311 and a pull-down circuit 312. The driver circuit 311 may include a PMOS transistor MP0 and a first NMOS transistor MN0. Specifically, in the PMOS transistor MP0, the drive signal PXID0 may be connected to the source terminal, the word line enable signal NWEI may be connected to the gate terminal, and the first word line WL0 may be connected to the drain terminal. The PMOS transistor MP0 may be a pull-up transistor and may drive the first word line WL0 connected to the drain terminal in response to the word line enable signal NWEI and the drive signal PXID0. In the first NMOS transistor MN0, a precharge voltage corresponding to the reverse bias voltage VBB may be connected to the source terminal, the word line enable signal NWEI may be connected to the gate terminal, and the first word line WL0 may be connected to the drain terminal. The first NMOS transistor MN0 may be a pull-down transistor.

[0041] The pull-down circuit 312 may include a second NMOS transistor MN1. In the second NMOS transistor MN1, the complementary drive signal PXIB0 may be connected to a gate terminal, a precharge voltage corresponding to a reverse bias voltage VBB may be connected to a source terminal, and the first word line WL0 may be connected to a drain terminal. The second NMOS transistor MN1 may be a holding transistor for maintaining the corresponding word line at a reverse bias voltage (VBB) level when the first word line WL0 is not selected.

[0042] Figure 3 The sub-word line drivers 310 and 320 shown in the figure are shown as using the PMOS transistor MP0 as a pull-up transistor and using the NMOS transistors MN0 and MN1 as pull-down transistors and holding transistors, but are not limited thereto. However, in the following description, it is assumed that the sub-word line drivers 310 and 320 use the PMOS transistor MP0 as a pull-up transistor and use the NMOS transistors MN0 and MN1 as pull-down transistors and holding transistors.

[0043] Similar to the driver circuit 311 and the pull-down circuit 312 of the sub word line driver 310, the sub word line driver 320 may be connected to the word line WL1, and may include the driver circuit 321 and the pull-down circuit 322. The sub word line driver 320 may have the same or similar structure as described above with respect to the sub word line driver 310, and may perform the same or similar operation as described above with respect to the sub word line driver 310.

[0044] Figure 4 The operation of the sub-word line driver is shown in FIG. Figure 4 , the sub word line driver SWD can drive the word line WL with the boost voltage VPP or the reverse bias voltage VBB according to the word line enable signal NWEI.

[0045] The sub-word line driver SWD may pull up or down the voltage of the word line WL according to the word line enable signal NWEI. For example, before the first time point T1, the word line enable signal NWEI may have a high (H) level in an inactive state; from the first time point T1 to the second time point T2, the word line enable signal NWEI may have a low (L) level in an active state; and after the second time point T2, the word line enable signal NWEI may return to a high (H) level.

[0046] Before the first time point T1, the driving signal PXID may have a low level (e.g., a ground voltage VSS), and the complementary driving signal PXIB may have a high level (e.g., a boost voltage VPP). When the word line enable signal NWEI is in an inactive state, the word line WL may be maintained at a reverse bias voltage VBB. However, this is only an example, and the operation may not be limited thereto.

[0047] When a memory cell is accessed, a word line enable signal NWEI and a drive signal PXID corresponding to the memory cell may be activated. When the word line enable signal NWEI is activated at a low (L) level, the sub word line driver SWD may provide a boost voltage VPP provided by the drive signal PXID to the word line WL. Therefore, the sub word line driver SWD may drive the word line WL with the boost voltage VPP.

[0048] In an embodiment, when the word line enable signal NWEI is activated at a low (L) level at a first time point T1, the drive signal PXID may be converted to a boost voltage VPP, and the complementary drive signal PXIB may be converted to a low level (e.g., a ground voltage VSS). At the first time point T1, the PMOS transistor MP0 corresponding to the pull-up transistor of the sub-word line driver SWD may be turned on, and the first NMOS transistor MN0 corresponding to the pull-down transistor may be turned off. In addition, when the complementary drive signal PXIB is maintained at a low level, the second NMOS transistor MN1 corresponding to the holding transistor may be turned off. Therefore, the source terminals of the word line WL and the second NMOS transistor MN1 may be electrically disconnected, and the source terminals of the word line WL and the PMOS transistor MP0 may be electrically connected, so that the drive signal PXID having the boost voltage VPP level may be supplied to the word line WL.

[0049] When the memory cell access operation is completed, the sub-word line driver SWD may precharge the word line WL with the reverse bias voltage VBB. For example, the reverse bias voltage VBB may be a precharge voltage, however, this is only an example, and the precharge voltage is not limited thereto, and may be higher than the reverse bias voltage VBB and lower than the ground voltage VSS.

[0050] In an embodiment, when the word line enable signal (NWEI) is deactivated at a high (H) level at the second time point T2, the drive signal PXID may be converted to a low (L) level (ie, a ground voltage VSS level), and the complementary drive signal PXIB may be converted to a high (H) level.

[0051] When the complementary drive signal PXIB is turned to a high level, the second NMOS transistor MN1 may be turned on, and the source terminal of the second NMOS transistor MN1 may be electrically connected to the word line WL. In addition, when the drive signal PXID is turned to a ground voltage (VSS) level, the PMOS transistor MP0 may be turned off, and the source terminal of the PMOS transistor MP0 and the word line WL may be electrically disconnected. Therefore, the voltage of the word line WL may be reduced to a precharge voltage corresponding to the reverse bias voltage VBB.

[0052] In addition, the second NMOS transistor MN1 included in the sub-word line driver SWD can maintain the word line WL at a reverse bias voltage after the precharge operation. Therefore, regardless of the fluctuation or noise of the word line enable signal NWEI, the word line WL can maintain a stable voltage. Figure 2 and Figure 3, the word lines WL may share the word line enable signal NWEI in units of four or eight. For example, the sub-word line drivers 310 and 320 connected to the word lines WL0 and WL1 may receive the same word line enable signal NWEI. Therefore, the first word line WL0 connected to the first sub-word line driver 310 and the second word line WL1 connected to the second sub-word line driver 320 may be enabled or disabled by the same word line enable signal NWEI. In addition, the sub-word line drivers 310 and 320 receiving the same word line enable signal NWEI may be enabled or disabled by the drive signals PXID0, PXIB0, PXID1, and PXIB1 having different voltage levels. For example, even if the same word line enable signal NWEI is received, the first word line WL0 may be enabled by the drive signal PXID0 of the boost voltage VPP, and the second word line WL1 may be disabled by the drive signal PXIB1 of the reverse bias voltage VBB. In this case, the voltage of a disabled word line (e.g., WL1) adjacent to an enabled word line (e.g., WL0) may be unintentionally changed due to an undesirable parasitic coupling effect between word lines. For example, if the sub-word line driver SWD is the start point of word line WL1 at a node where it is connected to word line WL1, the end point of word line WL1 is adjacent to the sub-word line driver SWD of an adjacent word line (e.g., WL0). Therefore, areas where the influence of parasitic coupling between word lines is relatively high are located at the start point and the end point of the word line.

[0053] Figure 5 1 shows a structure of a sub-word line driver according to an embodiment. A first sub-word line driver SWD connected to a first word line WL0 according to an embodiment may include a driver circuit 511 and a pull-down circuit 513. The driver circuit 511 may include a PMOS transistor MP01 and a first NMOS transistor MN01, and the pull-down circuit 513 may include a second NMOS transistor MN1. The PMOS transistor MP01 and the first NMOS transistor MN01 of the driver circuit 511 may be connected in series, and the second NMOS transistor MN1 of the pull-down circuit 513 may be connected in parallel with the first NMOS transistor MN01. In an embodiment, the driver circuit 511 and the pull-down circuit 513 may be provided in different sub-word line driver blocks SWDB.

[0054] In an embodiment, the pull-down circuit 513 of the first sub word line driver SWD connected to the first word line WL0 may be spaced apart from the driver circuit 511. For example, when the driver circuit 511 is connected to one end of the first word line WL0, the pull-down circuit 513 may be connected to the other end of the first word line WL0. For example, when the point at which the driver circuit 511 is connected to the first word line WL0 is defined as the starting point of the first word line WL0, the pull-down circuit 513 may be connected to the end point of the first word line WL0. In an embodiment, a plurality of memory cells MC1 and MC2 connected to the first word line WL0 and the bit lines BL0 and BL1 may be arranged along one direction between the driver circuit 511 connected to the first word line WL0 and the pull-down circuit 513. For example, the driver circuit 511, the plurality of memory cells MC1 and MC2, and the pull-down circuit 513 may be arranged along the extending direction of the first word line WL0.

[0055] In an embodiment, the second sub word line driver SWD connected to the second word line WL1 may include a driver circuit 521 and a pull-down circuit 523. The structure of the second sub word line driver may be the same as that of the first sub word line driver. Figure 3 Compared with the sub word line driver of FIG. 1 , the position of the second NMOS transistor MN1 for applying the reverse bias voltage VBB to the word lines WL0 and WL1 is changed to the end point of the word lines WL0 and WL1, so that the disable time of the word lines WL0 and WL1 and the influence of coupling between the word lines can be improved.

[0056] Figure 6 A circuit block diagram of a memory device according to the structure of a sub-word line driver is shown. Figure 6 , the memory device may include a connection circuit block 610 including a drive signal generating circuit for generating drive signals PXID and PXIB, a sub word line driver block (SWDB) 620 including a sub word line driver (SWD), and a sub cell array (SCA) 630, wherein a plurality of memory cells are arranged in the sub cell array 630. A sub word line driver 621 may be arranged in one sub word line driver block SWDB. The sub word line driver 621 is connected to the word line WL1, and the sub word line driver 621 may drive the word line WL1 when the word line WL1 is selected or maintain the word line WL1 at a precharge voltage when the word line WL1 is not selected.

[0057] A plurality of sub-word line drivers SWD are distributed so as to drive each corresponding word line within a predetermined time. In addition, in order to more efficiently lay out the sub-word line drivers SWD and achieve improved performance, the sub-word line drivers SWD driving word lines adjacent to each other may be arranged in a zigzag pattern on the upper and lower sides of the corresponding middle sub-cell array 630. For example, Figure 6As highlighted in FIG. 6 , a sub word line driver 621 driving the second word line WL1 may be disposed at a lower side of the sub cell array 630 , and a sub word line driver 622 driving a third word line WL2 adjacent to the second word line WL1 may be disposed at an upper side of the sub cell array 630 .

[0058] In addition, as described above, the sub word line drivers SWD may be arranged so that most of the sub word line drivers SWD may be connected to word lines extending in a first direction and in a second direction opposite to the first direction. However, this structure may have a problem that the load of the word line increases as the distance from the sub word line drivers SWD increases.

[0059] Alternatively, when the sub-word line drivers SWD driving the word lines adjacent to each other are arranged in a zigzag shape on the upper and lower sides of the sub-cell array 630, the end of each word line is adjacent to the sub-word line driver SWD of the adjacent word line. Based on this favorable structure, the region with the greatest coupling effect between the word lines becomes the end of the word line.

[0060] Figures 7 to 10 FIG. 2 shows a circuit block diagram of a memory device including a sub-word line driver according to various embodiments. Figure 7, the PMOS transistor MP01 and the first NMOS transistor MN01 of the sub-word line driver SWD may be set in a different sub-word line driver block from the second NMOS transistor MN1. In an embodiment, the driver circuit 721 including the PMOS transistor MP01 and the first NMOS transistor MN01 of the sub-word line driver may be set in a different sub-word line driver block from the pull-down circuit 723 including the second NMOS transistor MN1. For example, the pull-down circuit 723 may be set in the first sub-word line driver block 720_1, and the driver circuit 721 may be set in the second sub-word line driver block 720_2. In an embodiment, the driver circuit 721 may be set in the second sub-word line driver block 720_2 closest to the row decoder 730. In an embodiment, the driver circuit 721 set in the second sub-word line driver block 720_2 closest to the row decoder 730 may be connected to the word line WL0 extending in one direction. This is also the same when the driver circuit 721 of the first sub-word line driver is set in the sub-word line driver block 720_3 farthest from the row decoder 730. That is, when the driver circuit 721 of the first sub-word line driver is disposed in the sub-word line driver block 720_3 farthest from the row decoder 730, the driver circuit 721 may be connected to the word line WL0 extending in one direction. In an embodiment, when the point at which the driver circuit 721 is connected to the word line WL0 is defined as the starting point of the word line WL0, the pull-down circuit 723 may be connected to the end point of the word line WL0. In an embodiment, when the driver circuit 721 is connected to one end of the word line WL0, the pull-down circuit 723 may be connected to the other end of the word line WL0. In an embodiment, a plurality of memory cells connected to the word line WL0 may be disposed between the driver circuit 721 connected to the word line WL0 and the pull-down circuit 723 along one direction.

[0061] Reference Figure 8, the first sub-word line driver SWD driving the word line WL1 may include a pair of pull-down circuits 823 and 825 connected in parallel to the driver circuit 821. In an embodiment, except for the driver circuits provided in the sub-word line driver block SWDB closest to or farthest from the row decoder 830, most of the driver circuits may be connected to the word lines extending in a first direction and a second direction opposite to the first direction centered on the driver circuit. In an embodiment, the pull-down circuits 823 and 825 connected to the word line WL1 may be provided in a different sub-driver block from the driver circuit 821. For example, the driver circuit 821 of the first sub-word line driver SWD may be provided in the first sub-word line driver block 820_1, the pull-down circuit 823 of the first sub-word line driver may be provided in the second sub-word line driver block 820_2, and the pull-down circuit 825 of the first sub-word line driver may be provided in the third sub-word line driver block 820_3. In an embodiment, word line WL1 may extend through first, second, and third sub word line driver blocks 820_1, 820_2, and 820_3. In an embodiment, pull-down circuits 823 and 825 connected to word line WL1 may be connected to both ends of word line WL1.

[0062] As reference Figure 6 As described above, when the word line WL extends in a first direction and a second direction opposite to the first direction relative to the sub word line driver SWD, as the distance from the sub word line driver SWD increases, the load of the word line WL may increase. According to an embodiment, when the driver circuit 721 is connected to one end of the word line WL0, an additional pull-down branch may be formed by connecting the pull-down circuit 723 to the other end of the word line WL0, or when the driver circuit 821 is connected to the word line WL1 extending in a first direction and a second direction opposite to the first direction centered on the driver circuit 821, an additional pull-down branch may be formed by connecting the pull-down circuits 823 and 825 to both ends of the word line WL1, which may advantageously increase the disable rate of the word line WL, thereby improving the disable slope of the word line WL and ensuring a better tRP of the memory device.

[0063] In addition, due to the characteristic that the coupling effect between word lines increases as the distance from the sub word line driver SWD increases, the sub word line driver SWD can reduce the coupling effect between word lines by providing pull-down circuits 823 and 825 for pull-down at the ends of the word lines. In particular, in a memory device having a 3D structure in which the distance between word lines is further narrowed, the coupling effect between word lines can be improved.

[0064] Reference Fig. 9, the first sub word line driver block 920_1 may include a first driver circuit 921 connected to the second word line WL1, pull-down circuits 923 and 925 connected to the third word line WL2 adjacent to the second word line WL1, and a third driver circuit 927 connected to the fourth word line WL3 adjacent to the third word line WL2. In an embodiment, a pull-down circuit connected to the same second word line WL1 as the first driver circuit 921 may be provided in the second sub word line driver block 920_2.

[0065] Reference Fig.10 , a first sub-word line driver SWD connected to a word line (such as WL2) may include a first driver circuit 1021 and a first pull-down circuit 1025. In an embodiment, the driver circuit and the pull-down circuit of the first sub-word line driver may be arranged in different sub-word line driver blocks SWDB. For example, the first pull-down circuit 1025 of the first sub-word line driver may be arranged in the first sub-word line driver block 1020_1, and the first driver circuit 1021 of the first sub-word line driver may be arranged in the second sub-word line driver block 1020_2. In this embodiment, the second driver circuit 1023 may be connected to the first pull-down circuit 1025. The second driver circuit 1023 and the first pull-down circuit 1025 may also be arranged in different sub-word line driver blocks. For example, the second driver circuit 1023 may be arranged in the third sub-word line driver block 1020_3, and the first pull-down circuit 1025 may be arranged in the first sub-word line driver block 1020_1. As shown, multiple spaced apart driver circuits 1021 and 1023 may be connected to the same first pull-down circuit 1025, which is generally located in the center between the driver circuit 1021 and the driver circuit 1023. Therefore, in the illustrated embodiment, multiple sub-word line drivers may share one NMOS transistor MN1 as a holding transistor used as a pull-down transistor.

[0066] Although not shown here, in an embodiment, a sub-word line driver block SWDB disposed on the opposite side of the first sub-word line driver block 1020_1 (with the third sub-word line driver block 1020_3 as the center) may be further included (that is, the third sub-word line driver block 1020_3 may be disposed between the first sub-word line driver block 1020_1 and the sub-word line driver block SWDB). In this case, the word line WL2 may extend through the sub-word line driver block SWDB disposed on the opposite side of the first sub-word line driver block 1020_1 with the third sub-word line driver block 1020_3 as the center, and the sub-word line driver block SWDB may include a pull-down circuit connected to the word line WL2.

[0067] Fig.11FIG. 2 is a diagram showing a simulation result of a change in a word line voltage according to a word line enable signal NWEI and a driving signal PXID. Fig.11 Together with Figure 4 At the first time point T1, when the word line enable signal NWEI of the sub word line driver SWD changes from a high level to a low level and the driving signal PXID changes from a low level to a high level, the sub word line driver SWD may drive the word line WL with the boost voltage VPP. At the second time point T2, when the word line enable signal NWEI of the sub word line driver SWD changes from a low level to a high level and the driving signal PXID changes from a high level to a low level, the sub word line driver SWD may precharge the word line WL with the reverse bias voltage VBB via the ground voltage VSS.

[0068] Reference Fig.11 , simulation results of the word line voltage 1131 of the sub-word line driver SWD according to the comparative example and the word line voltage 1132 of the sub-word line driver SWD according to the embodiment of the present disclosure are shown together. At the second time point T2 when the word line enable signal NWEI of the sub-word line driver SWD changes from a low level to a high level and the drive signal PXID changes from a high level to a low level, the word line voltage of the structure of the sub-word line driver SWD according to the comparative example is changed from the boost voltage VPP to the reverse bias voltage VBB. The disable time "ta" is 8.78ns. At the second time point T2, the disable time "tb" of the word line of the structure of the sub-word line driver SWD according to the embodiment of the present disclosure is 1.21ns. Therefore, as Fig.11 As shown by the curve of word line voltage 1131 relative to word line voltage 1132, in an embodiment, an additional pull-down branch can be formed by setting an NMOS transistor at the end or both ends of the word line WL, which can improve the disable slope of the word line WL.

[0069] Fig.12 A simulation result diagram of coupling noise 1210 between word lines of a sub word line driver SWD according to a comparative example and coupling noise 1220 between word lines of a sub word line driver SWD according to an embodiment is shown. As shown, at a first time point T1 when a word line enable signal NWEI of the sub word line driver SWD changes from a high level to a low level and a driving signal PXID changes from a low level to a high level, the coupling noise 1210 between word lines of the sub word line driver SWD according to the comparative example is 350 mV, while the coupling noise 1220 between word lines of the sub word line driver SWD according to an embodiment is much smaller, which is only 17 mV.

[0070] At the second time point T2 when the word line enable signal NWEI of the sub-word line driver SWD changes from a low level to a high level and the drive signal PXID changes from a high level to a low level, the coupling noise 1210 between the word lines of the conventional sub-word line driver SWD is 353 mV, and the coupling noise 1220 between the word lines of the sub-word line driver SWD according to the embodiment is about 45 mV. Therefore, according to the embodiment, the coupling noise between the word lines can be significantly improved by setting an NMOS "pull-down" transistor at the end (or both ends) of the word line WL. This has the advantage of reducing the distance between the word lines and increasing the number of memory cells MC connected to each bit line BL.

[0071] Fig.13 A block diagram of a memory system 1300 is shown according to an embodiment.

[0072] Reference Fig.13 , the memory system 1300 includes a processor 1310, a memory 1320, a memory controller 1330, a storage device 1340, a communication interface 1350, and a bus 1360. The memory system 1300 may also include other general constituent elements.

[0073] The processor 1310 controls the overall operation of each constituent element of the memory system 1300. The processor 1310 may be implemented as at least one of various processing units such as a central processing unit (CPU), an application processor (AP), and a graphic processing unit (GPU).

[0074] The memory 1320 stores various data and commands. The memory 1320 may be implemented as a reference Figures 7 to 10 Memory device described. In an embodiment, the memory 1320 may include a sub-word line driver SWD, the sub-word line driver SWD including a pull-up transistor, a pull-down transistor, and a holding transistor. In an embodiment, the memory 1320 may include a sub-word line driver SWD in which, when the pull-up transistor and the pull-down transistor are connected to one end of the word line WL, the holding transistor is connected to the other end of the word line WL. In an embodiment, the memory 1320 may include a sub-word line driver SWD in which the pull-down transistor is connected to both ends of the word line WL. In an embodiment, the memory 1320 may include a sub-word line driver SWD in which the holding transistor operates as a pull-down transistor. In an embodiment, the memory 1320 may include a plurality of sub-word line drivers SWD that share one holding transistor. The memory controller 1330 controls the transmission of data or commands to and from the memory 1320.

[0075] The storage device 1340 stores programs and data non-temporarily. In an embodiment, the storage device 1340 may be implemented as a non-volatile memory. The communication interface 1350 supports wired and wireless Internet communications of the memory system 1300. In addition, the communication interface 1350 may support various communication methods other than Internet communication. The bus 1360 provides a communication function between the constituent elements of the memory system 1300. The bus 1360 may include at least one type of bus according to the communication protocol between the constituent elements.

[0076] While embodiments of the disclosure have been described in connection with what are presently considered to be practical embodiments, it is to be understood that the disclosure is not limited to the disclosed embodiments, but on the contrary is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A semiconductor memory device, include: a first word line extending in a first direction; a sub word line driver including a first circuit and a second circuit connected to the first word line and spaced apart from each other along a first direction, wherein the first circuit is configured to drive the first word line with a first voltage, and the second circuit is configured to drive the first word line with a second voltage different from the first voltage; as well as A memory cell is connected to the first word line between the first circuit and the second circuit.

2. The semiconductor memory device according to claim 1, in, The first circuit includes a first transistor and a second transistor, the first transistor being connected between a first power source and a first node to which a first word line is connected, the second transistor being connected to the first node and being connected in series with the first transistor, The second circuit includes a third transistor connected between the first node and the second power supply. The first power supply is configured to provide a first voltage, the second power supply is configured to provide a second voltage, and The first voltage is higher than the second voltage.

3. The semiconductor memory device according to claim 1, in, The first circuit is connected to the first word line at one end of the first word line, and The second circuit is connected to the first word line at the other end of the first word line.

4. The semiconductor memory device according to claim 1, further comprising: include: The third circuit, which is provided on an opposite side of the second circuit with respect to the first circuit, is connected to the first word line and drives the first word line with a second voltage.

5. The semiconductor memory device according to claim 4, in, The second circuit is connected to the first word line at one end of the first word line, and The third circuit is connected to the first word line at the other end of the first word line.

6. The semiconductor memory device according to claim 4, further comprising: include: A memory cell is connected to a first word line between the first circuit and the third circuit along a first direction.

7. The semiconductor memory device according to claim 4, in, The second circuit and the third circuit have the same structure.

8. The semiconductor memory device according to claim 1, further comprising: include: a second word line adjacent to the first word line and extending in parallel with the first word line in a first direction; as well as The second sub-word line driver includes a fourth circuit and a fifth circuit, the fourth circuit is connected to the second word line, drives the second word line with a first voltage, and is arranged adjacent to the second circuit of the first word line in the second direction, and the fifth circuit is connected to the second word line, drives the second word line with a second voltage, and is arranged adjacent to the first circuit of the first word line in the second direction.

9. A semiconductor memory device, include: an array of memory cells; a first word line electrically connected to a first memory cell within the array of memory cells; a first block adjacent to a first side of the array of memory cells, the first block comprising a first circuit connected to a first word line and configured to drive the first word line with a first voltage; as well as A second block is adjacent to a second side of the array of memory cells, the second side opposite the first side, the second block including a second circuit connected to the first word line and configured to drive the first word line with a second voltage different from the first voltage.

10. The semiconductor memory device according to claim 9, in, The first circuit includes a pull-up transistor configured to pull the first word line down to a first voltage, and the second circuit includes a pull-down transistor configured to pull the first word line down to a second voltage.

11. The semiconductor memory device according to claim 10, further comprising: include: a third block disposed on an opposite side of the second block relative to the first block; wherein the first word line passes through the first block, the second block and the third block; and The third block includes a third circuit connected to the first word line and configured to drive the first word line with a second voltage.

12. The semiconductor memory device according to claim 11, in, The second circuit and the third circuit have the same structure.

13. The semiconductor memory device according to claim 12, in, The second circuit and the third circuit are connected to the first word line at one end and the other end of the first word line, respectively.

14. The semiconductor memory device according to claim 10, further comprising: include: a third block disposed on an opposite side of the first block relative to the second block; wherein the first word line extends through the first block, the second block, and the third block; and The third block includes a third circuit connected to the first word line and configured to drive the first word line with a first voltage.

15. The semiconductor memory device according to claim 14, in, The first circuit and the third circuit have the same structure.

16. The semiconductor memory device according to claim 15, further comprising: include: a fourth block disposed on an opposite side of the second block relative to the third block; wherein the first word line extends through the fourth block; and The fourth block includes a fourth circuit having a pull-down transistor connected to the first word line and configured to pull down the first word line to a second voltage.

17. The semiconductor memory device according to claim 10, in, The first circuit is connected to the first word line at one end of the first word line, and the second circuit is connected to the first word line at the other end of the first word line.

18. A memory system, include: a cell array including a plurality of memory cells connected to a plurality of word lines; a memory controller configured to generate address signals; a row decoder configured to receive an address signal, output a first signal for selecting a first word line from among the plurality of word lines based on the address signal, and output a plurality of driving signals; as well as The first sub-word line driver comprises: a first transistor connected to one end of the first word line and configured to apply a first voltage to the first word line based on the first signal and a first drive signal among the plurality of drive signals, a second transistor configured to apply a second voltage different from the first voltage to the first word line based on the first signal; as well as The third transistor is connected to the other end of the first word line and is configured to apply a second voltage to the first word line based on a second drive signal complementary to the first drive signal.

19. The memory system according to claim 18, further comprising: include: a first sub-word line driver block and a second sub-word line driver block, the first sub-word line driver block being disposed at a first side of the cell array, the second sub-word line driver block being disposed at a second side of the cell array, the first side being opposite to the second side relative to the cell array; wherein the first word line extends through the first sub-word line driver block, the cell array, and the second sub-word line driver block; and The first transistor and the second transistor are arranged in a first sub-word line driver block, and the third transistor is arranged in a second sub-word line driver block.

20. The memory system according to claim 19, in, The row decoder is further configured to output a second signal that selects a second word line adjacent to the first word line among the plurality of word lines based on the address signal; and Wherein, the memory system further includes a second sub-word line driver, and the second sub-word line driver includes: a fourth transistor connected to one end of the second word line, configured to apply a first voltage to the second word line based on the second signal and a third drive signal among the plurality of drive signals, and provided in the second sub word line driver block, a fifth transistor configured to apply a second voltage to the second word line based on the second signal and provided in the second sub word line driver block, and The sixth transistor is connected to the other end of the second word line, is configured to apply a second voltage to the second word line based on a fourth driving signal complementary to the third driving signal, and is disposed in the first sub word line driver block.

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