System and method for testing memory

Abstract

The invention provides a system for testing a memory. The system comprises a memory device and a testing device. The test device is operatively coupled to the memory device and transmits a plurality of surge signals and a plurality of control signals after the surge signals for a write operation of the memory device according to the data signal. The test device also determines whether read data output in a read operation of the memory device is bit shifted based on write data of the data signal to generate a test result. The system disclosed by the invention contributes to increasing the efficiency of memory testing.

Description

Technical Field

[0001] The present disclosure relates to a system and method for testing a memory, and more particularly to a system and method for testing a memory using a surge signal. Background Art

[0002] With the rapid development of memory technology, the size of memory is getting smaller and smaller while having high-density circuits. Higher-density circuits are beneficial to the speed and performance of memory, but errors and manufacturing problems increase accordingly. In order to ensure the reliability and yield of the product, it is crucial to effectively test the memory. Summary of the invention

[0003] In some embodiments, a system for testing a memory is provided. The system includes a memory device and a test device. The test device is operatively coupled to the memory device and transmits a plurality of burst signals and a plurality of control signals following the burst signals for a write operation of the memory device according to a data signal. The test device also determines whether the read data output in a read operation of the memory device is bit-shifted based on the write data of the data signal to generate a test result, and the test result indicates the interference to the write operation caused by the burst signals.

[0004] In some embodiments, the test device is operatively coupled to a first data strobe pin and a second data strobe pin of the memory device, the first and second data strobe pins receiving a differential data strobe signal pair, wherein the differential data strobe signal pair includes these control signals. The test device also outputs a first burst signal of these burst signals to the first data strobe pin and outputs a second burst signal inverted to the first burst signal to the second data strobe pin.

[0005] In some embodiments, in a write operation, the memory device latches data of the data signal in response to at least three rising / falling edges of a first burst signal of the burst signals and a first control signal of the idle signals.

[0006] In some embodiments, the first surge signal has a first voltage level in a first interval, and has a second voltage level in a second interval after the first interval.

[0007] In some embodiments, when the ratio of the first interval to the second interval is between 0.025 and 0.075, the read data and the write data are inconsistent.

[0008] In some embodiments, when the ratio of the first interval to the second interval is between 0.15 and 0.25, the read data and the write data are consistent.

[0009] In some embodiments, when the read data is bit-shifted compared to the write data, at least one inconsistent bit between the read data and the write data has a high logic value.

[0010] In some embodiments, a system for testing a memory is provided. The system includes a memory device and a test device. The memory device includes an input / output circuit. The test device is operatively coupled to the memory device and outputs a surge signal to the memory device and outputs a control signal after outputting the surge signal. The input / output circuit latches data for a write operation of the memory device in response to the surge signal and the control signal. The test device also compares the write data corresponding to the write operation with the read data output in the read operation of the memory device to determine whether the memory device is disturbed by the surge signal.

[0011] In some embodiments, the testing device further generates a surge signal at a first time point and generates a control signal at a second time point after the first time point.

[0012] In some embodiments, the input / output circuit latches the data at a third time after the second time.

[0013] In some embodiments, the burst signal has a first voltage level in a first interval and has a second voltage level greater than the first voltage level in a second interval after the first interval. When the ratio between the first interval and the second interval is greater than 0.125, the read data and the write data are consistent.

[0014] In some embodiments, the first interval and the second interval after the first interval of the burst signal have different voltage levels. When the ratio of the first interval to the second interval is less than 0.1, the written data and the read data are inconsistent.

[0015] In some embodiments, a method for testing a memory device is provided. The method includes: generating a write data signal to a first pin of the memory device; generating a burst signal and a control signal to a second pin of the memory device; latching data from the write data signal for a write operation in response to at least one of the burst signal and the control signal; performing a write operation to generate a read data signal; and outputting a test result by comparing the write data signal and the read data signal.

[0016] In some embodiments, the duration of the burst signal is shorter than the time interval of the memory device.

[0017] In some embodiments, the burst signal has a first voltage level in a first interval and has a second voltage level in a second interval different from the first interval.

[0018] In some embodiments, when the second interval is larger than the first interval, the read data is inconsistent with the written data.

[0019] In some embodiments, the method further includes displaying the write data signal and the read data signal by a display device to compare the write data signal and the read data signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The aspects of one embodiment of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0021] Figure 1 A schematic diagram of a system according to some embodiments of the present disclosure is shown;

[0022] Figure 2 Some embodiments of the present disclosure are shown in FIG. Figure 1 part of a system;

[0023] Figure 3A is a schematic diagram illustrating an exemplary waveform of a surge signal according to some embodiments of the present disclosure;

[0024] Figure 3B is a schematic diagram illustrating an exemplary waveform of a surge signal according to some embodiments of the present disclosure;

[0025] Figure 4 A schematic diagram illustrating an example waveform of a signal on a pin according to some embodiments of the present disclosure;

[0026] Figure 5 An exemplary waveform diagram of a signal on a pin is shown according to some embodiments of the present disclosure;

[0027] Figure 6 An exemplary waveform diagram of a signal of a pin according to some embodiments of the present disclosure is shown;

[0028] Figure 7 An exemplary waveform diagram of a signal of a pin according to some embodiments of the present disclosure is shown;

[0029] Figure 8 An exemplary waveform diagram of a signal of a pin according to some embodiments of the present disclosure is shown;

[0030] Fig. 9 A waveform diagram showing an example of a signal of a pin according to some embodiments of the present disclosure; and

[0031] Fig.10 The following is a flow chart illustrating an example of a method of a corresponding system according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0032] The following disclosure provides many different embodiments or examples for realizing the different features of the subject matter provided. The following describes specific examples of components and arrangements to simplify an embodiment of the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first and second features are directly contacted to form, and may also include an embodiment in which additional features are formed between the first and second features so that the first and second features may not be directly contacted. In addition, the present disclosure may repeat component symbols or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments or configurations discussed.

[0033] The terms used in this specification generally have their ordinary meaning in the art and in the specific context in which each term is used. The use of examples in this specification, including examples of any term discussed herein, is illustrative only and in no way limits the scope and meaning of an embodiment of the case or any exemplary term. Likewise, an embodiment of the case is not limited to the various embodiments given in this specification.

[0034] In this document, all terms such as "including", "with", "having", "containing", "involving", "having", "composed of", etc. should be construed as open-ended, ie, meaning including, but not limited to.

[0035] Reference throughout this specification to "one embodiment" or "some embodiments" means that a particular feature, structure, configuration, or characteristic described in conjunction with the embodiment is included in at least one embodiment. Therefore, the phrases "in one embodiment" or "in some embodiments" appearing in various places throughout this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular features, structures, configurations, or characteristics may be combined in any suitable manner.

[0036] Further, for ease of description, spatially relative terms such as "below," "under," "below," "above," and "above" may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0037] As used herein, "approximately", "about", "approximately" or "substantially" shall generally refer to any approximation of a given value or range, where it varies depending on the various fields involved, and its scope shall be consistent with the broadest interpretation understood by those skilled in the art to cover all such modifications and similar structures. In some embodiments, it shall generally refer to within 20 percent of a given value or range, preferably within 10 percent, and more preferably within 5 percent. The numerical values ​​given herein are approximate, meaning that if not explicitly stated, the terms "approximately", "about", "approximately" or "substantially" can be inferred, or other approximate values ​​are meant.

[0038] refer to Figure 1 According to some embodiments of the present disclosure, Figure 1 is a schematic diagram of the system 100. To illustrate, the system 100 includes a memory device 110, a test device 120, and a display device 130. In some embodiments, the display device 130 is operatively coupled to the test device 120 and the display device 130.

[0039] In some embodiments, the test device 120 is a test machine for testing memory, including but not limited to dynamic random access memory (DRAM) and static random access memory (SRAM). In some embodiments, the test device 120 is a programmable test machine. Figure 1 In the illustrated implementation, the testing device 120 includes a processor 121 .

[0040] According to different embodiments, the processor 121 includes a central processing unit (CPU), or other programmable general-purpose or special-purpose micro control unit (MCU), microprocessor, digital signal processor (DSP), programmable controller, application specific integrated circuit (ASIC), graphics processing unit (GPU), arithmetic logic unit (ALU), complex programmable logic device (CPLD), field programmable gate array (FPGA) or other similar components or combinations of the above components.

[0041] In some embodiments, the display device 130 is a device that displays information in the form of images, including a computer monitor, an oscilloscope, and other suitable devices.

[0042] In some embodiments, the memory device 110 is a hardware component that stores data, such as a DRAM device or an SRAM device. In some embodiments, the memory device 110 is a fifth-generation double data rate synchronous dynamic random-access memory (DDR5 SDRAM) chip. Figure 1 As shown, according to some embodiments, the memory device 110 includes a memory array 111, a control circuit 112, and a data input / output circuit 113. The memory array 111 includes a plurality of memory cells 114 (storage units) arranged in a two-dimensional or three-dimensional array. According to different embodiments, the memory cells 114 include volatile memory cells, non-volatile memory cells, or a combination thereof.

[0043] Operationally, the memory array 111 further includes word lines WL0, WL1, ... WLJ and bit lines BL0, BL1, ... BLK. In some embodiments, the word lines WL0-WLJ and the bit lines BL0-BLK include conductive metal or conductive rails. For illustration, each of the memory cells 114 is coupled to a corresponding word line WL (one of the word lines WL0-WLJ) and a corresponding bit line (one of the bit lines BL0-BLK). In some embodiments, the memory array 111 includes additional lines, such as a select line, a reference line, a reference control line, and a power rail.

[0044] According to some embodiments of the present disclosure, the control circuit 112 is a hardware component that performs operations on the memory array 111 according to instructions (e.g., instructions from the test device 120). For example, in some embodiments, the control circuit 112 performs a write operation or a read operation on the memory array 111 according to the instructions from the control circuit 112. In some embodiments, the control circuit 112 is used to write data to the memory array 111 or read data from the memory array 111 through word lines WL0-WLJ and bit lines BL0-BLK.

[0045] In some embodiments, the data input / output circuit 113 is a hardware component that receives data for a write operation or outputs data for a read operation. For example, in some embodiments, the data input / output circuit 113 receives data from the test device 120 and the control circuit 112 writes the data into the memory array 111 according to an instruction from the test device 120. For example, in some embodiments, the control circuit 112 reads data from the memory array 111 according to an instruction from the test device 120 and the data input / output circuit 113 outputs the data to the test device 120.

[0046] Figure 1 The configuration is given for illustrative purposes. Figure 1 For example, in some embodiments, the system 100 further includes a processor different from the processor 121 and operatively coupled to the memory device 110 and / or the display device 130 .

[0047] refer to Figure 2 According to some embodiments of the present disclosure, Figure 2 yes Figure 1 Part of system 100. Relative to Figure 1 For ease of understanding, Figure 2Similar components in the present invention are denoted by the same reference numerals. For the sake of brevity, the specific operations of similar components that have been discussed in detail in the above paragraphs are omitted in this article unless there is a need to introduce the same Figure 1 The collaborative relationship of the components shown in .

[0048] For illustration, the memory device 110 further includes a pin DQ, a pin DQS_t, and a pin DQS_c. The pin DQ is used to receive a (write) data signal corresponding to data of a write operation or to output a (read) data signal corresponding to data retrieved through a read operation. For example, in some embodiments, the test device 120 generates a data signal to the pin DQ for a write operation, and the memory device 110 outputs a data signal corresponding to a read operation to the test device 120 through the pin DQ.

[0049] In some embodiments, the pin DQS_t and the pin DQS_c are used to transmit a differential data strobe (DQS) signal pair. Specifically, in some embodiments, the pin DQS_t is used to transmit a data strobe signal in the data strobe signal pair, and the pin DQS_c is used to transmit a complementary data strobe signal in the data strobe signal pair, and the complementary data strobe signal and the data strobe signal are inverted to each other. For example, in some implementations, the memory device 110 receives a data strobe signal pair from the test device 120 through the pin DQS_t and the pin DQS_c for a write operation, and outputs a data strobe signal pair corresponding to a read operation to the test device 120 through the pin DQS_t and the pin DQS_c.

[0050] like Figure 2 As shown, according to some embodiments of the present disclosure, the data input / output circuit 113 is coupled to the pin DQ, the pin DQS_t, and the pin DQS_c. In some embodiments, the data input / output circuit 113 is used to latch the data corresponding to the pin DQ according to the signal (e.g., data strobe signal pair) received from the pin DQS_t and the pin DQS_c for the write operation (in other words, the data signal received from the pin DQ is sampled to obtain data). In some embodiments, the data input / output circuit 113 is also used to transmit the data signal and the data strobe signal pair corresponding to the read operation through the pin DQ, the pin DQS_t, and the pin DQS_c. The following paragraphs will be discussed in more detail.

[0051] Figure 2 The configuration is given for illustrative purposes. Figure 2 Various implementations are within the contemplated scope of an embodiment of the present invention. For example, in some embodiments, the pin DQ, the pin DQS_t, and the pin DQS_c are further coupled to the display device 130.

[0052] like Figure 3A , Figure 3B , Figures 4 to 9 As shown, according to some embodiments, the test device 120 generates a surge signal to determine whether the tested device 110 is susceptible to unexpected noise interference, such as generating a surge signal g_t and a surge signal g_c to interfere with the write operation of the memory device 110. The relevant configuration is described in detail in the following paragraphs.

[0053] refer to Figure 3A and Figure 3B According to some embodiments of the present disclosure, Figure 3A and Figure 3B are schematic diagrams of exemplary waveforms of the surge signal g_t and the surge signal g_c. Figure 1 to Figure 2 For ease of understanding, Figure 3A and Figure 3B Similar components in the drawings are marked with the same reference numerals.

[0054] In some embodiments, the test device 120 is used to generate a surge signal (noise) to interfere with the memory device 110. For example, in some embodiments, the test device 120 generates a surge signal to the memory device 110 to prevent the memory device 110 from correctly performing a write operation. In some embodiments, in order to interfere with the memory device 110, the test device 120 generates a surge signal g_t to the pin DQS_t and generates a surge signal g_c to the pin DQS_c.

[0055] like Figure 3A As shown, in some embodiments, the test device 120 generates a surge signal g_t to the pin DQS_t having a voltage level VL in the interval T1 (time point t1 to time point t2) and a voltage level VH in the interval T2 (time point t2 to time point t3) after the interval T1. The delay time of the voltage level rising and falling is omitted in this article. Similarly, Figure 3B As shown, the test device 120 generates a surge signal g_c having a voltage level VH in interval T1 and a voltage level VL in interval T2 after interval T1 to the pin DQS_c. In some embodiments, the voltage level VH is greater than the voltage level VL. In some embodiments, the surge signal g_t and the surge signal g_c are in opposite phases.

[0056] Figure 3A and Figure 3B The configuration is given for illustrative purposes. Figure 3A and Figure 3B Various implementations of are within the contemplated scope of an embodiment of the present invention. For example, in some embodiments, the voltage level VL is 0V or less than 0V.

[0057] refer to Figure 4 According to some embodiments of the present disclosure, Figure 4 FIG. 1 is a diagram showing example waveforms of the signals on pins DQ, DQS_t, and DQS_c. Figure 1 to Figure 2 and FIG. 3A to FIG. 3B For ease of understanding, Figure 4 Similar components in the drawings are marked with the same reference numerals.

[0058] For illustration, in some embodiments, the test device 120 generates a burst signal g_t and a burst signal g_c to the pin DQS_t and the pin DQS_c respectively from the time point t1 to the time point t3. At the time point t3, the test device 120 generates a data strobe signal and a complementary data strobe signal constituting a differential data strobe signal pair to the pin DQS_t and the pin DQS_c for a write operation. In some embodiments, the data strobe signal and the complementary data strobe signal of the differential data strobe signal pair are inverted to each other. In some embodiments, at the time point t6 after the time point t3, the test device 120 generates a data signal wd corresponding to the write operation to the pin DQ. In some embodiments, the pin DQ has a preset voltage level (e.g., voltage level VH) before receiving the data signal wd (time point t6).

[0059] like Figure 4 As shown, in some embodiments, the data strobe signal generated to the pin DQS_t described in the previous paragraph includes two parts (signals): a write preamble signal wp_t and a toggle signal t_t. In some embodiments, the test device 120 generates the write preamble signal wp_t from time point t3 to time point t7 and generates the toggle signal t_t from time point t7 to time point t23.

[0060] Similarly, in some embodiments, the complementary data strobe signal generated to the pin DQS_c includes two parts (signals): a write preamble signal wp_c and a toggle signal t_c. In some embodiments, the test device 120 generates the write preamble signal wp_c from time point t3 to time point t7 and generates the toggle signal t_c from time point t7 to time point t23. In some embodiments, the write preamble signal wp_t and the write preamble signal wp_c are also referred to as control signals.

[0061] For the sake of brevity, based on the fact that the write preamble signal wp_t and the write preamble signal wp_c are complementary to each other and the switching signal t_t and the switching signal t_c are complementary to each other, only one of the write preamble signal wp_t and the write preamble signal wp_c and one of the switching signal t_t and the switching signal t_c are described in the following paragraphs.

[0062] In some embodiments, the write preamble signal wp_t has a voltage level VL from time point t3 to time point t4, and the interval Tck formed by time point t3 and time point t4 is equal to one clock cycle of the memory device 110. The write preamble signal wp_t has a voltage level VH from time point t4 to time point t5 and has a voltage level VL from time point t5 to time point t7. The interval formed by time point t3 and time point t4 and the interval formed by time point t5 and time point t7 are equal to half of the interval Tck (interval Tck / 2). In some embodiments, the write preamble signal wp_t and the write preamble signal wp_c are inverted to each other.

[0063] In some embodiments, the voltage level of the switching signal t_t is switched between the voltage level VL and the voltage level VH in units of interval Tck / 2. The interval between each adjacent time point from time point t7 to time point t23 is equal to interval Tck / 2. Specifically, Figure 4 As shown, the switching signal t_t has a voltage level VH from the time point t7 to the time point t8 and has a voltage level VL from the time point t8 to the time point t9.

[0064] For a write operation of the memory device 110 , the data input / output circuit 113 latches data from the pin DQ in response to a rising / falling edge (eg, sensing three rising / falling edges) of a signal at the pin DQS_t.

[0065] In different embodiments, since the rise and fall of the data strobe signal have a delay time, the data input / output circuit 113 latches data from the pin DQ in response to the intersection of the signals on the pins DQS_t and DQS_c (in other words, the values ​​of the signals are equal). For example, in some embodiments, the data input / output circuit 113 latches data from the pin DQ in response to sensing three signal intersections.

[0066] In some embodiments, when there is no spike signal g_t and spike signal g_c before the differential data selection signal pair during a write operation, or the memory device 110 under test is not disturbed by the spike signal g_t and the spike signal g_c, the data input / output circuit 113 latches data from the pin DQ in response to the write preamble signal wp_t and the write preamble signal wp_c (when the write preamble signal wp_t ends) at time point t7 and the control circuit 112 writes the latched data into the memory array 111.

[0067] In addition, in some embodiments, the data input / output circuit 113 latches the write data in response to the rising / falling edge of the switching signal t_t and the switching signal t_c (or when the switching signal t_t and the switching signal t_c intersect each other). Figure 4In the illustrated embodiment, from time point t7 to time point t22, the data input / output circuit 113 responds to the rising / falling edge of the switching signal t_t (or when the switching signal t_t and the switching signal t_c intersect / are equal to each other), and latches the data corresponding to the voltage level of the data signal wd to obtain a 16-bit data sequence. For example, Figure 4 As shown, the data input / output circuit 113 latches the data "1" of the bit when the switching signal t_t and the switching signal t_c intersect at the time point t14. Figure 4 In the embodiment of the present invention, the latched 16-bit data sequence is “0000000100000000”. In some embodiments, the control circuit 112 writes each bit of the 16-bit data sequence into the corresponding memory cell 114 according to the memory address output by the test device 120 for the write operation.

[0068] In some embodiments, the memory device 110 is disturbed by the surge signal g_t and / or the surge signal g_c when performing a write operation, so that the data input / output circuit 113 starts latching data from the pin DQ before the time point t7 (in other words, before the write leading signal wp_t ends). Figure 4 In the embodiment of the present invention, the data input / output circuit 113 starts to latch data at time point t4 in response to the surge signal g_t and the write leading signal wp_t. The data input / output circuit 113 latches data corresponding to the voltage level of the pin DQ at time points t4-t5 and t7-t20 in response to the rising / falling edges of the write leading signal wp_t and the switching signal t_t (or the intersection of the write leading signals wp_t and wp_c and the intersection of the switching signals t_t and t_c).

[0069] It should be noted that from time point t1 to time point t6, the voltage level of pin DQ is a preset voltage level (i.e., the voltage level of pin DQ when no data is transmitted through pin DQ). In different embodiments, the preset voltage level is voltage level VH or voltage level VL. Figure 4 In the illustrated embodiment, the preset voltage level is the voltage level VH. Therefore, in the embodiment where the memory device 110 is disturbed by the surge signal g_t and / or the surge signal g_c, the latched 16-bit data sequence is “1100000001000000”.

[0070] Figure 4 The configuration is given for illustrative purposes. Figure 4Various implementations are within the expected scope of an embodiment of the present invention. For example, in some embodiments, the voltage level of the data signal wd at each time point from time point t7 to time point t22 may be the voltage level VL or the voltage level VH. In other words, the data transmitted from the test device 120 for the write operation may be arbitrary. For example, in some embodiments, for the data signal wd corresponding to the data "0000000010000000", among the time points from time point t7 to time point t22, only the voltage level at time point t15 is the voltage level VH.

[0071] refer to Figure 5 According to some embodiments of the present disclosure, Figure 5 The following is an example of the waveform diagram of the signals on the pins DQ, DQS_t and DQS_c. Figure 1 to Figure 2 , FIG. 3A to FIG. 3B and Figure 4 For ease of understanding, Figure 5 Similar components in the drawings are marked with the same reference numerals.

[0072] For illustration, in some embodiments of the read operation, the test device 120 outputs a command to the memory device 110 for the read operation. In some embodiments, the write operation and the read operation correspond to the same memory address. At time point t24, the data input / output circuit 113 generates a data strobe signal and a complementary data strobe signal to form another interpolation data strobe signal pair to the pins DQS_t and DQS_c, respectively. In some embodiments, at time point t26 after time point t24, the data input / output circuit 113 outputs a data signal rd to the test device 120 through the pin DQ, and the data signal rd corresponds to the data read in the read operation.

[0073] like Figure 5 As shown, in some embodiments, the data strobe signal generated to the pin DQS_t and corresponding to the read operation described in the previous paragraph includes two parts (signals): a read leading signal rp_t and a switching signal t_t. In some embodiments, the memory device 110 generates a read leading signal rp_t that lasts from time point t24 to time point t26 and a switching signal t_t that lasts from time point t26 to time point t42.

[0074] In some embodiments, the read leading signal rp_t has a voltage level VH between time point t24 and time point t25, and the interval formed by time point t24 and time point t25 is two-thirds of the interval Tck (interval 3Tck / 2). The read leading signal rp_t also has a voltage value VL between time point t25 and time point t26. The interval formed by time point t25 and time point t26 is interval Tck / 2. In some embodiments, the read leading signal rp_t and the read leading signal rp_c are inverted.

[0075] In some embodiments, the voltage level of the switching signal t_t starting from the time point t28 alternately has the voltage level VL and the voltage level VH in units of interval Tck / 2. Figure 5 As shown, the switching signal t_t has a voltage level VH from time point t26 to time point t27 and has a voltage level VL from time point t27 to time point t28. It should be noted that the interval between each adjacent time point from time point t26 to time point t42 is interval Tck / 2.

[0076] In some embodiments, the data input / output circuit 113 starts to output the data signal rd when the preamble signal rp_t is finished reading at the time point t26 , and the data signal rd corresponds to the data stored in the memory cell 114 corresponding to the memory address of the read operation.

[0077] In addition, in some embodiments, when the memory device 110 is not disturbed by the surge signal g_t and / or the surge signal g_c and correctly performs the write operation, the data of the corresponding data signal rd is consistent with the data of the corresponding write data signal wd. Figure 5 In the embodiment of the present invention, the 16-bit data sequence "0000000100000000" corresponding to the data signal rd (the data signal rd marked as "not interfered") generated by the data input / output signal 113 is consistent with the 16-bit data sequence of the write data signal wd. It should be noted that in the interval corresponding to a pair of adjacent rising / falling edges of the switching signal t_t, the voltage level of the data signal rd corresponds to the bit data.

[0078] In some embodiments, when the memory device 110 is disturbed by the surge signal g_t and / or the surge signal g_c and cannot correctly perform a write operation, the read data corresponding to the read signal rd and the write data corresponding to the write operation (data corresponding to the write signal wd) are inconsistent. Figure 5In the embodiment of the present invention, the 16-bit read data sequence "1100000001000000" corresponding to the data signal rd (the data signal rd marked as "interference") generated by the data input / output circuit 113 is inconsistent with the 16-bit read data sequence "0000000100000000" corresponding to the write signal wd. Specifically, the data corresponding to the data signal rd is equal to the data of the corresponding write operation after bitwise shifting.

[0079] In some embodiments, when the read data is bit-shifted relative to the write data, at least one of the inconsistent bits in the read data and the write data has a high logic value. For example, the read data "1100000001000000" corresponding to the data signal rd marked "interference" is the 16-bit write data "0000000100000000" shifted two bits to the right and shifted in two bits "1" from the left to replace the shifted-out bits. According to some embodiments, the logic value ("1" or "0") of the bit shifted in to replace the shifted-out bit is related to the preset voltage level on the pin DQ. When the write operation is disturbed, the number of bits shifted is related to how many intervals Tck the latching operation of the write data is advanced.

[0080] In some embodiments, the test device 120 performs a test on the memory device 110. The test device 120 compares the data signal wd and the data signal rd to generate a test result. When it is determined that the data signal wd and the data signal rd are consistent with each other, the test device 120 outputs a test result indicating that the memory device 110 passes the test. On the contrary, when it is determined that the data signal wd and the data signal rd are consistent with each other, the test device 120 outputs a test result indicating that the memory device 110 fails the test (in other words, it is interfered by the surge signal g_t and / or the surge signal g_c).

[0081] Specifically, when the test device 120 determines that the data corresponding to the read signal rd is equal to the data corresponding to the bit-shifted write signal wd, the test device 120 outputs a test result indicating that the memory device 110 has not passed the test (in other words, it is interfered by the surge signal g_t and / or the surge signal g_c). In some embodiments, when the test device 120 determines that the read data is equal to the write data after bit shifting, at least one high logic value "1" is shifted in to replace at least one shifted-out bit, the test device 120 outputs a test result indicating that the memory device 110 has not passed the test.

[0082] refer to Figure 3A , Figure 3B , Figure 4 and Figure 5According to some embodiments, the interval T1 and the interval T2 have different lengths. The following table records different configurations of the interval T1 and the interval T2 and test results of examples of multiple memory devices 110 corresponding to these configurations.

[0083] T1 / T2 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 No surge signal P P P P P P P P P P 0.01Tck / 0.4Tck F F F F F F F F F F 0.02Tck / 0.4Tck F F F F F F F F F F 0.03Tck / 0.4Tck F F F F F F F F F F 0.04Tck / 0.4Tck F P F F F F F F F P 0.05Tck / 0.4Tck P P P F P P F F P P 0.06Tck / 0.4Tck P P P P P P P P P P 0.07Tck / 0.4Tck P P P P P P P P P P 0.08Tck / 0.4Tck P P P P P P P P P P 0.09Tck / 0.4Tck P P P P P P P P P P 0.10Tck / 0.4Tck P P P P P P P P P P

[0084] For illustration, the first column in the table corresponds to the length of interval T1 and interval T2. For example, "0.01Tck / 0.4Tck" indicates that interval T1 is set to 0.01 interval Tck and interval T2 is set to 0.4 interval Tck. The second to tenth columns correspond to the test results of ten memory devices 110 (labeled as D1 to D10) and corresponding to different length configurations of intervals T1 and T2. "F" indicates that the memory device 110 failed the test and "P" indicates that the memory device 110 passed the test.

[0085] Referring to the table, in some embodiments, when the ratio of interval T1 to interval T2 is greater than 0.125, the memory device 110 passes the test. In some embodiments, when the ratio of interval T1 to interval T2 is less than 0.1, the memory device 110 fails the test. In some embodiments, when the ratio of interval T1 to interval T2 is between 0.15 and 0.25, the memory device 110 passes the test. In some embodiments, when the ratio of interval T1 to interval T2 is between 0.025 and 0.075, the memory device 110 fails the test.

[0086] refer to Figure 6 and Figure 7 According to some embodiments of the present disclosure, Figure 6 and Figure 7 The following are waveform diagrams of the signals on the pins DQ, DQS_t, and DQS_c. Figure 1 , Figure 2 , Figure 3A , Figure 3B , Figure 4 and Figure 5 For ease of understanding, Figure 6 and Figure 7 Similar components in the drawings are marked with the same reference numerals.

[0087] In some embodiments, the test device 120 generates a plurality of write instructions to enable the memory device 110 to perform a plurality of write operations and generates a plurality of read instructions after the plurality of write operations to enable the memory device 110 to perform a plurality of read instructions. In some embodiments, the test device 120 generates a differential data strobe signal pair and a data signal corresponding to the plurality of write operations and generates a corresponding burst signal before each of the differential data strobe signal pair. In some embodiments, each of the plurality of write operations and the corresponding write operation correspond to the same memory device. In some embodiments, the memory addresses corresponding to each of the plurality of write operations are different from each other.

[0088] In terms of description, Figure 6 As shown, the test device 120 generates a data strobe signal to the pin DQS_t for the first write operation, the data strobe signal includes a write preamble signal wp_t from time point t3 to time point t7 and a switching signal t_t starting from time point t7. Similarly, the test device 120 generates a complementary data strobe signal for the first write operation, the complementary data strobe signal includes a write preamble signal wp_c from time point t3 to time point t7 and a switching signal t_c to the pin DQS_c starting from time point t7. The test device 120 generates a data signal wd corresponding to the first write operation to the contact DQ at time point t6. The test device 120 generates a surge signal g_t and g_c to the pin DQS_t and the pin DQS_c from time point t1 to time point t3 to interfere with the memory device 110 performing the first write operation.

[0089] In addition, if Figure 6 As shown, the test device 120 generates a data strobe signal to the pin DQS_t for the second write operation, the data strobe signal includes a write preamble signal wp_t from time point tb to time point td and a switching signal t_t starting from time point td. Similarly, the test device 120 generates a complementary data strobe signal to the pin DQS_c for the second write operation, the complementary data strobe signal includes a write preamble signal wp_c from time point tb to time point td and a switching signal t_c starting from time point td. The test device 120 generates a data signal wd corresponding to the second write operation to the contact DQ at time point tc. The test device 120 generates a surge signal g_t and g_c to the pin DQS_t and the pin DQS_c from time point ta to time point tb to interfere with the memory device 110 performing the second write operation.

[0090] In some embodiments, Figure 7As shown, the data input / output circuit 113 generates a data strobe signal corresponding to the first read operation to the pin DQS_t, and the data strobe signal corresponding to the first read operation includes a read leader signal rp_t from time point t24 to time point t26 and a switching signal t_t starting from time point t26. The first read operation and the first write operation correspond to the same memory address. Similarly, the data input / output circuit 113 generates a complementary data strobe signal corresponding to the first read operation, and the complementary data strobe signal corresponding to the first read operation includes a read leader signal rp_c from time point t24 to time point t26 and a switching signal t_c starting from time point t26 to the pin DQS_c. The data input / output circuit 113 generates a data signal rd corresponding to the first read operation to the contact DQ at time point t26.

[0091] Furthermore, in some embodiments, Figure 7 As shown, the data input / output circuit 113 generates a data strobe signal corresponding to the second read operation to the pin DQS_t, and the data strobe signal corresponding to the second read operation includes a read leader signal rp_t from time point te to time point tf and a switching signal t_t starting from time point tf. The second read operation and the second write operation correspond to the same memory address. Similarly, the data input / output circuit 113 generates a complementary data strobe signal corresponding to the second read operation, and the complementary data strobe signal corresponding to the second read operation includes a read leader signal rp_c from time point te to time point tf and a switching signal t_c starting from time point tf to the pin DQS_c. The data input / output circuit 113 generates a data signal rd corresponding to the second read operation to the contact DQ at time point tf.

[0092] In some embodiments, the test device 120 performs a test on the memory device 110. The test device 120 compares data signals wd corresponding to a plurality of write operations (including the first and second write operations) and data signals rd corresponding to a plurality of read operations (including the first and second read operations) to generate a test result.

[0093] In some embodiments, when it is determined that at least one data signal wd and the corresponding data signal rd are inconsistent, the test device 120 outputs a test result indicating that the memory device 110 has not passed the test. For example, when it is determined that the data signal wd of the first write operation and the data signal rd of the first read operation are consistent with each other, the test device 120 outputs test data indicating that the memory device 110 has not passed the test.

[0094] In some embodiments, the display device 130 displays a differential data signal pair, a data signal wd corresponding to a plurality of write operations, and a data signal rd corresponding to a plurality of read operations (eg, Figure 6 and Figure 7 The waveform shown is for comparison.

[0095] Figure 6 and Figure 7 The configuration is given for illustrative purposes. Figure 6 and Figure 7 Various implementations of are within the contemplated scope of an embodiment of the present invention. For example, in some embodiments, Figure 7 Any of the data signals rd may be Figure 6 The data signal wd in is consistent.

[0096] refer to Figure 8 and Fig. 9 According to some embodiments of the present disclosure, Figure 8 and Fig. 9 The following are waveform diagrams of the signals on the pins DQ, DQS_t, and DQS_c. Figure 1 , Figure 2 , Figure 3A , Figure 3B , Figures 4 to 7 For ease of understanding, Figure 8 and Fig. 9 Similar components in the present invention are marked with the same reference numerals. For the sake of brevity, the specific operations of similar components that have been discussed in detail in the above paragraphs are omitted herein.

[0097] In some embodiments, the test device 120 generates a plurality of write instructions to enable the memory device 110 to perform a plurality of write operations and generates a plurality of read instructions after the plurality of write operations to enable the memory device 110 to perform a plurality of read instructions. In some embodiments, the test device 120 generates a differential data strobe signal pair and data signals corresponding to the plurality of write operations. In some embodiments, the test device 120 generates a burst signal before each differential data signal pair except for the differential data signal pair corresponding to the first write operation.

[0098] In terms of description, Figure 8 As shown, the test device 120 generates a data strobe signal to the pin DQS_t for the first write operation, and the data strobe signal includes a write preamble signal wp_t from time point t3 to time point t7 and a switching signal t_t starting from time point t7. Similarly, the test device 120 generates a complementary data strobe signal for the first write operation, and the complementary data strobe signal includes a write preamble signal wp_c from time point t3 to time point t7 and a switching signal t_c to the pin DQS_c starting from time point t7. The test device 120 generates a data signal wd corresponding to the first write operation to the contact DQ at time point t6.

[0099] In addition, if Figure 8As shown, the test device 120 generates a data strobe signal to the pin DQS_t for the second write operation, the data strobe signal includes a write preamble signal wp_t from time point tb to time point td and a switching signal t_t starting from time point td. Similarly, the test device 120 generates a complementary data strobe signal to the pin DQS_c for the second write operation, the complementary data strobe signal includes a write preamble signal wp_c from time point tb to time point td and a switching signal t_c starting from time point td. The test device 120 generates a data signal wd corresponding to the second write operation to the contact DQ at time point tc. The test device 120 generates a surge signal g_t and g_c to the pin DQS_t and the pin DQS_c from time point ta to time point tb to interfere with the memory device 110 performing the second write operation.

[0100] In some embodiments, Fig. 9 As shown, the data input / output circuit 113 generates a data strobe signal corresponding to the first read operation to the pin DQS_t, and the data strobe signal corresponding to the first read operation includes a read leader signal rp_t from time point t24 to time point t26 and a switching signal t_t starting from time point t26. The first read operation and the first write operation correspond to the same memory address. Similarly, the data input / output circuit 113 generates a complementary data strobe signal corresponding to the first read operation, and the complementary data strobe signal corresponding to the first read operation includes a read leader signal rp_c from time point t24 to time point t26 and a switching signal t_c starting from time point t26 to the pin DQS_c. The data input / output circuit 113 generates a data signal rd corresponding to the first read operation to the contact DQ at time point t26.

[0101] Furthermore, in some embodiments, Fig. 9 As shown, the data input / output circuit 113 generates a data strobe signal corresponding to the second read operation to the pin DQS_t, and the data strobe signal corresponding to the second read operation includes a read leader signal rp_t from time point te to time point tf and a switching signal t_t starting from time point tf. The second read operation and the second write operation correspond to the same memory address. Similarly, the data input / output circuit 113 generates a complementary data strobe signal corresponding to the second read operation, and the complementary data strobe signal corresponding to the second read operation includes a read leader signal rp_c from time point te to time point tf and a switching signal t_c starting from time point tf to the pin DQS_c. The data input / output circuit 113 generates a data signal rd corresponding to the second read operation to the contact DQ at time point tf.

[0102] In some embodiments, the display device 130 displays a differential data strobe signal pair, a data signal wd corresponding to a plurality of write operations, and a read data rd corresponding to a plurality of read operations (eg, Figure 8 and Fig. 9 The waveform diagram shown is used to compare the normal write operation (without surge signal) and the abnormal write operation (with surge signal).

[0103] Figure 8 and Fig. 9 The configuration is given for illustrative purposes. Figure 8 and Fig. 9 Various implementations of are within the contemplated scope of an embodiment of the present invention. For example, in some embodiments, Fig. 9 In the example, the data signal rd at the time point td may be consistent with the data signal rd at the time point t26.

[0104] refer to Fig.10 According to some embodiments of the present disclosure, Fig.10 is a flow chart of an example of a method 1000 corresponding to the system 100. It should be understood that in Fig.10 Additional operations / steps are provided before, between, and after the operations / steps shown, and some of the operations / steps shown below may be replaced or removed for additional embodiments of method 1000. The order of the operations / steps may be changed. Throughout the various views and illustrative embodiments, the same reference numbers are used to represent similar components. Method 1000 includes reference Figure 1 , Figure 2 , Figure 3A , Figure 3B , Figures 4 to 9 Operations 1001 to 1005 are described below.

[0105] In operation 1001, the test device 120 generates a write data signal (eg, data signal wd) to a first pin (eg, pin DQ) of the memory device 110. The write data signal corresponds to write data of a write operation.

[0106] In operation 1002 , the test device 120 generates a surge signal (eg, a surge signal g_t) and a control signal (eg, a write preamble signal wp_t) to a second pin (eg, a pin DQS_t) of the memory device 110 .

[0107] In operation 1003, the data input / output circuit 113 latches data from a write data signal of a write operation in response to at least one of a burst signal and a control signal. Figure 4As shown, in some embodiments, the data input / output circuit 113 latches data from the write data signal in response to the write preamble signal wp_t (control signal). In some embodiments, the control circuit 112 writes data to the memory array 111 according to the memory address corresponding to the write operation.

[0108] In operation 1004, the memory device 110 performs a read operation to generate a read data signal (e.g., data signal rd). In some embodiments, the test device outputs a read instruction to the memory device 110 according to the memory address corresponding to the write operation to perform the read operation. The data input / output circuit 113 obtains the read data according to the memory address and generates a read data signal according to the read data.

[0109] In operation 1005, a processor (e.g., processor 121 of test device 120) outputs a test result by comparing a write data signal (write data) and a read data signal (read data). In some embodiments, when the write data signal (write data) and the read data signal (read data) are consistent, test device 120 outputs a test result indicating that memory device 110 has passed the test (not interfered by the surge signal). On the contrary, when the write data signal (write data) and the read data signal (read data) are inconsistent, test device 120 outputs a test result indicating that memory device 110 has not passed the test (interfered by the surge signal).

[0110] In some embodiments, when the read data is bit-shifted relative to the write data, the test device 120 outputs a test result indicating that the memory device 110 has failed the test (interfered by the surge signal).

[0111] In some embodiments, the duration of the burst signal is shorter than a clock cycle (interval Tck) of the memory device 110. For example, in some embodiments, the duration of the burst signal is equal to 0.41 times of the clock cycle of the memory device 110.

[0112] In some embodiments, the surge signal g_t has a voltage level VL in the interval T1 and has a voltage level VH in the interval T2 which is different from the interval T1. In some embodiments, the surge signal g_c has a voltage level VH in the interval T1 and has a voltage level VL in the interval T2.

[0113] In some embodiments, when interval T2 is greater than interval T1, the written data and the read data are inconsistent. For example, in some embodiments, interval T2 is 0.4 times interval Tck and interval T1 is 0.01 times interval Tck, and the read data and the written data are inconsistent.

[0114] In some embodiments, the display device 130 displays the write data signal (data signal wd) and the read data signal (data signal rd) for comparison between the two.

[0115] In summary, the system and method provided by the present disclosure are helpful to test whether a memory device is disturbed by a surge signal (noise) during a write operation to evaluate the reliability of the memory device. By generating a surge signal to the memory device through a test device during a write operation and observing the data obtained during a read operation, a defective memory device can be detected.

[0116] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of an embodiment of the present invention. Those skilled in the art should understand that an embodiment of the present invention can be easily used as a basis for designing or modifying other processes and structures to implement the same purpose and / or achieve the same advantages of the embodiments introduced in the present invention. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of an embodiment of the present invention, and various changes, substitutions and modifications can be performed in an embodiment of the present invention without departing from the spirit and scope of an embodiment of the present invention.

[0117]

Explanation of symbols

[0118] 100: System

[0119] 110: Memory device

[0120] 111: Memory array

[0121] 112: Control circuit

[0122] 113: Data input / output circuit

[0123] 114: memory unit

[0124] 120: Test device

[0125] 121: Processor

[0126] 130: Display device

[0127] 1000:Method

[0128] 1001~1002: Operation

[0129] BL0: bit line

[0130] BL1: Bit Line

[0131] BL2: Bit Line

[0132] BLK: Bit Line

[0133] DQS_t: pin

[0134] DQS_c: pin

[0135] DQ: Pin

[0136] g_c: Surge signal

[0137] g_t: Surge signal

[0138] rd: data signal

[0139] rp_c: read leading signal

[0140] rp_t: read leading signal

[0141] t1~t42: time point

[0142] ta~tg: time point

[0143] T1: interval

[0144] T2: interval

[0145] Tck: interval

[0146] Tck / 2: interval

[0147] 3Tck / 2: interval

[0148] t_c: switching signal

[0149] t_t: switching signal

[0150] VH: Voltage level

[0151] VL: Voltage level

[0152] wd: data signal

[0153] WL0: word line

[0154] WL1: character line

[0155] WLJ: Character Line

[0156] wp_c: write leading signal

[0157] wp_t: write preamble signal.

Claims

1. A system for testing a memory, characterized in that: Include: Memory device; A test device is operatively coupled to the memory device and is used to transmit a plurality of burst signals and a plurality of control signals following the burst signals for a write operation of the memory device according to a data signal, The test device is further used to determine whether the read data outputted in the read operation of the memory device is bit-shifted based on the write data of the data signal, so as to generate a test result indicating the interference to the write operation caused by the surge signals.

2. The system of claim 1 , wherein the test device is operatively coupled to a first data strobe pin and a second data strobe pin of the memory device, the first and second data strobe pins being configured to receive a differential data strobe signal pair, wherein the differential data strobe signal pair comprises the control signals, The testing device is further used for outputting a first surge signal among the surge signals to the first data strobe pin and outputting a second surge signal which is inverted to the first surge signal to the second data strobe pin.

3. The system of claim 1, wherein in the write operation, the memory device is configured to latch the data of the data signal in response to at least three rising / falling edges of a first burst signal of the burst signals and a first control signal of the idle signals. 4 . The system of claim 3 , wherein the first surge signal has a first voltage level in a first interval, and has a second voltage level in a second interval after the first interval. 5 . The system of claim 3 , wherein when a ratio of the first interval to the second interval is between 0.025 and 0.075, the read data and the write data are inconsistent. 6 . The system of claim 3 , wherein when a ratio of the first interval to the second interval is between 0.15 and 0.25, the read data is consistent with the write data. 7 . The system of claim 1 , wherein when the read data is bit-shifted compared to the write data, at least one inconsistent bit in the read data and the write data has a high logic value.

8. A system for testing a memory, characterized in that: Include: A memory device comprising an input / output circuit; and A test device is operatively coupled to the memory device and configured to output a burst signal to the memory device and output a control signal after outputting the burst signal. The input / output circuit is used to latch data for a write operation of a memory device in response to the surge signal and the control signal. The test device is also used to compare the write data corresponding to the write operation with the read data output in the read operation of the memory device to determine whether the memory device is disturbed by the surge signal. 9 . The system according to claim 8 , wherein the testing device is further configured to generate the surge signal at a first time point and generate the control signal at a second time point after the first time point.

10. The system of claim 9, wherein the input / output circuit latches the data at a third time after the second time.

11. The system of claim 8, wherein the surge signal has a first voltage level in a first interval and has a second voltage level greater than the first voltage level in a second interval after the first interval, When the ratio between the first interval and the second interval is greater than 0.125, the read data is consistent with the written data.

12. The system according to claim 8, wherein the surge signal has different voltage levels in a first interval and a second interval after the first interval, When the ratio of the first interval to the second interval is less than 0.1, the written data and the read data are inconsistent.

13. A method for testing a memory, characterized in that: Include: generating a write data signal to a first pin of a memory device; Generating a surge signal and a control signal to a second pin of the memory device; latching data from the write data signal for a write operation in response to at least one of the burst signal and the control signal; performing a read operation to generate a read data signal; as well as By comparing the write data signal and the read data signal, a test result is output.

14. The method of claim 13, wherein a duration of the surge signal is shorter than a time interval of the memory device. 15 . The method of claim 13 , wherein the surge signal has a first voltage level in a first interval and has a second voltage level in a second interval different from the first interval. 16 . The method according to claim 15 , wherein when the second interval is larger than the first interval, the read data is inconsistent with the write data.

17. The method according to claim 15, wherein: Also includes: The write data signal and the read data signal are displayed by a display device to compare the write data signal and the read data signal.

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