Method for manufacturing semiconductor structure and semiconductor processing system

Abstract

A method of manufacturing a semiconductor structure includes disposing a substrate within a chamber device; depositing the boron-doped silicon germanium layer on the substrate; and depositing a boron-doped silicon layer onto the boron-doped silicon germanium layer. Deposition of the boron-doped silicon layer includes: stopping flow of a boron-containing precursor to a chamber device; reducing flow of the germanium-containing precursor to the chamber device; increasing the flow of the silicon-containing precursor to the chamber device; after increasing the flow of the silicon-containing precursor, stopping the flow of the germanium-containing precursor to the chamber device; and resuming the flow of the boron-containing precursor to the chamber device. Semiconductor structures as well as semiconductor processing systems and computer program products for manufacturing semiconductor structures are also described.

Description

Technical Field

[0001] The present disclosure relates generally to fabricating semiconductor devices and, more particularly, to depositing layers to form semiconductor structures for fabricating semiconductor devices. Background Art

[0002] Semiconductor devices, such as logic and memory devices having three-dimensional architectures, are typically formed by depositing layers of material on a substrate. Material layer deposition is typically accomplished by supporting a substrate within a reactor, providing one or more precursors to the reactor, and exposing the substrate to the one or more precursors under selected conditions so that the desired material layer is deposited onto the substrate surface. Once the material layer has formed desired properties (e.g., resistivity and / or thickness), the flow of the one or more precursors is stopped, and the substrate is typically removed from the reactor for further processing, which is suitable for semiconductor devices manufactured using the layer. Precursors are typically selected based on the desired properties to impart to the material layer deposited on the substrate, and the precursors may include dopants and / or alloying components for incorporation into the material layer.

[0003] In some material layer deposition operations, constituents may compete with each other for incorporation into a material layer formed on a substrate. For example, under certain processing conditions, an alloy constituent such as germanium (Ge) may have a greater binding affinity than a matrix constituent such as silicon. Similarly, certain dopant constituents may have a greater binding affinity than both alloy constituents, such as in certain processes using boron (B). This may result in a variation in constituent concentration within a layer, such as at the end of a deposition, where a residual constituent with a greater binding affinity may result in a material layer having a higher constituent concentration at the end surface of the material layer, such as Fig. 9 Interface A and interface B in FIG. Without being bound by a particular theory or mode of operation, it is believed that the energy state may affect the incorporation rate, with components requiring lower activation energy being more easily incorporated into the growth face of the developing layer than components requiring higher activation energy. Therefore, processing conditions are generally selected to match the incorporation rates of the various layer components with the desired properties of the developing layer.

[0004] Various techniques may be employed to manage components with different binding affinities. For example, the mass flow rate of precursors providing the various components may be limited, such that the binding rate is constrained by the atomic mass of the components available within the reactor atmosphere. In a multilayer processing scheme, where two or more layers of different composition are sequentially deposited within a reactor, the reactor atmosphere may be purged between deposition of a first layer and deposition of a second layer, the purge removing residual precursors and components used to deposit the first layer from the reactor prior to deposition of the second layer to limit their incorporation into the second layer.

[0005] Such systems and methods for manufacturing semiconductor devices are generally acceptable for their intended purposes. However, there is still a need in the art for improved methods of manufacturing semiconductor structures, semiconductor structures, semiconductor processing systems, and related computer program products for manufacturing semiconductor structures. The present disclosure provides a solution to this need. Summary of the invention

[0006] A method for manufacturing a semiconductor structure is provided. The method includes placing a substrate in a chamber device, depositing a boron-doped silicon germanium (SiGe:B) layer covering the substrate, and depositing a boron-doped silicon (Si:B) layer covering the boron-doped silicon germanium layer. The deposition of the boron-doped silicon layer is accomplished by: stopping the flow of a boron-containing precursor to the chamber device; reducing the flow of a germanium-containing precursor to the chamber device; increasing the flow of a silicon-containing precursor to the chamber device; after increasing the flow of the silicon-containing precursor, stopping the flow of a germanium-containing precursor to the chamber device; and resuming the flow of a boron-containing precursor to the chamber device.

[0007] In addition to or instead of one or more of the above features, other examples of the method may include the SiGe:B layer having a SiGe:B layer boron concentration, the Si:B layer having a Si:B layer boron concentration, and the Si:B layer boron concentration being greater than the SiGe:B layer boron concentration.

[0008] In addition to or as an alternative to one or more of the features described above, other examples of the method may include depositing a silicon germanium (SiGe) layer onto the substrate. A SiGe:B layer may be deposited onto the SiGe layer.

[0009] In addition to or in lieu of one or more of the features described above, other examples of the method can include continuously and uninterruptedly flowing a silicon-containing layer precursor to the chamber apparatus during deposition of the SiGe:B layer and the Si:B layer.

[0010] In addition to or instead of one or more of the above features, other examples of the method may include the first SiGe:B layer having a first boron concentration, the second SiGe:B layer having a second boron concentration, and the second boron concentration being greater than the first boron concentration.

[0011] In addition to or as an alternative to one or more of the above features, other examples of the method may include the Si:B layer having a third boron concentration. The third boron concentration may be greater than the second boron concentration.

[0012] In addition to or as an alternative to one or more of the above features, other examples of the method may include the Si:B layer having a third boron concentration. The third boron concentration may be greater than the second boron concentration.

[0013] In addition to or instead of one or more of the above features, other examples of the method may include the first SiGe:B layer having a first germanium concentration, the second SiGe:B layer having a second germanium concentration, and the second germanium concentration being greater than the first germanium concentration.

[0014] In addition to or in lieu of one or more of the above features, other examples of the method may include depositing the first SiGe:B layer and depositing the second SiGe:B layer including flowing a silicon-containing layer precursor to the chamber device. During deposition of the first SiGe:B layer and the second Si:B layer, the silicon-containing layer precursor may flow continuously and without interruption.

[0015] In addition to or in lieu of one or more of the above features, other examples of the method may include depositing the SiGe:B layer including flowing a boron-containing precursor to a chamber device at a first boron-containing precursor flow rate. During the deposition of the SiGe:B layer, the flow rate of the boron-containing precursor may be increased to a second boron-containing precursor flow rate, the second boron-containing precursor flow rate being greater than the first boron-containing precursor flow rate.

[0016] In addition to or instead of one or more of the features described above, other examples of the method may include a substrate having a silicon surface portion and a dielectric surface portion, and the method may also include flowing an etchant to the chamber device to etch the dielectric surface portion of the substrate during depositing the SiGe:B layer and depositing the Si:B layer.

[0017] In addition to or instead of one or more of the features described above, other examples of the method can include defining an interface between the SiGe:B layer and the Si:B layer between stopping the flow of the boron-containing precursor and resuming the flow of the boron-containing precursor to the chamber apparatus.

[0018] A semiconductor structure is provided, and the semiconductor structure is formed using the method for forming a semiconductor structure as described above.

[0019] In addition to or as an alternative to the above one or more features, other examples of semiconductor structures may include a semiconductor structure including a SiGe layer covering a substrate, a first SiGe:B layer covering the SiGe layer, a second SiGe:B layer covering the first SiGe:B layer, and a Si:B layer covering the second SiGe:B layer. The Si:B layer and the second SiGe:B layer may define a defect-free interface at an interface between the second SiGe:B layer and the Si:B layer.

[0020] In addition to or instead of one or more of the above features, other examples of semiconductor structures may include a SiGe layer covering a substrate, a first SiGe:B layer covering the SiGe layer, a second SiGe:B layer covering the first SiGe:B layer, and a Si:B layer covering the second SiGe:B layer.

[0021] In addition to or instead of one or more of the features described above, other examples of semiconductor structures may include a first SiGe:B layer deposited onto (e.g., directly deposited onto) a SiGe layer, a second SiGe:B layer deposited onto (e.g., directly deposited onto) the first SiGe:B layer, and a Si:B layer deposited onto (e.g., directly deposited onto) the second SiGe:B layer.

[0022] A semiconductor processing system is provided. The semiconductor processing system includes: a precursor delivery device; a chamber device having a substrate support connected to the precursor delivery device; and a controller operably connected to the precursor delivery device and the chamber device. The controller responds to instructions recorded on a memory to: place a substrate in the chamber device; deposit a SiGe:B layer covering the substrate; and deposit a Si:B layer covering the SiGe:B layer. The Si:B layer is deposited by: stopping the flow of a boron-containing precursor to the chamber device during the deposition of the SiGe:B layer; reducing the flow of a germanium-containing precursor to the chamber device during the deposition of the SiGe:B layer; and increasing the flow of a silicon-containing precursor to the chamber device while stopping at least one of the flow of a boron-containing precursor and reducing the flow of a germanium-containing precursor to the chamber device. The flow of the germanium-containing precursor is stopped after increasing the flow of the silicon-containing precursor to the chamber device, and after stopping the flow of the germanium-containing precursor to the chamber device, the flow of the boron-containing precursor to the chamber device is subsequently resumed.

[0023] In addition to or instead of one or more of the features described above, other examples of semiconductor processing systems may include the SiGe:B layer being a first SiGe:B layer, and the instructions further causing the controller to deposit a SiGe layer onto the substrate, deposit the first SiGe:B layer onto the first SiGe layer, deposit the second SiGe:B layer onto the first SiGe:B layer, and deposit the Si:B layer onto the second SiGe:B layer.

[0024] In addition to or instead of one or more of the features described above, other examples of semiconductor processing systems may include instructions that cause the controller to: flow an etchant to the chamber device during deposition of at least one of the SiGe layer, the first SiGe:B layer, the second SiGe:B layer, and the Si:B layer; and etch a dielectric surface portion of the substrate during deposition of at least one of the SiGe layer, the first SiGe:B layer, the second SiGe:B layer, and the Si:B layer that covers a silicon surface portion of the substrate.

[0025] A computer program product is provided. The computer program product includes a memory including a non-transitory machine-readable medium having instructions, the instructions causing a controller operably connected to a precursor delivery device and a chamber device to: place a substrate in the chamber device; deposit a SiGe:B layer covering the substrate; and deposit a Si:B layer covering the SiGe:B layer. The Si:B layer can be deposited by: stopping the flow of a boron-containing precursor to the chamber device; reducing the flow of a germanium-containing precursor to the chamber device; increasing the flow of a silicon-containing precursor to the chamber device; after increasing the flow of the silicon-containing precursor, stopping the flow of a germanium-containing precursor to the chamber device; and after stopping the flow of the germanium-containing precursor to the chamber device, resuming the flow of a boron-containing precursor to the chamber device.

[0026] The present invention summary is provided to introduce some concepts in a simplified form. These concepts are further described in detail in the detailed description of the examples of the following disclosure. The present invention summary is not intended to identify the key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] These and other features, aspects and advantages of the present invention disclosed herein are described below with reference to the accompanying drawings of certain embodiments, which are intended to illustrate rather than to limit the present invention.

[0028] Figure 1 is a schematic diagram of a semiconductor processing system according to the present disclosure, showing formation of a semiconductor structure on a substrate disposed in a chamber apparatus using a precursor provided by a precursor delivery apparatus;

[0029] Figure 2 and 3 yes Figure 1 A schematic diagram of a precursor delivery device and a gas delivery device showing elements of a precursor delivery device and a chamber device according to an example of the present disclosure;

[0030] Figure 4 yes Figure 1 A schematic cross-sectional side view of a semiconductor structure of , showing an interface between boron-containing layers;

[0031] Figures 5 to 8 yes Figure 1 A cross-sectional side view of a semiconductor structure showing the order in which layers are deposited to form the semiconductor structure;

[0032] Fig. 9 and 10 is a graph of boron concentration as a function of depth within a semiconductor structure formed without and with precursor sequencing; and

[0033] Figures 11 to 14 According to the present disclosure Figure 1FIG. 1 is a block diagram of a method of manufacturing a semiconductor structure of FIG. 1 , showing operations of the method according to an illustrative and non-limiting example of the present disclosure.

[0034] It should be understood that the elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the relative sizes of some elements in the drawings may be enlarged relative to other elements to help improve the understanding of the illustrated embodiments of the present disclosure. DETAILED DESCRIPTION

[0035] Reference will now be made to the drawings, wherein like reference numerals represent similar structural features or aspects of the subject disclosure. Fig.11 A partial view of an example of a method of manufacturing a semiconductor structure according to the present disclosure is shown in FIG. 1 and is generally indicated by the reference numeral 300. Other examples of methods of manufacturing a semiconductor structure, semiconductor structures, and semiconductor processing systems and computer program products for manufacturing semiconductor structures are shown in FIG. Figure 1-8 12-14, which will be described. The systems and methods of the present disclosure can be used to deposit material layers on a substrate during the manufacture of a semiconductor structure, such as a doped silicon-containing material layer for a source and drain portion of a semiconductor device having a three-dimensional structure formed using epitaxial deposition techniques. However, the present disclosure is generally limited to any particular type of material, semiconductor device architecture, or semiconductor device.

[0036] refer to Figure 1 , a semiconductor processing system 100 is shown. The semiconductor processing system 100 includes a precursor delivery apparatus 102, a chamber apparatus 104, an exhaust apparatus 106, and a controller 108. The precursor delivery apparatus 102 is connected to the chamber apparatus 104 and is configured to provide a precursor 10 to the chamber apparatus 104. The chamber apparatus 104 is connected to the exhaust apparatus 106, the precursor delivery apparatus 102 is fluidly coupled to the exhaust apparatus 106, and is configured to support the substrate 2 during the formation of the semiconductor structure 200 on the substrate 2. The exhaust apparatus 106 is fluidly coupled to an external environment 16 outside the semiconductor processing system 100, and is configured to transfer a stream or residual precursor and / or reaction product 18 generated during the deposition of the layer 14 onto the substrate 12 to the external environment 16 outside the semiconductor processing system 100, for example, using one or more vacuum pumps configured to maintain the substrate 2 in a reduced pressure atmosphere (e.g., less than 760 Torr). The controller 108 is operably connected to the semiconductor processing system 100, such as via a wired or wireless link 110, and in this regard may communicate with at least one of the precursor delivery apparatus 102, the chamber apparatus 104, and the exhaust apparatus 106. Although shown and described herein as including certain elements and having a particular arrangement, it should be understood and appreciated that the semiconductor processing system 100 may include additional elements and / or omit elements shown and described herein and still be within the scope of the present disclosure.

[0037] As used herein, the term "substrate" may refer to any one or more underlying materials, including any one or more underlying materials that may be modified or on which a device, circuit, or film may be formed. The substrate may be continuous or non-continuous; rigid or flexible; solid or porous; and combinations thereof. The substrate may be in any form, such as (but not limited to) a powder, a plate, or a workpiece. Plate-like substrates may include wafers of various shapes and sizes, including, for example, 300 mm wafers.

[0038] The substrate may be formed of a semiconductor material, including, for example, silicon (Si), silicon germanium (SiGe), silicon oxide (SiO2), gallium arsenide (GaAs), gallium nitride (GaN), and silicon carbide (SiC). The substrate may include a pattern or may be an unpatterned blanket substrate. For example, a substrate in powder form may be used in drug manufacturing. The porous substrate may include one or more polymers. Examples of workpieces may include medical devices (e.g., stents and syringes), jewelry, tool equipment, components for battery manufacturing (e.g., anodes, cathodes, or separators), or components of photovoltaic cells, etc.

[0039] The continuous substrate can extend beyond the boundaries of the treatment chamber where the deposition process occurs. In some processes, the continuous substrate can be moved through the treatment chamber so that the process continues until the end of the substrate is reached. The continuous substrate can be provided by a continuous substrate feeding system to allow the continuous substrate to be manufactured and output in any suitable form. The non-limiting example of a continuous substrate may include a sheet, a nonwoven film, a roll, a foil, a net, a flexible material, a bundle of continuous filaments or fibers (e.g., ceramic fibers or polymer fibers). The continuous substrate may also include a carrier or a thin sheet on which one or more non-continuous substrates are mounted.

[0040] refer to Figure 2 , a precursor delivery device 102 according to an example of the present disclosure is shown. In the example shown, the precursor delivery device 102 includes a first precursor source 112, a second precursor source 114, and a third precursor source 116. As shown and described herein, the precursor delivery device 102 also includes a carrier gas / purge gas source 118 and an etchant source 120. In some examples, the precursor delivery device 102 can be as shown and described in U.S. Patent No. 11,053,591 issued to Ma et al. on July 6, 2021, the contents of which are incorporated herein by reference in their entirety. Although shown and described herein as having certain elements and specific arrangements, it should be understood and appreciated that the precursor delivery arrangement 102 may include other elements and / or exclude elements shown and described in other examples herein, and / or have different arrangements in other examples, and still be within the scope of the present disclosure.

[0041] The first precursor source 112 includes a first precursor 20 and is connected to the chamber apparatus 104 via a first precursor supply valve 122 and is configured to provide a flow of the first precursor 20 to the chamber apparatus 104 to form the semiconductor structure 200. In this regard, the first precursor supply valve 122 can be operably associated with the controller 108 and can include a mass flow controller (MFC) device and / or a diverter valve. In some examples, the first precursor 20 can include a silicon-containing layer precursor, such as one or more non-halogenated silicon-containing precursors and / or one or more chlorinated silicon-containing layer precursors. Examples of suitable non-halogenated layer precursors include silane (SiH4), disilane (Si2H6), trisilane (Si3H8), and tetrasilane (Si4H 10 ). Examples of suitable halogenated silicon-containing layer precursors include dichlorosilane (H2SiCl2) and trichlorosilane (HCl3Si). In view of the present disclosure, one skilled in the art will appreciate that the first precursor source 112 may include another other silicon-containing layer precursor and / or mixtures thereof and still be within the scope of the present disclosure.

[0042] The second precursor source 114 is connected to the chamber apparatus 104 through the second precursor supply valve 124 and is configured to provide a flow of the second precursor 22 to the chamber apparatus 104 to form the semiconductor structure 200. In this regard, the second precursor supply valve 124 can be similar to the first precursor supply valve 122 and is also operably associated with the controller 108. In some examples, the second precursor 22 may include an alloy component, such as a material that cooperates with the first precursor 20 to form the layer 14 as an alloy. In this regard, the second precursor 22 may include a germanium-containing material, such as a non-chlorinated germanium-containing material and / or a chlorinated germanium-containing material. Examples of suitable non-chlorinated germanium-containing materials include germanium (GeH4). Examples of suitable chlorinated germanium-containing materials include germanium tetrachloride (GeCl4). In view of the present disclosure, those skilled in the art will understand that other alloy components, such as gallium (Ga) and / or indium (In), may be used and still be within the scope of the present disclosure. In some examples, the first precursor may include a first material layer component that has a lower affinity for incorporation into a material layer forming semiconductor structure 200 than a second material layer component provided by the second precursor. For example, the first precursor may provide silicon (Si) for incorporation into a material layer deposited on a substrate during formation of semiconductor structure 200, and the second precursor may provide germanium (Ge) for incorporation into a deposited material layer during formation of semiconductor structure 200.

[0043] The third precursor source 116 is connected to the chamber apparatus 104 through a third precursor supply valve 126 and is configured to provide a flow of the third precursor 24 to the chamber apparatus 104 to form the semiconductor structure 200. The third precursor supply valve 126 can be similar to the first precursor supply valve 122 and further operably associated with the first precursor supply valve 122. In some examples, the third precursor 24 can include a dopant-containing material (e.g., the second precursor 22). In this regard, it is expected that the third precursor 24 may include a p-type dopant, such as boron (B) or gallium (Ga). Examples of suitable dopant-containing materials include diborane (B2H6), gallium nitrate (Ga(NO3)3). In view of the present disclosure, those skilled in the art will appreciate that other dopant-containing materials can be employed and are still within the scope of the present disclosure.

[0044] In some examples, the third precursor may include a third material layer component that has a greater affinity for incorporation into a material layer forming semiconductor structure 200 than a second material layer component provided by the second precursor. For example, the third precursor may provide boron (B) for incorporation into a material layer deposited on a substrate during formation of semiconductor structure 200, and the second precursor may provide germanium (Ge) for incorporation into a layer deposited to form semiconductor structure 200. The third material layer component may also have a greater affinity for incorporation into the layer than the first component incorporated into the layer. For example, a material layer may include silicon (Si) and boron (B), and available boron (B) may outcompete silicon (Si) for incorporation into the layer. Similarly, a material layer may include silicon (Si), germanium (Ge), and boron (B), and boron (B) may outcompete silicon (Si) and germanium (Ge) for incorporation into the material layer.

[0045] The carrier gas / purge gas source 118 and the etchant source 120 are further connected to the chamber device 104 through the carrier gas / purge gas supply valve 128 and the etchant supply valve 130, respectively. The carrier gas / purge gas supply valve 128 is configured to provide a carrier gas / purge gas 28 flow to the chamber device 104, which can be similar to the first precursor supply valve 122, and can be operably associated with the controller 108. In some examples, the carrier gas / purge gas source 118 may include an inert gas and / or a rare gas. Examples of suitable inert gases include nitrogen (N2). Examples of suitable rare gases include helium (He), argon (Ar) and krypton (Kr). According to some examples, the carrier gas / purge gas source 118 can be alternatively (or additionally) configured to provide a hydrogen (H2) flow to the chamber device 104. It is contemplated that the carrier / purge gas 28 may be used to throttle the concentration of one or more of the first precursor 20, the second precursor 22, the third precursor 24, and / or the etchant 26 provided to the chamber apparatus 104 during the formation of the semiconductor structure 200, as well as to provide a purge atmosphere within the chamber apparatus 104. In view of the present disclosure, those skilled in the art will appreciate that other carrier / purge gases and / or etchants may be used and still be within the scope of the present disclosure.

[0046] The etchant source 120 is configured to provide an etchant 26 to the chamber device 104 through an etchant supply valve 130. The etchant supply valve 130 can be similar to the first precursor supply valve 122 and can be operably associated with the controller 108, for example, for throttling the flow of the etchant 26 provided to the chamber device 104. Examples of suitable etchants include halide-containing materials, such as materials containing fluorine (F) or chlorine (Cl). Examples of suitable halide-containing materials include hydrofluoric acid (HF), hydrochloric acid (HCl) and / or chlorine (Cl2). In view of the present disclosure, those skilled in the art will understand that the etchant 26 can be used to impart selectivity to one or more deposition processes employed in the chamber device 104 to form the semiconductor structure 200, such as etching an amorphous or polycrystalline material deposited on the substrate 2 faster than an epitaxial material of substantially equivalent composition.

[0047] refer to Figure 3, shows a chamber apparatus 104 and a controller 108 according to an example of the present disclosure. In the example shown, the chamber apparatus 104 has a single wafer crossflow apparatus, and in this regard includes a chamber body 132, an injection flange 134, and an exhaust flange 136. In another aspect, the chamber apparatus 104 also includes an upper heater element array 138, a lower heater element array 140, a divider 142, a substrate support 144, a support member 146, an axis member 148, and a lift and rotation module 150. Although shown and described herein as including certain elements and having a particular arrangement in the example shown, it should be understood and appreciated that the chamber apparatus 104 may include additional elements and / or exclude elements shown and described herein, or have a different arrangement than shown and described herein, and remain within the scope of the present disclosure.

[0048] The chamber body 132 is formed of a transmissive material 152 (e.g., transmissive electromagnetic radiation within the infrared band) and has an upper wall 154, a lower wall 156, a first side wall 158, and a second side wall 160. The upper wall 154 extends between an injection end 162 and a longitudinally opposite discharge end 164 of the chamber body 132. The lower wall 156 is spaced apart from the upper wall 154 by an interior 166 of the chamber body 132, extends between the injection end 162 and the discharge end 164 of the chamber body 132, and is coupled to the upper wall 154 by the first side wall 158 and the second side wall 160. In some examples, the transmissive material 152 may include a ceramic material. Non-limiting examples of suitable ceramic materials include quartz, fused silica, and sapphire. According to some examples, the chamber body 132 may include a plurality of external ribs extending around the exterior of the chamber body 132 and spaced apart from each other longitudinally between the injection end 162 and the discharge end 164 of the chamber body 132. Although shown and described herein as having a planar shape, it should be understood and appreciated that chamber body 132 may have an arcuate or dome-like shape and still be within the scope of the present disclosure.

[0049] The injection flange 134 is connected to the injection end 162 of the chamber body 132, couples the precursor delivery device 102 to the chamber body 132, and is configured to inject the precursor delivery device 102 ( Figure 1 The precursor 10 provided by the chamber assembly 104 is delivered to the interior 166 of the chamber body 132. The exhaust flange 136 is connected to the exhaust end 164 of the chamber body 132, couples the chamber body 132 to the exhaust device 106, and is configured to deliver the residual precursor and / or reaction product 18 emitted by the chamber assembly 104 to the exhaust device 106.

[0050] The upper heater element array 138 is supported above the chamber body 132 and is configured to transfer heat into the interior 166 of the chamber body 132 through the upper wall 154 of the chamber body 132, for example radiatively using electromagnetic radiation in the infrared band transmitted by the transmissive material 152 forming the upper wall 154 of the chamber body 132. The lower heater element array 140 is similar to the upper heater element array 138, is additionally supported below the chamber body 132, and is configured to transfer heat into the interior 166 of the chamber body 132 through the lower wall 156 of the chamber body 132. In some examples, the upper heater element array 138 may include a plurality of upper linear lamps, the lower heater element array 140 may include a plurality of lower linear lamps, and the plurality of lower linear lamps may be orthogonal relative to the plurality of upper linear lamps. According to some examples, the plurality of upper linear lamps may extend laterally between the first side wall 158 and the second side wall 160, and the plurality of linear lamps may be longitudinally spaced apart from each other between the injection end 162 and the exhaust end 164 of the chamber body 132. It is also contemplated that a plurality of upper linear lamps may extend longitudinally between the injection end 162 and the exhaust end 164 of the chamber body 132 and be laterally spaced apart from one another between the first side wall 158 and the second side wall 160 and still be within the scope of the present disclosure. In view of the present disclosure, one skilled in the art will appreciate that either (or both) of the upper and lower heater element arrays 138, 140 may include bulb or spotlight type heater elements and still be within the scope of the present disclosure.

[0051] The divider 142 is formed of an opaque material 168 (e.g., a material that is opaque to electromagnetic radiation in the infrared band), is fixed within the interior 166 of the chamber body 132, and divides the interior 166 of the chamber body 132 into an upper chamber 170 and a lower chamber 172. The divider 142 further defines a hole 174 that fluidly couples the upper chamber 170 of the interior 166 of the chamber body 132 to the lower chamber 172. The substrate support 144 is supported to rotate R about a rotation axis 176 extending through the hole 174, is at least partially disposed within the hole 174, and is configured to support the substrate during layer deposition onto the substrate surface (e.g., support the substrate 2 during formation of the semiconductor structure 200 layer 14 onto the upper surface of the substrate 2). In this regard, it is contemplated that the substrate support 144 can be formed of an opaque material, such as opaque material 168, and optically coupled to at least one of the upper and lower heater element arrays 138, 140 through the upper and lower walls 154, 156, respectively, of the chamber body 132. In some examples, the opaque material 168 can include a carbonaceous material, such as silicon carbide and / or bulk graphite, by way of example and not limitation.

[0052] The support member 146 is disposed within the lower chamber 172 of the chamber body 132 along an axis of rotation 176, is rotationally fixed relative to the substrate support 144, and couples the substrate support 144 to the shaft member 148. The shaft member 148 is rotationally fixed relative to the support member 146, extends through the lower wall 156 of the chamber body 132 and into the environment outside the chamber body 132, and couples the substrate support 144 to the lift and rotation module 150 through the support member 146. The lift and rotation module 150 is operably connected to the substrate support 144 and is configured to rotate the substrate support 144 about the axis of rotation 176 during deposition of the layer 14 onto the substrate 12. The lift and rotation module 150 may also be configured to, for example, cooperate with the gate valve 178 and the substrate transfer robot 180 to place a substrate (e.g., substrate 12) on and remove it from the substrate support 144. In some examples, either (or both) support member 146 and shaft member 148 may be formed from a transmissive material, such as transmissive material 152 .

[0053] In the illustrated example, the controller 108 includes a device interface 182, a processor 184, a user interface 186, and a memory 188. The device interface 182 couples the controller 108 to one or more of the precursor delivery device 102, the chamber device 104, and the exhaust device 106, for example, via a wired or wireless link 110. The processor 184 is configured to communicate with the device interface 182 and the memory 188, and is operably connected to the user interface 186, for example, to receive input and / or provide user output therethrough. The memory 188 includes a non-transitory machine-readable medium having a plurality of program modules 190 recorded thereon, and when the processor 184 reads the program modules 190, the program modules 190 cause the processor 184 to perform certain operations. These operations include manufacturing a semiconductor structure (e.g., semiconductor structure 200 (e.g., Figure 4 Method 300 (as shown)) Fig.10 192. Although shown and described herein as including certain elements and having a particular arrangement in the illustrated example, it should be understood and appreciated that the controller 108 may include additional elements and / or exclude elements shown and described herein, or have a different arrangement than shown and described herein, and still be within the scope of the present disclosure.

[0054] refer to Figure 4 and Figure 5-8 , showing the semiconductor structure 200 and the sequential (eg, layer-by-layer) formation of the semiconductor structure 200. Figure 4, semiconductor structure 200 includes substrate 2, silicon germanium (SiGe) layer 202, first boron-doped SiGe (SiGe:B) layer 204, second SiGe:B layer 206, and boron-doped silicon (Si:B) layer 208. Substrate 2 is formed of a semiconductor material such as silicon, defines a trench 4, and has a silicon surface portion 6 and a dielectric surface portion 8. Trench 4 is defined within the upper surface of the substrate and is at least partially bounded by silicon surface portion 6. Dielectric surface portion 8 is outside trench 4 and may include (or consist of or consist essentially of) oxide in some examples.

[0055] The SiGe layer 202 is arranged (e.g., deposited) in the trench 4, covers the silicon surface portion 6 (e.g., on the bottom and sidewalls of the trench), and can be epitaxially grown together with the silicon surface portion 6 of the substrate 2. The first SiGe:B layer 204 is also arranged (e.g., deposited) in the trench 4 (e.g., conformally covers the SiGe layer 202 covering the bottom of the trench 4 and the sidewalls of the trench 4), additionally covers the SiGe layer 202, and can also be epitaxially grown together with the SiGe layer 202. The second SiGe:B layer 206 is further arranged (at least partially) in the trench 4 (e.g., can overfill the trench 4), covers the first SiGe:B layer 204, and can be epitaxially grown together with the SiGe layer 204. The Si:B layer 208 covers the second SiGe:B layer 206, can be arranged outside the portion of the trench 4 (e.g., can cover the second SiGe:B layer 206), and can be epitaxially grown together with the second SiGe:B layer 206. In some examples, the Si:B layer 208 may cover the second SiGe:B layer 206, and the Si:B layer 208 separates the second SiGe:B layer 206 from structures overlying the Si:B layer 208. According to some examples, the semiconductor structure 200 may form a portion of a three-dimensional semiconductor device 400. In this regard, the semiconductor structure 200 may be included in a source portion or a drain portion of a gate-all-around semiconductor device, a finFET semiconductor device, or a 3D DRAM semiconductor device.

[0056] like Figure 5As shown, SiGe layer 202 can be deposited in trench 4 and conformally deposited onto silicon surface portion 6 (e.g., directly onto it). It is contemplated that SiGe layer 202 is formed with SiGe layer thickness 210 and SiGe layer germanium content 212. SiGe layer thickness 210 can be between about 25 angstroms and 100 angstroms, such as between about 25 angstroms and about 50 angstroms, or between about 50 angstroms and about 75 angstroms, or even between about 75 angstroms and about 100 angstroms. SiGe layer germanium content 212 can be between about 5 atomic weight % and about 55 atomic weight %, such as between about 5 atomic weight % and about 25 atomic weight %, or between about 25 atomic weight % and about 40 atomic weight %, or even between about 40 atomic weight % and about 55 atomic weight %. According to some examples, the germanium concentration can be graded within SiGe layer 202, with the concentration varying within the thickness of SiGe layer 202. It is also contemplated that the germanium concentration can be constant within the SiGe layer 202 and still be within the scope of the present disclosure. Advantageously, forming the SiGe layer 202 with a SiGe layer thickness 210 and / or a SiGe layer germanium content 212 within these ranges can grade strain within the semiconductor structure 200 due to a lattice mismatch between the silicon surface portion 6 and the lattice defined by the SiGe layer 202, thereby reducing (or eliminating) the tendency to form crystal slip defects at the silicon surface-SiGe layer interface 214 due to strain associated with the lattice mismatch.

[0057] like Figure 6As shown, a first SiGe:B layer 204 can be deposited within the trench 4 and conformally deposited onto the SiGe layer 202. It is contemplated that the first SiGe:B layer 204 is formed with a first SiGe:B layer thickness 216, a first SiGe:B layer germanium content 218, and a first SiGe:B layer boron content 220. The first SiGe:B layer thickness 216 can be between about 25 angstroms and about 250 angstroms, such as between about 25 angstroms and about 100 angstroms, or between about 100 angstroms and about 175 angstroms, or even between about 175 angstroms and about 250 angstroms. The first SiGe:B layer germanium content 218 can be between 5 atomic weight % and about 55 atomic weight %, such as between about 5 atomic weight % and about 25 atomic weight %, or between about 25 atomic weight % and about 40 atomic weight %, or even between about 40 atomic weight % and about 55 atomic weight %. In some examples, the first SiGe:B layer germanium content 218 can be less than the SiGe layer germanium content 212. According to some examples, the germanium concentration can be graded within the first SiGe:B layer 204, with the concentration varying within the thickness of the first SiGe:B layer 204. It is also contemplated that the germanium concentration can be constant within the first SiGe:B layer 204 and still be within the scope of the present disclosure. Advantageously, forming the first SiGe:B layer 204 with the first SiGe:B layer germanium content 218 and / or the first SiGe:B layer boron content 220 can grade the strain within the semiconductor structure 200, thereby reducing (or eliminating) the risk of crystal slip defects that may otherwise occur within the semiconductor structure 200, such as at a SiGe layer-first SiGe:B layer interface 222 defined between the SiGe layer 202 and the first SiGe:B layer 204.

[0058] The boron content of the first SiGe:B layer 220 may be about 1e 18 atoms / cm3 (cm 3 ) and about 1e 22 atoms / cm 3 between, for example, about 1e 18 atoms / cm 3 With about 1e 19 atoms / cm 3 between, or about 1e 19 atoms / cm 3 With about 1e 20 atoms / cm 3 or even around 1e 20 atoms / cm 3 With about 1e 21 atoms / cm 3In some examples, the first SiGe:B layer 204 can be composed essentially of SiGe:B. According to some examples, the first SiGe:B layer boron content 220 can be substantially uniform throughout the first SiGe:B layer thickness 216. It is expected that in some examples, the first SiGe:B layer germanium content 218 can be substantially uniform throughout the first SiGe:B layer thickness 216. It is also expected that, according to some examples, the first SiGe:B layer 204 can be epitaxially grown with the SiGe layer 202. Advantageously, forming the first SiGe:B layer 204 having a first SiGe:B layer boron content 220 within these ranges can impart electrical characteristics to the semiconductor structure 200, which makes the semiconductor structure 200 suitable for use as a source and / or drain portion of a semiconductor device, such as in a PMOS device.

[0059] like Figure 7 As shown, the second SiGe:B layer 206 can be deposited within the trench 4 and conformally deposited onto the first SiGe:B layer 204. It is contemplated that the second SiGe:B layer 206 is formed with a second SiGe:B layer thickness 224, a second SiGe:B layer germanium content 226, and a second SiGe:B layer boron content 228. The second SiGe:B layer thickness 224 can be between about 100 angstroms and about 1000 angstroms, such as between about 100 angstroms and about 300 angstroms, or between about 300 angstroms and about 600 angstroms, or even between about 600 angstroms and about 1000 angstroms. The second SiGe:B layer germanium content 226 can be between about 3 atomic weight % and about 70 atomic weight %, such as between about 3 atomic weight % and about 20 atomic weight %, or between about 20 atomic weight % and about 40 atomic weight %, or even between about 40 atomic weight % and about 70 atomic weight %. In some examples, the second SiGe:B layer germanium content 226 can be less than the first SiGe:B layer germanium content 218. According to some examples, the germanium concentration can be graded within the second SiGe:B layer 206, with the concentration varying within the thickness of the second SiGe:B layer 206. It is also contemplated that the germanium concentration can be constant within the second SiGe:B layer 206 and still be within the scope of the present disclosure. Advantageously, forming the second SiGe:B layer 206 with the second SiGe:B layer germanium content 226 and / or the second SiGe:B layer boron content 228 can grade the strain within the semiconductor structure 200, thereby reducing (or eliminating) the risk of crystal slip defects that may otherwise occur within the semiconductor structure 200, such as at the first SiGe:B layer-second SiGe:B layer interface 230 defined between the second SiGe:B layer 206 and the first SiGe:B layer 204.

[0060] The boron content of the second SiGe:B layer 228 may be about 1e 18 atoms / cm3 With about 1e 22 atoms / cm 3 between, for example, about 1e 18 atoms / cm 3 With about 1e 19 atoms / cm 3 between, or about 1e 19 atoms / cm 3 With about 1e 20 atoms / cm 3 or even around 1e 20 atoms / cm 3 With about 1e 21 atoms / cm 3 In some examples, the second SiGe:B layer 206 may consist of or consist essentially of SiGe:B. According to some examples, the second SiGe:B layer boron content 228 may be substantially uniform throughout the second SiGe:B layer thickness 224. It is contemplated that in some examples, the second SiGe:B layer germanium content 226 may be substantially uniform throughout the second SiGe:B layer thickness 224. It is also contemplated that, according to some examples, the second SiGe:B layer 206 may be epitaxially grown with the first SiGe:B layer 204. Advantageously, forming the second SiGe:B layer 206 having a second SiGe:B layer boron content 228 within these ranges may, in cooperation with the first SiGe:B layer 204, impart electrical characteristics to the semiconductor structure 200, which makes the semiconductor structure 200 suitable for use as a source and / or drain portion of a semiconductor device, such as in a PMOS semiconductor device.

[0061] like Figure 8 As shown, Si:B layer 208 covers second SiGe:B layer 206, which is at least partially disposed in trench 4, and has a Si:B layer thickness 232 and a Si:B layer boron content 234. Si:B layer thickness 232 can be between about 50 angstroms and about 200 angstroms, such as between about 50 angstroms and about 100 angstroms, or between about 100 angstroms and about 150 angstroms, or even between about 150 angstroms and about 200 angstroms. Si:B layer boron content 234 can be between about 1e 19 atoms / cm 3 With about 1e 22 atoms / cm 3 between, for example, about 1e 19 atoms / cm 3 With about 1e 20 atoms / cm 3 between, or about 1e 20 atoms / cm 3 With about 1e 21 atoms / cm3 or even around 1e 20 atoms / cm 3 With about 1e 21 atoms / cm 3 In some examples, the Si:B layer 208 can be conformal with the second SiGe:B layer 206, such as by being directly deposited onto the second SiGe:B layer 206. According to some examples, the Si:B layer 208 can be epitaxially grown with the second SiGe:B layer 206. It is contemplated that the Si:B layer 208 can be conformal with the second SiGe:B layer 206, such as by being directly deposited onto the second SiGe:B layer 206. It is also contemplated that the Si:B layer 208 can be epitaxially grown with the second SiGe:B layer 206, according to some examples. Advantageously, forming the semiconductor structure 200 with the Si:B layer thickness 232 and the Si:B layer boron content 234 can limit (or eliminate) strain within the Si:B layer 208, limiting (or eliminating) the risk of crystal slip defects within the Si:B layer 206 that may be associated with a lattice mismatch between the crystal structure of the second SiGe: layer 206 and the crystal structure of the Si:B layer 208.

[0062] It is contemplated that a Si:B layer-second SiGe:B layer interface 236 (eg, Figure 4 As shown in Fig.10 As shown, the interface 236 of the Si:B layer-second SiGe:B layer may be substantially defect-free, for example, with respect to changes in boron concentration at the interface (e.g., Fig. 9 In this regard, it has been discovered that controlling the binding rates of germanium (Ge) and boron (B) during deposition of the second SiGe:B layer 206—and boron (B) during deposition of the Si:B layer 208, using sequential precursor flow throttling independent of the silicon-containing precursor, limits the defect rate at the interface caused by changes in boron (B) concentration due to the tendency of boron (B) to compete with other components at the growth face exposed to the precursor during formation of the semiconductor structure 200. Without being bound by a particular theory or mode of operation, it is believed that the greater binding affinity of boron (B) relative to germanium (Ge) can locally increase the boron concentration at the Si:B layer-second SiGe:B layer interface 236 relative to the boron concentration within the second SiGe:B layer 206 and Si:B layer 208. In certain semiconductor structures, the increased boron (B) concentration at the Si:B layer-second SiGe:B layer interface 236 can change the electrical characteristics of the semiconductor structure. The increased boron (B) concentration may also locally change the lattice mismatch between the second SiGe:B layer 206 and the Si:B layer 208 , locally increase the strain associated with the lattice mismatch, and increase the risk of generating crystal slip defects near or at the Si:B layer-second SiGe:B layer interface 236 .

[0063] In some examples, the Si:B layer-second SiGe:B layer interface 236 can be substantially defect-free. The defect-free interface Si:B layer-second SiGe:B layer interface 236 can be formed by throttling the precursor flow during deposition of the second SiGe:B layer 206 and the Si:B layer 208 according to the relative binding affinities of the layer components provided in the precursor flow. For example, during deposition of the second SiGe:B layer 206, the boron-containing precursor is introduced into the chamber assembly 104 ( Figure 1 The flow of the germanium-containing precursor (e.g., third precursor 24) may then be stopped during the deposition of the second SiGe:B layer 206. The flow of the silicon-containing precursor (e.g., first precursor 20) may be increased (either in correspondence with or subsequent to the reduction of either or both of the boron-containing precursor and the germanium-containing precursor), and then the flow of the boron-containing precursor may be resumed. Advantageously, this prevents boron concentration variations that may otherwise occur if the germanium-containing precursor and the boron-containing precursor are shut down simultaneously with each other, such as during the process in which the atmosphere within a chamber apparatus used to form the semiconductor structure 200 is purged between the deposition of the second SiGe:B layer 208 and the deposition of the Si:B layer 208.

[0064] Also like Fig. 9 Related Fig.10 As shown, stopping the flow of the boron-containing precursor before stopping the flow of the germanium-containing precursor causes the available boron remaining in the atmosphere of the chamber device 104 after the boron-containing precursor is stopped to be gradually consumed during the deposition of the terminal portion of the second SiGe:B layer 208, preventing the remaining available boron from competing with the available germanium to be incorporated into the second SiGe:B layer 208 being formed. In view of the present disclosure, those skilled in the art will understand that this allows the Si:B layer-second SiGe:B layer interface 236 to be defined by the depletion of boron in the atmosphere of the chamber device 104, rather than by purging the atmosphere to drive off the available boron and germanium remaining in the atmosphere to stop the deposition process. In view of the present disclosure, those skilled in the art will also understand that this can also limit the time required to form the semiconductor structure 200, because during the deposition of the second SiGe:B layer 206 and the Si:B layer 208 (and the Si:B layer-second SiGe:B layer interface 236), the silicon-containing precursor can flow continuously, thereby improving the throughput relative to the process that uses a purge between the deposition of the second SiGe:B layer 206 and the Si:B layer 208.

[0065] refer to Figure 11-14 , according to an illustrative and non-limiting example of the present disclosure, a semiconductor structure such as semiconductor structure 200 ( Figure 1 As shown in FIG. Fig.11As shown, method 300 includes placing a substrate in a chamber device of a semiconductor processing system, for example, placing a substrate 2 ( Figure 1 ) is disposed in a semiconductor processing system 100 ( Figure 1 Chamber device 104 (shown) Figure 1 ), as shown in block 302. The method 300 also includes forming a silicon germanium layer, such as SiGe layer 202 (such as Figure 4 ) is deposited onto the substrate, as shown in block 304. The method 300 also includes depositing a first boron-doped silicon germanium layer onto the SiGe layer, and depositing a second boron-doped silicon germanium layer on the first boron-doped silicon germanium layer, for example, depositing the first SiGe:B layer 204 (as shown in block 304) onto the substrate. Figure 4 ) is deposited onto the SiGe layer and a second SiGe:B layer 206 (as shown Figure 4 ) is deposited onto the first SiGe:B layer, as shown in blocks 306 and 308. It is contemplated that method 300 also includes depositing a boron-doped silicon layer onto a second SiGe:B layer, such as Si:B layer 208 (as shown in FIG. Figure 4 ), and the semiconductor structure may be used to form a semiconductor device, as shown in blocks 308 and 310. Fig.12 As shown, it is contemplated that the semiconductor structure may be used to form a planar semiconductor device, a 3D DRAM semiconductor device, a finFET semiconductor device, and / or a GAA semiconductor device, as shown in blocks 378 - 384 .

[0066] Likewise Fig.12 As shown, placing the substrate 302 in the chamber device may include placing a and a substrate in the chamber device, as shown in block 312. Placing the substrate 302 in the chamber device may include placing the substrate in a chamber device having a single wafer cross flow device, as shown in block 314. Placing the substrate 302 in the chamber device may include placing a groove defined in the upper surface of the substrate, such as groove 4 (such as Figure 4 ) as shown in block 316. Placing 302 the substrate in the chamber apparatus may include placing a substrate having an exposed silicon surface portion and an exposed dielectric surface portion on an upper surface of the substrate, such as silicon surface portion 6 (as shown in FIG. Figure 4 as shown) and the dielectric surface portion 8 (as shown Figure 4 ), as shown in blocks 318 and 320. By way of illustration and not limitation, it is contemplated that the dielectric surface may include an oxide, such as silicon oxide.

[0067] like Fig.12As further shown, depositing 304 the SiGe layer may include depositing the SiGe layer at a predetermined SiGe layer deposition pressure, as shown in block 322. The predetermined SiGe layer deposition pressure may be between about 10 Torr and about 150 Torr, also shown in block 322. Depositing 304 the SiGe layer may include depositing the SiGe layer at a predetermined SiGe layer deposition temperature, as shown in block 324. The predetermined SiGe layer deposition temperature may be between about 400 degrees Celsius and about 800 degrees Celsius, also shown in block 324. Depositing 304 the SiGe layer may also include depositing the SiGe layer at a predetermined SiGe layer deposition temperature, as shown in block 324. The predetermined SiGe layer deposition temperature may be between about 400 degrees Celsius and about 800 degrees Celsius, also shown in block 324. Depositing 304 the SiGe layer may also include depositing the SiGe layer at a predetermined SiGe layer deposition pressure, as shown in block 322. Figure 1 326. The silicon-containing precursor may flow, for example, at a flow rate of about 10 standard cubic centimeters per minute (SCCM) to about 700 SCCM of the SiGe layer silicon-containing precursor, also as shown in block 326. Depositing 304 the SiGe layer may also include mixing the germanium-containing precursor with a silicon-containing precursor, such as a second precursor 22 (such as Figure 2 The germanium-containing precursor may be co-flowed into the chamber apparatus together with the germanium-containing precursor (shown in block 328), as shown in block 328. The germanium-containing precursor may flow, for example, at a SiGe layer germanium-containing precursor flow rate between about 5 SCCM and about 70 SCCM, as also shown in block 328.

[0068] Depositing 304 the SiGe layer may further include applying an etchant (e.g., etchant 26 (e.g., Figure 2 The etchant 26 may be co-flowed into the chamber apparatus along with the silicon-containing precursor and the germanium-containing precursor, as shown in block 330. The etchant may be flowed to the chamber apparatus at a SiGe layer etchant flow rate, such as at a SiGe layer etchant flow rate between about 10 SCCM and about 200 SCCM, also as shown in block 330. In view of the present disclosure, one skilled in the art will appreciate that the etchant 26 may provide selectivity to the location of the SiGe layer deposited on the substrate, such as by depositing more SiGe than covering the silicon surface portion 6 (e.g., Figure 4 ) to more quickly etch the SiGe deposited on the dielectric surface portion 4 (as shown Figure 4 Advantageously, this can completely inhibit deposition of amorphous material 30 (amorphous SiGe, SiGe:B and / or Si:B) onto dielectric surface portion 4 during formation of semiconductor structure 200. In view of this disclosure, one skilled in the art will also appreciate that carrier / purge gases such as carrier / purge gas 28 ( Figure 2 ) may be mixed with one or more precursors provided to the chamber apparatus during deposition of the SiGe layer.

[0069] like Fig.12As further shown, depositing 306 the first SiGe:B layer may include depositing the first SiGe:B layer at a predetermined first SiGe:B layer deposition pressure, as shown in block 332. The predetermined first SiGe:B layer deposition pressure may be between about 10 Torr and about 150 Torr, as also shown in block 332. Depositing 306 the first SiGe:B layer may include depositing the first SiGe:B layer at a predetermined first SiGe:B layer deposition temperature, as shown in block 334. The predetermined first SiGe:B layer deposition temperature may be between about 400 degrees Celsius and about 800 degrees Celsius, as also shown in block 334. Depositing 306 the first SiGe:B layer may include depositing the first SiGe:B layer by flowing a silicon-containing precursor to the chamber apparatus, as shown in block 336. The silicon-containing precursor may flow at a first SiGe:B layer silicon-containing precursor flow rate, such as flowing at a first SiGe:B layer silicon-containing precursor flow rate between about 10 SCCM and about 700 SCCM, as also shown in block 336. Depositing 306 the first SiGe:B layer may include co-flowing a germanium containing precursor into the chamber apparatus with the silicon containing precursor, as shown in block 338. The germanium containing precursor may flow at a germanium containing precursor flow rate between about 5 SCCM and about 50 SCCM, also shown in block 338.

[0070] Depositing 306 the first SiGe:B layer may include mixing a boron-containing precursor with a silicon-containing precursor and a germanium-containing precursor (eg, third precursor 28 (eg, Figure 2 SCCM and about 40 SCCM) into the chamber arrangement, as shown in block 340. The boron-containing precursor may flow, for example, at a first SiGe:B layer boron-containing precursor flow rate between about 0.25 SCCM and about 5 SCCM, also as shown in block 340. Depositing 306 the first SiGe:B layer may include flowing an etchant to the chamber arrangement along with the silicon-containing precursor and the germanium-containing precursor, as shown in block 342. The etchant may flow to the chamber arrangement at a first SiGe:B layer etchant flow rate, for example, at a first SiGe:B layer etchant flow rate between about 10 SCCM and about 40 SCCM, also as shown in block 342. In view of the present disclosure, one skilled in the art will appreciate that the etchant provided during deposition of the first SiGe:B layer may provide selectivity to the location on the substrate where the first SiGe:B layer is deposited, for example by etching SiGe:B deposition on dielectric surface portions of the substrate faster than SiGe:B deposition overlying silicon surface portions of the substrate. In view of the present disclosure, those skilled in the art will also appreciate that during deposition of the first SiGe:B layer, a carrier gas / purge gas may be mixed with one or more precursors provided to the chamber apparatus.

[0071] like Fig.12As shown, depositing 308 the second SiGe:B layer may include depositing the second SiGe:B layer at a predetermined second SiGe:B layer deposition pressure, as shown in block 346. The predetermined second SiGe:B layer deposition pressure may be between about 10 Torr and about 100 Torr, as also shown in block 346. Depositing 308 the second SiGe:B layer may include depositing the second SiGe:B layer at a predetermined second SiGe:B layer deposition temperature, as shown in block 348. The predetermined second SiGe:B layer deposition temperature may be between about 400 degrees Celsius and about 800 degrees Celsius, as also shown in block 348. Depositing 308 the second SiGe:B layer may include depositing the second SiGe:B layer by flowing a silicon-containing precursor to the chamber apparatus, as shown in block 350. The silicon-containing precursor may flow at a second SiGe:B layer silicon-containing precursor flow rate between about 10 SCCM and about 700 SCCM, as also shown in block 350. Depositing 308 the second SiGe:B layer may include co-flowing a germanium-containing precursor with a silicon-containing precursor into the chamber apparatus, as shown in block 352. The germanium-containing precursor may flow at a germanium-containing precursor flow rate between about 10 SCCM and about 100 SCCM, also shown in block 352. Depositing 308 the second SiGe:B layer may include co-flowing a boron-containing precursor with a silicon-containing precursor and a germanium-containing precursor (e.g., a third precursor 28 (e.g., Figure 2 The boron-containing precursor may flow to the chamber apparatus at a second SiGe:B layer boron-containing precursor flow rate of, for example, between about 3 SCCM and about 150 SCCM, as also shown in block 354.

[0072] Depositing 308 the second SiGe:B layer may include co-flowing an etchant into the chamber apparatus along with the silicon-containing precursor, the germanium-containing precursor, and the boron-containing precursor, as shown in block 356. The etchant may flow to the chamber apparatus at a second SiGe:B layer etchant flow rate, such as at a second SiGe:B etchant flow rate between about 10 SCCM and about 400 SCCM, also shown in block 356. In view of the present disclosure, one skilled in the art will appreciate that the etchant may provide selectivity to the location where the second SiGe:B layer is deposited, such as by etching SiGe:B deposition on dielectric surface portions faster than SiGe:B deposition covering silicon surface portions of the substrate. In view of the present disclosure, one skilled in the art will also appreciate that during deposition of the second SiGe:B layer, a carrier gas / purge gas may be mixed with one or more precursors provided to the chamber apparatus.

[0073] Also like Fig.13As shown, depositing 310 the Si:B layer may include depositing the Si:B layer at a predetermined second Si:B layer deposition pressure, as shown in block 358. The predetermined Si:B layer deposition pressure may be between about 10 Torr and about 100 Torr, also shown in block 358. Depositing 310 the Si:B layer may include depositing the second SiGe:B layer at a predetermined Si:B layer deposition temperature, as shown in block 360. The predetermined Si:B layer deposition temperature may be between about 400 degrees Celsius and about 800 degrees Celsius, also shown in block 360. Depositing 310 the Si:B layer may include depositing the Si:B layer by flowing a silicon-containing precursor to the chamber arrangement, as shown in block 362. The silicon-containing precursor may flow at a predetermined Si:B layer silicon-containing precursor flow rate between about 10 SCCM and about 700 SCCM, also shown in block 362. Depositing 364 the Si:B layer may include co-flowing a boron-containing precursor into the chamber arrangement with the silicon-containing precursor, as shown in block 364. The boron-containing precursor may flow at a predetermined Si:B layer boron-containing precursor flow rate, for example, between about 3 SCCM and about 150 SCCM, as also shown at block 364 .

[0074] In some examples, depositing 310 the Si:B layer may include flowing an etchant to the chamber apparatus along with the silicon-containing precursor and the boron-containing precursor, as shown in block 366. The etchant may flow to the chamber apparatus, for example, at a predetermined Si:B layer etchant flow rate between about 10 SCCM and about 300 SCCM, also as shown in block 366. In view of the present disclosure, one skilled in the art will appreciate that the etchant provided during deposition of the Si:B layer may provide selectivity to the location on the substrate where the Si:B layer is deposited, such as by etching Si:B deposition on dielectric surface portions faster than Si:B deposition covering silicon surface portions of the substrate. In view of the present disclosure, one skilled in the art will also appreciate that during deposition of the Si:B layer, a carrier gas / purge gas may be mixed with one or more precursors provided to the chamber apparatus.

[0075] like Fig.14 As shown, depositing 306 the second SiGe:B layer may include stopping the flow of the boron-containing precursor during the deposition of the second SiGe:B layer, as shown in block 368. In this regard, it is contemplated that the Si:B layer-second SiGe:B layer interface (e.g., Si:B layer-second SiGe:B layer interface 326 (e.g., Figure 8 Before the boron-containing precursor is stopped (as shown), the flow of the boron-containing fluid to the chamber arrangement is stopped (or reduced to a predetermined flow rate and thereafter stopped by diverting to the exhaust port), as also shown in block 368. In some examples, deposition of the second SiGe:B layer can continue after the flow of the boron-containing precursor to the chamber arrangement is stopped, and the continued deposition of the second SiGe:B layer consumes the residual boron content contained in the chamber arrangement, which houses the substrate and semiconductor structure formed thereon, as further shown in block 368.

[0076] Depositing 306 the second SiGe:B layer may include reducing the flow of a germanium-containing precursor in the chamber apparatus, as shown in block 370. The flow of the germanium-containing precursor may be reduced after the flow of the boron-containing precursor to the chamber apparatus is stopped, also as shown in block 370. It is contemplated that deposition of the second SiGe:B layer may continue during the flow reduction and / or after the flow of the germanium-containing precursor to the chamber apparatus is stopped, the continued deposition of the second SiGe:B layer consuming the residual germanium component within the atmosphere of the chamber apparatus. It is also contemplated that during deposition of the second SiGe:B layer, the flow of the germanium-containing precursor to the chamber apparatus is stopped thereafter, as shown in block 372. Thereafter, the second SiGe:B layer may continue to be deposited, consuming the residual germanium-containing component within the chamber apparatus, and thereafter, when the concentrations of the residual boron component and germanium component in the atmosphere of the chamber apparatus are insufficient to further deposit the second SiGe:B layer, the Si:B layer-second SiGe:B layer is defined. As shown in block 374 , during deposition of the second SiGe layer, flow of the silicon-containing precursor to the chamber apparatus may be increased, such as coincident with cessation of flow of the boron-containing precursor to the chamber apparatus and / or coincident with reduction of flow of the germanium-containing precursor to the chamber apparatus.

[0077] The deposition 308 of the Si:B layer is completed by resuming the flow of the boron-containing precursor after the flow of the germanium-containing precursor to the chamber apparatus is stopped, as shown in block 376. In some examples, the flow of the boron-containing precursor can be resumed after the residual germanium component in the atmosphere of the chamber apparatus is consumed (e.g., to a level where the germanium component in the chamber apparatus cannot support further growth of the second SiGe:B layer), also shown in block 376. According to some examples, the flow of the silicon-containing precursor can continue during the deposition of the second SiGe:B layer and the Si:B layer, as shown in block 376.

[0078] Although the present disclosure has been provided in the context of certain embodiments and examples, it will be understood by those skilled in the art that the present disclosure extends to other alternative embodiments and / or uses of embodiments beyond the specifically described embodiments and obvious modifications and equivalents thereof. In addition, although several variations of the embodiments of the present disclosure have been shown and described in detail, other modifications within the scope of the present disclosure will be readily apparent to those skilled in the art based on the present disclosure. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments may be made and still fall within the scope of the present disclosure. It should be understood that the various features and aspects of the disclosed embodiments may be combined or substituted with one another to form different modes of the embodiments of the present disclosure. Therefore, the scope of the present disclosure should not be limited by the specific embodiments described above.

[0079] The headings provided herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the apparatus and methods disclosed herein.

Claims

1. A method for manufacturing a semiconductor structure, include: placing a substrate in a chamber device; depositing a boron-doped silicon germanium (SiGe:B) layer onto the substrate; and depositing a boron-doped silicon (Si:B) layer onto the SiGe:B layer; in Deposition of the Si:B layer includes: stopping the flow of the boron-containing precursor to the chamber assembly; reducing the flow of germanium-containing precursors to the chamber assembly; increasing the flow of a silicon-containing precursor to the chamber assembly; After increasing the flow of the silicon-containing precursor, stopping the flow of the germanium-containing precursor to the chamber; and The flow of the boron-containing precursor to the chamber assembly is resumed.

2. The method according to claim 1, in, The SiGe:B layer has a SiGe:B layer boron concentration, wherein the Si:B layer has a Si:B layer boron concentration, and wherein the Si:B layer boron concentration is greater than the SiGe:B layer boron concentration.

3. The method of claim 1 , further comprising depositing a silicon germanium (SiGe) layer onto the substrate, in, The SiGe:B layer is deposited onto the SiGe layer. 4 . The method of claim 1 , further comprising continuously and uninterruptedly flowing a silicon-containing layer precursor to the chamber arrangement during deposition of the SiGe:B layer and the Si:B layer.

5. The method according to claim 1, in, The SiGe:B layer is a first SiGe:B layer, and further comprising depositing a second SiGe:B layer onto the first SiGe:B layer, wherein the Si:B layer is deposited onto the second SiGe:B layer.

6. The method according to claim 5, in, The first SiGe:B layer has a first boron concentration, wherein the second SiGe:B layer has a second boron concentration, and wherein the second boron concentration is greater than the first boron concentration.

7. The method according to claim 6, in, The Si:B layer has a third boron concentration, and wherein the third boron concentration is greater than the second boron concentration.

8. The method according to claim 6, in, The first SiGe:B layer has a first germanium concentration, wherein the second SiGe:B layer has a second germanium concentration, and wherein the second germanium concentration is greater than the first germanium concentration.

9. The method according to claim 5, in, Depositing the first SiGe:B layer and depositing the second SiGe:B layer includes continuously and uninterruptedly flowing a silicon-containing layer precursor to the chamber arrangement during deposition of the first SiGe:B layer and the second Si:B layer.

10. The method according to claim 1, in, Depositing the SiGe:B layer includes flowing the boron-containing precursor to the chamber device at a first boron-containing precursor flow rate, and the method also includes increasing the flow rate of the boron-containing precursor to a second boron-containing precursor flow rate, the second boron-containing precursor flow rate being greater than the first boron-containing precursor flow rate.

11. The method according to claim 1, in, The substrate has an upper surface defining a trench therein, and wherein depositing the SiGe:B layer includes depositing the SiGe:B layer at least partially within the trench.

12. The method according to claim 1, in, The substrate has a silicon surface portion and a dielectric surface portion, and the method includes flowing an etchant to the chamber arrangement to etch the dielectric surface portion of the substrate during depositing the SiGe:B layer and depositing the Si:B layer. 13 . The method of claim 1 , further comprising forming a gate-all-around semiconductor device, a finFET semiconductor device, a planar semiconductor device, or a 3D DRAM semiconductor device using the SiGe:B layer and the Si:B layer.

14. The method of claim 1, further comprising defining an interface between the SiGe:B layer and the Si:B layer between stopping the flow of the boron-containing precursor and resuming the flow of the boron-containing precursor to the chamber arrangement.

15. A semiconductor device comprising a semiconductor structure formed using the method according to claim 1.

16. The semiconductor structure according to claim 15, in, The semiconductor structure comprises: a silicon germanium (SiGe) layer covering the substrate; A first SiGe:B layer covering the SiGe layer; a second SiGe:B layer covering the first SiGe:B layer; and A Si:B layer covers the second SiGe:B layer, wherein the second SiGe:B layer and the Si:B layer have no defects at an interface between the second SiGe:B layer and the Si:B layer.

17. A semiconductor processing system, include: a precursor delivery device; a chamber assembly having a substrate support coupled to a precursor delivery assembly; a controller operably connected to the precursor delivery means and the chamber means, the controller responsive to instructions recorded on the memory to: placing a substrate in a chamber device; depositing a boron-doped silicon germanium (SiGe:B) layer covering the substrate; A boron-doped silicon (Si:B) layer overlying the SiGe:B is deposited by: stopping the flow of the boron-containing precursor to the chamber assembly; reducing the flow of germanium-containing precursors to the chamber assembly; increasing the flow of a silicon-containing precursor to the chamber assembly; After increasing the flow of the silicon-containing precursor, stopping the flow of the germanium-containing precursor to the chamber apparatus; as well as After stopping the flow of the germanium-containing precursor to the chamber arrangement, the flow of the boron-containing precursor to the chamber arrangement is resumed.

18. The semiconductor processing system of claim 17, in, The SiGe:B layer is a first SiGe:B layer, and wherein the instructions further cause the controller to: depositing a silicon germanium (SiGe) layer onto a substrate; depositing a first SiGe:B layer onto the first SiGe layer; depositing a second SiGe:B layer onto the first SiGe:B layer; and A Si:B layer is deposited onto the second SiGe:B layer.

19. The semiconductor processing system of claim 17, in, The instructions also cause the controller to: flowing an etchant to the chamber means during deposition of at least one of the SiGe layer, the first SiGe:B layer, the second SiGe:B layer, and the Si:B layer; and During deposition of at least one of the SiGe layer, the first SiGe:B layer, the second SiGe:B layer, and the Si:B layer covering the silicon surface portion of the substrate, a dielectric surface portion of the substrate is etched.

20. A computer program product, include: A memory comprising a non-transitory machine-readable medium having instructions that cause a controller operably connected to the precursor delivery device to: placing a substrate in a chamber assembly connected to a precursor delivery assembly; depositing a boron-doped silicon germanium (SiGe:B) layer overlying the substrate; and A boron-doped silicon (Si:B) layer is deposited overlying the SiGe:B layer by: stopping the flow of the boron-containing precursor to the chamber assembly; reducing the flow of germanium-containing precursors to the chamber assembly; increasing the flow of a silicon-containing precursor to the chamber assembly; After increasing the flow of the silicon-containing precursor, stopping the flow of the germanium-containing precursor to the chamber apparatus; as well as After stopping the flow of the germanium-containing precursor to the chamber arrangement, the flow of the boron-containing precursor to the chamber arrangement is resumed.

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