Method for reducing gate source capacitance

Abstract

The invention provides a method for reducing gate-source capacitance. The method comprises the following steps: forming an epitaxial layer on a substrate in an epitaxial manner; forming a gate trench at the top of the epitaxial layer, and forming a first gate dielectric layer and a first polycrystalline silicon gate formed on the first gate dielectric layer at the bottom of the gate trench; an isolation layer is formed on the first polycrystalline silicon gate and the first gate dielectric layer; a second gate dielectric layer is formed on the side wall of the residual gate trench and the epitaxial layer; forming a second polycrystalline silicon gate filling the residual gate trench, and grinding the second polycrystalline silicon gate to the second gate dielectric layer; and etching the second polycrystalline silicon gate back to enable the second trench gate to form a groove with the depth of 1000-2000 angstroms at the gate trench, judging whether the thickness of the second gate dielectric layer on the step at the top end of the gate trench is smaller than a target value or not, and if so, forming an etching protection layer on the epitaxial layer and the groove. According to a wafer level test, the input capacitance value of the process is reduced by about 10% compared with that of the process in the prior art.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for reducing gate-source capacitance. Background Art

[0002] like Figure 1 The dynamic parameter parasitic capacitance of the power device shown directly affects its switching performance, wherein the input capacitance (Ciss) is composed of gate-source capacitance (Cgs) and gate-drain capacitance (Cgd). The gate polysilicon groove in the prior art is usually formed to a depth of 300 to 800 angstroms, and the input capacitance needs to be further reduced.

[0003] In order to solve the above problems, a new method of reducing gate-source capacitance needs to be proposed. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for reducing gate-source capacitance, which is used to solve the problem that the gate polysilicon groove is usually formed to a depth of 300 to 800 angstroms in the prior art and the input capacitance needs to be further reduced.

[0005] To achieve the above object and other related objects, the present invention provides a method for reducing gate-source capacitance, comprising:

[0006] Step 1: epitaxially forming an epitaxial layer of a second conductivity type on a substrate of a first conductivity type;

[0007] Step 2: forming a gate trench on the top of the epitaxial layer, wherein the gate trench extends downward from the upper surface of the epitaxial layer through the area where the body region needs to be formed, and a first gate dielectric layer and a first polysilicon gate formed on the first gate dielectric layer are formed at the bottom of the gate trench; an isolation layer is formed on the first polysilicon gate and the first gate dielectric layer; and a second gate dielectric layer is formed on the remaining sidewalls of the gate trench and the epitaxial layer;

[0008] Step 3, forming a second polysilicon gate filling the remaining gate trench, and grinding the second polysilicon gate onto the second gate dielectric layer;

[0009] Step 4: etching back the second polysilicon gate so that the second trench gate forms a groove with a depth of 1000 to 2000 angstroms at the gate trench, and judging whether the thickness of the second gate dielectric layer on the step at the top of the gate trench is less than a target value, and if so, forming an etching protection layer on the epitaxial layer and the groove;

[0010] Step 5: forming a side wall at the side wall of the groove by a deposition and etching method, which serves as a masking layer for ion implantation;

[0011] Step six: forming a body region and a source region on the epitaxial layer by ion implantation, with the sidewalls serving as a masking layer for ion implantation, and then removing the sidewalls.

[0012] Preferably, the method for forming the gate trench in step 2 includes: forming a photoresist layer on the epitaxial layer; photolithographically opening the photoresist layer to define a formation area of ​​the gate trench; forming the gate trench on the epitaxial layer by an etching method; and removing the remaining photoresist layer.

[0013] Preferably, the material of the isolation layer in step 2 is silicon dioxide.

[0014] Preferably, the grinding method in step three is chemical mechanical planarization grinding.

[0015] Preferably, the back etching method in step 4 is dry etching, and the back etching time is 30 to 60 seconds.

[0016] Preferably, the preset value in step 4 is 450 angstroms.

[0017] Preferably, the material of the etching protection layer in step 4 is oxide.

[0018] Preferably, the thickness of the etching protection layer in step 4 is 100 to 500 angstroms.

[0019] Preferably, the material of the sidewall spacer in step five is silicon nitride.

[0020] Preferably, the deposition thickness of the silicon nitride in step five is 500 to 1500 angstroms.

[0021] Preferably, in step five, the silicon nitride is formed by low pressure chemical vapor deposition.

[0022] Preferably, the etching method in step five is anisotropic dry etching.

[0023] Preferably, in step six, the sidewalls are removed by wet etching.

[0024] Preferably, the method further includes step seven, forming an interlayer dielectric layer covering the epitaxial layer by deposition and grinding methods; forming a contact hole connected to the second polysilicon gate on the interlayer dielectric layer; and forming a metal layer filling the contact hole.

[0025] Preferably, the method is used for manufacturing a power device.

[0026] As described above, the method for reducing gate-source capacitance of the present invention has the following beneficial effects:

[0027] The input capacitance value of the process of the present invention is reduced by about 10% compared with the prior art process in wafer-level testing, and the mass production can be started after the client's sealing and testing data is received. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Shown is a schematic diagram of dynamic parameter parasitic capacitance of a power device in the prior art;

[0029] Figure 2 Shown is a schematic diagram of the process flow of the present invention;

[0030] Figure 3 It is a schematic diagram showing the formation of a second polysilicon gate according to the present invention;

[0031] Figure 4 It is a schematic diagram of grinding the second polysilicon gate of the present invention;

[0032] Figure 5 It is a schematic diagram showing the formation of grooves and etching of a protective layer according to the present invention;

[0033] Figure 6 Shown is a schematic diagram of the etching protection layer of the present invention;

[0034] Figure 7 Shown is a schematic diagram of the deposition of a sidewall material layer of the present invention;

[0035] Figure 8 Shown is a schematic diagram of forming a side wall of the present invention;

[0036] Fig. 9 Shown is a schematic diagram of forming a body region and a source region of the present invention;

[0037] Fig.10 It is a schematic diagram of removing the sidewall of the present invention. DETAILED DESCRIPTION

[0038] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0039] See also Figure 2 The present invention provides a method for reducing gate-source capacitance, comprising:

[0040] Step 1: epitaxially forming an epitaxial layer 101 of a second conductivity type on a substrate of a first conductivity type (not shown in the figure);

[0041] Step 2: forming a gate trench on the top of the epitaxial layer 101, the gate trench extending downward from the upper surface of the epitaxial layer 101 through the area of ​​the body region 102 to be formed, a first gate dielectric layer 103 and a first polysilicon gate 104 formed on the first gate dielectric layer 103 are formed at the bottom of the gate trench; an isolation layer 105 is formed on the first polysilicon gate 104 and the first gate dielectric layer 103; and a second gate dielectric layer 106 is formed on the sidewalls of the remaining gate trench and the epitaxial layer 101;

[0042] In some embodiments, the gate dielectric layer may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SION). It may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The gate dielectric layer may also include a high-k dielectric layer, which may include hafnium oxide (HfO2). Alternatively, the gate dielectric layer may include other high-k dielectrics, such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HMO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO), barium titanium oxide (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride 108 (Si3N4), nitride oxide (SiON), and combinations thereof.

[0043] In some embodiments, the method for forming the gate trench in step 2 includes: forming a photoresist layer on the epitaxial layer 101; opening the photoresist layer by photolithography to define a formation area of ​​the gate trench; forming the gate trench on the epitaxial layer 101 by etching; and removing the remaining photoresist layer.

[0044] In some embodiments, the material of the isolation layer 105 in step 2 is silicon dioxide.

[0045] Step 3: forming a second polysilicon gate 107 filling the remaining gate trench, forming Figure 3 The structure shown in FIG. 1 is formed by grinding the second polysilicon gate 107 onto the second gate dielectric layer 106 to form a Figure 4 The structure shown;

[0046] In some embodiments, the polishing method in step three is chemical mechanical planarization polishing.

[0047] Step 4: Etch back the second polysilicon gate 107 so that the second trench gate forms a groove with a depth of 1000 to 2000 angstroms at the gate trench, forming a Figure 5 In the structure shown, the groove depth in the prior art is 300-800 angstroms, that is, increasing the etching depth of the groove effectively shortens the channel length that affects the gate-source capacitance, thereby reducing the gate-source capacitance (Cgs). Optionally, the depth of the groove is 1000 angstroms, 1100 angstroms, 1200 angstroms, 1300 angstroms, 1400 angstroms, 1500 angstroms, 1600 angstroms, 1700 angstroms, 1800 angstroms, 1900 angstroms or 2000 angstroms. In order to prevent the subsequent wet removal of the sidewall 110 from over-etching to produce a sharp corner structure on the top sidewall of the step, it is determined whether the thickness of the second gate dielectric layer 106 on the step at the top of the gate trench is less than the target value. If so, an etching protection layer 108 is formed on the epitaxial layer 101 and the groove to form a structure such as Figure 6 The structure shown;

[0048] In some embodiments, the back etching method in step 4 is dry etching, and the back etching time is 30 to 60 seconds. The specific back etching time is determined by the required groove depth.

[0049] In some embodiments, the preset value in step 4 is 450 angstroms.

[0050] In some embodiments, the material of the etching protection layer 108 in step 4 is oxide, which can be formed by low pressure chemical vapor deposition.

[0051] In some embodiments, the thickness of the etching protection layer 108 in step 4 is 100 to 500 angstroms.

[0052] Step 5: Use deposition and etching methods to form a sidewall 110 located at the sidewall of the groove, which serves as a masking layer for ion implantation. That is, first deposit a sidewall material layer 109 to form a sidewall 110 as shown in FIG. Figure 7 The structure shown in FIG. 1 is then formed by etching the sidewall material layer 109 to form a sidewall 110. Figure 8 The structure shown;

[0053] In some embodiments, the material of the spacer 110 in step five is silicon nitride.

[0054] In some embodiments, the thickness of the silicon nitride deposited in step 5 is 500 to 1500 angstroms.

[0055] In some embodiments, in step five, silicon nitride is formed by low pressure chemical vapor deposition.

[0056] In some embodiments, the etching method in step five is anisotropic dry etching.

[0057] Step 6: Use ion implantation to form a body region 102 and a source region 111 on the epitaxial layer 101, and use the sidewall 110 as a masking layer for ion implantation to form a body region 102 and a source region 111 on the epitaxial layer 101. Fig. 9 The structure shown in FIG. 1 can prevent the channel leakage caused by the side of the groove when the source region 111 is injected. In order to prevent the sidewall 110 from affecting the subsequent contact hole overlay range, the sidewall 110 is removed to form a Fig.10 The structure shown does not affect the final structure of the device.

[0058] In some embodiments, in step six, the sidewall spacer 110 is removed by wet etching, for example, using H 3 PO 4 solution.

[0059] In some embodiments, the method further includes step seven, forming an interlayer dielectric layer covering the epitaxial layer 101 by deposition and grinding; forming a contact hole connected to the second polysilicon gate 107 on the interlayer dielectric layer; and forming a metal layer filling the contact hole.

[0060] In some embodiments, the method is used in the manufacture of a power device.

[0061] The input capacitance value of the process of the present invention is reduced by about 10% compared with the prior art process in wafer-level testing, and the mass production can be started after the client's sealing and testing data is received.

[0062] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0063] In summary, the input capacitance value of the wafer-level test process of the present invention is about 10% lower than that of the prior art process, and the mass production state can be entered after the client seals and tests the data. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0064] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for reducing gate-source capacitance, characterized in that: At least: Step 1: epitaxially forming an epitaxial layer of a second conductivity type on a substrate of a first conductivity type; Step 2: forming a gate trench on the top of the epitaxial layer, wherein the gate trench extends downward from the upper surface of the epitaxial layer through the area where the body region needs to be formed, and a first gate dielectric layer and a first polysilicon gate formed on the first gate dielectric layer are formed at the bottom of the gate trench; an isolation layer is formed on the first polysilicon gate and the first gate dielectric layer; and a second gate dielectric layer is formed on the remaining sidewalls of the gate trench and the epitaxial layer; Step 3, forming a second polysilicon gate filling the remaining gate trench, and grinding the second polysilicon gate onto the second gate dielectric layer; Step 4: etching back the second polysilicon gate so that the second trench gate forms a groove with a depth of 1000 to 2000 angstroms at the gate trench, and judging whether the thickness of the second gate dielectric layer on the step at the top of the gate trench is less than a target value, and if so, forming an etching protection layer on the epitaxial layer and the groove; Step 5: forming a side wall at the side wall of the groove by a deposition and etching method, which serves as a masking layer for ion implantation; Step six: forming a body region and a source region on the epitaxial layer by ion implantation, with the sidewalls serving as a masking layer for ion implantation, and then removing the sidewalls.

2. The method for reducing gate-source capacitance according to claim 1, characterized in that: The method for forming the gate trench in step 2 includes: forming a photoresist layer on the epitaxial layer; opening the photoresist layer by photolithography to define a formation area of ​​the gate trench; forming the gate trench on the epitaxial layer by etching; and removing the remaining photoresist layer.

3. The method for reducing gate-source capacitance according to claim 1, characterized in that: The material of the isolation layer in step 2 is silicon dioxide.

4. The method for reducing gate-source capacitance according to claim 1, characterized in that: The grinding method in step three is chemical mechanical planarization grinding.

5. The method for reducing gate-source capacitance according to claim 1, characterized in that: The back etching method in step 4 is dry etching, and the back etching time is 30 to 60 seconds.

6. The method for reducing gate-source capacitance according to claim 1, characterized in that: The preset value in step 4 is 450 angstroms.

7. The method for reducing gate-source capacitance according to claim 1, characterized in that: The material of the etching protection layer in step 4 is oxide.

8. The method for reducing gate-source capacitance according to claim 1, characterized in that: The thickness of the etching protection layer in step 4 is 100 to 500 angstroms.

9. The method for reducing gate-source capacitance according to claim 1, characterized in that: The material of the sidewall in step five is silicon nitride.

10. The method for reducing gate-source capacitance according to claim 9, characterized in that: The deposition thickness of silicon nitride in step 5 is 500 to 1500 angstroms.

11. The method for reducing gate-source capacitance according to claim 9, characterized in that: In step five, the silicon nitride is formed by low pressure chemical vapor deposition.

12. The method for reducing gate-source capacitance according to claim 1, characterized in that: The etching method in step five is anisotropic dry etching.

13. The method for reducing gate-source capacitance according to claim 1, characterized in that: In step six, the sidewalls are removed by wet etching.

14. The method for reducing gate-source capacitance according to claim 1, characterized in that: The method also includes step seven, forming an interlayer dielectric layer covering the epitaxial layer by deposition and grinding; forming a contact hole connected to the second polysilicon gate on the interlayer dielectric layer; and forming a metal layer filling the contact hole.

15. The method for reducing gate-source capacitance according to claim 1, characterized in that: The method is used for manufacturing a power device.

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