Semiconductor Structure and Method of Forming the Same

Abstract

The present invention provides a semiconductor structure and a method for forming the same. The forming method includes: providing a substrate with a drift region therein; forming a gate structure covering a part of the drift region; forming a first body region in the substrate, with a first spacer region between the first body region and the drift region and having a different doping type from that of the drift region; forming a first inversion region in the drift region, at least a part of the first inversion region being covered by the gate structure and having a different doping type from that of the drift region; annealing the semiconductor structure to cause the first body region to diffuse into the first spacer region to obtain a second body region, the second body region being adjacent to the drift region, and the doping concentration of the second body region under the gate structure gradually decreasing in the direction adjacent to the drift region; and obtaining a second inversion region based on the first inversion region, at least a part of the second inversion region being covered by the gate structure, and the doping type of the second inversion region being the same as that of the first inversion region. By adopting the above technical solution, the breakdown voltage of the semiconductor structure can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] A voltage-controlled power device refers to an electronic device that can control its working state and output characteristics according to a voltage signal, and they are widely used in fields such as industrial control, power electronics, and power supply systems.

[0003] How to design a voltage-controlled power device is a problem worthy of discussion. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a semiconductor structure and a method for forming the same, which can improve the breakdown voltage of the semiconductor structure.

[0005] To solve the above technical problems, embodiments of the present invention provide a method for forming a semiconductor structure. The method for forming a semiconductor structure includes:

[0006] Providing a substrate having a drift region therein;

[0007] Forming a gate structure on the substrate, the gate structure covering a part of the drift region;

[0008] Forming a first body region in the substrate, there is a first spacer region between the first body region and the drift region, and the doping types of the first body region and the drift region are different;

[0009] Forming a first inversion region in the drift region, at least a part of the first inversion region is covered by the gate structure, and the doping types of the first inversion region and the drift region are different;

[0010] Annealing the semiconductor structure so that the first body region diffuses into the first spacer region to obtain a second body region, wherein the second body region is adjacent to the drift region, and the doping concentration of the second body region under the gate structure gradually decreases along the direction adjacent to the drift region;

[0011] Obtaining a second inversion region based on the first inversion region, at least a part of the second inversion region is covered by the gate structure, wherein the doping type of the second inversion region is the same as that of the first inversion region.

[0012] Optionally, there is a second spacer region between the second inversion region and the gate structure.

[0013] Optionally, the semiconductor structure is an LDMOS device;

[0014] Wherein, the depth of the bottom surface of the second inversion region is less than or equal to the depth of the bottom surface of the second body region.

[0015] Optionally, the gate structure includes a gate dielectric layer, a field dielectric layer, and a gate body. The field dielectric layer covers the drift region, the gate dielectric layer is adjacent to the field dielectric layer and covers the substrate adjacent to the drift region; the gate body covers the gate dielectric layer and the field dielectric layer;

[0016] Form a first body region, including:

[0017] Ion implant the substrate adjacent to the first spacer region to obtain the first body region, where this side is the side of the first spacer region away from the drift region.

[0018] Optionally, ion implanting the substrate adjacent to the first spacer region includes:

[0019] Form a patterned mask layer that exposes the substrate adjacent to the first spacer region, where this side is the side of the first spacer region away from the drift region;

[0020] Using the patterned mask layer as a mask, ion implant the substrate adjacent to the first spacer region to obtain the first body region.

[0021] Optionally, the gate body covers a part of the field dielectric layer adjacent to the gate dielectric layer and exposes another part of the field dielectric layer away from the gate dielectric layer.

[0022] Optionally, forming a first inversion region in the drift region includes:

[0023] Ion implant the substrate to obtain a first inversion region in the drift region not covered by the gate body.

[0024] Optionally, the thickness of the gate body is greater than or equal to 100 nanometers.

[0025] Optionally, the forming method further includes:

[0026] Form a drain region in the drift region not covered by the field dielectric layer;

[0027] Form a source region in the second body region not covered by the gate dielectric layer.

[0028] Optionally, obtaining a second inversion region based on the first inversion region includes:

[0029] During the process of forming the drain region, the first inversion region covered by the drain region is secondarily inverted, and the first inversion region covered by the field dielectric layer forms a second inversion region.

[0030] Optionally, the thickness of the field dielectric layer is greater than or equal to 100 nanometers.

[0031] To solve the above technical problems, an embodiment of the present invention provides a semiconductor structure. The semiconductor structure includes:

[0032] A substrate having a drift region therein;

[0033] A gate structure covering a part of the drift region;

[0034] A second body region adjacent to the drift region, and the doping concentration of the second body region under the gate structure gradually decreases in a direction adjacent to the drift region;

[0035] A second inversion region located in the drift region, at least a part of the second inversion region being covered by the gate structure, and the doping type of the second inversion region is different from that of the drift region.

[0036] Optionally, there is a second spacer region between the second inversion region and the gate structure.

[0037] Optionally, the semiconductor structure is an LDMOS device;

[0038] Wherein, the depth of the bottom surface of the second inversion region is less than or equal to the depth of the bottom surface of the second body region.

[0039] Optionally, the gate structure includes a gate dielectric layer, a field dielectric layer, and a gate body. Among them, the field dielectric layer covers the drift region, the gate dielectric layer is adjacent to the field dielectric layer and covers the substrate adjacent to the drift region; the gate body covers the gate dielectric layer and the field dielectric layer.

[0040] Optionally, the gate body covers a part of the field dielectric layer adjacent to the gate dielectric layer and exposes another part of the field dielectric layer away from the gate dielectric layer.

[0041] Optionally, the second inversion region is located in the drift region not covered by the gate body.

[0042] Optionally, the thickness of the gate body is greater than or equal to 100 nanometers.

[0043] Optionally, the semiconductor structure further includes:

[0044] A drain region located in the drift region not covered by the field dielectric layer;

[0045] A source region located in the second body region not covered by the gate dielectric layer.

[0046] Optionally, the thickness of the field dielectric layer is greater than or equal to 100 nanometers.

[0047] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0048] In the semiconductor formation method provided by the embodiment of the present invention, the doping concentration of the second body region below the gate structure gradually decreases along the direction adjacent to the drift region, which can reduce the doping concentration of the second body region adjacent to the drift region, thereby increasing the width of the depletion region in the second body region and improving the breakdown voltage of the semiconductor structure; the second inversion region is in the drift region and has a different doping type from the drift region, so the second inversion region forms a PN junction with the drift region in the drift region, and the second inversion region can assist in depleting the drift region, so that the depletion region can be fully widened without reducing the doping concentration of the drift region, which means that the second inversion region can further improve the breakdown voltage of the semiconductor structure without reducing the doping concentration of the drift region.

[0049] Furthermore, the first inversion region is in the drift region and has a different doping type from the drift region, so the first inversion region forms a PN junction with the drift region in the drift region, and the first inversion region can assist in depleting the drift region, so that the depletion region can be fully widened without reducing the doping concentration of the drift region, which means that the first inversion region can improve the breakdown voltage of the semiconductor structure without reducing the doping concentration of the drift region.

[0050] Furthermore, during the ion implantation process of the substrate after removing the patterned mask layer, by setting the thickness of the gate body, a suitable ion implantation intensity is selected, and the gate body can prevent ions from being implanted into the substrate below the gate body, so that the first inversion region is formed in the drift region exposed by the gate body; that is to say, before forming the first inversion region, there is no need to form a new patterned mask layer above the gate body to prevent ions from being implanted into the substrate below the gate body. Therefore, the manufacturing cost of the semiconductor structure can be reduced.

[0051] Furthermore, there is a second spacer region between the first inversion region and the field dielectric layer, and the conduction path of the semiconductor structure in the drift region passes through the second spacer region. Compared with the case where the first inversion region is adjacent to the field dielectric layer, the conduction path of the semiconductor structure in the drift region passes below the first inversion region, and the former conduction path is shorter and the conduction resistance is smaller.

[0052] Furthermore, the first inversion region exposed by the field dielectric layer and covered by the drain region is secondarily inverted, and the remaining first inversion region covered by the field dielectric layer forms the second inversion region. The second spacer region between the second inversion region and the field dielectric layer is the second spacer region between the remaining first inversion region covered by the field dielectric layer and the field dielectric layer.

[0053] Furthermore, the depth of the bottom surface of the second inversion region is less than or equal to the depth of the bottom surface of the second body region, which can make the region where the second inversion region assists in depletion in the drift region be on one side of the second body region, thereby improving the breakdown voltage of the semiconductor structure along the direction parallel to the substrate surface. Description of the Drawings

[0054] To more clearly illustrate the technical solutions of the embodiments of this specification, the following will briefly introduce the drawings required for describing the embodiments of this specification or the prior art. Obviously, the following described drawings are only some embodiments of this specification. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0055] Figure 1 is a flowchart of a method for forming a semiconductor structure in an embodiment of the present invention;

[0056] Figures 2 to 5 is a schematic cross-sectional structure diagram corresponding to each step in a method for forming a semiconductor structure in an embodiment of the present invention.

[0057] Description of reference numerals:

[0058] Substrate 100, drift region 110, first body region 120, second body region 121, first inversion region 130, second inversion region 131, source region 140, drain region 150, extraction region 160, first spacer region 101, second spacer region 102, isolation ring 200, gate structure 300, gate dielectric layer 310, field dielectric layer 320, gate body 330, mask layer 400. Detailed implementation manners

[0059] As can be seen from the background technology, how to design a voltage-controlled power device is a problem worthy of discussion.

[0060] Taking LDMOS as an example, LDMOS has a drift region and a body region, and a depletion region is formed at the junction of the drift region and the body region.

[0061] In a specific application scenario, in order to obtain a high-voltage-resistant LDMOS device, it is necessary to reduce the doping concentration of the drift region so that the depletion region is fully widened, which will increase the on-resistance of the LDMOS device.

[0062] In another specific application scenario, in order to obtain a low-resistance LDMOS device, it is necessary to increase the doping concentration of the device, which will prevent the depletion layer of the drift region from widening and reduce the breakdown voltage of the LDMOS device.

[0063] To solve the above technical problems, in the embodiments of the present invention, the doping concentration of the second body region below the gate structure gradually decreases along the direction adjacent to the drift region, which can reduce the doping concentration of the second body region adjacent to the drift region, thereby increasing the width of the depletion region in the second body region and improving the breakdown voltage of the semiconductor structure; the second inversion region is within the drift region and has a different doping type from the drift region, so the second inversion region forms a PN junction with the drift region within the drift region, and the second inversion region can assist in depleting the drift region, thereby enabling the depletion region to be fully widened without reducing the doping concentration of the drift region. That is to say, the second inversion region can further improve the breakdown voltage of the semiconductor structure without reducing the doping concentration of the drift region.

[0064] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description will be given to the specific embodiments of the present invention with reference to the accompanying drawings.

[0065] Refer to Figure 1 , Figure 1 which shows a flowchart of a method for forming a semiconductor structure in an embodiment of the present invention. The method for forming the semiconductor structure may include steps S11 to S16:

[0066] Step S11: Provide a substrate with a drift region therein;

[0067] Step S12: Form a gate structure on the substrate, and the gate structure covers a part of the drift region;

[0068] Step S13: Form a first body region in the substrate, with a first spacer region between the first body region and the drift region, and the first body region and the drift region have different doping types;

[0069] Step S14: Form a first inversion region in the drift region, at least a part of the first inversion region is covered by the gate structure, and the first inversion region and the drift region have different doping types;

[0070] Step S15: Anneal the semiconductor structure to make the first body region diffuse into the first spacer region to obtain a second body region, wherein the second body region is adjacent to the drift region, and the doping concentration of the second body region below the gate structure gradually decreases along the direction adjacent to the drift region;

[0071] Step S16: Obtain a second inversion region based on the first inversion region, at least a part of the second inversion region is covered by the gate structure, wherein the doping type of the second inversion region is the same as that of the first inversion region.

[0072] The following will be combined with Figures 2 to 5 to explain the above formation method.

[0073] Figures 2 to 5It is a schematic cross-sectional structure diagram corresponding to each step in a method for forming a semiconductor structure in an embodiment of the present invention.

[0074] Referring to Figure 2 , a substrate 100 is provided;

[0075] Specifically, the substrate 100 is used to provide a process platform for the subsequent formation of the semiconductor structure.

[0076] In some embodiments, the substrate 100 may be a silicon substrate, or the material of the substrate 100 may further include germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide. The substrate 100 may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or a substrate with an epitaxial layer grown thereon.

[0077] In some embodiments, the doping type of the substrate 100 may be P-type doping or N-type doping.

[0078] It should be noted that in the following description, P-type doping may be used as an example for illustration, but it does not limit the specific doping type adopted by the substrate 100.

[0079] Continuing to refer to Figure 2 , an isolation ring 200 is formed on the substrate 100.

[0080] Specifically, the steps of forming the isolation ring 200 may include: etching the surface of the substrate 100 to obtain an isolation ring groove (not shown); filling the isolation ring groove to obtain the isolation ring 200.

[0081] Specifically, the isolation ring 200 is a ring-shaped structure that can achieve electrical isolation between the inside and outside of the ring.

[0082] In some embodiments, the material of the isolation ring 200 may be silicon dioxide.

[0083] Continuing to refer to Figure 2 , a drift region 110 is formed in the substrate 100.

[0084] In some embodiments, the drift region 110 may be formed in the isolation ring groove by an ion implantation process.

[0085] In some embodiments, the doping type of the drift region 110 may be N-type doping or P-type doping.

[0086] It should be noted that in the following description, N-type trench doping may be used as an example for illustration, but it does not limit the specific doping type adopted by the drift region 110.

[0087] Continuing to refer to Figure 2 , a gate structure 300 is formed on the substrate 100.

[0088] Specifically, the steps of forming the gate structure 300 may include: forming a gate dielectric layer 310 and a field dielectric layer 320 of the gate structure 300 on the substrate 100; and forming a gate body 330 of the gate structure 300 on the gate dielectric layer 310 and the field dielectric layer 320.

[0089] Among them, the field dielectric layer 320 covers the drift region 110, the gate dielectric layer 310 is adjacent to the field dielectric layer 320, and covers the substrate 100 adjacent to the drift region 110.

[0090] It should be noted that reducing the thickness of the gate dielectric layer 310 can improve the control ability of the gate body 330 over the conducting channel, where the conducting channel is formed in the substrate 100 covered by the gate dielectric layer 310; increasing the thickness of the field dielectric layer 320 can improve its ability to block ion implantation.

[0091] In some embodiments, the thickness of the gate dielectric layer 310 is less than that of the field dielectric layer 320.

[0092] Continue to refer to Figure 2 , and form a patterned mask layer 400.

[0093] Among them, the patterned mask layer 400 covers the gate structure 300 and the exposed drift region 110 of the gate structure 300, and exposes the substrate 100 adjacent to the gate dielectric layer 310, and this adjacent side is the side of the gate dielectric layer 310 far from the field dielectric layer 320.

[0094] Refer to Figure 3 , and form a first body region 120 in the substrate 100.

[0095] Among them, the doping type of the first body region 120 is different from that of the drift region 110.

[0096] Specifically, ion implantation is performed on the substrate 100 to obtain the first body region 120 in the substrate 100 adjacent to the gate dielectric layer 310, and this adjacent side is the side of the gate dielectric layer 310 far from the field dielectric layer 320.

[0097] Specifically, during the process of forming the first body region 120, the patterned mask layer 400 can prevent ion implantation into the substrate 100 under the mask layer 400, so that the first body region 120 is formed in the substrate 100 adjacent to the gate dielectric layer 310.

[0098] In some embodiments, there is a first spacer region 101 between the first body region 120 and the drift region 110. The first spacer region 101 belongs to the substrate 100 and is located under the gate dielectric layer 310.

[0099] Refer to Figure 4 , and form a first inversion region 130.

[0100] Specifically, the step of forming the first inversion region 130 may include: removing the patterned mask layer 400; performing ion implantation on the substrate 100 to obtain the first inversion region 130 in the drift region 110 exposed by the gate body 330.

[0101] Wherein, the doping type of the first inversion region 130 is different from that of the drift region 110.

[0102] Specifically, since the first inversion region 130 is within the drift region 110 and has a different doping type from the drift region 110, a PN junction is formed between the first inversion region 130 and the drift region 110 within the drift region 110. The first inversion region 130 can assist in depleting the drift region 110, so that the depletion region can be fully widened without reducing the doping concentration of the drift region 110. That is to say, the first inversion region 130 can increase the breakdown voltage of the semiconductor structure without reducing the doping concentration of the drift region 110.

[0103] In some embodiments, the gate body 330 covers a part of the field dielectric layer 320 adjacent to the gate dielectric layer 310 and exposes another part of the field dielectric layer 320 away from the gate dielectric layer 310.

[0104] Specifically, during the ion implantation process of the substrate 100 after removing the patterned mask layer 400, by setting the thickness of the gate body 330 and selecting an appropriate ion implantation intensity, the gate body 330 can prevent ions from being implanted into the substrate 100 below the gate body 330, so that the first inversion region 130 is formed in the drift region 110 exposed by the gate body 330. That is to say, before forming the first inversion region 130, there is no need to form a new patterned mask layer 400 above the gate body 330 to prevent ions from being implanted into the substrate 100 below the gate body 330. Therefore, the manufacturing cost of the semiconductor structure can be reduced.

[0105] In some embodiments, the thickness of the gate body 330 may be greater than or equal to 100 nanometers.

[0106] It should be noted that the thickness referred to herein is the dimension in the direction perpendicular to the surface of the substrate 100.

[0107] In some embodiments, during the process of performing ion implantation on the substrate 100 to obtain the first inversion region 130, the doping concentration of the first body region 120 increases.

[0108] Specifically, before and after removing the patterned mask layer 400, the same type of ion implantation is performed on the substrate 100 corresponding to the first body region 120, so that the doping concentration of the first body region 120 increases.

[0109] In some embodiments, at least a portion of the first inversion region 130 is covered by the field dielectric layer 320.

[0110] In some embodiments, the first inversion region 130 is adjacent to the field dielectric layer 320.

[0111] In some embodiments, there is a second spacer region 102 between the first inversion region 130 and the field dielectric layer 320, and the second spacer region 102 belongs to the drift region 110.

[0112] Specifically, there is a second spacer region 102 between the first inversion region 130 and the field dielectric layer 320, and the conduction path of the semiconductor structure within the drift region 110 passes through the second spacer region 102. Compared with the case where the first inversion region 130 is adjacent to the field dielectric layer 320, the conduction path (such as Figure 5 the path represented by the arrow shown in) passes under the first inversion region 130, and the former conduction path is shorter and the conduction resistance is smaller.

[0113] Referring to Figure 5 , the second body region 121 is formed.

[0114] Specifically, the step of forming the second body region 121 may include: annealing the semiconductor structure so that the first body region 120 diffuses into the first spacer region 101 to obtain the second body region 121, where the second body region 121 is adjacent to the drift region 110, and the doping concentration of the second body region 121 under the gate dielectric layer 310 gradually decreases along the direction adjacent to the drift region 110.

[0115] Specifically, this can reduce the doping concentration of the second body region 121 near the drift region 110, thereby increasing the width of the depletion region within the second body region 121 and further improving the breakdown voltage of the semiconductor structure.

[0116] Continuing to refer to Figure 5 , a source region 140 is formed within the second body region 121 exposed by the gate structure 300; a drain region 150 is formed within the drift region 110 exposed by the gate structure 300.

[0117] Among them, the doping type of the source region 140 is different from that of the body region, the doping type of the drain region 150 is the same as that of the source region 140, and the doping concentration of the drain region 150 is higher than that of the drift region 110.

[0118] In some embodiments, the source region 140 and the drain region 150 can have various formation sequences. For example, during the formation of the source region 140, the drain region 150 is formed. For example, the source region 140 can be formed after the drain region 150. For example, the source region 140 can be formed before the drain region 150.

[0119] In some embodiments, during the process of forming the drain region 150, the first inversion region 130 covered by the drain region 150 is inverted a second time, and the first inversion region 130 covered by the field dielectric layer 320 forms a second inversion region 131.

[0120] Specifically, the exposed field dielectric layer 320 and the first inversion region 130 covered by the drain region 150 are inverted a second time, and the remaining first inversion region 130 covered by the field dielectric layer 320 forms the second inversion region 131. The second spacer region 102 between the second inversion region 131 and the field dielectric layer 320 is the second spacer region 102 between the remaining first inversion region 130 covered by the field dielectric layer 320 and the field dielectric layer 320.

[0121] It should be noted that the second inversion region 131 is within the drift region 110 and has a doping type different from that of the drift region 110. Then, a PN junction is formed between the second inversion region 131 and the drift region 110 within the drift region 110. The second inversion region 131 can assist in depleting the drift region 110, so that the depletion region can be fully widened without reducing the doping concentration of the drift region 110. That is to say, the second inversion region 131 can increase the breakdown voltage of the semiconductor structure without reducing the doping concentration of the drift region 110.

[0122] In some embodiments, the depth of the top surface of the second inversion region 131 is greater than or equal to the depth of the bottom surface of the source region 140; and / or, the depth of the top surface of the second inversion region 131 is greater than or equal to the depth of the bottom surface of the drain region 150.

[0123] Specifically, this can increase the breakdown voltage of the semiconductor structure in the direction parallel to the surface of the substrate 100 while preventing the second spacer region 102 from being inverted.

[0124] In some embodiments, at least a part of the second inversion region 131 is covered by the field dielectric layer 320.

[0125] It should be noted that during the process of ion-implanting the second body region 121 to form the source region 140, by setting the thickness of the field dielectric layer 320 and selecting an appropriate ion implantation intensity, the field dielectric layer 320 can prevent ions from being implanted into the substrate 100 below the field dielectric layer 320, so that the first inversion region 130 under the field dielectric layer 320 will not be inverted during this round of ion implantation.

[0126] In some embodiments, the depth of the bottom surface of the second inversion region 131 is less than or equal to the depth of the bottom surface of the second body region 121.

[0127] Specifically, this can make the region where the second inversion region 131 assists in depleting within the drift region 110 be on one side of the second body region 121, thereby increasing the breakdown voltage of the semiconductor structure in the direction parallel to the surface of the substrate 100.

[0128] In some embodiments, the thickness of the field dielectric layer 320 may be greater than or equal to 100 nanometers.

[0129] Continuing to refer to Figure 5 , an extraction region 160 is formed within the source region 140.

[0130] Among them, the bottom surface of the extraction region 160 covers the second body region 121. The doping type of the extraction region 160 is the same as that of the second body region 121, and the doping concentration is higher than that of the second body region 121.

[0131] Specifically, the extraction region 160 can extract the charges accumulated in the second body region 121, thereby reducing the potential fluctuation of the second body region 121.

[0132] In some embodiments, the semiconductor structure may be an LDMOS device. The LDMOS device includes semiconductor cells. Among them, the semiconductor cells may include a drift region 110, a second body region 121, a source region 140, a drain region 150, an extraction region 160, a second inversion region 131, and a gate structure 300.

[0133] Furthermore, the semiconductor structure may be a symmetric LDMOS device. The symmetric LDMOS device includes two symmetric semiconductor cells. The two symmetric semiconductor cells share the same second body region 121, source region 140, and extraction region 160.

[0134] Specifically, sharing the same second body region 121, source region 140, and extraction region 160 can improve the current driving ability of the LDMOS device, and at the same time can simplify the layout and improve the device integration.

[0135] It should be noted that except for the shared second body region 121, source region 140, and extraction region 160, each semiconductor cell in the symmetric LDMOS device may have its own drift region 110, drain region 150, and second inversion region 131, and the above-mentioned respective parts may be completely the same or may not be completely the same.

[0136] Furthermore, the semiconductor cells may be located within the region surrounded by the isolation ring 200.

[0137] As shown, the two symmetric semiconductor cells may be located within the region surrounded by the same isolation ring 200.

[0138] Specifically, the isolation ring 200 is arranged around the semiconductor cells, which can achieve electrical isolation between the semiconductor cells of adjacent semiconductor structures. More specifically, the isolation between semiconductor structures can be achieved through the isolation ring 200, and it does not affect the electrical conduction between the two semiconductor cells within the same semiconductor structure.

[0139] In an embodiment of the present invention, a semiconductor structure may also be provided. With reference to Figures 2 to 5 , the semiconductor structure includes: a substrate 100 having a drift region 110 therein; a gate structure 300 covering a part of the drift region 110; a second body region 121 adjacent to the drift region 110, and the doping concentration of the second body region 121 below the gate structure 300 gradually decreases in a direction adjacent to the drift region 110; a second inversion region 131 located in the drift region 110, at least a part of the second inversion region 131 is covered by the gate structure 300, and the doping type of the second inversion region 131 is different from that of the drift region 110.

[0140] In some embodiments, a second spacer region 102 may be provided between the second inversion region 131 and the gate structure 300.

[0141] In some embodiments, the depth of the bottom surface of the second inversion region 131 may be less than or equal to the depth of the bottom surface of the second body region 121.

[0142] In some embodiments, the gate structure 300 may include a gate dielectric layer 310, a field dielectric layer 320, and a gate body 330. Among them, the field dielectric layer 320 covers the drift region 110, the gate dielectric layer 310 is adjacent to the field dielectric layer 320 and covers the substrate 100 adjacent to the drift region 110; the gate body 330 covers the gate dielectric layer 310 and the field dielectric layer 320.

[0143] In some embodiments, the gate body 330 covers a part of the field dielectric layer 320 adjacent to the gate dielectric layer 310 and exposes another part of the field dielectric layer 320 away from the gate dielectric layer 310.

[0144] In some embodiments, the second inversion region 131 is located in the drift region 110 not covered by the gate body 330.

[0145] In some embodiments, the thickness of the gate body 330 is greater than or equal to 100 nanometers.

[0146] In some embodiments, the semiconductor structure may further include: a drain region 150 located in the drift region 110 not covered by the field dielectric layer 320; a source region 140 located in the second body region 121 not covered by the gate dielectric layer 310.

[0147] In some embodiments, the thickness of the field dielectric layer 320 is greater than or equal to 100 nanometers.

[0148] In some embodiments, the semiconductor structure may further include an extraction region 160 located within the source region 140, where the bottom surface of the extraction region 160 covers the second body region 121. The extraction region 160 has the same doping type as the second body region 121 and a higher doping concentration than the second body region 121.

[0149] In some embodiments, the semiconductor structure may be an LDMOS device, and the LDMOS device includes semiconductor cells. Among them, the semiconductor cells may include a drift region 110, a second body region 121, a source region 140, a drain region 150, an extraction region 160, a second inversion region 131, and a gate structure 300.

[0150] Furthermore, the semiconductor structure may be a symmetric LDMOS device, and the symmetric LDMOS device includes two symmetric semiconductor cells that share the same second body region 121, source region 140, and extraction region 160.

[0151] Specifically, sharing the same second body region 121, source region 140, and extraction region 160 can improve the current driving ability of the LDMOS device, and at the same time, it can also simplify the layout and improve the device integration.

[0152] It should be noted that except for the shared second body region 121, source region 140, and extraction region 160, each semiconductor cell in the symmetric LDMOS device may have its own drift region 110, drain region 150, and second inversion region 131, and the above-mentioned respective parts may be completely the same or may not be completely the same.

[0153] In some embodiments, the semiconductor structure may further include an isolation ring 200, and the semiconductor cells may be located within the region surrounded by the isolation ring 200.

[0154] As shown in the figure, the two symmetric semiconductor cells may be located within the region surrounded by the same isolation ring 200.

[0155] Specifically, the isolation ring 200 is disposed around the semiconductor cells, which can achieve electrical isolation between the semiconductor cells of adjacent semiconductor structures. More specifically, the isolation between semiconductor structures can be achieved through the isolation ring 200 without affecting the electrical conduction between the two semiconductor cells within the same semiconductor structure.

[0156] It should be noted that the semiconductor structure in the embodiments of the present invention may be formed by the formation method described in the foregoing embodiments or may be formed by other formation methods. For the specific description of the semiconductor structure in the embodiments of the present invention, reference may be made to the corresponding description in the foregoing embodiments, and details are not described herein again.

[0157] It can be understood that the term "and / or" in this text is merely a description of the association relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. Additionally, the character " / " in this text indicates that the associated objects before and after are in an "or" relationship.

[0158] It can be understood that the "multiple" mentioned in this text refers to two or more. The descriptions such as the first and the second that appear in the embodiments of this application are only for illustration and to distinguish the described objects, without an order, nor do they represent a special limitation on the number of devices in the embodiments of this application, and cannot constitute any limitation on the embodiments of this application.

[0159] It can be understood that the above text describes multiple embodiment solutions provided by the embodiments of the present invention. Each optional manner introduced in each embodiment solution can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible embodiment solutions, and all of these can be considered as the embodiment solutions disclosed and made public by the present invention.

[0160] Although the embodiments of the present invention are disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate having a drift region therein; A gate structure is formed on the substrate, wherein the gate structure covers a portion of the drift region, wherein the gate structure comprises a gate dielectric layer, a field dielectric layer and a gate body, the field dielectric layer covers the drift region, the gate dielectric layer is adjacent to the field dielectric layer and covers the substrate adjacent to the drift region; the gate body covers the gate dielectric layer and a portion of the field dielectric layer; forming a first body region in the substrate, wherein a first spacing region is provided between the first body region and the drift region, and the first body region and the drift region have different doping types; Performing ion implantation on the substrate to form a first inversion region in the drift region and performing secondary doping on the first body region, wherein the previously formed gate body can prevent ions from being implanted into the substrate below the gate body, and a boundary of the first inversion region close to the first body region is determined, at least a portion of the first inversion region is located in the drift region covered by the field dielectric layer of the gate structure, and at least a portion of the first inversion region is located in the drift region exposed by the field dielectric layer of the gate structure, and the first inversion region and the drift region have different doping types; Annealing the semiconductor structure so that the first body region diffuses into the first spacing region to obtain a second body region, wherein the second body region is adjacent to the drift region, and the doping concentration of the second body region under the gate structure gradually decreases in a direction adjacent to the drift region; A second inversion region is obtained based on the first inversion region, at least a portion of the second inversion region is covered by the gate structure, wherein the doping type of the second inversion region is consistent with that of the first inversion region.

2. The forming method according to claim 1, characterized in that: A second spacing region is provided between the second inversion region and the gate structure.

3. The forming method according to claim 2, characterized in that: The semiconductor structure is an LDMOS device; The depth of the bottom surface of the second inversion region is less than or equal to the depth of the bottom surface of the second body region.

4. The forming method according to claim 1, characterized in that: Forming the first body region comprises: Ion implantation is performed on the substrate adjacent to the first spacing region to obtain the first body region, wherein the side is a side of the first spacing region away from the drift region.

5. The forming method according to claim 4, characterized in that: Performing ion implantation on the substrate adjacent to the first spacing region comprises: forming a patterned mask layer, wherein the patterned mask layer exposes the substrate adjacent to the first spacing region, wherein the side is a side of the first spacing region away from the drift region; Using the patterned mask layer as a mask, ion implantation is performed on the substrate adjacent to the first spacing region to obtain the first body region.

6. The forming method according to claim 4, characterized in that: The gate body covers a portion of the field dielectric layer adjacent to the gate dielectric layer and exposes another portion of the field dielectric layer away from the gate dielectric layer.

7. The forming method according to claim 6, characterized in that: The thickness of the gate body is greater than or equal to 100 nanometers.

8. The forming method according to claim 4, characterized in that: The method further comprises: forming a drain region in the drift region not covered by the field dielectric layer; A source region is formed in the second body region not covered by the gate dielectric layer.

9. The forming method according to claim 8, characterized in that: Obtaining a second inversion region based on the first inversion region comprises: In the process of forming the drain region, the first inversion region covered by the drain region is inverted twice, and the first inversion region covered by the field dielectric layer forms the second inversion region.

10. The forming method according to claim 8, characterized in that: The thickness of the field dielectric layer is greater than or equal to 100 nanometers.

11. A semiconductor structure, characterized in that: The semiconductor structure is formed by the forming method according to any one of claims 1 to 10, wherein the semiconductor structure comprises: a substrate having a drift region therein; A gate structure, wherein the gate structure covers a portion of the drift region, wherein the gate structure comprises a gate dielectric layer, a field dielectric layer and a gate body, the field dielectric layer covers the drift region, the gate dielectric layer is adjacent to the field dielectric layer and covers the substrate adjacent to the drift region; the gate body covers the gate dielectric layer and a portion of the field dielectric layer; a second body region, the second body region being adjacent to the drift region, and the doping concentration of the second body region below the gate structure gradually decreases along a direction adjacent to the drift region; A second inversion region, wherein the second inversion region is located in the drift region, a boundary of the second inversion layer close to the second body region is determined by the gate body, at least a portion of the second inversion region is located in the drift region covered by the field dielectric layer of the gate structure, and the second inversion region has a different doping type from that of the drift region.

12. The semiconductor structure according to claim 11, characterized in that: A second spacing region is provided between the second inversion region and the gate structure.

13. The semiconductor structure according to claim 12, characterized in that: The semiconductor structure is an LDMOS device; The depth of the bottom surface of the second inversion region is less than or equal to the depth of the bottom surface of the second body region.

14. The semiconductor structure according to claim 11, characterized in that: The gate body covers a portion of the field dielectric layer adjacent to the gate dielectric layer and exposes another portion of the field dielectric layer away from the gate dielectric layer.

15. The semiconductor structure according to claim 14, characterized in that: The thickness of the gate body is greater than or equal to 100 nanometers.

16. The semiconductor structure according to claim 11, characterized in that The semiconductor structure further comprises: a drain region, the drain region being located in a drift region not covered by the field dielectric layer; A source region is located in the second body region not covered by the gate dielectric layer.

17. The semiconductor structure according to claim 16, characterized in that: The thickness of the field dielectric layer is greater than or equal to 100 nanometers.

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