Methods for forming semiconductor structures

Abstract

A method for forming a semiconductor structure includes: providing a substrate; forming a sacrificial layer on the substrate, the thickness of which ranges from 500 angstroms to 5000 angstroms; forming a photoresist layer with a shallow trench isolation structure pattern on the sacrificial layer; using the photoresist layer as a mask, sequentially etching the sacrificial layer and the substrate to form shallow trenches within the sacrificial layer and the substrate; filling the shallow trenches with an insulating material; and etching away the sacrificial layer and part of the insulating material until the substrate surface is exposed, thus forming a shallow trench isolation structure. By forming a sacrificial layer on the substrate and etching the sacrificial layer and the substrate to form shallow trenches, the height of the shallow trenches is increased, allowing voids to form at the top of the shallow trenches. Subsequent etching removes the shallow trench isolation structure with voids at the top of the shallow trenches, ensuring the integrity of the shallow trench isolation structure and thereby improving the yield, reliability, and performance of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] In semiconductor manufacturing processes, shallow trench isolation (STI) is achieved by depositing, patterning, and etching silicon using a silicon nitride mask to form trenches, which are then filled with deposited oxides for isolation from silicon.

[0003] However, existing shallow trench isolation is prone to premature sealing during the filling process, which can lead to voids, resulting in low yield and low reliability of semiconductor devices and reducing their performance. Summary of the Invention

[0004] The technical problem solved by this invention is how to address the issues of reduced yield, reliability, and performance of semiconductor devices.

[0005] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate; forming a sacrificial layer on the substrate, the thickness of the sacrificial layer ranging from 500 angstroms to 5000 angstroms; forming a photoresist layer having a shallow trench isolation structure pattern on the sacrificial layer; using the photoresist layer as a mask, sequentially etching the sacrificial layer and the substrate to form shallow trenches within the sacrificial layer and the substrate; filling the shallow trenches with an insulating material; and etching away the sacrificial layer and part of the insulating material until the substrate surface is exposed, thereby forming a shallow trench isolation structure.

[0006] Optionally, the process for forming the sacrificial layer is a chemical vapor deposition process, wherein the parameters of the chemical vapor deposition process are: a deposition rate of 2000 angstroms per minute to 3000 angstroms per minute and a deposition time of 3 seconds to 10 seconds; or a deposition rate of 400 angstroms per minute to 600 angstroms per minute and a deposition time of 5 seconds to 10 seconds.

[0007] Optionally, the density of the sacrificial layer is in the range of 3.24 g / cm³. 3 Up to 3.26 g / cm 3 The stress range of the sacrificial layer is from 100 MPa to 500 MPa, and the coefficient of thermal expansion of the sacrificial layer is in the range of 2.8 × 10⁻⁶. -6 / ℃ to 3.1*10 -6 / ℃, the thickness of the sacrificial layer ranges from 500 angstroms to 5000 angstroms.

[0008] Optionally, the material of the sacrificial layer is one or more of the following: silicon oxide, APF film, silicon nitride, and tetraethyl orthosilicate oxide.

[0009] Optionally, the process for forming the shallow trench isolation structure in the shallow trench is: high-density plasma chemical vapor deposition process, wherein the parameters of the high-density plasma chemical vapor deposition process are a deposition rate of 2000 angstroms per minute to 3000 angstroms per minute and a deposition time of 3 seconds to 10 seconds.

[0010] Optionally, before the step of forming a sacrificial layer on the substrate, the method further includes forming an etch stop layer on the substrate.

[0011] Optionally, the etch stop layer may be a single layer or multiple layers stacked together, and the material of the etch stop layer may be one or more of silicon nitride, silicon oxide, and silicon carbon nitride.

[0012] Optionally, the step of forming a shallow trench includes: using the photoresist layer as a mask, etching the sacrificial layer and the stop layer until the substrate surface is exposed to form a first shallow trench; and continuing to use the photoresist layer as a mask to etch the substrate to form a shallow trench.

[0013] Optionally, the etching process for the sacrificial layer, the etch stop layer, and the substrate is a dry etching process. The process parameters for etching the sacrificial layer and the etch stop layer are as follows: the etching gas is one or more combinations of H2, CF4, CHF3, CH2F2, C4F8, and Ar; the gas flow rate is 30 sccm to 80 sccm; the source power is 800 W to 1200 W; the bias power is 100 W to 400 W; and the etching pressure is 10 mTor. The etching process parameters for etching the substrate are as follows: the etching gas is one or more combinations of H2, CF4, CHF3, CH2F2, C4F8 and Ar; the gas flow rate of the etching gas is 30 sccm to 80 sccm; the source power is 800 W to 1200 W; the bias power is 100 W to 400 W; the etching pressure is 10 mTorr to 50 mTorr; and the etching time is 30 to 70 seconds.

[0014] Optionally, the step of etching away the sacrificial layer and a portion of the insulating material includes: etching away the sacrificial layer and a portion of the insulating material to expose the etch stop layer; and etching away the etch stop layer to expose the substrate surface.

[0015] Optionally, the etching process for removing the sacrificial layer and part of the insulating material is one or a combination of dry etching and planarization processes. The process parameters for the dry etching process are as follows: the etching gas is one or a combination of H2, CF4, CHF3, CH2F2, C4F8 and Ar; the gas flow rate of the etching gas is 30 sccm to 80 sccm; the source power is 800 W to 1200 W; the bias power is 100 W to 400 W; the etching pressure is 10 mTorr to 50 mTorr; and the etching time is 30 seconds to 70 seconds.

[0016] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0017] This invention increases the height of the shallow trench by forming a sacrificial layer on the substrate and etching the sacrificial layer and the substrate to form shallow trenches. This increases the contact area during the subsequent deposition of shallow trench isolation structures, resulting in shallow trench isolation structures with good morphology. During the deposition of the shallow trench isolation structure, the filling gas reaches the bottom of the shallow trench slowly, meaning the filling rate at the bottom of the shallow trench is slow, while the filling rate at the top of the shallow trench is relatively fast. This makes it easier to seal the trench early, forming filling voids at the top of the shallow trench. These voids are then removed by etching at the top of the shallow trench, ensuring the integrity of the shallow trench isolation structure and thus improving the yield, reliability, and performance of semiconductor devices.

[0018] Furthermore, by forming an etching stop layer on the substrate, the present invention avoids etching damage to the substrate during subsequent etching of the sacrificial layer and part of the shallow trench isolation structure, thus ensuring the integrity of the substrate. Attached Figure Description

[0019] Figures 1 to 3 This is a schematic diagram of the formation process of a semiconductor structure in one embodiment;

[0020] Figures 4 to 10 This is a schematic diagram of the formation process of a semiconductor structure in one embodiment of the present invention;

[0021] Figure 11 This is a schematic diagram of a wafer scan of a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0022] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0023] Figures 1 to 3 This is a schematic diagram of the formation process of a semiconductor structure in one embodiment.

[0024] Regarding the current memory manufacturing process, please refer to... Figures 1 to 3 , Figure 1 This is a top view of the memory. Figure 2 yes Figure 1 Cross-sectional view along the AA1 direction. Figure 3 yes Figure 1 In the cross-sectional view along the BB1 ​​direction, due to process requirements, the active area 101 of the memory 100 needs to be made into a grid shape, and shallow trenches (not shown in the figure) are formed between adjacent active areas 101. An isolation structure 102 is formed in the shallow trenches. However, when forming the isolation structure 102, it is easier to form filling voids 103 when filling the shallow trenches in the middle part between adjacent active areas 101 compared to filling the shallow trenches at both ends between adjacent active areas 101. These voids will bring low yield and low reliability to the product, causing adjacent memory cells to interfere with each other when working, and causing the product to fail.

[0025] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure. A sacrificial layer is formed on the substrate to increase the height of the subsequently formed shallow trench. This increases the contact area of ​​the shallow trench surface during the deposition of the shallow trench isolation structure, resulting in a shallow trench isolation structure with a good morphology. Furthermore, the voids are formed at the top of the shallow trench. Subsequently, the void-containing shallow trench isolation structure at the top of the shallow trench is removed by etching, ensuring the integrity of the shallow trench isolation structure and thereby improving the yield, reliability, and performance of the semiconductor device.

[0026] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0027] Figures 4 to 10 This is a schematic diagram of the formation process of a semiconductor structure in one embodiment of the present invention.

[0028] Please refer to Figure 4 Substrate 200 is provided.

[0029] In this embodiment, the substrate 200 is made of silicon.

[0030] In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium; in other embodiments, the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0031] Please refer to Figure 5 A sacrificial layer 203 is formed on the substrate 200.

[0032] The process for forming the sacrificial layer 203 is a chemical vapor deposition process, wherein the parameters of the chemical vapor deposition process are: a deposition rate of 2000 angstroms per minute to 3000 angstroms per minute and a deposition time of 3 seconds to 10 seconds; or a deposition rate of 400 angstroms per minute to 600 angstroms per minute and a deposition time of 5 seconds to 10 seconds.

[0033] In this embodiment, the density range of the sacrificial layer 203 is 3.24 g / cm³. 3 Up to 3.26 g / cm 3 The stress range of the sacrificial layer 203 is from 100 MPa to 500 MPa, and the coefficient of thermal expansion of the sacrificial layer 203 is in the range of 2.8 × 10⁻⁶. -6 / ℃ to 3.1*10 -6 / ℃, the thickness of the sacrificial layer 203 ranges from 500 angstroms to 5000 angstroms.

[0034] Specifically, the thickness of the sacrificial layer 203 is 800 angstroms, 1000 angstroms, or 2000 angstroms.

[0035] In this embodiment, the thickness of the sacrificial layer 203 is selected through testing. Specifically, a set of experiments with different thicknesses of the sacrificial layer 203 is conducted, and then the number of voids under different thicknesses of the sacrificial layer 203 is counted by the fixed-point shooting API method, thereby determining the optimal thickness. For example, the number of voids is the least with a sacrificial layer thickness of 800 angstroms, that is, the sacrificial layer thickness of 800 angstroms is the optimal thickness.

[0036] In some embodiments, the material of the sacrificial layer 203 is one or more of silicon oxide, APF film, silicon nitride, and tetraethyl orthosilicate oxide.

[0037] As can be seen from the above, the sacrificial layer 203 has a low density, making it easy to remove in the future. The sacrificial layer 203 has a high coefficient of thermal expansion and low stress, which means it is a material with good thermal stability and high-temperature performance. Therefore, it can maintain the stability of the structure in high-temperature environments and avoid the wafer from warping or even fragmenting, thus ensuring the integrity of the wafer.

[0038] The increased thickness of the sacrificial layer 203 leads to an increased depth of the subsequently formed shallow trench 207. This increases the contact area during the deposition of the shallow trench isolation structure 2081 within the shallow trench 207, resulting in a well-formed shallow trench isolation structure. Furthermore, during the deposition of the shallow trench isolation structure, the filling gas reaches the bottom of the shallow trench 207 slowly (i.e., the filling rate at the bottom of the shallow trench 207 is slow), while the filling rate at the top of the shallow trench 207 is relatively faster. This makes it easier to seal the trench earlier, forming filling voids 209 at the top of the shallow trench 207. These voids 209 are then removed by etching, ensuring the integrity of the shallow trench isolation structure and thereby improving the yield, reliability, and performance of the semiconductor device.

[0039] In this embodiment, before forming the sacrificial layer 203, the method further includes: forming a protective layer 201 on the substrate 200; and forming an etch stop layer 202 on the surface of the protective layer 201.

[0040] In this embodiment, the material of the protective layer 201 is silicon oxide or silicon oxynitride.

[0041] In this embodiment, the thickness of the etching stop layer 202 ranges from 30 angstroms to 50 angstroms.

[0042] In some embodiments, the etching stop layer 202 is a single layer or multiple layers stacked together.

[0043] When the etch stop layer 202 is a single layer, the material of the etch stop layer 202 is silicon nitride.

[0044] When the etching stop layer 202 is a multilayer stack, the material of the etching stop layer 202 is one or a combination of silicon nitride, silicon oxide, and carbon-rich silicon nitride.

[0045] The etching stop layer 202 is used to protect the substrate 200 from damage during the subsequent removal of the sacrificial layer 203.

[0046] As can be seen, by forming an etch stop layer 202 on the substrate 200, the present invention avoids etching damage to the substrate 200 during subsequent etching of the sacrificial layer 203 and part of the shallow trench isolation structure, thus ensuring the integrity of the substrate 200.

[0047] Please refer to Figure 6 A photoresist layer 205 with an isolation structure pattern is formed on the sacrificial layer 203.

[0048] In this embodiment, before forming the photoresist layer 205, the method further includes: forming a hard mask layer 204 on the surface of the sacrificial layer 203; forming an initial photoresist layer (not shown in the figure) on the anti-reflection layer; and performing exposure and development treatment on the initial photoresist layer until the hard mask layer 204 is exposed to form the photoresist layer 205.

[0049] In this embodiment, the material of the hard mask layer 204 includes one or more combinations of TiN, SiN, and SiO2.

[0050] In this embodiment, after the photoresist layer 205 is formed, the hard mask layer 204, the sacrificial layer 203, the etch stop layer 202 and the protective layer 201 are etched sequentially using the photoresist layer 205 as a mask until the surface of the substrate 200 is exposed, forming a first shallow trench 206.

[0051] In this embodiment, the etching process for the hard mask layer 204, the sacrificial layer 203, the etch stop layer 202, and the protective layer 201 is a dry etching process. The process parameters for the dry etching process are as follows: the etching gas is one or more combinations of H2, CF4, CHF3, CH2F2, C4F8, and Ar; the gas flow rate of the etching gas is 30 sccm to 80 sccm; the source power is 800 W to 1200 W; the bias power is 100 W to 400 W; the etching pressure is 10 mTorr to 50 mTorr; and the etching time is 30 seconds to 70 seconds.

[0052] Please refer to Figure 7 Using the photoresist layer 205 as a mask, the substrate 200 is etched to form shallow trenches 207.

[0053] In this embodiment, an insulating layer 210 is formed on the surface of the substrate 200 and the surface of the protective layer 201 within the shallow trench 207.

[0054] The process for forming the insulating layer 210 is high-temperature furnace tube annealing, and the process parameters for the high-temperature furnace tube annealing are: annealing temperature of 1015 degrees Celsius and annealing time of 18 seconds.

[0055] In this embodiment, the etching process of the substrate 200 is a dry etching process. The process parameters of the dry etching process are as follows: the etching gas is one or more combinations of H2, CF4, CHF3, CH2F2, C4F8 and Ar; the gas flow rate of the etching gas is 30 sccm to 80 sccm; the source power is 800W to 1200W; the bias power is 100W to 400W; the etching pressure is 10 mTorr to 50 mTorr; and the etching time is 30 seconds to 70 seconds.

[0056] In the above scheme, since the etching rates of the hard mask layer 204, the sacrificial layer 203, the etch stop layer 202, and the protective layer 201 are close, and the etching selectivity ratio of the hard mask layer 204, the sacrificial layer 203, the etch stop layer 202, and the protective layer 201 to the substrate 200 is 3:1, the depth of the shallow trench 207 cannot be precisely controlled under the same etching process parameters. Therefore, the present invention forms the shallow trench 207 by two etching processes. Specifically, the first etching removes the hard mask layer 204, the sacrificial layer 203, the etch stop layer 202, and the protective layer 201, and the second etching removes part of the substrate 200, so that the depth of the shallow trench 207 can be precisely controlled.

[0057] Please refer to Figure 8 The shallow trench 207 is filled with insulating material to form an initial shallow trench isolation structure 208.

[0058] In this embodiment, the material of the initial shallow trench isolation structure 208 is silicon oxide.

[0059] Before filling with insulating material, the process also includes: removing the photoresist layer 205 and the hard mask layer 204 to expose the surface of the sacrificial layer 203.

[0060] In this embodiment, during the process of filling the shallow trench 207 with insulating material, a void 209 appears in the insulating material at the top of the shallow trench 207.

[0061] The process of filling the shallow trench 207 with insulating material is a high-density plasma chemical vapor deposition process, wherein the parameters of the high-density plasma chemical vapor deposition process are a deposition rate of 2000 angstroms per minute to 3000 angstroms per minute and a deposition time of 3 seconds to 10 seconds.

[0062] In the above scheme, since the void 209 appears in the sacrificial layer 203 at the top of the shallow trench 207, the void 209 is also removed during the subsequent removal of the sacrificial layer 203. This ensures that the shallow trench isolation structure 2081 at the bottom of the shallow trench 207 is relatively dense, avoids the appearance of the void 209, ensures the integrity of the shallow trench isolation structure 2081, and thus improves the yield, reliability and performance of semiconductor devices.

[0063] Please refer to Figure 9 The sacrificial layer 203 and part of the insulating material are etched away to expose the surface of the etch stop layer 202, forming a shallow trench isolation structure 2081.

[0064] The shallow trench isolation structure 2081 has a thickness ranging from 2000 angstroms to 4000 angstroms, and the height of the shallow trench isolation structure 2081 above the surface of the substrate 200 ranges from 0 angstroms to 80 angstroms.

[0065] In this embodiment, the etching process for removing the sacrificial layer 203 and part of the insulating material is one or a combination of dry etching and planarization processes. The process parameters of the dry etching process are as follows: the etching gas is one or a combination of H2, CF4, CHF3, CH2F2, C4F8 and Ar; the gas flow rate of the etching gas is 30 sccm to 80 sccm; the source power is 800 W to 1200 W; the bias power is 100 W to 400 W; the etching pressure is 10 mTorr to 50 mTorr; and the etching time is 30 seconds to 70 seconds.

[0066] In this embodiment, the planarization method includes mechanical polishing, chemical polishing, fluid polishing, and chemical mechanical polishing. Specifically, in this embodiment, the planarization method is chemical mechanical polishing. Unlike traditional purely mechanical or purely chemical polishing methods, chemical mechanical polishing, through the combined action of chemicals and machinery, avoids the surface damage caused by purely mechanical polishing and the drawbacks of purely chemical polishing, such as slow polishing speed, poor surface flatness, and poor polishing consistency. Chemical mechanical polishing is widely used for high planarization polishing of various materials at the nanoscale.

[0067] During the planarization process, the polishing rate ratio between the shallow trench isolation structure 2081 and the etch stop layer 202 is 2:1, meaning the polishing rate of the shallow trench isolation structure 2081 is greater than the polishing rate of the etch stop layer 202, resulting in... Figure 9 In this case, the top of the shallow trench isolation structure 2081 is lower than the top of the etch stop layer 202.

[0068] Please refer to Figure 10 The etching stop layer 202 is removed until the surface of the protective layer 201 is exposed.

[0069] In this embodiment, the etching process for removing the etching stop layer 202 is a dry etching process. The process parameters of the dry etching process are as follows: the etching gas is one or more combinations of H2, CF4, CHF3, CH2F2, C4F8 and Ar; the gas flow rate of the etching gas is 30 sccm to 80 sccm; the source power is 800W to 1200W; the bias power is 100W to 400W; the etching pressure is 10 mTorr to 50 mTorr; and the etching time is 30 seconds to 70 seconds.

[0070] Figure 11This is a schematic diagram of a wafer scan of a semiconductor structure according to an embodiment of the present invention.

[0071] Depend on Figure 11 As can be seen, when the shallow trench isolation structure 2081 is formed using the above scheme, after scanning the wafer, only one void 209 is found on the wafer, reducing the possibility of void 209 formation.

[0072] In summary, this invention increases the height of the shallow trench 207 by forming a sacrificial layer 203 on the substrate 200 and etching the sacrificial layer 203 and the substrate 200 to form a shallow trench 207. This increases the contact area during the subsequent deposition of the shallow trench isolation structure 2081 within the shallow trench 207, resulting in a shallow trench isolation structure 2081 with a good morphology. Furthermore, during the deposition of the shallow trench isolation structure 2081, the filling gas reaches the shallow trench 207. The bottom of the shallow trench 207 has a slow filling rate, while the top of the shallow trench 207 fills relatively faster than the bottom. This makes it easier to seal the trench earlier and form a filling cavity 209. The cavity 209 is formed at the top of the shallow trench 207. Subsequently, the shallow trench isolation structure 2081 with the cavity 209 at the top of the shallow trench 207 is removed by etching to ensure the integrity of the shallow trench isolation structure 2081, thereby improving the yield, reliability and performance of the semiconductor device.

[0073] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A sacrificial layer is formed on a substrate, the thickness of which ranges from 500 angstroms to 5000 angstroms, wherein, prior to the step of forming the sacrificial layer on the substrate, an etch stop layer is formed on the substrate; A photoresist layer with a shallow trench isolation structure pattern is formed on the sacrificial layer; Using the photoresist layer as a mask, the sacrificial layer, the etch stop layer, and the substrate are etched sequentially, forming shallow trenches in the sacrificial layer, the etch stop layer, and the substrate; The shallow trenches are filled with insulating material; The sacrificial layer and part of the insulating material are etched away to expose the surface of the etch stop layer, forming a shallow trench isolation structure.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for forming the sacrificial layer is chemical vapor deposition (CVD), and the parameters of the CVD process are: a deposition rate of 2000 Å to 3000 Å per minute and a deposition time of 3 to 10 seconds; or a deposition rate of 400 Å to 600 Å per minute and a deposition time of 5 to 10 seconds.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The density range of the sacrificial layer is 3.24 g / cm³. 3 Up to 3.26 g / cm 3 The stress range of the sacrificial layer is from 100 MPa to 500 MPa, and the coefficient of thermal expansion of the sacrificial layer is in the range of 2.8 × 10⁻⁶. -6 / ℃ to 3.1*10 -6 / ℃, the thickness of the sacrificial layer ranges from 500 angstroms to 5000 angstroms.

4. The method for forming a semiconductor structure as described in claim 2, characterized in that, The sacrificial layer is made of one or more of the following materials: silicon oxide, APF film, silicon nitride, and tetraethyl orthosilicate oxide.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for forming the shallow trench isolation structure in the shallow trench is a high-density plasma chemical vapor deposition process, wherein the parameters of the high-density plasma chemical vapor deposition process are: a deposition rate of 2000 angstroms per minute to 3000 angstroms per minute and a deposition time of 3 seconds to 10 seconds.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The etching stop layer is a single layer or multiple layers stacked together, and the material of the etching stop layer is one or more of silicon nitride, silicon oxide, and carbon-rich silicon nitride.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The steps to form a shallow trench include: Using the photoresist layer as a mask, the sacrificial layer and the etching stop layer are etched until the substrate surface is exposed, forming a first shallow trench; Using the photoresist layer as a mask, the substrate is etched to form shallow trenches.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The etching process for the sacrificial layer, the etch stop layer, and the substrate is a dry etching process. The process parameters for etching the sacrificial layer and the etch stop layer are as follows: the etching gas is one or more combinations of H2, CF4, CHF3, CH2F2, C4F8, and Ar; the gas flow rate of the etching gas is 30 sccm to 80 sccm; the source power is 800 W to 1200 W; the bias power is 100 W to 400 W; the etching pressure is 10 mTorr to 50 mTorr; and the etching time is 30 to 70 seconds. The process parameters for etching the substrate are as follows: the chamber pressure is 5 mT to 15 mT; the source power is 350 W to 1200 W; the bias voltage is 150 V to 600 V; the gas flow rate is 20 sccm to 200 sccm; and the etching time is 8 s to 60 s.

9. The method for forming a semiconductor structure as described in claim 7, characterized in that, The step of etching away the sacrificial layer and a portion of the insulating material includes: Etch away the sacrificial layer and part of the insulating material to expose the etch stop layer; The etching stop layer is removed until the substrate surface is exposed.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The etching process for removing the sacrificial layer and part of the insulating material is one or a combination of dry etching and planarization processes. The process parameters of the dry etching process are as follows: the etching gas is one or a combination of H2, CF4, CHF3, CH2F2, C4F8 and Ar; the gas flow rate of the etching gas is 30 sccm to 80 sccm; the source power is 800 W to 1200 W; the bias power is 100 W to 400 W; the etching pressure is 10 mTorr to 50 mTorr; and the etching time is 30 seconds to 70 seconds.

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