Through silicon via adapter plate, manufacturing method thereof, 2.5 D integrated module and manufacturing method thereof

Abstract

The invention discloses a through silicon via adapter plate and a manufacturing method thereof, and a 2.5 D integrated module and a manufacturing method thereof, and in the manufacturing method of the through silicon via adapter plate, a Si O2 layer of a slide is in contact with a through silicon via to form a Cu-SiO2 mixed bonding interface which is used for replacing temporary bonding, so that the difficulty of a back surface process of the through silicon via adapter plate is reduced. The method comprises the following steps: providing a bare wafer; forming a deep hole in the front surface of the bare wafer; forming a first insulating layer; filling metal copper in the deep hole to form a silicon through hole; providing a slide glass, wherein the slide glass comprises a SiO2 layer; enabling the S O < 2 > layer on the slide glass to be in contact with the silicon through hole to form a Cu-Si < 2 > mixed bonding interface; thinning the back surface of the bare wafer so that the bottom of the silicon through hole is exposed out of the back surface of the bare wafer; forming a second insulating layer; forming a multi-layer metal interconnection unit and a first bump unit; removing the slide glass; and forming a second salient point unit.

Description

Technical Field

[0001] The present invention relates to the technical field of TVS adapter boards, and in particular to a through silicon via adapter board and a manufacturing method thereof, and a 2.5D integrated module and a manufacturing method thereof. Background Art

[0002] 2.5D integrated modules have brought new development opportunities to the semiconductor industry by improving performance, reducing size, and enhancing flexibility.

[0003] However, the manufacturing difficulty of the silicon via adapter board of the 2.5D integrated module is relatively high, resulting in problems such as difficult process control, narrow process window and poor controllability.

[0004] Therefore, how to reduce the difficulty of manufacturing the through silicon via adapter plate has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0005] The present application provides a through silicon via adapter plate and a manufacturing method thereof, a 2.5D integrated module and a manufacturing method thereof. In the manufacturing method of the through silicon via adapter plate, the SiO2 layer of the carrier is in contact with the through silicon via to form a Cu-SiO2 mixed bonding interface, which is used to replace temporary bonding, thereby reducing the difficulty of the back side process of the through silicon via adapter plate.

[0006] According to a first aspect of the present invention, a method for manufacturing a through silicon via adapter plate is provided, comprising:

[0007] Providing a bare wafer;

[0008] forming a deep hole on the front side of the bare wafer;

[0009] forming a first insulating layer, wherein the first insulating layer covers the front surface of the bare wafer and the surface of the deep hole;

[0010] Filling the deep hole with metal copper to form a through silicon via;

[0011] Providing a carrier, the carrier comprising a SiO2 layer;

[0012] The SiO2 layer on the carrier wafer is brought into contact with the through silicon via to form a Cu-SiO2 mixed bonding interface;

[0013] Thinning the back side of the bare wafer so that the bottom of the through silicon via is exposed from the back side of the bare wafer;

[0014] forming a second insulating layer, wherein the second insulating layer covers the back side of the thinned bare wafer;

[0015] Forming a multi-layer metal interconnect unit and a first bump unit, wherein one end of the multi-layer metal interconnect unit is connected to the first bump unit, and the other end of the multi-layer metal interconnect unit is connected to the bottom of the through silicon via that exposes the back side of the bare wafer;

[0016] Removing the carrier wafer so that an end of the through silicon via away from the multi-layer metal interconnection unit is exposed;

[0017] A second bump unit is formed, wherein the second bump unit is connected to an end of the through silicon via far away from the multi-layer metal interconnection unit.

[0018] In some embodiments, before the step of filling the deep hole with copper metal to form a through silicon via, the method further includes:

[0019] forming an adhesion layer, the adhesion layer being located on the surface of the deep hole;

[0020] A seed layer is formed, wherein the seed layer is located on the adhesion layer.

[0021] In some embodiments, the step of filling the deep hole with copper metal to form a through silicon via comprises:

[0022] Using electroplating to fill the deep hole covered with the adhesion layer with metal copper;

[0023] The metal copper filled in the deep hole and exceeding the upper surface of the first insulating layer is removed by a chemical mechanical polishing process.

[0024] In some embodiments, the step of forming the second insulating layer includes:

[0025] Depositing a SiO2 insulating layer on the back side of the thinned bare wafer and the upper surface of the bottom of the through silicon via beyond the back side of the bare wafer by plasma enhanced chemical vapor deposition;

[0026] The SiO2 insulating layer is polished by using a chemical mechanical polishing process so that the bottom of the through silicon via is exposed, and the remaining SiO2 insulating layer is the second insulating layer.

[0027] In some embodiments, the step of thinning the back side of the bare wafer includes:

[0028] Thinning the back side of the bare wafer to a preset thickness;

[0029] The back side of the bare wafer thinned to the preset thickness is dry-etched so that the bottom of the through silicon via is exposed on the back side of the bare wafer.

[0030] In some embodiments, the step of forming the multi-layer metal interconnection unit and the first bump unit includes:

[0031] A multi-layer metal interconnection unit and a first bump unit are formed by photolithography and electroplating processes.

[0032] In some embodiments, the step of forming the second bump unit includes:

[0033] The second bump unit is formed by photolithography and electroplating processes.

[0034] According to a second aspect of the present invention, there is provided a method for manufacturing a 2.5D integrated module, comprising: the method for manufacturing a through silicon via adapter plate, forming a chip on a first bump unit, forming an underfill layer between the lower surface of the chip and the upper surface of the multi-layer metal interconnect unit, forming a plastic layer on the side wall of the chip, and dicing to form a 2.5D integrated module; wherein, the step of forming the chip on the first bump unit, forming an underfill unit between the lower surface of the chip and the upper surface of the multi-layer metal interconnect unit, and forming a plastic layer on the side wall of the chip is between the step of forming the multi-layer metal interconnect unit and the first bump unit, and the step of removing the carrier; the step of dicing to form the 2.5D integrated module is after the step of forming the second bump unit.

[0035] According to a third aspect of the present invention, there is provided a through silicon via adapter plate, comprising:

[0036] Bare wafer;

[0037] A through silicon via, wherein the through silicon via is arranged on the bare wafer; the through silicon via comprises a first insulating layer and metal copper;

[0038] A multi-layer metal interconnect unit and a first bump unit, wherein one end of the multi-layer metal interconnect unit is connected to the first bump unit, and the other end of the multi-layer metal interconnect unit is connected to the bottom of the through silicon via that exposes the back side of the bare wafer;

[0039] A second bump unit is connected to an end of the through silicon via far away from the multi-layer metal interconnection unit.

[0040] According to a fourth aspect of the present invention, a 2.5D integrated module is provided, comprising the through silicon via adapter plate, and also comprising a chip, an underfill layer and a plastic encapsulation layer; wherein the chip is located on a first bump unit; the underfill layer is located between the lower surface of the chip and the upper surface of the multi-layer metal interconnection unit; and the plastic encapsulation layer is located on the side wall of the chip.

[0041] In the above embodiments, a through silicon via adapter plate and a manufacturing method thereof, a 2.5D integrated module and a manufacturing method thereof are provided. In the manufacturing method of the through silicon via adapter plate, the SiO2 layer of the carrier contacts the through silicon via to form a Cu-SiO2 mixed bonding interface, which is used to replace temporary bonding, thereby reducing the difficulty of the back process of the through silicon via adapter plate. The method comprises: providing a bare wafer; forming a deep hole on the front side of the bare wafer; forming a first insulating layer; filling metal copper in the deep hole to form a through silicon via; providing a carrier, the carrier comprising a SiO2 layer; contacting the SiO2 layer on the carrier with the through silicon via to form a Cu-SiO2 mixed bonding interface; thinning the back side of the bare wafer so that the bottom of the through silicon via is exposed on the back side of the bare wafer; forming a second insulating layer; forming a multi-layer metal interconnect unit and a first bump unit; removing the carrier; and forming a second bump unit.

[0042] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A flowchart of a method for manufacturing a through silicon via adapter plate according to some embodiments is exemplarily shown;

[0044] Figure 2 A schematic structural diagram of a bare wafer provided according to some embodiments is exemplarily shown;

[0045] Figure 3 A schematic structural diagram of a bare wafer for forming deep holes according to some embodiments is exemplarily shown;

[0046] Figure 4 A schematic structural diagram of a bare wafer provided with a deep hole and a first insulating layer according to some embodiments is exemplarily shown;

[0047] Figure 5 A schematic structural diagram of a bare wafer provided with through silicon vias according to some embodiments is exemplarily shown;

[0048] Figure 6 A schematic diagram of a structure including a carrier and a bare wafer provided according to some embodiments is exemplarily shown;

[0049] Figure 7 A schematic structural diagram of a bare wafer including a carrier and a back thinned wafer according to some embodiments is exemplarily shown;

[0050] Figure 8A schematic structural diagram of a bare wafer including a second insulating layer, a carrier wafer and a back thinned wafer according to some embodiments is exemplarily shown;

[0051] Fig. 9 A schematic structural diagram of a bare wafer including a multi-layer metal interconnection unit, a first bump unit, a second insulating layer, a carrier, and a back thinned wafer according to some embodiments is exemplarily shown;

[0052] Fig.10 A schematic diagram of a structure including a chip provided according to some embodiments is exemplarily shown;

[0053] Fig.11 A schematic diagram of a structure including a chip, an underfill unit and a plastic packaging layer provided according to some embodiments is exemplarily shown;

[0054] Fig.12 A schematic diagram of a structure after a slide is removed according to some embodiments is exemplarily shown;

[0055] Fig.13 A schematic diagram of a structure including a second bump unit provided according to some embodiments is exemplarily shown. DETAILED DESCRIPTION

[0056] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0057] It should be noted that, in the description of the present application, the meaning of the terms "on", "above", "above", and "above" should be interpreted in the broadest sense, meaning that the description containing these terms is interpreted as "the component can be set on another component in direct contact, or there can be an intermediate component or layer between the components". In addition, for the convenience of description, the present application may also use spatial relative terms such as "under", "below", "under", "on", "above", "above", "lower", "upper", etc. to describe the relationship between an element or component and another element or component shown in the drawings. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90° or in other orientations), and the spatial relative descriptors used in the present application can be interpreted accordingly.

[0058] The term "layer" as used in this application refers to a portion of a material that includes an area having a certain thickness. A layer may extend over the entire underlying or superstructure, or may extend over a localized area of ​​the underlying or superstructure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure whose thickness is less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically and / or along a tapered surface.

[0059] 2.5D integrated modules have brought new development opportunities to the semiconductor industry by improving performance, reducing size, and enhancing flexibility.

[0060] However, the manufacturing difficulty of the silicon via adapter board of the 2.5D integrated module is relatively high, resulting in problems such as difficult process control, narrow process window and poor controllability.

[0061] In the related technologies, 2.5D integration technology uses a temporary bonding glass carrier when performing the through silicon via back exposure process, and completes the through silicon via back exposure process with the assistance of the glass carrier. Since the temporary bonding glue is an organic material with a relatively low Tg temperature and cannot withstand a temperature above 200°C, the TSV back process temperature is limited. After the temporary bonding glue is temporarily bonded, the uniformity of the glue thickness is difficult to control, especially when thick glue is used, which brings great difficulties to the through silicon via exposure process.

[0062] Therefore, how to reduce the difficulty of manufacturing the through silicon via adapter plate has become a technical problem that needs to be solved urgently by those skilled in the art.

[0063] The present application embodiment provides a method for manufacturing a through silicon via adapter (TSV adapter), in which the SiO2 layer of the carrier contacts the through silicon via to form a Cu-SiO2 hybrid bonding interface, which is used to replace temporary bonding, thereby reducing the difficulty of the back side process of the through silicon via adapter. The method includes S100-S1200. Figure 1 A flow chart of a method for manufacturing a through silicon via adapter plate according to some embodiments is exemplified.

[0064] S100, providing a bare wafer 101. The bare wafer may be a standard bare wafer. Figure 2 A schematic structural diagram of a bare wafer provided according to some embodiments is exemplarily shown.

[0065] S200 , forming a deep hole 102 on the front side of the bare wafer.

[0066] In some embodiments, a deep hole of a certain size and depth can be formed according to requirements through photolithography and etching processes. Figure 3A schematic structural diagram of a bare wafer for forming deep holes according to some embodiments is exemplarily shown.

[0067] S300 , forming a first insulating layer 103 , wherein the first insulating layer 103 covers the front surface of the bare wafer 101 and the surface of the deep hole 102 .

[0068] In some embodiments, a first insulating layer may be deposited on the front surface of the bare wafer 101 and the surface of the deep hole 102 by a plasma enhanced chemical vapor deposition process (PECVD process). Exemplarily, the thickness of the first insulating layer is greater than or equal to 200 nm.

[0069] Figure 4 A schematic structural diagram of a bare wafer provided with deep holes and a first insulating layer according to some embodiments is exemplarily shown.

[0070] S500 , filling the deep hole with metal copper to form a through silicon via (TSV) 104 , wherein the through silicon via 104 is filled in the deep hole 102 . Figure 5 A schematic structural diagram of a bare wafer provided with through silicon vias according to some embodiments is exemplarily shown.

[0071] In some embodiments, in order to make the connection between the deep hole and the surface of the through silicon via more firmly, before the step of filling the deep hole with metal copper and forming the through silicon via, the method further includes: S400, forming an adhesion layer, the adhesion layer being located on the surface of the deep hole; forming a seed layer, the seed layer being located on the adhesion layer. In some embodiments, the adhesion layer and the seed layer can be deposited on the surface of the deep hole 102 using a physical vapor deposition process (PVD process). Figure 5 The adhesion layer and the adhesion layer are not shown. In some embodiments, the adhesion layer is Ti or Ta. The seed layer is metal copper.

[0072] In some embodiments, the step of filling the deep hole with copper metal to form a through silicon via comprises:

[0073] Filling the deep hole covered with the seed layer with metal copper by electroplating;

[0074] The metal copper filled in the deep hole and exceeding the upper surface of the first insulating layer is removed by a chemical mechanical polishing process (CMP process).

[0075] S600, providing a carrier 105, wherein the carrier 105 comprises a SiO2 layer 1051. The carrier also comprises a silicon substrate 1052, wherein the silicon substrate is located above the SiO2 layer.

[0076] S700, contacting the SiO2 layer on the carrier with the through silicon via to form a Cu-SiO2 mixed bonding interface. Figure 6 A schematic diagram of a structure including a carrier and a bare wafer provided according to some embodiments is exemplarily shown.

[0077] In the embodiment of the present application, the SiO2 layer is in direct contact with the silicon via to form a Cu-SiO2 hybrid bond. In this way, the temporary bonding in the related technology is replaced by Cu-SiO2 hybrid bonding, which can solve the process difficulties of the silicon via back side exposure process due to the limitation of material properties such as temperature resistance of the temporary bonding glue and organic materials, such as process temperature, high vacuum, and uniformity of bonding glue coating, and avoid problems such as difficult process control, narrow process window, and poor controllability.

[0078] S800 , thinning the back side of the bare wafer 101 so that the bottom of the through silicon via 104 is exposed from the back side of the bare wafer 101 (ie, exposed). Figure 7 A schematic structural diagram of a bare wafer including a carrier and a back thinned wafer according to some embodiments is exemplarily shown. Figure 7 The structure in is Figure 6 After the structure in the figure is turned over, the back side of the bare wafer substrate 101 is thinned.

[0079] In some embodiments, the step of thinning the back side of the bare wafer includes:

[0080] The back side of the bare wafer is thinned to a preset thickness. In this embodiment, the back side of the bare wafer is thinned with the aid of a carrier.

[0081] The back side of the bare wafer thinned to the preset thickness is dry-etched so that the bottom of the through silicon via is exposed on the back side of the bare wafer.

[0082] S900 , forming a second insulating layer 106 , wherein the second insulating layer 106 covers the back side of the thinned bare wafer 101 . Figure 8 A schematic structural diagram of a bare wafer including a second insulating layer, a carrier wafer and a back thinned wafer according to some embodiments is exemplarily shown.

[0083] In some embodiments, the step of forming the second insulating layer includes:

[0084] Depositing a SiO2 insulating layer on the back side of the thinned bare wafer and the upper surface of the bottom of the through silicon via beyond the back side of the bare wafer by plasma enhanced chemical vapor deposition (PECVD process);

[0085] The SiO2 insulating layer is polished by a chemical mechanical polishing process so that the bottom of the through silicon via is exposed.

[0086] S1000, forming a multilayer metal interconnection unit 107 and a first bump unit 108, wherein one end of the multilayer metal interconnection unit 107 is connected to the first bump unit 108, and the other end of the multilayer metal interconnection unit 107 is connected to the bottom of the silicon through via 104 exposing the back side of the bare wafer 101. Fig. 9 A schematic structural diagram of a bare wafer including a multi-layer metal interconnection unit, a first bump unit, a second insulating layer, a carrier, and a back-thinned wafer according to some embodiments is exemplarily shown.

[0087] In the embodiment of the present application, since a Cu-SiO2 hybrid bonded silicon substrate is used as a carrier, the Damascus process can be compatible when metal interconnection is made after the back side of the TSV is exposed.

[0088] In some embodiments, the step of forming the multi-layer metal interconnection unit and the first bump unit includes: forming the multi-layer metal interconnection unit and the first bump unit by using photolithography and electroplating processes.

[0089] In some embodiments, the chip can be added during the manufacturing process of the TSV adapter board, so that the 2.5D integrated module can also be manufactured when the TSV adapter board is manufactured. In some embodiments, between step S1000 and step S1100, the following is also included:

[0090] The chip 109 is formed on the first bump unit 108, an underfill unit is formed between the lower surface of the chip and the upper surface of the multi-layer metal interconnection unit, and a plastic encapsulation layer is formed on the side wall of the chip.

[0091] In the embodiment of the present application, the TSV etched surface is connected to the carrier, and the chip is mounted on the TSV exposed surface, thereby greatly simplifying the process flow of using a hybrid bonding solution.

[0092] In some embodiments, the chip is mounted by FC flip-chip welding process (flip chip welding process). An underfill is performed between the lower surface of the chip and the upper surface of the multi-layer metal interconnection unit to form an underfill unit. A plastic encapsulation and plastic encapsulation thinning process are used to form a plastic encapsulation layer on the side wall of the chip.

[0093] Fig.10 A schematic diagram of a structure including a chip provided according to some embodiments is exemplarily shown.

[0094] Fig.11 A schematic diagram of a structure including a chip, an underfill unit and a plastic packaging layer provided according to some embodiments is exemplarily shown. Fig.11 In the figure, the black structure 1010 includes an underfill unit and a plastic encapsulation layer.

[0095] S1100 , removing the carrier 105 , so that an end of the through silicon via 104 away from the multi-layer metal interconnection unit is exposed.

[0096] In some embodiments, the entire carrier is removed by wafer thinning and CMP processes to expose the upper surface of the TSV. Fig.12 A schematic structural diagram of a structure after a slide is removed according to some embodiments is exemplarily shown. Fig.12 The structure in Fig.11 The structure in the slide is turned over and removed.

[0097] S1200 , forming a second bump unit 1011 , wherein the second bump unit 1011 is connected to an end of the through silicon via 104 away from the multi-layer metal interconnection unit 107 .

[0098] In some embodiments, the step of forming the second bump unit includes: forming the second bump unit by photolithography and electroplating processes. Fig.13 A schematic diagram of a structure including a second bump unit provided according to some embodiments is exemplarily shown.

[0099] The present application also provides a method for manufacturing a 2.5D integrated module in an embodiment, including: the method for manufacturing a through silicon via adapter plate, forming a chip on a first bump unit, forming an underfill layer between the lower surface of the chip and the upper surface of the multi-layer metal interconnect unit, forming a plastic layer on the side wall of the chip, and dicing to form a 2.5D integrated module; wherein, the step of forming a chip on the first bump unit, forming an underfill unit between the lower surface of the chip and the upper surface of the multi-layer metal interconnect unit, and forming a plastic layer on the side wall of the chip is between the step of forming the multi-layer metal interconnect unit and the first bump unit, and the step of removing the carrier; the step of dicing to form the 2.5D integrated module is after the step of forming the second bump unit.

[0100] The present application also provides a through silicon via adapter plate, including:

[0101] Bare wafer;

[0102] A through silicon via, wherein the through silicon via is arranged on the bare wafer; the through silicon via comprises a first insulating layer and metal copper;

[0103] A multi-layer metal interconnect unit and a first bump unit, wherein one end of the multi-layer metal interconnect unit is connected to the first bump unit, and the other end of the multi-layer metal interconnect unit is connected to the bottom of the through silicon via that exposes the back side of the bare wafer;

[0104] A second bump unit is connected to an end of the through silicon via far away from the multi-layer metal interconnection unit.

[0105] It should be noted that the device structure, shape, and material, etc. in the embodiments of the through silicon via adapter plate in the present application can refer to the above-mentioned embodiments of the method for manufacturing the through silicon via adapter plate, and will not be repeated here.

[0106] The present application also provides a 2.5D integrated module, such as Fig.13 As shown, it includes the silicon via adapter plate, and also includes a chip, an underfill layer and a plastic encapsulation layer; wherein the chip is located on the first bump unit; the underfill layer is located between the lower surface of the chip and the upper surface of the multi-layer metal interconnection unit; the plastic encapsulation layer is located on the side wall of the chip.

[0107] It should be noted that the device structure, shape, material, etc. in the embodiment of the 2.5D integrated module in the present application can refer to the above-mentioned embodiment of the manufacturing method of the 2.5D integrated module, and will not be repeated here.

[0108] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for manufacturing a through silicon via adapter plate, characterized in that: include: Providing a bare wafer; forming a deep hole on the front side of the bare wafer; forming a first insulating layer, wherein the first insulating layer covers the front surface of the bare wafer and the surface of the deep hole; Filling the deep hole with metal copper to form a through silicon via; Providing a carrier, the carrier comprising a SiO2 layer; The SiO2 layer on the carrier wafer is brought into contact with the through silicon via to form a Cu-SiO2 mixed bonding interface; Thinning the back side of the bare wafer so that the bottom of the through silicon via is exposed from the back side of the bare wafer; forming a second insulating layer, wherein the second insulating layer covers the back side of the thinned bare wafer; Forming a multi-layer metal interconnect unit and a first bump unit, wherein one end of the multi-layer metal interconnect unit is connected to the first bump unit, and the other end of the multi-layer metal interconnect unit is connected to the bottom of the through silicon via that exposes the back side of the bare wafer; Removing the carrier wafer so that an end of the through silicon via away from the multi-layer metal interconnection unit is exposed; A second bump unit is formed, wherein the second bump unit is connected to an end of the through silicon via far away from the multi-layer metal interconnection unit.

2. The method according to claim 1, characterized in that Before the step of filling the deep hole with copper metal to form a through silicon via, the method further comprises: forming an adhesion layer, the adhesion layer being located on the surface of the deep hole; A seed layer is formed, wherein the seed layer is located on the adhesion layer.

3. The method according to claim 2, characterized in that The step of filling the deep hole with copper metal to form a through silicon via comprises: Filling the deep hole covered with the seed layer with metal copper by electroplating; The metal copper filled in the deep hole and exceeding the upper surface of the first insulating layer is removed by a chemical mechanical polishing process.

4. The method according to claim 1, characterized in that: The step of forming the second insulating layer comprises: Depositing a SiO2 insulating layer on the back side of the thinned bare wafer and the upper surface of the bottom of the through silicon via beyond the back side of the bare wafer by plasma enhanced chemical vapor deposition; The SiO2 insulating layer is polished by using a chemical mechanical polishing process so that the bottom of the through silicon via is exposed, and the remaining SiO2 insulating layer is the second insulating layer.

5. The method according to claim 1, characterized in that The step of thinning the back side of the bare wafer comprises: Thinning the back side of the bare wafer to a preset thickness; The back side of the bare wafer thinned to the preset thickness is dry-etched so that the bottom of the through silicon via is exposed on the back side of the bare wafer.

6. The method according to claim 1, characterized in that The step of forming a multi-layer metal interconnection unit and a first bump unit comprises: A multi-layer metal interconnection unit and a first bump unit are formed by photolithography and electroplating processes.

7. The method according to claim 1, characterized in that The step of forming the second bump unit comprises: The second bump unit is formed by photolithography and electroplating processes.

8. A method for manufacturing a 2.5D integrated module, characterized in that: include: The method for manufacturing a through silicon via adapter plate according to any one of claims 1 to 7, forming a chip on the first bump unit, forming an underfill layer between the lower surface of the chip and the upper surface of the multi-layer metal interconnect unit, forming a plastic sealing layer on the side wall of the chip, and dicing to form a 2.5D integrated module; Among them, the chip is formed on the first bump unit, an underfill unit is formed between the lower surface of the chip and the upper surface of the multi-layer metal interconnection unit, and the step of forming a plastic encapsulation layer on the side wall of the chip is between the step of forming the multi-layer metal interconnection unit and the first bump unit and the step of removing the carrier; the dicing to form a 2.5D integrated module is after the step of forming the second bump unit.

9. A through silicon via adapter plate, characterized in that: include: Bare wafer; A through silicon via, wherein the through silicon via is arranged on the bare wafer; the through silicon via comprises a first insulating layer and metal copper; A multi-layer metal interconnect unit and a first bump unit, wherein one end of the multi-layer metal interconnect unit is connected to the first bump unit, and the other end of the multi-layer metal interconnect unit is connected to the bottom of the through silicon via that exposes the back side of the bare wafer; A second bump unit is connected to an end of the through silicon via far away from the multi-layer metal interconnection unit.

10. A 2.5D integrated module, characterized in that: The through silicon via adapter plate according to claim 9 further comprises a chip, an underfill layer and a plastic encapsulation layer; wherein the chip is located on the first bump unit; the underfill layer is located between the lower surface of the chip and the upper surface of the multi-layer metal interconnection unit; and the plastic encapsulation layer is located on the side wall of the chip.

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