Preparation method and device of semiconductor metal interconnection structure and electronic equipment

Abstract

The invention provides a preparation method and device of a semiconductor metal interconnection structure and electronic equipment, and relates to the technical field of semiconductor manufacturing, and the method comprises the steps: carrying out the photoetching of a preset semiconductor device, forming a metal interconnection substrate, and forming a groove in the surface of the metal interconnection substrate; and depositing metal tungsten and metal aluminum on the surface of the metal interconnection substrate in sequence to obtain the target semiconductor metal interconnection structure. The groove is filled by using the metal tungsten and the metal aluminum in a combined manner, so that the semiconductor device is prevented from being damaged while the filling performance is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a method, device and electronic equipment for preparing a semiconductor metal interconnect structure. Background Art

[0002] In the process of semiconductor chip preparation, metal interconnection plays an important role. In this process, due to the low resistivity of metal aluminum Al and metal tungsten W, specifically, the resistivity of metal tungsten W is 8uΩ·cm (microohm·cm), and the resistivity of metal aluminum Al is 2.65uΩ·cm, so metal aluminum Al and metal tungsten W are often used in metal interconnection. Due to the excellent filling performance of metal tungsten W, it is widely used in the filling process of semiconductor back-end metal interconnection structure. Generally speaking, metal aluminum Al is usually used for planar wire connection in the back-end of semiconductor preparation due to its poor filling performance.

[0003] However, for larger hole filling widths, such as CD>1.4um (micrometers), hole filling depth>0.7um, and hole sidewall angle angle≥80° (degrees), if the hole is completely filled, the metal tungsten W needs to be thicker, and its stress will be too large, which will damage the semiconductor device structure and bring difficulties to the subsequent process. Although the stress and resistivity of metal aluminum Al are smaller, its filling performance is poor, so metal tungsten W or metal aluminum Al is used alone for filling. Summary of the invention

[0004] In view of this, the purpose of the present application is to at least provide a method, device and electronic device for preparing a semiconductor metal interconnect structure, by using metal tungsten and metal aluminum to fill the grooves, thereby improving the filling performance and preventing damage to the semiconductor device.

[0005] This application mainly includes the following aspects: In a first aspect, an embodiment of the present application provides a method for preparing a semiconductor metal interconnect structure, the method comprising: performing photolithography on a preset semiconductor device to form a metal interconnect substrate, wherein a groove is formed on the surface of the metal interconnect substrate; and successively depositing metal tungsten and metal aluminum on the surface of the metal interconnect substrate to obtain a target semiconductor metal interconnect structure.

[0006] In one possible implementation, the target semiconductor metal interconnect structure is obtained by: depositing metal tungsten on the surface of the metal interconnect substrate to form a metal tungsten layer; performing an etching back process on the metal tungsten layer to obtain a structure layer to be processed formed by a target metal tungsten structure layer located on the sidewall of the groove and the metal interconnect substrate; and depositing metal aluminum on the surface of the structure layer to be processed to obtain the target semiconductor metal interconnect structure.

[0007] In a possible implementation, before depositing metal tungsten on the surface of the metal interconnect substrate to form a metal tungsten layer, the method further includes: depositing an adhesion material on the surface of the metal interconnect substrate to form an adhesion isolation layer on the surface of the metal interconnect substrate.

[0008] In one possible implementation, the target semiconductor metal interconnect structure is obtained by: depositing metal tungsten on the surface of the adhesion isolation layer to form a metal tungsten layer; etching back the metal tungsten layer on the surface of the adhesion isolation layer according to a preset etching back process standard to obtain a target metal tungsten structure layer on the surface of the adhesion isolation layer at the inner side wall of the groove; forming a target structure to be processed by a metal interconnect substrate, an adhesion isolation layer and a target metal tungsten structure layer; and depositing metal aluminum on the surface of the target structure to be processed to obtain a target semiconductor metal interconnect structure.

[0009] In a possible implementation manner, the corresponding material of the metal interconnect substrate is silicon oxide, and the corresponding material of the adhesion isolation layer is metal titanium and titanium nitride.

[0010] In the second aspect, an embodiment of the present application also provides a device for preparing a semiconductor metal interconnection structure, the device comprising: a photolithography module, used to form a metal interconnection substrate after performing photolithography processing on a preset semiconductor device, wherein a groove is formed on the surface of the metal interconnection substrate; a deposition module, used to successively deposit metal tungsten and metal aluminum on the surface of the metal interconnection substrate to obtain a target semiconductor metal interconnection structure.

[0011] In a possible embodiment, the deposition module also includes: a first deposition unit, used to deposit metal tungsten on the surface of the metal interconnect substrate to form a metal tungsten layer; an etching back processing unit, used to perform an etching back process on the metal tungsten layer to obtain a structure layer to be processed formed by a target metal tungsten structure layer located on the side wall of the groove and the metal interconnect substrate; a second deposition unit, used to deposit metal aluminum on the surface of the structure layer to be processed to obtain a target semiconductor metal interconnect structure.

[0012] In a possible embodiment, the deposition module further includes: a third deposition unit for depositing metal tungsten on the surface of the metal interconnect substrate, and before forming the metal tungsten layer, depositing an adhesion material on the surface of the metal interconnect substrate to form an adhesion isolation layer on the surface of the metal interconnect substrate.

[0013] In a third aspect, an embodiment of the present application further provides an electronic device, comprising: a processor, a memory and a bus, the memory storing machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate through the bus, and the machine-readable instructions are executed by the processor to execute the steps of the method for preparing a semiconductor metal interconnect structure in the above-mentioned first aspect or any possible implementation of the first aspect.

[0014] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of preparing the semiconductor metal interconnect structure in the above-mentioned first aspect or any possible implementation of the first aspect are executed.

[0015] The method, device and electronic device for preparing a semiconductor metal interconnect structure provided in the embodiment of the present application include: performing photolithography on a preset semiconductor device to form a metal interconnect substrate, wherein a groove is formed on the surface of the metal interconnect substrate; and depositing metal tungsten and metal aluminum on the surface of the metal interconnect substrate in sequence to obtain a target semiconductor metal interconnect structure. By using metal tungsten and metal aluminum to fill the groove, the filling performance is improved while preventing damage to the semiconductor device.

[0016] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A schematic diagram of using metal aluminum to prepare a semiconductor metal interconnect structure is shown; Figure 2 A schematic diagram of using metal tungsten to prepare a semiconductor metal interconnect structure is shown; Figure 3 A flow chart showing a method for preparing a semiconductor metal interconnect structure provided in an embodiment of the present application is shown; Figure 4 A schematic diagram showing a process for preparing a semiconductor metal interconnect structure provided by an embodiment of the present application is shown; Figure 5 A mapping relationship curve between the thickness of the metal tungsten layer and the warpage of the semiconductor in the trench filling process provided by an embodiment of the present application is shown; Figure 6 A mapping relationship curve between the thickness of the metal aluminum layer and the warpage of the semiconductor during the trench filling process provided by an embodiment of the present application is shown; Figure 7 The scanning electron microscope images of metal aluminum deposition at different metal tungsten layer thicknesses provided in the embodiments of the present application are shown; Figure 8A functional module diagram of a semiconductor metal interconnect structure manufacturing device provided by an embodiment of the present application is shown; Fig. 9 A schematic structural diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0019] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of explanation and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of sequence, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art, under the guidance of the content of the present application, can add one or more other operations to the flowchart, or remove one or more operations from the flowchart.

[0020] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0021] In the process of preparing semiconductor chips, metal interconnection plays an important role. In the process of preparing semiconductor metal interconnection structure, due to the low resistivity of metal aluminum Al and metal tungsten W, specifically, the resistivity of metal tungsten W is 8uΩ·cm (microohm·cm), and the resistivity of metal aluminum Al is 2.65uΩ·cm, so metal aluminum Al and metal tungsten W are often used in metal interconnection. Due to the excellent filling performance of metal tungsten W, it is widely used in the filling process of semiconductor back-end metal interconnection structure. Generally speaking, metal aluminum Al is usually used for planar wire connection in the back-end of semiconductor preparation due to its poor filling performance.

[0022] See also Figure 1 , Figure 1 A schematic diagram of using aluminum to prepare a semiconductor metal interconnect structure is shown. Figure 1As shown in (a1), a metal interconnect substrate ① is first formed by a preliminary exposure and etching process, a groove ② is formed on the surface of the metal interconnect substrate ①, and the material of the metal interconnect substrate ① is silicon dioxide SiO2. Figure 1 As shown in (b1) in FIG. 1 , an adhesive material is deposited on the surface of the metal interconnect substrate ① to form an adhesive isolation layer ③, such as Figure 1 As shown in (c1), metal aluminum Al is deposited on the upper surface of the adhesion isolation layer ③ to obtain a metal aluminum layer ④, thereby forming the metal interconnect structure shown in (c1). Specifically, the adhesion isolation layer ③ is composed of metal titanium Ti and titanium nitride TiN. The main function of metal titanium Ti is adhesion, and the function of titanium nitride TiN is to prevent aluminum fluoride from corroding the metal interconnect substrate during the deposition of metal aluminum.

[0023] Depend on Figure 1 As shown in (c1), due to the poor filling performance of metal aluminum Al, over-hang will occur when using metal aluminum Al to fill the groove, resulting in premature sealing of the filling process. That is, premature sealing is performed before the void Void is filled, forming a metal interconnect structure with a void Void inside as shown in (c1). After the metal interconnect structure shown in (c1) is subsequently exposed and etched, the void Void will leak out, which will seriously affect the performance of the semiconductor device.

[0024] See also Figure 2 , Figure 2 A schematic diagram of using metal tungsten to prepare a semiconductor metal interconnect structure is shown. Figure 2 As shown in (a2) in FIG. 1 , a metal interconnect substrate ① is first formed by a preliminary exposure and etching process, and a groove ② is formed on the surface of the metal interconnect substrate ①. Figure 2 As shown in (b2) in FIG. 1 , an adhesive material is deposited on the surface of the metal interconnect substrate ① to form an adhesive isolation layer ③, such as Figure 2 As shown in (c2), metal tungsten W is deposited on the upper surface of the adhesion isolation layer ③ to fill the groove with metal tungsten W to obtain a metal tungsten layer ⑤, thereby forming the metal interconnection structure shown in (c2).

[0025] However, although the use of metal tungsten W to fill the trench has good filling performance, if metal tungsten W is used for larger trenches, such as a trench CD (Critical Dimension)>1.4um, trench depth>0.7um, and trench sidewall inclination angle angle≥80° (degrees), the thickness of the metal tungsten W is also required to be relatively large to completely fill the changed trench. In this way, the stress of the metal tungsten W is too large, which can easily cause the semiconductor device to crack or excessively warp, thereby damaging the semiconductor device. More seriously, due to the bending of the semiconductor device, it is very easy to make the subsequent process for the metal interconnect structure unable to proceed, which brings difficulties to the subsequent process.

[0026] Based on this, an embodiment of the present application provides a method for preparing a semiconductor metal interconnect structure, by using metal tungsten and metal aluminum to fill the trench, thereby improving the filling performance and preventing damage to the semiconductor device, as follows: See also Figure 3 , Figure 3 A flow chart of a method for preparing a semiconductor metal interconnect structure provided by an embodiment of the present application is shown. Figure 3 As shown, the method provided in the embodiment of the present application comprises the following steps: S100, performing photolithography on a preset semiconductor device to form a metal interconnection matrix.

[0027] Wherein, a groove is formed on the surface of the metal interconnection substrate.

[0028] S200, depositing metal tungsten and metal aluminum on the surface of the metal interconnect substrate in sequence to obtain a target semiconductor metal interconnect structure.

[0029] In step S100 to step S200, the trench is filled with metal tungsten and metal aluminum in combination, thereby improving the filling performance and preventing damage to the semiconductor device.

[0030] In a preferred embodiment, step S200 includes: Metal tungsten is deposited on the surface of the metal interconnect substrate to form a metal tungsten layer, and the metal tungsten layer is subjected to an etching back process to obtain a structure to be processed formed by the metal tungsten layer located on the sidewall of the groove and the metal interconnect substrate, and metal aluminum is deposited on the surface of the structure to be processed to obtain a target semiconductor metal interconnect structure.

[0031] Preferably, the present application discloses a novel filling process in which metal tungsten W is first partially filled, then the groove morphology is regulated through a back etching process, and then the groove is filled with metal Al. In this way, the target semiconductor metal interconnect structure obtained by combining metal tungsten W and metal Al avoids the problem of insufficient filling and premature sealing caused by filling with metal aluminum Al alone, and also solves the problem of excessive warping of the semiconductor metal interconnect structure obtained by filling with metal tungsten W alone.

[0032] See also Figure 4 , Figure 4 FIG. 1 is a schematic diagram showing a process for preparing a semiconductor metal interconnect structure provided by an embodiment of the present application. In step S100, as Figure 4 As shown, after preliminary exposure and etching treatment of the preset semiconductor device, a metal interconnect substrate ① as shown in (a3) ​​can be formed. The metal interconnect substrate ① is composed of silicon oxide, more specifically, silicon dioxide SiO2, and a groove ② is formed on the surface of the metal interconnect substrate ①.

[0033] In a preferred embodiment, if Figure 4 As shown in (b3), before executing step S200, the method further includes: An adhesion material is deposited on the surface of the metal interconnect substrate ① to form an adhesion isolation layer ③ (red part) on the surface of the metal interconnect substrate ①, wherein the corresponding materials of the adhesion isolation layer ③ are metal titanium Ti and titanium nitride TiN.

[0034] In a preferred embodiment, if Figure 4 As shown in (c3), step S200 includes: Metal tungsten W is deposited on the surface of the adhesion isolation layer ③ to fill the groove with the metal tungsten W to obtain a metal tungsten layer ⑤.

[0035] like Figure 4 As shown in (d) in FIG. 1 , step S300 includes: According to the preset etching process standard Figure 4 The metal tungsten layer ⑤ in the structure shown in (c3) is etched back to obtain the target metal tungsten structure layer ⑦ in the structure shown in (d).

[0036] Preferably, the target metal tungsten structure layer ⑦ is a metal tungsten layer located on the surface of the adhesion isolation layer at the sidewall of the trench.

[0037] Specifically, for grooves of different morphologies, different back-etching process standards need to be determined in advance according to actual needs. Specifically, the back-etching process standards include multiple back-etching process parameters, and the multiple back-etching process parameters include but are not limited to at least one of the following items: the metal tungsten etching depth and the retention angle corresponding to the metal tungsten layer on the groove sidewall. Generally speaking, the smaller the retention angle, the lower the metal tungsten etching depth value, and the more conducive to the use of metal aluminum Al for subsequent filling.

[0038] Therefore, based on the metal tungsten etching depth indicated by the etch-back process standard, the metal tungsten layer located on the surface of the adhesion isolation layer at the bottom of the trench can be divided into two categories: complete removal and partial removal.

[0039] It is composed of a metal interconnect substrate ①, an adhesion isolation layer ② and a target metal tungsten structure layer ⑦. Figure 4 The target structure to be processed is shown in (d).

[0040] In a preferred embodiment, if Figure 4 As shown in (e) in the figure, metal aluminum Al is deposited on the surface of the target structure to be processed to obtain the target semiconductor metal interconnect structure as shown in (e).

[0041] By Figure 4 It can be seen that the target semiconductor metal interconnect structure formed by the method of the present application also has corresponding voids, but compared with Figure 1 By simply using metal aluminum Al for deposition, the hole area is greatly reduced, thus avoiding the problems caused by over-hang of metal aluminum deposition to a great extent.

[0042] In a preferred embodiment, see Figure 5 , Figure 5 The first mapping relationship curve between the thickness of the metal tungsten layer and the warpage of the semiconductor during the trench filling process provided by the embodiment of the present application is shown. Figure 6 , Figure 6 A second mapping relationship curve between the thickness of the metal aluminum layer and the semiconductor warpage during the trench filling process provided by an embodiment of the present application is shown.

[0043] Specifically, Figure 5 , the horizontal axis x1 represents the thickness of the metal tungsten layer, the unit is nm (nanometer), the vertical axis Y BOW1 Indicates the semiconductor warpage, in um (micrometer), where the first mapping relationship curve is represented by Y BOW1 =0.5395x1+136.52.

[0044] Specifically, a warpage test may be performed on the metal tungsten material in advance to obtain actual warpage test data corresponding to the metal tungsten. The actual warpage test data includes a plurality of warpage test samples, each of which includes the thickness of the metal tungsten and its corresponding semiconductor warpage value, for example Figure 5 The coordinate system shows 7 warpage test samples from left to right ( Figure 5 Middle dots), including (250nm, 255.9um), (300nm, 290.1um), (500nm, 437.4um), (800nm, 570um), (850nm, 593.9um), (900nm, 626um) and (1100nm, 717.8um).

[0045] Using multiple warpage test samples for fitting, the first mapping relationship curve is represented by Y BOW1 =0.5395x1+136.52, such as Figure 5 The curve ML shown is the Y curve fitted by multiple warpage test samples. BOW1 =0.5395x1+136.52 corresponding relationship curve.

[0046] like Figure 6 is the second mapping relationship curve between the thickness of the metal aluminum layer and the warpage of the semiconductor device. The horizontal axis x2 represents the thickness of the metal aluminum layer in nm (nanometers), and the vertical axis Y BOW2 represents the semiconductor warpage, in um (micrometer), where the second mapping relationship curve is represented by Y BOW2 =0.0009x2+35.894.

[0047] Through the first mapping relationship curve and the second mapping relationship curve, it can be clearly determined that metal aluminum Al and metal tungsten W have corresponding different degrees of warping at different thicknesses. The user can determine the deposition thickness of metal tungsten and metal aluminum based on the first mapping curve and the second mapping curve according to actual conditions.

[0048] See also Figure 7 , Figure 7 The scanning electron microscope images of metal aluminum deposition under different metal tungsten layer thicknesses provided in the embodiment of the present application are shown. In the process of forming a semiconductor metal interconnect structure using the method provided in the embodiment of the present application: like Figure 7 (G1) is a low-magnification scanning electron microscope image of metal aluminum deposition with a metal tungsten layer thickness of 4000 angstroms, as shown in Figure 7 (G2) in the figure is a partial enlarged schematic diagram of (G1). As shown in (G2), when the thickness of the metal tungsten layer is 4000 angstroms, the top sealing rate is 1 / 4, the hole is located in the groove, and the retention angle of the target metal tungsten structure layer located on the right side of the groove is 78.3°.

[0049] like Figure 7 (G3) is a low-magnification scanning electron microscope image of aluminum deposition under a 5000 angstrom metal tungsten layer thickness. Figure 7 (G4) in the figure is a partial enlarged schematic diagram of (G3). As shown in (G3), when the thickness of the metal tungsten layer is 5000 angstroms, the top sealing rate is 3 / 4, the hole is located in the groove, and the retention angle of the target metal tungsten structure layer located on the right side of the groove is 77°.

[0050] As Figure 7 (G5) is a low-magnification scanning electron microscope image of aluminum deposition under a 6000 angstrom metal tungsten layer thickness. Figure 7 (G6) in the figure is a partial enlarged schematic diagram of (G5). As shown in (G6), when the thickness of the metal tungsten layer is 6000 angstroms, the top sealing rate is 4 / 4, the hole is located above the groove, and the angle of the target metal tungsten structure layer on the right side of the groove is 61°.

[0051] It can be seen from (G1) to (G3) that the larger the retention angle corresponding to the target metal tungsten structure layer, the less conducive it is to filling, and the smaller the retention angle, the more conducive it is to filling.

[0052] Based on the same application concept, the embodiments of the present application also provide a device for preparing a semiconductor metal interconnect structure corresponding to the method for preparing a semiconductor metal interconnect structure provided in the above embodiments. Since the principle of solving the problem by the device in the embodiments of the present application is similar to the method for preparing a semiconductor metal interconnect structure in the above embodiments of the present application, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be repeated.

[0053] See also Figure 8 , Figure 8 The functional module diagram of a semiconductor metal interconnect structure manufacturing device provided by an embodiment of the present application is shown. Figure 8 As shown, the device provided by the present application includes: The photolithography module 600 is used to form a metal interconnection substrate after performing photolithography on a preset semiconductor device, wherein a groove is formed on the surface of the metal interconnection substrate.

[0054] The deposition module 610 is used to deposit metal tungsten and metal aluminum on the surface of the metal interconnect substrate in sequence to obtain a target semiconductor metal interconnect structure.

[0055] Preferably, the deposition module 610 includes: A first deposition unit (not shown in the figure) is used to deposit metal tungsten on the surface of the metal interconnect substrate to form a metal tungsten layer; The etching back unit (not shown in the figure) is used to perform etching back process on the metal tungsten layer to obtain a structure layer to be processed formed by the target metal tungsten structure layer located on the side wall of the groove and the metal interconnect substrate; The second deposition unit (not shown in the figure) is used to deposit metal aluminum on the surface of the structure layer to be processed to obtain a target semiconductor metal interconnect structure.

[0056] Preferably, the device further comprises: The third deposition unit (not shown) is used to deposit metal tungsten on the surface of the metal interconnect substrate. Before forming the metal tungsten layer, an adhesion material is deposited on the surface of the metal interconnect substrate to form an adhesion isolation layer on the surface of the metal interconnect substrate.

[0057] Preferably, the first deposition unit is further used to deposit metal tungsten on the surface of the adhesion isolation layer to form a metal tungsten layer.

[0058] The back-etching unit is also used to: back-etch the metal tungsten layer on the surface of the adhesion isolation layer according to a preset back-etching process standard to obtain a target metal tungsten structural layer on the surface of the adhesion isolation layer located at the inner side wall of the groove, and form a target structure to be processed by the metal interconnect substrate, the adhesion isolation layer and the target metal tungsten structural layer.

[0059] The second deposition unit is also used to deposit metal aluminum on the surface of the target structure to be processed to obtain a target semiconductor metal interconnect structure.

[0060] Based on the same application idea, please refer to Fig. 9 , Fig. 9 FIG. 1 is a schematic diagram showing the structure of an electronic device provided by an embodiment of the present application. Fig. 9 As shown, the electronic device 700 includes: a processor 710, a memory 720 and a bus 730. The memory 720 stores machine-readable instructions executable by the processor 710. When the electronic device 700 is running, the processor 710 and the memory 720 communicate with each other through the bus 730. The machine-readable instructions are executed by the processor 710 when it is running, such as the steps of the method for preparing a semiconductor metal interconnection structure provided in any of the above embodiments.

[0061] Based on the same application concept, an embodiment of the present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method for preparing a semiconductor metal interconnect structure provided in the above embodiment are executed.

[0062] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. In the several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0063] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0064] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0065] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0066] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for preparing a semiconductor metal interconnect structure, characterized in that: The method comprises: After performing photolithography on the preset semiconductor device, a metal interconnection substrate is formed, wherein a groove is formed on the surface of the metal interconnection substrate; Metal tungsten and metal aluminum are deposited successively on the surface of the metal interconnect substrate to obtain a target semiconductor metal interconnect structure.

2. The method according to claim 1, characterized in that The target semiconductor metal interconnect structure is obtained by: Depositing metal tungsten on the surface of the metal interconnect substrate to form a metal tungsten layer; Performing an etching back process on the metal tungsten layer to obtain a structure layer to be processed formed by a target metal tungsten structure layer located on the sidewall of the trench and the metal interconnect substrate; Metal aluminum is deposited on the surface of the structure layer to be processed to obtain a target semiconductor metal interconnect structure.

3. The method according to claim 2, characterized in that Before depositing metal tungsten on the surface of the metal interconnect substrate to form a metal tungsten layer, the method further comprises: Adhesion material is deposited on the surface of the metal interconnection substrate to form an adhesion isolation layer on the surface of the metal interconnection substrate.

4. The method according to claim 3, characterized in that: The target semiconductor metal interconnect structure is obtained by: Depositing metal tungsten on the surface of the adhesion isolation layer to form a metal tungsten layer; Etch back the metal tungsten layer on the surface of the adhesion isolation layer according to a preset etching back process standard to obtain a target metal tungsten structure layer on the surface of the adhesion isolation layer at the inner side wall of the groove; The target structure to be processed is formed by the metal interconnect substrate, the adhesion isolation layer and the target metal tungsten structure layer; Metal aluminum is deposited on the surface of the target structure to be processed to obtain a target semiconductor metal interconnect structure.

5. The method according to claim 3, characterized in that: The corresponding material of the metal interconnect substrate is silicon oxide, and the corresponding material of the adhesion isolation layer is metal titanium and titanium nitride.

6. A device for preparing a semiconductor metal interconnect structure, characterized in that: The device comprises: A photolithography module, used for performing photolithography on a preset semiconductor device to form a metal interconnection matrix, wherein a groove is formed on the surface of the metal interconnection matrix; The deposition module is used to deposit metal tungsten and metal aluminum on the surface of the metal interconnect substrate in sequence to obtain a target semiconductor metal interconnect structure.

7. The device according to claim 6, characterized in that The deposition module further comprises: A first deposition unit is used to deposit metal tungsten on the surface of the metal interconnect substrate to form a metal tungsten layer; An etching back processing unit, used for performing an etching back process on the metal tungsten layer to obtain a structure layer to be processed formed by a target metal tungsten structure layer located on the sidewall of the groove and the metal interconnect substrate; The second deposition unit is used to deposit metal aluminum on the surface of the structure layer to be processed to obtain a target semiconductor metal interconnect structure.

8. The device according to claim 7, characterized in that The deposition module further comprises: The third deposition unit is used to deposit metal tungsten on the surface of the metal interconnect substrate. Before forming the metal tungsten layer, an adhesion material is deposited on the surface of the metal interconnect substrate to form an adhesion isolation layer on the surface of the metal interconnect substrate.

9. An electronic device, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate through the bus, and the machine-readable instructions are executed by the processor to execute the steps of the method for preparing a semiconductor metal interconnect structure as described in any one of claims 1 to 5.

10. A computer-readable storage medium, characterized in that: The computer readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method for preparing a semiconductor metal interconnect structure according to any one of claims 1 to 5 are executed.

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